root / hw / cirrus_vga.c @ 3ced9f7a
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1 | e6e5ad80 | bellard | /*
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2 | aeb3c85f | bellard | * QEMU Cirrus CLGD 54xx VGA Emulator.
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3 | 5fafdf24 | ths | *
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4 | e6e5ad80 | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | aeb3c85f | bellard | * Copyright (c) 2004 Makoto Suzuki (suzu)
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6 | 5fafdf24 | ths | *
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7 | e6e5ad80 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | e6e5ad80 | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | e6e5ad80 | bellard | * in the Software without restriction, including without limitation the rights
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10 | e6e5ad80 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | e6e5ad80 | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | e6e5ad80 | bellard | * furnished to do so, subject to the following conditions:
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13 | e6e5ad80 | bellard | *
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14 | e6e5ad80 | bellard | * The above copyright notice and this permission notice shall be included in
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15 | e6e5ad80 | bellard | * all copies or substantial portions of the Software.
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16 | e6e5ad80 | bellard | *
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17 | e6e5ad80 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | e6e5ad80 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | e6e5ad80 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | e6e5ad80 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | e6e5ad80 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | e6e5ad80 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | e6e5ad80 | bellard | * THE SOFTWARE.
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24 | e6e5ad80 | bellard | */
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25 | aeb3c85f | bellard | /*
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26 | aeb3c85f | bellard | * Reference: Finn Thogersons' VGADOC4b
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27 | aeb3c85f | bellard | * available at http://home.worldonline.dk/~finth/
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28 | aeb3c85f | bellard | */
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29 | 87ecb68b | pbrook | #include "hw.h" |
30 | 87ecb68b | pbrook | #include "pc.h" |
31 | 87ecb68b | pbrook | #include "pci.h" |
32 | 87ecb68b | pbrook | #include "console.h" |
33 | e6e5ad80 | bellard | #include "vga_int.h" |
34 | 2bec46dc | aliguori | #include "kvm.h" |
35 | 5245d57a | Gerd Hoffmann | #include "loader.h" |
36 | e6e5ad80 | bellard | |
37 | a5082316 | bellard | /*
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38 | a5082316 | bellard | * TODO:
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39 | ad81218e | bellard | * - destination write mask support not complete (bits 5..7)
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40 | a5082316 | bellard | * - optimize linear mappings
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41 | a5082316 | bellard | * - optimize bitblt functions
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42 | a5082316 | bellard | */
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43 | a5082316 | bellard | |
44 | e36f36e1 | bellard | //#define DEBUG_CIRRUS
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45 | a21ae81d | bellard | //#define DEBUG_BITBLT
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46 | e36f36e1 | bellard | |
47 | e6e5ad80 | bellard | /***************************************
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48 | e6e5ad80 | bellard | *
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49 | e6e5ad80 | bellard | * definitions
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50 | e6e5ad80 | bellard | *
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51 | e6e5ad80 | bellard | ***************************************/
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52 | e6e5ad80 | bellard | |
53 | e6e5ad80 | bellard | // ID
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54 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5422 (0x23<<2) |
55 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5426 (0x24<<2) |
56 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5424 (0x25<<2) |
57 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5428 (0x26<<2) |
58 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5430 (0x28<<2) |
59 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5434 (0x2A<<2) |
60 | a21ae81d | bellard | #define CIRRUS_ID_CLGD5436 (0x2B<<2) |
61 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5446 (0x2E<<2) |
62 | e6e5ad80 | bellard | |
63 | e6e5ad80 | bellard | // sequencer 0x07
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64 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_VGA 0x00 |
65 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_SVGA 0x01 |
66 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_MASK 0x0e |
67 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_8 0x00 |
68 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02 |
69 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_24 0x04 |
70 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_16 0x06 |
71 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_32 0x08 |
72 | e6e5ad80 | bellard | #define CIRRUS_SR7_ISAADDR_MASK 0xe0 |
73 | e6e5ad80 | bellard | |
74 | e6e5ad80 | bellard | // sequencer 0x0f
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75 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_512k 0x08 |
76 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_1M 0x10 |
77 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_2M 0x18 |
78 | e6e5ad80 | bellard | #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled. |
79 | e6e5ad80 | bellard | |
80 | e6e5ad80 | bellard | // sequencer 0x12
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81 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_SHOW 0x01 |
82 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_HIDDENPEL 0x02 |
83 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear |
84 | e6e5ad80 | bellard | |
85 | e6e5ad80 | bellard | // sequencer 0x17
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86 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_VLBFAST 0x10 |
87 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_PCI 0x20 |
88 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_VLBSLOW 0x30 |
89 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_ISA 0x38 |
90 | e6e5ad80 | bellard | #define CIRRUS_MMIO_ENABLE 0x04 |
91 | e6e5ad80 | bellard | #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared. |
92 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80 |
93 | e6e5ad80 | bellard | |
94 | e6e5ad80 | bellard | // control 0x0b
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95 | e6e5ad80 | bellard | #define CIRRUS_BANKING_DUAL 0x01 |
96 | e6e5ad80 | bellard | #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k |
97 | e6e5ad80 | bellard | |
98 | e6e5ad80 | bellard | // control 0x30
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99 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_BACKWARDS 0x01 |
100 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_MEMSYSDEST 0x02 |
101 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_MEMSYSSRC 0x04 |
102 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08 |
103 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PATTERNCOPY 0x40 |
104 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_COLOREXPAND 0x80 |
105 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30 |
106 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00 |
107 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10 |
108 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20 |
109 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30 |
110 | e6e5ad80 | bellard | |
111 | e6e5ad80 | bellard | // control 0x31
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112 | e6e5ad80 | bellard | #define CIRRUS_BLT_BUSY 0x01 |
113 | e6e5ad80 | bellard | #define CIRRUS_BLT_START 0x02 |
114 | e6e5ad80 | bellard | #define CIRRUS_BLT_RESET 0x04 |
115 | e6e5ad80 | bellard | #define CIRRUS_BLT_FIFOUSED 0x10 |
116 | a5082316 | bellard | #define CIRRUS_BLT_AUTOSTART 0x80 |
117 | e6e5ad80 | bellard | |
118 | e6e5ad80 | bellard | // control 0x32
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119 | e6e5ad80 | bellard | #define CIRRUS_ROP_0 0x00 |
120 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_AND_DST 0x05 |
121 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOP 0x06 |
122 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_AND_NOTDST 0x09 |
123 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTDST 0x0b |
124 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC 0x0d |
125 | e6e5ad80 | bellard | #define CIRRUS_ROP_1 0x0e |
126 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_AND_DST 0x50 |
127 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_XOR_DST 0x59 |
128 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_OR_DST 0x6d |
129 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90 |
130 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95 |
131 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_OR_NOTDST 0xad |
132 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC 0xd0 |
133 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6 |
134 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda |
135 | e6e5ad80 | bellard | |
136 | a5082316 | bellard | #define CIRRUS_ROP_NOP_INDEX 2 |
137 | a5082316 | bellard | #define CIRRUS_ROP_SRC_INDEX 5 |
138 | a5082316 | bellard | |
139 | a21ae81d | bellard | // control 0x33
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140 | a5082316 | bellard | #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04 |
141 | 4c8732d7 | bellard | #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02 |
142 | a5082316 | bellard | #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01 |
143 | a21ae81d | bellard | |
144 | e6e5ad80 | bellard | // memory-mapped IO
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145 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword |
146 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword |
147 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTWIDTH 0x08 // word |
148 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word |
149 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word |
150 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word |
151 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword |
152 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword |
153 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte |
154 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTMODE 0x18 // byte |
155 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTROP 0x1a // byte |
156 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte |
157 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word? |
158 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word? |
159 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word |
160 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word |
161 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word |
162 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word |
163 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte |
164 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte |
165 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte |
166 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte |
167 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word |
168 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word |
169 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word |
170 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word |
171 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte |
172 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte |
173 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte |
174 | e6e5ad80 | bellard | |
175 | e6e5ad80 | bellard | // PCI 0x04: command(word), 0x06(word): status
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176 | e6e5ad80 | bellard | #define PCI_COMMAND_IOACCESS 0x0001 |
177 | e6e5ad80 | bellard | #define PCI_COMMAND_MEMACCESS 0x0002 |
178 | e6e5ad80 | bellard | #define PCI_COMMAND_BUSMASTER 0x0004 |
179 | e6e5ad80 | bellard | #define PCI_COMMAND_SPECIALCYCLE 0x0008 |
180 | e6e5ad80 | bellard | #define PCI_COMMAND_MEMWRITEINVALID 0x0010 |
181 | e6e5ad80 | bellard | #define PCI_COMMAND_PALETTESNOOPING 0x0020 |
182 | e6e5ad80 | bellard | #define PCI_COMMAND_PARITYDETECTION 0x0040 |
183 | e6e5ad80 | bellard | #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080 |
184 | e6e5ad80 | bellard | #define PCI_COMMAND_BACKTOBACKTRANS 0x0200 |
185 | e6e5ad80 | bellard | // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
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186 | e6e5ad80 | bellard | #define PCI_CLASS_BASE_DISPLAY 0x03 |
187 | e6e5ad80 | bellard | // PCI 0x08, 0x00ff0000
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188 | e6e5ad80 | bellard | #define PCI_CLASS_SUB_VGA 0x00 |
189 | e6e5ad80 | bellard | // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
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190 | e6e5ad80 | bellard | // 0x10-0x3f (headertype 00h)
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191 | e6e5ad80 | bellard | // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
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192 | e6e5ad80 | bellard | // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
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193 | e6e5ad80 | bellard | #define PCI_MAP_MEM 0x0 |
194 | e6e5ad80 | bellard | #define PCI_MAP_IO 0x1 |
195 | e6e5ad80 | bellard | #define PCI_MAP_MEM_ADDR_MASK (~0xf) |
196 | e6e5ad80 | bellard | #define PCI_MAP_IO_ADDR_MASK (~0x3) |
197 | e6e5ad80 | bellard | #define PCI_MAP_MEMFLAGS_32BIT 0x0 |
198 | e6e5ad80 | bellard | #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1 |
199 | e6e5ad80 | bellard | #define PCI_MAP_MEMFLAGS_64BIT 0x4 |
200 | e6e5ad80 | bellard | #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8 |
201 | e6e5ad80 | bellard | // PCI 0x28: cardbus CIS pointer
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202 | e6e5ad80 | bellard | // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
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203 | e6e5ad80 | bellard | // PCI 0x30: expansion ROM base address
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204 | e6e5ad80 | bellard | #define PCI_ROMBIOS_ENABLED 0x1 |
205 | e6e5ad80 | bellard | // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
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206 | e6e5ad80 | bellard | // PCI 0x38: reserved
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207 | e6e5ad80 | bellard | // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
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208 | e6e5ad80 | bellard | |
209 | a21ae81d | bellard | #define CIRRUS_PNPMMIO_SIZE 0x1000 |
210 | e6e5ad80 | bellard | |
211 | b2b183c2 | aliguori | #define ABS(a) ((signed)(a) > 0 ? a : -a) |
212 | b2b183c2 | aliguori | |
213 | b2eb849d | aurel32 | #define BLTUNSAFE(s) \
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214 | b2eb849d | aurel32 | ( \ |
215 | b2eb849d | aurel32 | ( /* check dst is within bounds */ \
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216 | b2b183c2 | aliguori | (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \ |
217 | b2eb849d | aurel32 | + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \ |
218 | 4e12cd94 | Avi Kivity | (s)->vga.vram_size \ |
219 | b2eb849d | aurel32 | ) || \ |
220 | b2eb849d | aurel32 | ( /* check src is within bounds */ \
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221 | b2b183c2 | aliguori | (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \ |
222 | b2eb849d | aurel32 | + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \ |
223 | 4e12cd94 | Avi Kivity | (s)->vga.vram_size \ |
224 | b2eb849d | aurel32 | ) \ |
225 | b2eb849d | aurel32 | ) |
226 | b2eb849d | aurel32 | |
227 | a5082316 | bellard | struct CirrusVGAState;
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228 | a5082316 | bellard | typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s, |
229 | a5082316 | bellard | uint8_t * dst, const uint8_t * src,
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230 | e6e5ad80 | bellard | int dstpitch, int srcpitch, |
231 | e6e5ad80 | bellard | int bltwidth, int bltheight); |
232 | a5082316 | bellard | typedef void (*cirrus_fill_t)(struct CirrusVGAState *s, |
233 | a5082316 | bellard | uint8_t *dst, int dst_pitch, int width, int height); |
234 | e6e5ad80 | bellard | |
235 | e6e5ad80 | bellard | typedef struct CirrusVGAState { |
236 | 4e12cd94 | Avi Kivity | VGACommonState vga; |
237 | e6e5ad80 | bellard | |
238 | e6e5ad80 | bellard | int cirrus_linear_io_addr;
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239 | a5082316 | bellard | int cirrus_linear_bitblt_io_addr;
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240 | e6e5ad80 | bellard | int cirrus_mmio_io_addr;
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241 | e6e5ad80 | bellard | uint32_t cirrus_addr_mask; |
242 | 78e127ef | bellard | uint32_t linear_mmio_mask; |
243 | e6e5ad80 | bellard | uint8_t cirrus_shadow_gr0; |
244 | e6e5ad80 | bellard | uint8_t cirrus_shadow_gr1; |
245 | e6e5ad80 | bellard | uint8_t cirrus_hidden_dac_lockindex; |
246 | e6e5ad80 | bellard | uint8_t cirrus_hidden_dac_data; |
247 | e6e5ad80 | bellard | uint32_t cirrus_bank_base[2];
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248 | e6e5ad80 | bellard | uint32_t cirrus_bank_limit[2];
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249 | e6e5ad80 | bellard | uint8_t cirrus_hidden_palette[48];
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250 | a5082316 | bellard | uint32_t hw_cursor_x; |
251 | a5082316 | bellard | uint32_t hw_cursor_y; |
252 | e6e5ad80 | bellard | int cirrus_blt_pixelwidth;
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253 | e6e5ad80 | bellard | int cirrus_blt_width;
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254 | e6e5ad80 | bellard | int cirrus_blt_height;
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255 | e6e5ad80 | bellard | int cirrus_blt_dstpitch;
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256 | e6e5ad80 | bellard | int cirrus_blt_srcpitch;
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257 | a5082316 | bellard | uint32_t cirrus_blt_fgcol; |
258 | a5082316 | bellard | uint32_t cirrus_blt_bgcol; |
259 | e6e5ad80 | bellard | uint32_t cirrus_blt_dstaddr; |
260 | e6e5ad80 | bellard | uint32_t cirrus_blt_srcaddr; |
261 | e6e5ad80 | bellard | uint8_t cirrus_blt_mode; |
262 | a5082316 | bellard | uint8_t cirrus_blt_modeext; |
263 | e6e5ad80 | bellard | cirrus_bitblt_rop_t cirrus_rop; |
264 | a5082316 | bellard | #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */ |
265 | e6e5ad80 | bellard | uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE]; |
266 | e6e5ad80 | bellard | uint8_t *cirrus_srcptr; |
267 | e6e5ad80 | bellard | uint8_t *cirrus_srcptr_end; |
268 | e6e5ad80 | bellard | uint32_t cirrus_srccounter; |
269 | a5082316 | bellard | /* hwcursor display state */
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270 | a5082316 | bellard | int last_hw_cursor_size;
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271 | a5082316 | bellard | int last_hw_cursor_x;
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272 | a5082316 | bellard | int last_hw_cursor_y;
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273 | a5082316 | bellard | int last_hw_cursor_y_start;
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274 | a5082316 | bellard | int last_hw_cursor_y_end;
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275 | 78e127ef | bellard | int real_vram_size; /* XXX: suppress that */ |
276 | 4abc796d | blueswir1 | int device_id;
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277 | 4abc796d | blueswir1 | int bustype;
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278 | e6e5ad80 | bellard | } CirrusVGAState; |
279 | e6e5ad80 | bellard | |
280 | e6e5ad80 | bellard | typedef struct PCICirrusVGAState { |
281 | e6e5ad80 | bellard | PCIDevice dev; |
282 | e6e5ad80 | bellard | CirrusVGAState cirrus_vga; |
283 | e6e5ad80 | bellard | } PCICirrusVGAState; |
284 | e6e5ad80 | bellard | |
285 | a5082316 | bellard | static uint8_t rop_to_index[256]; |
286 | 3b46e624 | ths | |
287 | e6e5ad80 | bellard | /***************************************
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288 | e6e5ad80 | bellard | *
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289 | e6e5ad80 | bellard | * prototypes.
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290 | e6e5ad80 | bellard | *
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291 | e6e5ad80 | bellard | ***************************************/
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292 | e6e5ad80 | bellard | |
293 | e6e5ad80 | bellard | |
294 | 8926b517 | bellard | static void cirrus_bitblt_reset(CirrusVGAState *s); |
295 | 8926b517 | bellard | static void cirrus_update_memory_access(CirrusVGAState *s); |
296 | e6e5ad80 | bellard | |
297 | e6e5ad80 | bellard | /***************************************
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298 | e6e5ad80 | bellard | *
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299 | e6e5ad80 | bellard | * raster operations
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300 | e6e5ad80 | bellard | *
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301 | e6e5ad80 | bellard | ***************************************/
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302 | e6e5ad80 | bellard | |
303 | a5082316 | bellard | static void cirrus_bitblt_rop_nop(CirrusVGAState *s, |
304 | a5082316 | bellard | uint8_t *dst,const uint8_t *src,
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305 | a5082316 | bellard | int dstpitch,int srcpitch, |
306 | a5082316 | bellard | int bltwidth,int bltheight) |
307 | a5082316 | bellard | { |
308 | e6e5ad80 | bellard | } |
309 | e6e5ad80 | bellard | |
310 | a5082316 | bellard | static void cirrus_bitblt_fill_nop(CirrusVGAState *s, |
311 | a5082316 | bellard | uint8_t *dst, |
312 | a5082316 | bellard | int dstpitch, int bltwidth,int bltheight) |
313 | e6e5ad80 | bellard | { |
314 | a5082316 | bellard | } |
315 | e6e5ad80 | bellard | |
316 | a5082316 | bellard | #define ROP_NAME 0 |
317 | a5082316 | bellard | #define ROP_OP(d, s) d = 0 |
318 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
319 | e6e5ad80 | bellard | |
320 | a5082316 | bellard | #define ROP_NAME src_and_dst
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321 | a5082316 | bellard | #define ROP_OP(d, s) d = (s) & (d)
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322 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
323 | e6e5ad80 | bellard | |
324 | a5082316 | bellard | #define ROP_NAME src_and_notdst
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325 | a5082316 | bellard | #define ROP_OP(d, s) d = (s) & (~(d))
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326 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
327 | e6e5ad80 | bellard | |
328 | a5082316 | bellard | #define ROP_NAME notdst
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329 | a5082316 | bellard | #define ROP_OP(d, s) d = ~(d)
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330 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
331 | e6e5ad80 | bellard | |
332 | a5082316 | bellard | #define ROP_NAME src
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333 | a5082316 | bellard | #define ROP_OP(d, s) d = s
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334 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
335 | e6e5ad80 | bellard | |
336 | a5082316 | bellard | #define ROP_NAME 1 |
337 | 4c8732d7 | bellard | #define ROP_OP(d, s) d = ~0 |
338 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
339 | a5082316 | bellard | |
340 | a5082316 | bellard | #define ROP_NAME notsrc_and_dst
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341 | a5082316 | bellard | #define ROP_OP(d, s) d = (~(s)) & (d)
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342 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
343 | a5082316 | bellard | |
344 | a5082316 | bellard | #define ROP_NAME src_xor_dst
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345 | a5082316 | bellard | #define ROP_OP(d, s) d = (s) ^ (d)
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346 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
347 | a5082316 | bellard | |
348 | a5082316 | bellard | #define ROP_NAME src_or_dst
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349 | a5082316 | bellard | #define ROP_OP(d, s) d = (s) | (d)
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350 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
351 | a5082316 | bellard | |
352 | a5082316 | bellard | #define ROP_NAME notsrc_or_notdst
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353 | a5082316 | bellard | #define ROP_OP(d, s) d = (~(s)) | (~(d))
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354 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
355 | a5082316 | bellard | |
356 | a5082316 | bellard | #define ROP_NAME src_notxor_dst
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357 | a5082316 | bellard | #define ROP_OP(d, s) d = ~((s) ^ (d))
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358 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
359 | e6e5ad80 | bellard | |
360 | a5082316 | bellard | #define ROP_NAME src_or_notdst
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361 | a5082316 | bellard | #define ROP_OP(d, s) d = (s) | (~(d))
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362 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
363 | a5082316 | bellard | |
364 | a5082316 | bellard | #define ROP_NAME notsrc
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365 | a5082316 | bellard | #define ROP_OP(d, s) d = (~(s))
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366 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
367 | a5082316 | bellard | |
368 | a5082316 | bellard | #define ROP_NAME notsrc_or_dst
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369 | a5082316 | bellard | #define ROP_OP(d, s) d = (~(s)) | (d)
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370 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
371 | a5082316 | bellard | |
372 | a5082316 | bellard | #define ROP_NAME notsrc_and_notdst
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373 | a5082316 | bellard | #define ROP_OP(d, s) d = (~(s)) & (~(d))
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374 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
375 | a5082316 | bellard | |
376 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = { |
377 | a5082316 | bellard | cirrus_bitblt_rop_fwd_0, |
378 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_and_dst, |
379 | a5082316 | bellard | cirrus_bitblt_rop_nop, |
380 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_and_notdst, |
381 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notdst, |
382 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src, |
383 | a5082316 | bellard | cirrus_bitblt_rop_fwd_1, |
384 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_and_dst, |
385 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_xor_dst, |
386 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_or_dst, |
387 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_or_notdst, |
388 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_notxor_dst, |
389 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_or_notdst, |
390 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc, |
391 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_or_dst, |
392 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_and_notdst, |
393 | a5082316 | bellard | }; |
394 | a5082316 | bellard | |
395 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = { |
396 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_0, |
397 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_and_dst, |
398 | a5082316 | bellard | cirrus_bitblt_rop_nop, |
399 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_and_notdst, |
400 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notdst, |
401 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src, |
402 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_1, |
403 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_and_dst, |
404 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_xor_dst, |
405 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_or_dst, |
406 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_or_notdst, |
407 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_notxor_dst, |
408 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_or_notdst, |
409 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc, |
410 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_or_dst, |
411 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_and_notdst, |
412 | a5082316 | bellard | }; |
413 | 96cf2df8 | ths | |
414 | 96cf2df8 | ths | #define TRANSP_ROP(name) {\
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415 | 96cf2df8 | ths | name ## _8,\ |
416 | 96cf2df8 | ths | name ## _16,\ |
417 | 96cf2df8 | ths | } |
418 | 96cf2df8 | ths | #define TRANSP_NOP(func) {\
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419 | 96cf2df8 | ths | func,\ |
420 | 96cf2df8 | ths | func,\ |
421 | 96cf2df8 | ths | } |
422 | 96cf2df8 | ths | |
423 | 96cf2df8 | ths | static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = { |
424 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0), |
425 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst), |
426 | 96cf2df8 | ths | TRANSP_NOP(cirrus_bitblt_rop_nop), |
427 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst), |
428 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst), |
429 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src), |
430 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1), |
431 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst), |
432 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst), |
433 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst), |
434 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst), |
435 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst), |
436 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst), |
437 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc), |
438 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst), |
439 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst), |
440 | 96cf2df8 | ths | }; |
441 | 96cf2df8 | ths | |
442 | 96cf2df8 | ths | static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = { |
443 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0), |
444 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst), |
445 | 96cf2df8 | ths | TRANSP_NOP(cirrus_bitblt_rop_nop), |
446 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst), |
447 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst), |
448 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src), |
449 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1), |
450 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst), |
451 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst), |
452 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst), |
453 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst), |
454 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst), |
455 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst), |
456 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc), |
457 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst), |
458 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst), |
459 | 96cf2df8 | ths | }; |
460 | 96cf2df8 | ths | |
461 | a5082316 | bellard | #define ROP2(name) {\
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462 | a5082316 | bellard | name ## _8,\ |
463 | a5082316 | bellard | name ## _16,\ |
464 | a5082316 | bellard | name ## _24,\ |
465 | a5082316 | bellard | name ## _32,\ |
466 | a5082316 | bellard | } |
467 | a5082316 | bellard | |
468 | a5082316 | bellard | #define ROP_NOP2(func) {\
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469 | a5082316 | bellard | func,\ |
470 | a5082316 | bellard | func,\ |
471 | a5082316 | bellard | func,\ |
472 | a5082316 | bellard | func,\ |
473 | a5082316 | bellard | } |
474 | a5082316 | bellard | |
475 | e69390ce | bellard | static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = { |
476 | e69390ce | bellard | ROP2(cirrus_patternfill_0), |
477 | e69390ce | bellard | ROP2(cirrus_patternfill_src_and_dst), |
478 | e69390ce | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
479 | e69390ce | bellard | ROP2(cirrus_patternfill_src_and_notdst), |
480 | e69390ce | bellard | ROP2(cirrus_patternfill_notdst), |
481 | e69390ce | bellard | ROP2(cirrus_patternfill_src), |
482 | e69390ce | bellard | ROP2(cirrus_patternfill_1), |
483 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_and_dst), |
484 | e69390ce | bellard | ROP2(cirrus_patternfill_src_xor_dst), |
485 | e69390ce | bellard | ROP2(cirrus_patternfill_src_or_dst), |
486 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_or_notdst), |
487 | e69390ce | bellard | ROP2(cirrus_patternfill_src_notxor_dst), |
488 | e69390ce | bellard | ROP2(cirrus_patternfill_src_or_notdst), |
489 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc), |
490 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_or_dst), |
491 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_and_notdst), |
492 | e69390ce | bellard | }; |
493 | e69390ce | bellard | |
494 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = { |
495 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_0), |
496 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_and_dst), |
497 | a5082316 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
498 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_and_notdst), |
499 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notdst), |
500 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src), |
501 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_1), |
502 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_and_dst), |
503 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_xor_dst), |
504 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_or_dst), |
505 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_or_notdst), |
506 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_notxor_dst), |
507 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_or_notdst), |
508 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc), |
509 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_or_dst), |
510 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_and_notdst), |
511 | a5082316 | bellard | }; |
512 | a5082316 | bellard | |
513 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = { |
514 | a5082316 | bellard | ROP2(cirrus_colorexpand_0), |
515 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_and_dst), |
516 | a5082316 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
517 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_and_notdst), |
518 | a5082316 | bellard | ROP2(cirrus_colorexpand_notdst), |
519 | a5082316 | bellard | ROP2(cirrus_colorexpand_src), |
520 | a5082316 | bellard | ROP2(cirrus_colorexpand_1), |
521 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_and_dst), |
522 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_xor_dst), |
523 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_or_dst), |
524 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_or_notdst), |
525 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_notxor_dst), |
526 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_or_notdst), |
527 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc), |
528 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_or_dst), |
529 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_and_notdst), |
530 | a5082316 | bellard | }; |
531 | a5082316 | bellard | |
532 | b30d4608 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = { |
533 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_0), |
534 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_and_dst), |
535 | b30d4608 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
536 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst), |
537 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notdst), |
538 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src), |
539 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_1), |
540 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst), |
541 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst), |
542 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_or_dst), |
543 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst), |
544 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst), |
545 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst), |
546 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc), |
547 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst), |
548 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst), |
549 | b30d4608 | bellard | }; |
550 | b30d4608 | bellard | |
551 | b30d4608 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = { |
552 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_0), |
553 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_and_dst), |
554 | b30d4608 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
555 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_and_notdst), |
556 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notdst), |
557 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src), |
558 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_1), |
559 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_and_dst), |
560 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_xor_dst), |
561 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_or_dst), |
562 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst), |
563 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_notxor_dst), |
564 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_or_notdst), |
565 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc), |
566 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_or_dst), |
567 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst), |
568 | b30d4608 | bellard | }; |
569 | b30d4608 | bellard | |
570 | a5082316 | bellard | static const cirrus_fill_t cirrus_fill[16][4] = { |
571 | a5082316 | bellard | ROP2(cirrus_fill_0), |
572 | a5082316 | bellard | ROP2(cirrus_fill_src_and_dst), |
573 | a5082316 | bellard | ROP_NOP2(cirrus_bitblt_fill_nop), |
574 | a5082316 | bellard | ROP2(cirrus_fill_src_and_notdst), |
575 | a5082316 | bellard | ROP2(cirrus_fill_notdst), |
576 | a5082316 | bellard | ROP2(cirrus_fill_src), |
577 | a5082316 | bellard | ROP2(cirrus_fill_1), |
578 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_and_dst), |
579 | a5082316 | bellard | ROP2(cirrus_fill_src_xor_dst), |
580 | a5082316 | bellard | ROP2(cirrus_fill_src_or_dst), |
581 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_or_notdst), |
582 | a5082316 | bellard | ROP2(cirrus_fill_src_notxor_dst), |
583 | a5082316 | bellard | ROP2(cirrus_fill_src_or_notdst), |
584 | a5082316 | bellard | ROP2(cirrus_fill_notsrc), |
585 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_or_dst), |
586 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_and_notdst), |
587 | a5082316 | bellard | }; |
588 | a5082316 | bellard | |
589 | a5082316 | bellard | static inline void cirrus_bitblt_fgcol(CirrusVGAState *s) |
590 | e6e5ad80 | bellard | { |
591 | a5082316 | bellard | unsigned int color; |
592 | a5082316 | bellard | switch (s->cirrus_blt_pixelwidth) {
|
593 | a5082316 | bellard | case 1: |
594 | a5082316 | bellard | s->cirrus_blt_fgcol = s->cirrus_shadow_gr1; |
595 | a5082316 | bellard | break;
|
596 | a5082316 | bellard | case 2: |
597 | 4e12cd94 | Avi Kivity | color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8); |
598 | a5082316 | bellard | s->cirrus_blt_fgcol = le16_to_cpu(color); |
599 | a5082316 | bellard | break;
|
600 | a5082316 | bellard | case 3: |
601 | 5fafdf24 | ths | s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 | |
602 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16); |
603 | a5082316 | bellard | break;
|
604 | a5082316 | bellard | default:
|
605 | a5082316 | bellard | case 4: |
606 | 4e12cd94 | Avi Kivity | color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) | |
607 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24); |
608 | a5082316 | bellard | s->cirrus_blt_fgcol = le32_to_cpu(color); |
609 | a5082316 | bellard | break;
|
610 | e6e5ad80 | bellard | } |
611 | e6e5ad80 | bellard | } |
612 | e6e5ad80 | bellard | |
613 | a5082316 | bellard | static inline void cirrus_bitblt_bgcol(CirrusVGAState *s) |
614 | e6e5ad80 | bellard | { |
615 | a5082316 | bellard | unsigned int color; |
616 | e6e5ad80 | bellard | switch (s->cirrus_blt_pixelwidth) {
|
617 | e6e5ad80 | bellard | case 1: |
618 | a5082316 | bellard | s->cirrus_blt_bgcol = s->cirrus_shadow_gr0; |
619 | a5082316 | bellard | break;
|
620 | e6e5ad80 | bellard | case 2: |
621 | 4e12cd94 | Avi Kivity | color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8); |
622 | a5082316 | bellard | s->cirrus_blt_bgcol = le16_to_cpu(color); |
623 | a5082316 | bellard | break;
|
624 | e6e5ad80 | bellard | case 3: |
625 | 5fafdf24 | ths | s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 | |
626 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16); |
627 | a5082316 | bellard | break;
|
628 | e6e5ad80 | bellard | default:
|
629 | a5082316 | bellard | case 4: |
630 | 4e12cd94 | Avi Kivity | color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) | |
631 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24); |
632 | a5082316 | bellard | s->cirrus_blt_bgcol = le32_to_cpu(color); |
633 | a5082316 | bellard | break;
|
634 | e6e5ad80 | bellard | } |
635 | e6e5ad80 | bellard | } |
636 | e6e5ad80 | bellard | |
637 | e6e5ad80 | bellard | static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin, |
638 | e6e5ad80 | bellard | int off_pitch, int bytesperline, |
639 | e6e5ad80 | bellard | int lines)
|
640 | e6e5ad80 | bellard | { |
641 | e6e5ad80 | bellard | int y;
|
642 | e6e5ad80 | bellard | int off_cur;
|
643 | e6e5ad80 | bellard | int off_cur_end;
|
644 | e6e5ad80 | bellard | |
645 | e6e5ad80 | bellard | for (y = 0; y < lines; y++) { |
646 | e6e5ad80 | bellard | off_cur = off_begin; |
647 | b2eb849d | aurel32 | off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask; |
648 | e6e5ad80 | bellard | off_cur &= TARGET_PAGE_MASK; |
649 | e6e5ad80 | bellard | while (off_cur < off_cur_end) {
|
650 | 4e12cd94 | Avi Kivity | cpu_physical_memory_set_dirty(s->vga.vram_offset + off_cur); |
651 | e6e5ad80 | bellard | off_cur += TARGET_PAGE_SIZE; |
652 | e6e5ad80 | bellard | } |
653 | e6e5ad80 | bellard | off_begin += off_pitch; |
654 | e6e5ad80 | bellard | } |
655 | e6e5ad80 | bellard | } |
656 | e6e5ad80 | bellard | |
657 | e6e5ad80 | bellard | static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s, |
658 | e6e5ad80 | bellard | const uint8_t * src)
|
659 | e6e5ad80 | bellard | { |
660 | e6e5ad80 | bellard | uint8_t *dst; |
661 | e6e5ad80 | bellard | |
662 | 4e12cd94 | Avi Kivity | dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask); |
663 | b2eb849d | aurel32 | |
664 | b2eb849d | aurel32 | if (BLTUNSAFE(s))
|
665 | b2eb849d | aurel32 | return 0; |
666 | b2eb849d | aurel32 | |
667 | e69390ce | bellard | (*s->cirrus_rop) (s, dst, src, |
668 | 5fafdf24 | ths | s->cirrus_blt_dstpitch, 0,
|
669 | e69390ce | bellard | s->cirrus_blt_width, s->cirrus_blt_height); |
670 | e6e5ad80 | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
671 | e69390ce | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
672 | e69390ce | bellard | s->cirrus_blt_height); |
673 | e6e5ad80 | bellard | return 1; |
674 | e6e5ad80 | bellard | } |
675 | e6e5ad80 | bellard | |
676 | a21ae81d | bellard | /* fill */
|
677 | a21ae81d | bellard | |
678 | a5082316 | bellard | static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop) |
679 | a21ae81d | bellard | { |
680 | a5082316 | bellard | cirrus_fill_t rop_func; |
681 | a21ae81d | bellard | |
682 | b2eb849d | aurel32 | if (BLTUNSAFE(s))
|
683 | b2eb849d | aurel32 | return 0; |
684 | a5082316 | bellard | rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
685 | 4e12cd94 | Avi Kivity | rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
686 | a5082316 | bellard | s->cirrus_blt_dstpitch, |
687 | a5082316 | bellard | s->cirrus_blt_width, s->cirrus_blt_height); |
688 | a21ae81d | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
689 | a21ae81d | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
690 | a21ae81d | bellard | s->cirrus_blt_height); |
691 | a21ae81d | bellard | cirrus_bitblt_reset(s); |
692 | a21ae81d | bellard | return 1; |
693 | a21ae81d | bellard | } |
694 | a21ae81d | bellard | |
695 | e6e5ad80 | bellard | /***************************************
|
696 | e6e5ad80 | bellard | *
|
697 | e6e5ad80 | bellard | * bitblt (video-to-video)
|
698 | e6e5ad80 | bellard | *
|
699 | e6e5ad80 | bellard | ***************************************/
|
700 | e6e5ad80 | bellard | |
701 | e6e5ad80 | bellard | static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s) |
702 | e6e5ad80 | bellard | { |
703 | e6e5ad80 | bellard | return cirrus_bitblt_common_patterncopy(s,
|
704 | 4e12cd94 | Avi Kivity | s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
|
705 | b2eb849d | aurel32 | s->cirrus_addr_mask)); |
706 | e6e5ad80 | bellard | } |
707 | e6e5ad80 | bellard | |
708 | 24236869 | bellard | static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h) |
709 | e6e5ad80 | bellard | { |
710 | 24236869 | bellard | int sx, sy;
|
711 | 24236869 | bellard | int dx, dy;
|
712 | 24236869 | bellard | int width, height;
|
713 | 24236869 | bellard | int depth;
|
714 | 24236869 | bellard | int notify = 0; |
715 | 24236869 | bellard | |
716 | 4e12cd94 | Avi Kivity | depth = s->vga.get_bpp(&s->vga) / 8;
|
717 | 4e12cd94 | Avi Kivity | s->vga.get_resolution(&s->vga, &width, &height); |
718 | 24236869 | bellard | |
719 | 24236869 | bellard | /* extra x, y */
|
720 | d85d0d38 | aliguori | sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth; |
721 | d85d0d38 | aliguori | sy = (src / ABS(s->cirrus_blt_srcpitch)); |
722 | d85d0d38 | aliguori | dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth; |
723 | d85d0d38 | aliguori | dy = (dst / ABS(s->cirrus_blt_dstpitch)); |
724 | 24236869 | bellard | |
725 | 24236869 | bellard | /* normalize width */
|
726 | 24236869 | bellard | w /= depth; |
727 | 24236869 | bellard | |
728 | 24236869 | bellard | /* if we're doing a backward copy, we have to adjust
|
729 | 24236869 | bellard | our x/y to be the upper left corner (instead of the lower
|
730 | 24236869 | bellard | right corner) */
|
731 | 24236869 | bellard | if (s->cirrus_blt_dstpitch < 0) { |
732 | 24236869 | bellard | sx -= (s->cirrus_blt_width / depth) - 1;
|
733 | 24236869 | bellard | dx -= (s->cirrus_blt_width / depth) - 1;
|
734 | 24236869 | bellard | sy -= s->cirrus_blt_height - 1;
|
735 | 24236869 | bellard | dy -= s->cirrus_blt_height - 1;
|
736 | 24236869 | bellard | } |
737 | 24236869 | bellard | |
738 | 24236869 | bellard | /* are we in the visible portion of memory? */
|
739 | 24236869 | bellard | if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 && |
740 | 24236869 | bellard | (sx + w) <= width && (sy + h) <= height && |
741 | 24236869 | bellard | (dx + w) <= width && (dy + h) <= height) { |
742 | 24236869 | bellard | notify = 1;
|
743 | 24236869 | bellard | } |
744 | 24236869 | bellard | |
745 | 24236869 | bellard | /* make to sure only copy if it's a plain copy ROP */
|
746 | 24236869 | bellard | if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
|
747 | 24236869 | bellard | *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src) |
748 | 24236869 | bellard | notify = 0;
|
749 | 24236869 | bellard | |
750 | 24236869 | bellard | /* we have to flush all pending changes so that the copy
|
751 | 24236869 | bellard | is generated at the appropriate moment in time */
|
752 | 24236869 | bellard | if (notify)
|
753 | 24236869 | bellard | vga_hw_update(); |
754 | 24236869 | bellard | |
755 | 4e12cd94 | Avi Kivity | (*s->cirrus_rop) (s, s->vga.vram_ptr + |
756 | b2eb849d | aurel32 | (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
757 | 4e12cd94 | Avi Kivity | s->vga.vram_ptr + |
758 | b2eb849d | aurel32 | (s->cirrus_blt_srcaddr & s->cirrus_addr_mask), |
759 | e6e5ad80 | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch, |
760 | e6e5ad80 | bellard | s->cirrus_blt_width, s->cirrus_blt_height); |
761 | 24236869 | bellard | |
762 | 24236869 | bellard | if (notify)
|
763 | 4e12cd94 | Avi Kivity | qemu_console_copy(s->vga.ds, |
764 | 38334f76 | balrog | sx, sy, dx, dy, |
765 | 38334f76 | balrog | s->cirrus_blt_width / depth, |
766 | 38334f76 | balrog | s->cirrus_blt_height); |
767 | 24236869 | bellard | |
768 | 24236869 | bellard | /* we don't have to notify the display that this portion has
|
769 | 38334f76 | balrog | changed since qemu_console_copy implies this */
|
770 | 24236869 | bellard | |
771 | 31c05501 | aliguori | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
772 | 31c05501 | aliguori | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
773 | 31c05501 | aliguori | s->cirrus_blt_height); |
774 | 24236869 | bellard | } |
775 | 24236869 | bellard | |
776 | 24236869 | bellard | static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s) |
777 | 24236869 | bellard | { |
778 | 65d35a09 | aurel32 | if (BLTUNSAFE(s))
|
779 | 65d35a09 | aurel32 | return 0; |
780 | 65d35a09 | aurel32 | |
781 | 4e12cd94 | Avi Kivity | cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr, |
782 | 4e12cd94 | Avi Kivity | s->cirrus_blt_srcaddr - s->vga.start_addr, |
783 | 7d957bd8 | aliguori | s->cirrus_blt_width, s->cirrus_blt_height); |
784 | 24236869 | bellard | |
785 | e6e5ad80 | bellard | return 1; |
786 | e6e5ad80 | bellard | } |
787 | e6e5ad80 | bellard | |
788 | e6e5ad80 | bellard | /***************************************
|
789 | e6e5ad80 | bellard | *
|
790 | e6e5ad80 | bellard | * bitblt (cpu-to-video)
|
791 | e6e5ad80 | bellard | *
|
792 | e6e5ad80 | bellard | ***************************************/
|
793 | e6e5ad80 | bellard | |
794 | e6e5ad80 | bellard | static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s) |
795 | e6e5ad80 | bellard | { |
796 | e6e5ad80 | bellard | int copy_count;
|
797 | a5082316 | bellard | uint8_t *end_ptr; |
798 | 3b46e624 | ths | |
799 | e6e5ad80 | bellard | if (s->cirrus_srccounter > 0) { |
800 | a5082316 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
801 | a5082316 | bellard | cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf); |
802 | a5082316 | bellard | the_end:
|
803 | a5082316 | bellard | s->cirrus_srccounter = 0;
|
804 | a5082316 | bellard | cirrus_bitblt_reset(s); |
805 | a5082316 | bellard | } else {
|
806 | a5082316 | bellard | /* at least one scan line */
|
807 | a5082316 | bellard | do {
|
808 | 4e12cd94 | Avi Kivity | (*s->cirrus_rop)(s, s->vga.vram_ptr + |
809 | b2eb849d | aurel32 | (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
810 | b2eb849d | aurel32 | s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1); |
811 | a5082316 | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
|
812 | a5082316 | bellard | s->cirrus_blt_width, 1);
|
813 | a5082316 | bellard | s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch; |
814 | a5082316 | bellard | s->cirrus_srccounter -= s->cirrus_blt_srcpitch; |
815 | a5082316 | bellard | if (s->cirrus_srccounter <= 0) |
816 | a5082316 | bellard | goto the_end;
|
817 | a5082316 | bellard | /* more bytes than needed can be transfered because of
|
818 | a5082316 | bellard | word alignment, so we keep them for the next line */
|
819 | a5082316 | bellard | /* XXX: keep alignment to speed up transfer */
|
820 | a5082316 | bellard | end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
821 | a5082316 | bellard | copy_count = s->cirrus_srcptr_end - end_ptr; |
822 | a5082316 | bellard | memmove(s->cirrus_bltbuf, end_ptr, copy_count); |
823 | a5082316 | bellard | s->cirrus_srcptr = s->cirrus_bltbuf + copy_count; |
824 | a5082316 | bellard | s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
825 | a5082316 | bellard | } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
|
826 | a5082316 | bellard | } |
827 | e6e5ad80 | bellard | } |
828 | e6e5ad80 | bellard | } |
829 | e6e5ad80 | bellard | |
830 | e6e5ad80 | bellard | /***************************************
|
831 | e6e5ad80 | bellard | *
|
832 | e6e5ad80 | bellard | * bitblt wrapper
|
833 | e6e5ad80 | bellard | *
|
834 | e6e5ad80 | bellard | ***************************************/
|
835 | e6e5ad80 | bellard | |
836 | e6e5ad80 | bellard | static void cirrus_bitblt_reset(CirrusVGAState * s) |
837 | e6e5ad80 | bellard | { |
838 | f8b237af | aliguori | int need_update;
|
839 | f8b237af | aliguori | |
840 | 4e12cd94 | Avi Kivity | s->vga.gr[0x31] &=
|
841 | e6e5ad80 | bellard | ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED); |
842 | f8b237af | aliguori | need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
|
843 | f8b237af | aliguori | || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
|
844 | e6e5ad80 | bellard | s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
845 | e6e5ad80 | bellard | s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
|
846 | e6e5ad80 | bellard | s->cirrus_srccounter = 0;
|
847 | f8b237af | aliguori | if (!need_update)
|
848 | f8b237af | aliguori | return;
|
849 | 8926b517 | bellard | cirrus_update_memory_access(s); |
850 | e6e5ad80 | bellard | } |
851 | e6e5ad80 | bellard | |
852 | e6e5ad80 | bellard | static int cirrus_bitblt_cputovideo(CirrusVGAState * s) |
853 | e6e5ad80 | bellard | { |
854 | a5082316 | bellard | int w;
|
855 | a5082316 | bellard | |
856 | e6e5ad80 | bellard | s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC; |
857 | e6e5ad80 | bellard | s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
858 | e6e5ad80 | bellard | s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
|
859 | e6e5ad80 | bellard | |
860 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
861 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
862 | a5082316 | bellard | s->cirrus_blt_srcpitch = 8;
|
863 | e6e5ad80 | bellard | } else {
|
864 | b30d4608 | bellard | /* XXX: check for 24 bpp */
|
865 | a5082316 | bellard | s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth; |
866 | e6e5ad80 | bellard | } |
867 | a5082316 | bellard | s->cirrus_srccounter = s->cirrus_blt_srcpitch; |
868 | e6e5ad80 | bellard | } else {
|
869 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
870 | a5082316 | bellard | w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth; |
871 | 5fafdf24 | ths | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
|
872 | a5082316 | bellard | s->cirrus_blt_srcpitch = ((w + 31) >> 5); |
873 | a5082316 | bellard | else
|
874 | a5082316 | bellard | s->cirrus_blt_srcpitch = ((w + 7) >> 3); |
875 | e6e5ad80 | bellard | } else {
|
876 | c9c0eae8 | bellard | /* always align input size to 32 bits */
|
877 | c9c0eae8 | bellard | s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3; |
878 | e6e5ad80 | bellard | } |
879 | a5082316 | bellard | s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height; |
880 | e6e5ad80 | bellard | } |
881 | a5082316 | bellard | s->cirrus_srcptr = s->cirrus_bltbuf; |
882 | a5082316 | bellard | s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
883 | 8926b517 | bellard | cirrus_update_memory_access(s); |
884 | e6e5ad80 | bellard | return 1; |
885 | e6e5ad80 | bellard | } |
886 | e6e5ad80 | bellard | |
887 | e6e5ad80 | bellard | static int cirrus_bitblt_videotocpu(CirrusVGAState * s) |
888 | e6e5ad80 | bellard | { |
889 | e6e5ad80 | bellard | /* XXX */
|
890 | a5082316 | bellard | #ifdef DEBUG_BITBLT
|
891 | e6e5ad80 | bellard | printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
|
892 | e6e5ad80 | bellard | #endif
|
893 | e6e5ad80 | bellard | return 0; |
894 | e6e5ad80 | bellard | } |
895 | e6e5ad80 | bellard | |
896 | e6e5ad80 | bellard | static int cirrus_bitblt_videotovideo(CirrusVGAState * s) |
897 | e6e5ad80 | bellard | { |
898 | e6e5ad80 | bellard | int ret;
|
899 | e6e5ad80 | bellard | |
900 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
901 | e6e5ad80 | bellard | ret = cirrus_bitblt_videotovideo_patterncopy(s); |
902 | e6e5ad80 | bellard | } else {
|
903 | e6e5ad80 | bellard | ret = cirrus_bitblt_videotovideo_copy(s); |
904 | e6e5ad80 | bellard | } |
905 | e6e5ad80 | bellard | if (ret)
|
906 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
907 | e6e5ad80 | bellard | return ret;
|
908 | e6e5ad80 | bellard | } |
909 | e6e5ad80 | bellard | |
910 | e6e5ad80 | bellard | static void cirrus_bitblt_start(CirrusVGAState * s) |
911 | e6e5ad80 | bellard | { |
912 | e6e5ad80 | bellard | uint8_t blt_rop; |
913 | e6e5ad80 | bellard | |
914 | 4e12cd94 | Avi Kivity | s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
|
915 | a5082316 | bellard | |
916 | 4e12cd94 | Avi Kivity | s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1; |
917 | 4e12cd94 | Avi Kivity | s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1; |
918 | 4e12cd94 | Avi Kivity | s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8)); |
919 | 4e12cd94 | Avi Kivity | s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8)); |
920 | e6e5ad80 | bellard | s->cirrus_blt_dstaddr = |
921 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16)); |
922 | e6e5ad80 | bellard | s->cirrus_blt_srcaddr = |
923 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16)); |
924 | 4e12cd94 | Avi Kivity | s->cirrus_blt_mode = s->vga.gr[0x30];
|
925 | 4e12cd94 | Avi Kivity | s->cirrus_blt_modeext = s->vga.gr[0x33];
|
926 | 4e12cd94 | Avi Kivity | blt_rop = s->vga.gr[0x32];
|
927 | e6e5ad80 | bellard | |
928 | a21ae81d | bellard | #ifdef DEBUG_BITBLT
|
929 | 0b74ed78 | bellard | printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
|
930 | 5fafdf24 | ths | blt_rop, |
931 | a21ae81d | bellard | s->cirrus_blt_mode, |
932 | a5082316 | bellard | s->cirrus_blt_modeext, |
933 | a21ae81d | bellard | s->cirrus_blt_width, |
934 | a21ae81d | bellard | s->cirrus_blt_height, |
935 | a21ae81d | bellard | s->cirrus_blt_dstpitch, |
936 | a21ae81d | bellard | s->cirrus_blt_srcpitch, |
937 | a21ae81d | bellard | s->cirrus_blt_dstaddr, |
938 | a5082316 | bellard | s->cirrus_blt_srcaddr, |
939 | 4e12cd94 | Avi Kivity | s->vga.gr[0x2f]);
|
940 | a21ae81d | bellard | #endif
|
941 | a21ae81d | bellard | |
942 | e6e5ad80 | bellard | switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
|
943 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH8:
|
944 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 1;
|
945 | e6e5ad80 | bellard | break;
|
946 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH16:
|
947 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 2;
|
948 | e6e5ad80 | bellard | break;
|
949 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH24:
|
950 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 3;
|
951 | e6e5ad80 | bellard | break;
|
952 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH32:
|
953 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 4;
|
954 | e6e5ad80 | bellard | break;
|
955 | e6e5ad80 | bellard | default:
|
956 | a5082316 | bellard | #ifdef DEBUG_BITBLT
|
957 | e6e5ad80 | bellard | printf("cirrus: bitblt - pixel width is unknown\n");
|
958 | e6e5ad80 | bellard | #endif
|
959 | e6e5ad80 | bellard | goto bitblt_ignore;
|
960 | e6e5ad80 | bellard | } |
961 | e6e5ad80 | bellard | s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK; |
962 | e6e5ad80 | bellard | |
963 | e6e5ad80 | bellard | if ((s->
|
964 | e6e5ad80 | bellard | cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC | |
965 | e6e5ad80 | bellard | CIRRUS_BLTMODE_MEMSYSDEST)) |
966 | e6e5ad80 | bellard | == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) { |
967 | a5082316 | bellard | #ifdef DEBUG_BITBLT
|
968 | e6e5ad80 | bellard | printf("cirrus: bitblt - memory-to-memory copy is requested\n");
|
969 | e6e5ad80 | bellard | #endif
|
970 | e6e5ad80 | bellard | goto bitblt_ignore;
|
971 | e6e5ad80 | bellard | } |
972 | e6e5ad80 | bellard | |
973 | a5082316 | bellard | if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
|
974 | 5fafdf24 | ths | (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST | |
975 | a21ae81d | bellard | CIRRUS_BLTMODE_TRANSPARENTCOMP | |
976 | 5fafdf24 | ths | CIRRUS_BLTMODE_PATTERNCOPY | |
977 | 5fafdf24 | ths | CIRRUS_BLTMODE_COLOREXPAND)) == |
978 | a21ae81d | bellard | (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) { |
979 | a5082316 | bellard | cirrus_bitblt_fgcol(s); |
980 | a5082316 | bellard | cirrus_bitblt_solidfill(s, blt_rop); |
981 | e6e5ad80 | bellard | } else {
|
982 | 5fafdf24 | ths | if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
|
983 | 5fafdf24 | ths | CIRRUS_BLTMODE_PATTERNCOPY)) == |
984 | a5082316 | bellard | CIRRUS_BLTMODE_COLOREXPAND) { |
985 | a5082316 | bellard | |
986 | a5082316 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
|
987 | b30d4608 | bellard | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
|
988 | 4c8732d7 | bellard | cirrus_bitblt_bgcol(s); |
989 | b30d4608 | bellard | else
|
990 | 4c8732d7 | bellard | cirrus_bitblt_fgcol(s); |
991 | b30d4608 | bellard | s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
992 | a5082316 | bellard | } else {
|
993 | a5082316 | bellard | cirrus_bitblt_fgcol(s); |
994 | a5082316 | bellard | cirrus_bitblt_bgcol(s); |
995 | a5082316 | bellard | s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
996 | a5082316 | bellard | } |
997 | e69390ce | bellard | } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { |
998 | b30d4608 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
999 | b30d4608 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
|
1000 | b30d4608 | bellard | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
|
1001 | b30d4608 | bellard | cirrus_bitblt_bgcol(s); |
1002 | b30d4608 | bellard | else
|
1003 | b30d4608 | bellard | cirrus_bitblt_fgcol(s); |
1004 | b30d4608 | bellard | s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
1005 | b30d4608 | bellard | } else {
|
1006 | b30d4608 | bellard | cirrus_bitblt_fgcol(s); |
1007 | b30d4608 | bellard | cirrus_bitblt_bgcol(s); |
1008 | b30d4608 | bellard | s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
1009 | b30d4608 | bellard | } |
1010 | b30d4608 | bellard | } else {
|
1011 | b30d4608 | bellard | s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
1012 | b30d4608 | bellard | } |
1013 | a21ae81d | bellard | } else {
|
1014 | 96cf2df8 | ths | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
|
1015 | 96cf2df8 | ths | if (s->cirrus_blt_pixelwidth > 2) { |
1016 | 96cf2df8 | ths | printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
|
1017 | 96cf2df8 | ths | goto bitblt_ignore;
|
1018 | 96cf2df8 | ths | } |
1019 | 96cf2df8 | ths | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
|
1020 | 96cf2df8 | ths | s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; |
1021 | 96cf2df8 | ths | s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; |
1022 | 96cf2df8 | ths | s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
1023 | 96cf2df8 | ths | } else {
|
1024 | 96cf2df8 | ths | s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
1025 | 96cf2df8 | ths | } |
1026 | 96cf2df8 | ths | } else {
|
1027 | 96cf2df8 | ths | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
|
1028 | 96cf2df8 | ths | s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; |
1029 | 96cf2df8 | ths | s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; |
1030 | 96cf2df8 | ths | s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]]; |
1031 | 96cf2df8 | ths | } else {
|
1032 | 96cf2df8 | ths | s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]]; |
1033 | 96cf2df8 | ths | } |
1034 | 96cf2df8 | ths | } |
1035 | 96cf2df8 | ths | } |
1036 | a21ae81d | bellard | // setup bitblt engine.
|
1037 | a21ae81d | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
|
1038 | a21ae81d | bellard | if (!cirrus_bitblt_cputovideo(s))
|
1039 | a21ae81d | bellard | goto bitblt_ignore;
|
1040 | a21ae81d | bellard | } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) { |
1041 | a21ae81d | bellard | if (!cirrus_bitblt_videotocpu(s))
|
1042 | a21ae81d | bellard | goto bitblt_ignore;
|
1043 | a21ae81d | bellard | } else {
|
1044 | a21ae81d | bellard | if (!cirrus_bitblt_videotovideo(s))
|
1045 | a21ae81d | bellard | goto bitblt_ignore;
|
1046 | a21ae81d | bellard | } |
1047 | e6e5ad80 | bellard | } |
1048 | e6e5ad80 | bellard | return;
|
1049 | e6e5ad80 | bellard | bitblt_ignore:;
|
1050 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
1051 | e6e5ad80 | bellard | } |
1052 | e6e5ad80 | bellard | |
1053 | e6e5ad80 | bellard | static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value) |
1054 | e6e5ad80 | bellard | { |
1055 | e6e5ad80 | bellard | unsigned old_value;
|
1056 | e6e5ad80 | bellard | |
1057 | 4e12cd94 | Avi Kivity | old_value = s->vga.gr[0x31];
|
1058 | 4e12cd94 | Avi Kivity | s->vga.gr[0x31] = reg_value;
|
1059 | e6e5ad80 | bellard | |
1060 | e6e5ad80 | bellard | if (((old_value & CIRRUS_BLT_RESET) != 0) && |
1061 | e6e5ad80 | bellard | ((reg_value & CIRRUS_BLT_RESET) == 0)) {
|
1062 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
1063 | e6e5ad80 | bellard | } else if (((old_value & CIRRUS_BLT_START) == 0) && |
1064 | e6e5ad80 | bellard | ((reg_value & CIRRUS_BLT_START) != 0)) {
|
1065 | e6e5ad80 | bellard | cirrus_bitblt_start(s); |
1066 | e6e5ad80 | bellard | } |
1067 | e6e5ad80 | bellard | } |
1068 | e6e5ad80 | bellard | |
1069 | e6e5ad80 | bellard | |
1070 | e6e5ad80 | bellard | /***************************************
|
1071 | e6e5ad80 | bellard | *
|
1072 | e6e5ad80 | bellard | * basic parameters
|
1073 | e6e5ad80 | bellard | *
|
1074 | e6e5ad80 | bellard | ***************************************/
|
1075 | e6e5ad80 | bellard | |
1076 | a4a2f59c | Juan Quintela | static void cirrus_get_offsets(VGACommonState *s1, |
1077 | 83acc96b | bellard | uint32_t *pline_offset, |
1078 | 83acc96b | bellard | uint32_t *pstart_addr, |
1079 | 83acc96b | bellard | uint32_t *pline_compare) |
1080 | e6e5ad80 | bellard | { |
1081 | 4e12cd94 | Avi Kivity | CirrusVGAState * s = container_of(s1, CirrusVGAState, vga); |
1082 | 83acc96b | bellard | uint32_t start_addr, line_offset, line_compare; |
1083 | e6e5ad80 | bellard | |
1084 | 4e12cd94 | Avi Kivity | line_offset = s->vga.cr[0x13]
|
1085 | 4e12cd94 | Avi Kivity | | ((s->vga.cr[0x1b] & 0x10) << 4); |
1086 | e6e5ad80 | bellard | line_offset <<= 3;
|
1087 | e6e5ad80 | bellard | *pline_offset = line_offset; |
1088 | e6e5ad80 | bellard | |
1089 | 4e12cd94 | Avi Kivity | start_addr = (s->vga.cr[0x0c] << 8) |
1090 | 4e12cd94 | Avi Kivity | | s->vga.cr[0x0d]
|
1091 | 4e12cd94 | Avi Kivity | | ((s->vga.cr[0x1b] & 0x01) << 16) |
1092 | 4e12cd94 | Avi Kivity | | ((s->vga.cr[0x1b] & 0x0c) << 15) |
1093 | 4e12cd94 | Avi Kivity | | ((s->vga.cr[0x1d] & 0x80) << 12); |
1094 | e6e5ad80 | bellard | *pstart_addr = start_addr; |
1095 | 83acc96b | bellard | |
1096 | 4e12cd94 | Avi Kivity | line_compare = s->vga.cr[0x18] |
|
1097 | 4e12cd94 | Avi Kivity | ((s->vga.cr[0x07] & 0x10) << 4) | |
1098 | 4e12cd94 | Avi Kivity | ((s->vga.cr[0x09] & 0x40) << 3); |
1099 | 83acc96b | bellard | *pline_compare = line_compare; |
1100 | e6e5ad80 | bellard | } |
1101 | e6e5ad80 | bellard | |
1102 | e6e5ad80 | bellard | static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
|
1103 | e6e5ad80 | bellard | { |
1104 | e6e5ad80 | bellard | uint32_t ret = 16;
|
1105 | e6e5ad80 | bellard | |
1106 | e6e5ad80 | bellard | switch (s->cirrus_hidden_dac_data & 0xf) { |
1107 | e6e5ad80 | bellard | case 0: |
1108 | e6e5ad80 | bellard | ret = 15;
|
1109 | e6e5ad80 | bellard | break; /* Sierra HiColor */ |
1110 | e6e5ad80 | bellard | case 1: |
1111 | e6e5ad80 | bellard | ret = 16;
|
1112 | e6e5ad80 | bellard | break; /* XGA HiColor */ |
1113 | e6e5ad80 | bellard | default:
|
1114 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1115 | e6e5ad80 | bellard | printf("cirrus: invalid DAC value %x in 16bpp\n",
|
1116 | e6e5ad80 | bellard | (s->cirrus_hidden_dac_data & 0xf));
|
1117 | e6e5ad80 | bellard | #endif
|
1118 | e6e5ad80 | bellard | ret = 15; /* XXX */ |
1119 | e6e5ad80 | bellard | break;
|
1120 | e6e5ad80 | bellard | } |
1121 | e6e5ad80 | bellard | return ret;
|
1122 | e6e5ad80 | bellard | } |
1123 | e6e5ad80 | bellard | |
1124 | a4a2f59c | Juan Quintela | static int cirrus_get_bpp(VGACommonState *s1) |
1125 | e6e5ad80 | bellard | { |
1126 | 4e12cd94 | Avi Kivity | CirrusVGAState * s = container_of(s1, CirrusVGAState, vga); |
1127 | e6e5ad80 | bellard | uint32_t ret = 8;
|
1128 | e6e5ad80 | bellard | |
1129 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x07] & 0x01) != 0) { |
1130 | e6e5ad80 | bellard | /* Cirrus SVGA */
|
1131 | 4e12cd94 | Avi Kivity | switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) { |
1132 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_8:
|
1133 | e6e5ad80 | bellard | ret = 8;
|
1134 | e6e5ad80 | bellard | break;
|
1135 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
|
1136 | e6e5ad80 | bellard | ret = cirrus_get_bpp16_depth(s); |
1137 | e6e5ad80 | bellard | break;
|
1138 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_24:
|
1139 | e6e5ad80 | bellard | ret = 24;
|
1140 | e6e5ad80 | bellard | break;
|
1141 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_16:
|
1142 | e6e5ad80 | bellard | ret = cirrus_get_bpp16_depth(s); |
1143 | e6e5ad80 | bellard | break;
|
1144 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_32:
|
1145 | e6e5ad80 | bellard | ret = 32;
|
1146 | e6e5ad80 | bellard | break;
|
1147 | e6e5ad80 | bellard | default:
|
1148 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1149 | 4e12cd94 | Avi Kivity | printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]); |
1150 | e6e5ad80 | bellard | #endif
|
1151 | e6e5ad80 | bellard | ret = 8;
|
1152 | e6e5ad80 | bellard | break;
|
1153 | e6e5ad80 | bellard | } |
1154 | e6e5ad80 | bellard | } else {
|
1155 | e6e5ad80 | bellard | /* VGA */
|
1156 | aeb3c85f | bellard | ret = 0;
|
1157 | e6e5ad80 | bellard | } |
1158 | e6e5ad80 | bellard | |
1159 | e6e5ad80 | bellard | return ret;
|
1160 | e6e5ad80 | bellard | } |
1161 | e6e5ad80 | bellard | |
1162 | a4a2f59c | Juan Quintela | static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight) |
1163 | 78e127ef | bellard | { |
1164 | 78e127ef | bellard | int width, height;
|
1165 | 3b46e624 | ths | |
1166 | 78e127ef | bellard | width = (s->cr[0x01] + 1) * 8; |
1167 | 5fafdf24 | ths | height = s->cr[0x12] |
|
1168 | 5fafdf24 | ths | ((s->cr[0x07] & 0x02) << 7) | |
1169 | 78e127ef | bellard | ((s->cr[0x07] & 0x40) << 3); |
1170 | 78e127ef | bellard | height = (height + 1);
|
1171 | 78e127ef | bellard | /* interlace support */
|
1172 | 78e127ef | bellard | if (s->cr[0x1a] & 0x01) |
1173 | 78e127ef | bellard | height = height * 2;
|
1174 | 78e127ef | bellard | *pwidth = width; |
1175 | 78e127ef | bellard | *pheight = height; |
1176 | 78e127ef | bellard | } |
1177 | 78e127ef | bellard | |
1178 | e6e5ad80 | bellard | /***************************************
|
1179 | e6e5ad80 | bellard | *
|
1180 | e6e5ad80 | bellard | * bank memory
|
1181 | e6e5ad80 | bellard | *
|
1182 | e6e5ad80 | bellard | ***************************************/
|
1183 | e6e5ad80 | bellard | |
1184 | e6e5ad80 | bellard | static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) |
1185 | e6e5ad80 | bellard | { |
1186 | e6e5ad80 | bellard | unsigned offset;
|
1187 | e6e5ad80 | bellard | unsigned limit;
|
1188 | e6e5ad80 | bellard | |
1189 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */ |
1190 | 4e12cd94 | Avi Kivity | offset = s->vga.gr[0x09 + bank_index];
|
1191 | e6e5ad80 | bellard | else /* single bank */ |
1192 | 4e12cd94 | Avi Kivity | offset = s->vga.gr[0x09];
|
1193 | e6e5ad80 | bellard | |
1194 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0b] & 0x20) != 0) |
1195 | e6e5ad80 | bellard | offset <<= 14;
|
1196 | e6e5ad80 | bellard | else
|
1197 | e6e5ad80 | bellard | offset <<= 12;
|
1198 | e6e5ad80 | bellard | |
1199 | e3a4e4b6 | bellard | if (s->real_vram_size <= offset)
|
1200 | e6e5ad80 | bellard | limit = 0;
|
1201 | e6e5ad80 | bellard | else
|
1202 | e3a4e4b6 | bellard | limit = s->real_vram_size - offset; |
1203 | e6e5ad80 | bellard | |
1204 | 4e12cd94 | Avi Kivity | if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { |
1205 | e6e5ad80 | bellard | if (limit > 0x8000) { |
1206 | e6e5ad80 | bellard | offset += 0x8000;
|
1207 | e6e5ad80 | bellard | limit -= 0x8000;
|
1208 | e6e5ad80 | bellard | } else {
|
1209 | e6e5ad80 | bellard | limit = 0;
|
1210 | e6e5ad80 | bellard | } |
1211 | e6e5ad80 | bellard | } |
1212 | e6e5ad80 | bellard | |
1213 | e6e5ad80 | bellard | if (limit > 0) { |
1214 | 2bec46dc | aliguori | /* Thinking about changing bank base? First, drop the dirty bitmap information
|
1215 | 2bec46dc | aliguori | * on the current location, otherwise we lose this pointer forever */
|
1216 | 4e12cd94 | Avi Kivity | if (s->vga.lfb_vram_mapped) {
|
1217 | c227f099 | Anthony Liguori | target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000; |
1218 | 2bec46dc | aliguori | cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
|
1219 | 2bec46dc | aliguori | } |
1220 | e6e5ad80 | bellard | s->cirrus_bank_base[bank_index] = offset; |
1221 | e6e5ad80 | bellard | s->cirrus_bank_limit[bank_index] = limit; |
1222 | e6e5ad80 | bellard | } else {
|
1223 | e6e5ad80 | bellard | s->cirrus_bank_base[bank_index] = 0;
|
1224 | e6e5ad80 | bellard | s->cirrus_bank_limit[bank_index] = 0;
|
1225 | e6e5ad80 | bellard | } |
1226 | e6e5ad80 | bellard | } |
1227 | e6e5ad80 | bellard | |
1228 | e6e5ad80 | bellard | /***************************************
|
1229 | e6e5ad80 | bellard | *
|
1230 | e6e5ad80 | bellard | * I/O access between 0x3c4-0x3c5
|
1231 | e6e5ad80 | bellard | *
|
1232 | e6e5ad80 | bellard | ***************************************/
|
1233 | e6e5ad80 | bellard | |
1234 | 8a82c322 | Juan Quintela | static int cirrus_vga_read_sr(CirrusVGAState * s) |
1235 | e6e5ad80 | bellard | { |
1236 | 8a82c322 | Juan Quintela | switch (s->vga.sr_index) {
|
1237 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1238 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1239 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1240 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1241 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1242 | 8a82c322 | Juan Quintela | return s->vga.sr[s->vga.sr_index];
|
1243 | e6e5ad80 | bellard | case 0x06: // Unlock Cirrus extensions |
1244 | 8a82c322 | Juan Quintela | return s->vga.sr[s->vga.sr_index];
|
1245 | e6e5ad80 | bellard | case 0x10: |
1246 | e6e5ad80 | bellard | case 0x30: |
1247 | e6e5ad80 | bellard | case 0x50: |
1248 | e6e5ad80 | bellard | case 0x70: // Graphics Cursor X |
1249 | e6e5ad80 | bellard | case 0x90: |
1250 | e6e5ad80 | bellard | case 0xb0: |
1251 | e6e5ad80 | bellard | case 0xd0: |
1252 | e6e5ad80 | bellard | case 0xf0: // Graphics Cursor X |
1253 | 8a82c322 | Juan Quintela | return s->vga.sr[0x10]; |
1254 | e6e5ad80 | bellard | case 0x11: |
1255 | e6e5ad80 | bellard | case 0x31: |
1256 | e6e5ad80 | bellard | case 0x51: |
1257 | e6e5ad80 | bellard | case 0x71: // Graphics Cursor Y |
1258 | e6e5ad80 | bellard | case 0x91: |
1259 | e6e5ad80 | bellard | case 0xb1: |
1260 | e6e5ad80 | bellard | case 0xd1: |
1261 | a5082316 | bellard | case 0xf1: // Graphics Cursor Y |
1262 | 8a82c322 | Juan Quintela | return s->vga.sr[0x11]; |
1263 | aeb3c85f | bellard | case 0x05: // ??? |
1264 | aeb3c85f | bellard | case 0x07: // Extended Sequencer Mode |
1265 | aeb3c85f | bellard | case 0x08: // EEPROM Control |
1266 | aeb3c85f | bellard | case 0x09: // Scratch Register 0 |
1267 | aeb3c85f | bellard | case 0x0a: // Scratch Register 1 |
1268 | aeb3c85f | bellard | case 0x0b: // VCLK 0 |
1269 | aeb3c85f | bellard | case 0x0c: // VCLK 1 |
1270 | aeb3c85f | bellard | case 0x0d: // VCLK 2 |
1271 | aeb3c85f | bellard | case 0x0e: // VCLK 3 |
1272 | aeb3c85f | bellard | case 0x0f: // DRAM Control |
1273 | e6e5ad80 | bellard | case 0x12: // Graphics Cursor Attribute |
1274 | e6e5ad80 | bellard | case 0x13: // Graphics Cursor Pattern Address |
1275 | e6e5ad80 | bellard | case 0x14: // Scratch Register 2 |
1276 | e6e5ad80 | bellard | case 0x15: // Scratch Register 3 |
1277 | e6e5ad80 | bellard | case 0x16: // Performance Tuning Register |
1278 | e6e5ad80 | bellard | case 0x17: // Configuration Readback and Extended Control |
1279 | e6e5ad80 | bellard | case 0x18: // Signature Generator Control |
1280 | e6e5ad80 | bellard | case 0x19: // Signal Generator Result |
1281 | e6e5ad80 | bellard | case 0x1a: // Signal Generator Result |
1282 | e6e5ad80 | bellard | case 0x1b: // VCLK 0 Denominator & Post |
1283 | e6e5ad80 | bellard | case 0x1c: // VCLK 1 Denominator & Post |
1284 | e6e5ad80 | bellard | case 0x1d: // VCLK 2 Denominator & Post |
1285 | e6e5ad80 | bellard | case 0x1e: // VCLK 3 Denominator & Post |
1286 | e6e5ad80 | bellard | case 0x1f: // BIOS Write Enable and MCLK select |
1287 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1288 | 8a82c322 | Juan Quintela | printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
|
1289 | e6e5ad80 | bellard | #endif
|
1290 | 8a82c322 | Juan Quintela | return s->vga.sr[s->vga.sr_index];
|
1291 | e6e5ad80 | bellard | default:
|
1292 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1293 | 8a82c322 | Juan Quintela | printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
|
1294 | e6e5ad80 | bellard | #endif
|
1295 | 8a82c322 | Juan Quintela | return 0xff; |
1296 | e6e5ad80 | bellard | break;
|
1297 | e6e5ad80 | bellard | } |
1298 | e6e5ad80 | bellard | } |
1299 | e6e5ad80 | bellard | |
1300 | 31c63201 | Juan Quintela | static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val) |
1301 | e6e5ad80 | bellard | { |
1302 | 31c63201 | Juan Quintela | switch (s->vga.sr_index) {
|
1303 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1304 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1305 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1306 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1307 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1308 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index]; |
1309 | 31c63201 | Juan Quintela | if (s->vga.sr_index == 1) |
1310 | 31c63201 | Juan Quintela | s->vga.update_retrace_info(&s->vga); |
1311 | 31c63201 | Juan Quintela | break;
|
1312 | e6e5ad80 | bellard | case 0x06: // Unlock Cirrus extensions |
1313 | 31c63201 | Juan Quintela | val &= 0x17;
|
1314 | 31c63201 | Juan Quintela | if (val == 0x12) { |
1315 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = 0x12;
|
1316 | e6e5ad80 | bellard | } else {
|
1317 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = 0x0f;
|
1318 | e6e5ad80 | bellard | } |
1319 | e6e5ad80 | bellard | break;
|
1320 | e6e5ad80 | bellard | case 0x10: |
1321 | e6e5ad80 | bellard | case 0x30: |
1322 | e6e5ad80 | bellard | case 0x50: |
1323 | e6e5ad80 | bellard | case 0x70: // Graphics Cursor X |
1324 | e6e5ad80 | bellard | case 0x90: |
1325 | e6e5ad80 | bellard | case 0xb0: |
1326 | e6e5ad80 | bellard | case 0xd0: |
1327 | e6e5ad80 | bellard | case 0xf0: // Graphics Cursor X |
1328 | 31c63201 | Juan Quintela | s->vga.sr[0x10] = val;
|
1329 | 31c63201 | Juan Quintela | s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5); |
1330 | e6e5ad80 | bellard | break;
|
1331 | e6e5ad80 | bellard | case 0x11: |
1332 | e6e5ad80 | bellard | case 0x31: |
1333 | e6e5ad80 | bellard | case 0x51: |
1334 | e6e5ad80 | bellard | case 0x71: // Graphics Cursor Y |
1335 | e6e5ad80 | bellard | case 0x91: |
1336 | e6e5ad80 | bellard | case 0xb1: |
1337 | e6e5ad80 | bellard | case 0xd1: |
1338 | e6e5ad80 | bellard | case 0xf1: // Graphics Cursor Y |
1339 | 31c63201 | Juan Quintela | s->vga.sr[0x11] = val;
|
1340 | 31c63201 | Juan Quintela | s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5); |
1341 | e6e5ad80 | bellard | break;
|
1342 | e6e5ad80 | bellard | case 0x07: // Extended Sequencer Mode |
1343 | 2bec46dc | aliguori | cirrus_update_memory_access(s); |
1344 | e6e5ad80 | bellard | case 0x08: // EEPROM Control |
1345 | e6e5ad80 | bellard | case 0x09: // Scratch Register 0 |
1346 | e6e5ad80 | bellard | case 0x0a: // Scratch Register 1 |
1347 | e6e5ad80 | bellard | case 0x0b: // VCLK 0 |
1348 | e6e5ad80 | bellard | case 0x0c: // VCLK 1 |
1349 | e6e5ad80 | bellard | case 0x0d: // VCLK 2 |
1350 | e6e5ad80 | bellard | case 0x0e: // VCLK 3 |
1351 | e6e5ad80 | bellard | case 0x0f: // DRAM Control |
1352 | e6e5ad80 | bellard | case 0x12: // Graphics Cursor Attribute |
1353 | e6e5ad80 | bellard | case 0x13: // Graphics Cursor Pattern Address |
1354 | e6e5ad80 | bellard | case 0x14: // Scratch Register 2 |
1355 | e6e5ad80 | bellard | case 0x15: // Scratch Register 3 |
1356 | e6e5ad80 | bellard | case 0x16: // Performance Tuning Register |
1357 | e6e5ad80 | bellard | case 0x18: // Signature Generator Control |
1358 | e6e5ad80 | bellard | case 0x19: // Signature Generator Result |
1359 | e6e5ad80 | bellard | case 0x1a: // Signature Generator Result |
1360 | e6e5ad80 | bellard | case 0x1b: // VCLK 0 Denominator & Post |
1361 | e6e5ad80 | bellard | case 0x1c: // VCLK 1 Denominator & Post |
1362 | e6e5ad80 | bellard | case 0x1d: // VCLK 2 Denominator & Post |
1363 | e6e5ad80 | bellard | case 0x1e: // VCLK 3 Denominator & Post |
1364 | e6e5ad80 | bellard | case 0x1f: // BIOS Write Enable and MCLK select |
1365 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = val; |
1366 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1367 | e6e5ad80 | bellard | printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
|
1368 | 31c63201 | Juan Quintela | s->vga.sr_index, val); |
1369 | e6e5ad80 | bellard | #endif
|
1370 | e6e5ad80 | bellard | break;
|
1371 | 8926b517 | bellard | case 0x17: // Configuration Readback and Extended Control |
1372 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
|
1373 | 31c63201 | Juan Quintela | | (val & 0xc7);
|
1374 | 8926b517 | bellard | cirrus_update_memory_access(s); |
1375 | 8926b517 | bellard | break;
|
1376 | e6e5ad80 | bellard | default:
|
1377 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1378 | 31c63201 | Juan Quintela | printf("cirrus: outport sr_index %02x, sr_value %02x\n",
|
1379 | 31c63201 | Juan Quintela | s->vga.sr_index, val); |
1380 | e6e5ad80 | bellard | #endif
|
1381 | e6e5ad80 | bellard | break;
|
1382 | e6e5ad80 | bellard | } |
1383 | e6e5ad80 | bellard | } |
1384 | e6e5ad80 | bellard | |
1385 | e6e5ad80 | bellard | /***************************************
|
1386 | e6e5ad80 | bellard | *
|
1387 | e6e5ad80 | bellard | * I/O access at 0x3c6
|
1388 | e6e5ad80 | bellard | *
|
1389 | e6e5ad80 | bellard | ***************************************/
|
1390 | e6e5ad80 | bellard | |
1391 | 957c9db5 | Juan Quintela | static int cirrus_read_hidden_dac(CirrusVGAState * s) |
1392 | e6e5ad80 | bellard | { |
1393 | a21ae81d | bellard | if (++s->cirrus_hidden_dac_lockindex == 5) { |
1394 | 957c9db5 | Juan Quintela | s->cirrus_hidden_dac_lockindex = 0;
|
1395 | 957c9db5 | Juan Quintela | return s->cirrus_hidden_dac_data;
|
1396 | e6e5ad80 | bellard | } |
1397 | 957c9db5 | Juan Quintela | return 0xff; |
1398 | e6e5ad80 | bellard | } |
1399 | e6e5ad80 | bellard | |
1400 | e6e5ad80 | bellard | static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value) |
1401 | e6e5ad80 | bellard | { |
1402 | e6e5ad80 | bellard | if (s->cirrus_hidden_dac_lockindex == 4) { |
1403 | e6e5ad80 | bellard | s->cirrus_hidden_dac_data = reg_value; |
1404 | a21ae81d | bellard | #if defined(DEBUG_CIRRUS)
|
1405 | e6e5ad80 | bellard | printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
|
1406 | e6e5ad80 | bellard | #endif
|
1407 | e6e5ad80 | bellard | } |
1408 | e6e5ad80 | bellard | s->cirrus_hidden_dac_lockindex = 0;
|
1409 | e6e5ad80 | bellard | } |
1410 | e6e5ad80 | bellard | |
1411 | e6e5ad80 | bellard | /***************************************
|
1412 | e6e5ad80 | bellard | *
|
1413 | e6e5ad80 | bellard | * I/O access at 0x3c9
|
1414 | e6e5ad80 | bellard | *
|
1415 | e6e5ad80 | bellard | ***************************************/
|
1416 | e6e5ad80 | bellard | |
1417 | 5deaeee3 | Juan Quintela | static int cirrus_vga_read_palette(CirrusVGAState * s) |
1418 | e6e5ad80 | bellard | { |
1419 | 5deaeee3 | Juan Quintela | int val;
|
1420 | 5deaeee3 | Juan Quintela | |
1421 | 5deaeee3 | Juan Quintela | if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { |
1422 | 5deaeee3 | Juan Quintela | val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 + |
1423 | 5deaeee3 | Juan Quintela | s->vga.dac_sub_index]; |
1424 | 5deaeee3 | Juan Quintela | } else {
|
1425 | 5deaeee3 | Juan Quintela | val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
|
1426 | 5deaeee3 | Juan Quintela | } |
1427 | 4e12cd94 | Avi Kivity | if (++s->vga.dac_sub_index == 3) { |
1428 | 4e12cd94 | Avi Kivity | s->vga.dac_sub_index = 0;
|
1429 | 4e12cd94 | Avi Kivity | s->vga.dac_read_index++; |
1430 | e6e5ad80 | bellard | } |
1431 | 5deaeee3 | Juan Quintela | return val;
|
1432 | e6e5ad80 | bellard | } |
1433 | e6e5ad80 | bellard | |
1434 | 86948bb1 | Juan Quintela | static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value) |
1435 | e6e5ad80 | bellard | { |
1436 | 4e12cd94 | Avi Kivity | s->vga.dac_cache[s->vga.dac_sub_index] = reg_value; |
1437 | 4e12cd94 | Avi Kivity | if (++s->vga.dac_sub_index == 3) { |
1438 | 86948bb1 | Juan Quintela | if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { |
1439 | 86948bb1 | Juan Quintela | memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3], |
1440 | 86948bb1 | Juan Quintela | s->vga.dac_cache, 3);
|
1441 | 86948bb1 | Juan Quintela | } else {
|
1442 | 86948bb1 | Juan Quintela | memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3); |
1443 | 86948bb1 | Juan Quintela | } |
1444 | a5082316 | bellard | /* XXX update cursor */
|
1445 | 4e12cd94 | Avi Kivity | s->vga.dac_sub_index = 0;
|
1446 | 4e12cd94 | Avi Kivity | s->vga.dac_write_index++; |
1447 | e6e5ad80 | bellard | } |
1448 | e6e5ad80 | bellard | } |
1449 | e6e5ad80 | bellard | |
1450 | e6e5ad80 | bellard | /***************************************
|
1451 | e6e5ad80 | bellard | *
|
1452 | e6e5ad80 | bellard | * I/O access between 0x3ce-0x3cf
|
1453 | e6e5ad80 | bellard | *
|
1454 | e6e5ad80 | bellard | ***************************************/
|
1455 | e6e5ad80 | bellard | |
1456 | f705db9d | Juan Quintela | static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index) |
1457 | e6e5ad80 | bellard | { |
1458 | e6e5ad80 | bellard | switch (reg_index) {
|
1459 | aeb3c85f | bellard | case 0x00: // Standard VGA, BGCOLOR 0x000000ff |
1460 | f705db9d | Juan Quintela | return s->cirrus_shadow_gr0;
|
1461 | aeb3c85f | bellard | case 0x01: // Standard VGA, FGCOLOR 0x000000ff |
1462 | f705db9d | Juan Quintela | return s->cirrus_shadow_gr1;
|
1463 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1464 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1465 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1466 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1467 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1468 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1469 | f705db9d | Juan Quintela | return s->vga.gr[s->vga.gr_index];
|
1470 | e6e5ad80 | bellard | case 0x05: // Standard VGA, Cirrus extended mode |
1471 | e6e5ad80 | bellard | default:
|
1472 | e6e5ad80 | bellard | break;
|
1473 | e6e5ad80 | bellard | } |
1474 | e6e5ad80 | bellard | |
1475 | e6e5ad80 | bellard | if (reg_index < 0x3a) { |
1476 | f705db9d | Juan Quintela | return s->vga.gr[reg_index];
|
1477 | e6e5ad80 | bellard | } else {
|
1478 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1479 | e6e5ad80 | bellard | printf("cirrus: inport gr_index %02x\n", reg_index);
|
1480 | e6e5ad80 | bellard | #endif
|
1481 | f705db9d | Juan Quintela | return 0xff; |
1482 | e6e5ad80 | bellard | } |
1483 | e6e5ad80 | bellard | } |
1484 | e6e5ad80 | bellard | |
1485 | 22286bc6 | Juan Quintela | static void |
1486 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
1487 | e6e5ad80 | bellard | { |
1488 | a5082316 | bellard | #if defined(DEBUG_BITBLT) && 0 |
1489 | a5082316 | bellard | printf("gr%02x: %02x\n", reg_index, reg_value);
|
1490 | a5082316 | bellard | #endif
|
1491 | e6e5ad80 | bellard | switch (reg_index) {
|
1492 | e6e5ad80 | bellard | case 0x00: // Standard VGA, BGCOLOR 0x000000ff |
1493 | f22f5b07 | Juan Quintela | s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; |
1494 | aeb3c85f | bellard | s->cirrus_shadow_gr0 = reg_value; |
1495 | 22286bc6 | Juan Quintela | break;
|
1496 | e6e5ad80 | bellard | case 0x01: // Standard VGA, FGCOLOR 0x000000ff |
1497 | f22f5b07 | Juan Quintela | s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; |
1498 | aeb3c85f | bellard | s->cirrus_shadow_gr1 = reg_value; |
1499 | 22286bc6 | Juan Quintela | break;
|
1500 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1501 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1502 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1503 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1504 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1505 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1506 | 22286bc6 | Juan Quintela | s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; |
1507 | 22286bc6 | Juan Quintela | break;
|
1508 | e6e5ad80 | bellard | case 0x05: // Standard VGA, Cirrus extended mode |
1509 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value & 0x7f;
|
1510 | 8926b517 | bellard | cirrus_update_memory_access(s); |
1511 | e6e5ad80 | bellard | break;
|
1512 | e6e5ad80 | bellard | case 0x09: // bank offset #0 |
1513 | e6e5ad80 | bellard | case 0x0A: // bank offset #1 |
1514 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value; |
1515 | 8926b517 | bellard | cirrus_update_bank_ptr(s, 0);
|
1516 | 8926b517 | bellard | cirrus_update_bank_ptr(s, 1);
|
1517 | 2bec46dc | aliguori | cirrus_update_memory_access(s); |
1518 | 8926b517 | bellard | break;
|
1519 | e6e5ad80 | bellard | case 0x0B: |
1520 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value; |
1521 | e6e5ad80 | bellard | cirrus_update_bank_ptr(s, 0);
|
1522 | e6e5ad80 | bellard | cirrus_update_bank_ptr(s, 1);
|
1523 | 8926b517 | bellard | cirrus_update_memory_access(s); |
1524 | e6e5ad80 | bellard | break;
|
1525 | e6e5ad80 | bellard | case 0x10: // BGCOLOR 0x0000ff00 |
1526 | e6e5ad80 | bellard | case 0x11: // FGCOLOR 0x0000ff00 |
1527 | e6e5ad80 | bellard | case 0x12: // BGCOLOR 0x00ff0000 |
1528 | e6e5ad80 | bellard | case 0x13: // FGCOLOR 0x00ff0000 |
1529 | e6e5ad80 | bellard | case 0x14: // BGCOLOR 0xff000000 |
1530 | e6e5ad80 | bellard | case 0x15: // FGCOLOR 0xff000000 |
1531 | e6e5ad80 | bellard | case 0x20: // BLT WIDTH 0x0000ff |
1532 | e6e5ad80 | bellard | case 0x22: // BLT HEIGHT 0x0000ff |
1533 | e6e5ad80 | bellard | case 0x24: // BLT DEST PITCH 0x0000ff |
1534 | e6e5ad80 | bellard | case 0x26: // BLT SRC PITCH 0x0000ff |
1535 | e6e5ad80 | bellard | case 0x28: // BLT DEST ADDR 0x0000ff |
1536 | e6e5ad80 | bellard | case 0x29: // BLT DEST ADDR 0x00ff00 |
1537 | e6e5ad80 | bellard | case 0x2c: // BLT SRC ADDR 0x0000ff |
1538 | e6e5ad80 | bellard | case 0x2d: // BLT SRC ADDR 0x00ff00 |
1539 | a5082316 | bellard | case 0x2f: // BLT WRITEMASK |
1540 | e6e5ad80 | bellard | case 0x30: // BLT MODE |
1541 | e6e5ad80 | bellard | case 0x32: // RASTER OP |
1542 | a21ae81d | bellard | case 0x33: // BLT MODEEXT |
1543 | e6e5ad80 | bellard | case 0x34: // BLT TRANSPARENT COLOR 0x00ff |
1544 | e6e5ad80 | bellard | case 0x35: // BLT TRANSPARENT COLOR 0xff00 |
1545 | e6e5ad80 | bellard | case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff |
1546 | e6e5ad80 | bellard | case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00 |
1547 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value; |
1548 | e6e5ad80 | bellard | break;
|
1549 | e6e5ad80 | bellard | case 0x21: // BLT WIDTH 0x001f00 |
1550 | e6e5ad80 | bellard | case 0x23: // BLT HEIGHT 0x001f00 |
1551 | e6e5ad80 | bellard | case 0x25: // BLT DEST PITCH 0x001f00 |
1552 | e6e5ad80 | bellard | case 0x27: // BLT SRC PITCH 0x001f00 |
1553 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value & 0x1f;
|
1554 | e6e5ad80 | bellard | break;
|
1555 | e6e5ad80 | bellard | case 0x2a: // BLT DEST ADDR 0x3f0000 |
1556 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value & 0x3f;
|
1557 | a5082316 | bellard | /* if auto start mode, starts bit blt now */
|
1558 | 4e12cd94 | Avi Kivity | if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) { |
1559 | a5082316 | bellard | cirrus_bitblt_start(s); |
1560 | a5082316 | bellard | } |
1561 | a5082316 | bellard | break;
|
1562 | e6e5ad80 | bellard | case 0x2e: // BLT SRC ADDR 0x3f0000 |
1563 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value & 0x3f;
|
1564 | e6e5ad80 | bellard | break;
|
1565 | e6e5ad80 | bellard | case 0x31: // BLT STATUS/START |
1566 | e6e5ad80 | bellard | cirrus_write_bitblt(s, reg_value); |
1567 | e6e5ad80 | bellard | break;
|
1568 | e6e5ad80 | bellard | default:
|
1569 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1570 | e6e5ad80 | bellard | printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
|
1571 | e6e5ad80 | bellard | reg_value); |
1572 | e6e5ad80 | bellard | #endif
|
1573 | e6e5ad80 | bellard | break;
|
1574 | e6e5ad80 | bellard | } |
1575 | e6e5ad80 | bellard | } |
1576 | e6e5ad80 | bellard | |
1577 | e6e5ad80 | bellard | /***************************************
|
1578 | e6e5ad80 | bellard | *
|
1579 | e6e5ad80 | bellard | * I/O access between 0x3d4-0x3d5
|
1580 | e6e5ad80 | bellard | *
|
1581 | e6e5ad80 | bellard | ***************************************/
|
1582 | e6e5ad80 | bellard | |
1583 | b863d514 | Juan Quintela | static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index) |
1584 | e6e5ad80 | bellard | { |
1585 | e6e5ad80 | bellard | switch (reg_index) {
|
1586 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1587 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1588 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1589 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1590 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1591 | e6e5ad80 | bellard | case 0x05: // Standard VGA |
1592 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1593 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1594 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1595 | e6e5ad80 | bellard | case 0x09: // Standard VGA |
1596 | e6e5ad80 | bellard | case 0x0a: // Standard VGA |
1597 | e6e5ad80 | bellard | case 0x0b: // Standard VGA |
1598 | e6e5ad80 | bellard | case 0x0c: // Standard VGA |
1599 | e6e5ad80 | bellard | case 0x0d: // Standard VGA |
1600 | e6e5ad80 | bellard | case 0x0e: // Standard VGA |
1601 | e6e5ad80 | bellard | case 0x0f: // Standard VGA |
1602 | e6e5ad80 | bellard | case 0x10: // Standard VGA |
1603 | e6e5ad80 | bellard | case 0x11: // Standard VGA |
1604 | e6e5ad80 | bellard | case 0x12: // Standard VGA |
1605 | e6e5ad80 | bellard | case 0x13: // Standard VGA |
1606 | e6e5ad80 | bellard | case 0x14: // Standard VGA |
1607 | e6e5ad80 | bellard | case 0x15: // Standard VGA |
1608 | e6e5ad80 | bellard | case 0x16: // Standard VGA |
1609 | e6e5ad80 | bellard | case 0x17: // Standard VGA |
1610 | e6e5ad80 | bellard | case 0x18: // Standard VGA |
1611 | b863d514 | Juan Quintela | return s->vga.cr[s->vga.cr_index];
|
1612 | ca896ef3 | aurel32 | case 0x24: // Attribute Controller Toggle Readback (R) |
1613 | b863d514 | Juan Quintela | return (s->vga.ar_flip_flop << 7); |
1614 | e6e5ad80 | bellard | case 0x19: // Interlace End |
1615 | e6e5ad80 | bellard | case 0x1a: // Miscellaneous Control |
1616 | e6e5ad80 | bellard | case 0x1b: // Extended Display Control |
1617 | e6e5ad80 | bellard | case 0x1c: // Sync Adjust and Genlock |
1618 | e6e5ad80 | bellard | case 0x1d: // Overlay Extended Control |
1619 | e6e5ad80 | bellard | case 0x22: // Graphics Data Latches Readback (R) |
1620 | e6e5ad80 | bellard | case 0x25: // Part Status |
1621 | e6e5ad80 | bellard | case 0x27: // Part ID (R) |
1622 | b863d514 | Juan Quintela | return s->vga.cr[s->vga.cr_index];
|
1623 | e6e5ad80 | bellard | case 0x26: // Attribute Controller Index Readback (R) |
1624 | b863d514 | Juan Quintela | return s->vga.ar_index & 0x3f; |
1625 | e6e5ad80 | bellard | break;
|
1626 | e6e5ad80 | bellard | default:
|
1627 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1628 | e6e5ad80 | bellard | printf("cirrus: inport cr_index %02x\n", reg_index);
|
1629 | e6e5ad80 | bellard | #endif
|
1630 | b863d514 | Juan Quintela | return 0xff; |
1631 | e6e5ad80 | bellard | } |
1632 | e6e5ad80 | bellard | } |
1633 | e6e5ad80 | bellard | |
1634 | 4ec1ce04 | Juan Quintela | static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value) |
1635 | e6e5ad80 | bellard | { |
1636 | 4ec1ce04 | Juan Quintela | switch (s->vga.cr_index) {
|
1637 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1638 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1639 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1640 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1641 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1642 | e6e5ad80 | bellard | case 0x05: // Standard VGA |
1643 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1644 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1645 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1646 | e6e5ad80 | bellard | case 0x09: // Standard VGA |
1647 | e6e5ad80 | bellard | case 0x0a: // Standard VGA |
1648 | e6e5ad80 | bellard | case 0x0b: // Standard VGA |
1649 | e6e5ad80 | bellard | case 0x0c: // Standard VGA |
1650 | e6e5ad80 | bellard | case 0x0d: // Standard VGA |
1651 | e6e5ad80 | bellard | case 0x0e: // Standard VGA |
1652 | e6e5ad80 | bellard | case 0x0f: // Standard VGA |
1653 | e6e5ad80 | bellard | case 0x10: // Standard VGA |
1654 | e6e5ad80 | bellard | case 0x11: // Standard VGA |
1655 | e6e5ad80 | bellard | case 0x12: // Standard VGA |
1656 | e6e5ad80 | bellard | case 0x13: // Standard VGA |
1657 | e6e5ad80 | bellard | case 0x14: // Standard VGA |
1658 | e6e5ad80 | bellard | case 0x15: // Standard VGA |
1659 | e6e5ad80 | bellard | case 0x16: // Standard VGA |
1660 | e6e5ad80 | bellard | case 0x17: // Standard VGA |
1661 | e6e5ad80 | bellard | case 0x18: // Standard VGA |
1662 | 4ec1ce04 | Juan Quintela | /* handle CR0-7 protection */
|
1663 | 4ec1ce04 | Juan Quintela | if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) { |
1664 | 4ec1ce04 | Juan Quintela | /* can always write bit 4 of CR7 */
|
1665 | 4ec1ce04 | Juan Quintela | if (s->vga.cr_index == 7) |
1666 | 4ec1ce04 | Juan Quintela | s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10); |
1667 | 4ec1ce04 | Juan Quintela | return;
|
1668 | 4ec1ce04 | Juan Quintela | } |
1669 | 4ec1ce04 | Juan Quintela | s->vga.cr[s->vga.cr_index] = reg_value; |
1670 | 4ec1ce04 | Juan Quintela | switch(s->vga.cr_index) {
|
1671 | 4ec1ce04 | Juan Quintela | case 0x00: |
1672 | 4ec1ce04 | Juan Quintela | case 0x04: |
1673 | 4ec1ce04 | Juan Quintela | case 0x05: |
1674 | 4ec1ce04 | Juan Quintela | case 0x06: |
1675 | 4ec1ce04 | Juan Quintela | case 0x07: |
1676 | 4ec1ce04 | Juan Quintela | case 0x11: |
1677 | 4ec1ce04 | Juan Quintela | case 0x17: |
1678 | 4ec1ce04 | Juan Quintela | s->vga.update_retrace_info(&s->vga); |
1679 | 4ec1ce04 | Juan Quintela | break;
|
1680 | 4ec1ce04 | Juan Quintela | } |
1681 | 4ec1ce04 | Juan Quintela | break;
|
1682 | e6e5ad80 | bellard | case 0x19: // Interlace End |
1683 | e6e5ad80 | bellard | case 0x1a: // Miscellaneous Control |
1684 | e6e5ad80 | bellard | case 0x1b: // Extended Display Control |
1685 | e6e5ad80 | bellard | case 0x1c: // Sync Adjust and Genlock |
1686 | ae184e4a | bellard | case 0x1d: // Overlay Extended Control |
1687 | 4ec1ce04 | Juan Quintela | s->vga.cr[s->vga.cr_index] = reg_value; |
1688 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1689 | e6e5ad80 | bellard | printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
|
1690 | 4ec1ce04 | Juan Quintela | s->vga.cr_index, reg_value); |
1691 | e6e5ad80 | bellard | #endif
|
1692 | e6e5ad80 | bellard | break;
|
1693 | e6e5ad80 | bellard | case 0x22: // Graphics Data Latches Readback (R) |
1694 | e6e5ad80 | bellard | case 0x24: // Attribute Controller Toggle Readback (R) |
1695 | e6e5ad80 | bellard | case 0x26: // Attribute Controller Index Readback (R) |
1696 | e6e5ad80 | bellard | case 0x27: // Part ID (R) |
1697 | e6e5ad80 | bellard | break;
|
1698 | e6e5ad80 | bellard | case 0x25: // Part Status |
1699 | e6e5ad80 | bellard | default:
|
1700 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1701 | 4ec1ce04 | Juan Quintela | printf("cirrus: outport cr_index %02x, cr_value %02x\n",
|
1702 | 4ec1ce04 | Juan Quintela | s->vga.cr_index, reg_value); |
1703 | e6e5ad80 | bellard | #endif
|
1704 | e6e5ad80 | bellard | break;
|
1705 | e6e5ad80 | bellard | } |
1706 | e6e5ad80 | bellard | } |
1707 | e6e5ad80 | bellard | |
1708 | e6e5ad80 | bellard | /***************************************
|
1709 | e6e5ad80 | bellard | *
|
1710 | e6e5ad80 | bellard | * memory-mapped I/O (bitblt)
|
1711 | e6e5ad80 | bellard | *
|
1712 | e6e5ad80 | bellard | ***************************************/
|
1713 | e6e5ad80 | bellard | |
1714 | e6e5ad80 | bellard | static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address) |
1715 | e6e5ad80 | bellard | { |
1716 | e6e5ad80 | bellard | int value = 0xff; |
1717 | e6e5ad80 | bellard | |
1718 | e6e5ad80 | bellard | switch (address) {
|
1719 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 0): |
1720 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x00);
|
1721 | e6e5ad80 | bellard | break;
|
1722 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 1): |
1723 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x10);
|
1724 | e6e5ad80 | bellard | break;
|
1725 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 2): |
1726 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x12);
|
1727 | e6e5ad80 | bellard | break;
|
1728 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 3): |
1729 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x14);
|
1730 | e6e5ad80 | bellard | break;
|
1731 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 0): |
1732 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x01);
|
1733 | e6e5ad80 | bellard | break;
|
1734 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 1): |
1735 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x11);
|
1736 | e6e5ad80 | bellard | break;
|
1737 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 2): |
1738 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x13);
|
1739 | e6e5ad80 | bellard | break;
|
1740 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 3): |
1741 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x15);
|
1742 | e6e5ad80 | bellard | break;
|
1743 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 0): |
1744 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x20);
|
1745 | e6e5ad80 | bellard | break;
|
1746 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 1): |
1747 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x21);
|
1748 | e6e5ad80 | bellard | break;
|
1749 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 0): |
1750 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x22);
|
1751 | e6e5ad80 | bellard | break;
|
1752 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 1): |
1753 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x23);
|
1754 | e6e5ad80 | bellard | break;
|
1755 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 0): |
1756 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x24);
|
1757 | e6e5ad80 | bellard | break;
|
1758 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 1): |
1759 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x25);
|
1760 | e6e5ad80 | bellard | break;
|
1761 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 0): |
1762 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x26);
|
1763 | e6e5ad80 | bellard | break;
|
1764 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 1): |
1765 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x27);
|
1766 | e6e5ad80 | bellard | break;
|
1767 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 0): |
1768 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x28);
|
1769 | e6e5ad80 | bellard | break;
|
1770 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 1): |
1771 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x29);
|
1772 | e6e5ad80 | bellard | break;
|
1773 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 2): |
1774 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2a);
|
1775 | e6e5ad80 | bellard | break;
|
1776 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 0): |
1777 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2c);
|
1778 | e6e5ad80 | bellard | break;
|
1779 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 1): |
1780 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2d);
|
1781 | e6e5ad80 | bellard | break;
|
1782 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 2): |
1783 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2e);
|
1784 | e6e5ad80 | bellard | break;
|
1785 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTWRITEMASK:
|
1786 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2f);
|
1787 | e6e5ad80 | bellard | break;
|
1788 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTMODE:
|
1789 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x30);
|
1790 | e6e5ad80 | bellard | break;
|
1791 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTROP:
|
1792 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x32);
|
1793 | e6e5ad80 | bellard | break;
|
1794 | a21ae81d | bellard | case CIRRUS_MMIO_BLTMODEEXT:
|
1795 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x33);
|
1796 | a21ae81d | bellard | break;
|
1797 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
1798 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x34);
|
1799 | e6e5ad80 | bellard | break;
|
1800 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): |
1801 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x35);
|
1802 | e6e5ad80 | bellard | break;
|
1803 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): |
1804 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x38);
|
1805 | e6e5ad80 | bellard | break;
|
1806 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): |
1807 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x39);
|
1808 | e6e5ad80 | bellard | break;
|
1809 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTSTATUS:
|
1810 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x31);
|
1811 | e6e5ad80 | bellard | break;
|
1812 | e6e5ad80 | bellard | default:
|
1813 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1814 | e6e5ad80 | bellard | printf("cirrus: mmio read - address 0x%04x\n", address);
|
1815 | e6e5ad80 | bellard | #endif
|
1816 | e6e5ad80 | bellard | break;
|
1817 | e6e5ad80 | bellard | } |
1818 | e6e5ad80 | bellard | |
1819 | e6e5ad80 | bellard | return (uint8_t) value;
|
1820 | e6e5ad80 | bellard | } |
1821 | e6e5ad80 | bellard | |
1822 | e6e5ad80 | bellard | static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address, |
1823 | e6e5ad80 | bellard | uint8_t value) |
1824 | e6e5ad80 | bellard | { |
1825 | e6e5ad80 | bellard | switch (address) {
|
1826 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 0): |
1827 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x00, value);
|
1828 | e6e5ad80 | bellard | break;
|
1829 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 1): |
1830 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x10, value);
|
1831 | e6e5ad80 | bellard | break;
|
1832 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 2): |
1833 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x12, value);
|
1834 | e6e5ad80 | bellard | break;
|
1835 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 3): |
1836 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x14, value);
|
1837 | e6e5ad80 | bellard | break;
|
1838 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 0): |
1839 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x01, value);
|
1840 | e6e5ad80 | bellard | break;
|
1841 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 1): |
1842 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x11, value);
|
1843 | e6e5ad80 | bellard | break;
|
1844 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 2): |
1845 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x13, value);
|
1846 | e6e5ad80 | bellard | break;
|
1847 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 3): |
1848 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x15, value);
|
1849 | e6e5ad80 | bellard | break;
|
1850 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 0): |
1851 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x20, value);
|
1852 | e6e5ad80 | bellard | break;
|
1853 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 1): |
1854 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x21, value);
|
1855 | e6e5ad80 | bellard | break;
|
1856 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 0): |
1857 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x22, value);
|
1858 | e6e5ad80 | bellard | break;
|
1859 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 1): |
1860 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x23, value);
|
1861 | e6e5ad80 | bellard | break;
|
1862 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 0): |
1863 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x24, value);
|
1864 | e6e5ad80 | bellard | break;
|
1865 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 1): |
1866 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x25, value);
|
1867 | e6e5ad80 | bellard | break;
|
1868 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 0): |
1869 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x26, value);
|
1870 | e6e5ad80 | bellard | break;
|
1871 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 1): |
1872 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x27, value);
|
1873 | e6e5ad80 | bellard | break;
|
1874 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 0): |
1875 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x28, value);
|
1876 | e6e5ad80 | bellard | break;
|
1877 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 1): |
1878 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x29, value);
|
1879 | e6e5ad80 | bellard | break;
|
1880 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 2): |
1881 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2a, value);
|
1882 | e6e5ad80 | bellard | break;
|
1883 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 3): |
1884 | e6e5ad80 | bellard | /* ignored */
|
1885 | e6e5ad80 | bellard | break;
|
1886 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 0): |
1887 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2c, value);
|
1888 | e6e5ad80 | bellard | break;
|
1889 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 1): |
1890 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2d, value);
|
1891 | e6e5ad80 | bellard | break;
|
1892 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 2): |
1893 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2e, value);
|
1894 | e6e5ad80 | bellard | break;
|
1895 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTWRITEMASK:
|
1896 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2f, value);
|
1897 | e6e5ad80 | bellard | break;
|
1898 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTMODE:
|
1899 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x30, value);
|
1900 | e6e5ad80 | bellard | break;
|
1901 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTROP:
|
1902 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x32, value);
|
1903 | e6e5ad80 | bellard | break;
|
1904 | a21ae81d | bellard | case CIRRUS_MMIO_BLTMODEEXT:
|
1905 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x33, value);
|
1906 | a21ae81d | bellard | break;
|
1907 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
1908 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x34, value);
|
1909 | e6e5ad80 | bellard | break;
|
1910 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): |
1911 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x35, value);
|
1912 | e6e5ad80 | bellard | break;
|
1913 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): |
1914 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x38, value);
|
1915 | e6e5ad80 | bellard | break;
|
1916 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): |
1917 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x39, value);
|
1918 | e6e5ad80 | bellard | break;
|
1919 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTSTATUS:
|
1920 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x31, value);
|
1921 | e6e5ad80 | bellard | break;
|
1922 | e6e5ad80 | bellard | default:
|
1923 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1924 | e6e5ad80 | bellard | printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
|
1925 | e6e5ad80 | bellard | address, value); |
1926 | e6e5ad80 | bellard | #endif
|
1927 | e6e5ad80 | bellard | break;
|
1928 | e6e5ad80 | bellard | } |
1929 | e6e5ad80 | bellard | } |
1930 | e6e5ad80 | bellard | |
1931 | e6e5ad80 | bellard | /***************************************
|
1932 | e6e5ad80 | bellard | *
|
1933 | e6e5ad80 | bellard | * write mode 4/5
|
1934 | e6e5ad80 | bellard | *
|
1935 | e6e5ad80 | bellard | * assume TARGET_PAGE_SIZE >= 16
|
1936 | e6e5ad80 | bellard | *
|
1937 | e6e5ad80 | bellard | ***************************************/
|
1938 | e6e5ad80 | bellard | |
1939 | e6e5ad80 | bellard | static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, |
1940 | e6e5ad80 | bellard | unsigned mode,
|
1941 | e6e5ad80 | bellard | unsigned offset,
|
1942 | e6e5ad80 | bellard | uint32_t mem_value) |
1943 | e6e5ad80 | bellard | { |
1944 | e6e5ad80 | bellard | int x;
|
1945 | e6e5ad80 | bellard | unsigned val = mem_value;
|
1946 | e6e5ad80 | bellard | uint8_t *dst; |
1947 | e6e5ad80 | bellard | |
1948 | 4e12cd94 | Avi Kivity | dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); |
1949 | e6e5ad80 | bellard | for (x = 0; x < 8; x++) { |
1950 | e6e5ad80 | bellard | if (val & 0x80) { |
1951 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr1; |
1952 | e6e5ad80 | bellard | } else if (mode == 5) { |
1953 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr0; |
1954 | e6e5ad80 | bellard | } |
1955 | e6e5ad80 | bellard | val <<= 1;
|
1956 | 0b74ed78 | bellard | dst++; |
1957 | e6e5ad80 | bellard | } |
1958 | 4e12cd94 | Avi Kivity | cpu_physical_memory_set_dirty(s->vga.vram_offset + offset); |
1959 | 4e12cd94 | Avi Kivity | cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 7);
|
1960 | e6e5ad80 | bellard | } |
1961 | e6e5ad80 | bellard | |
1962 | e6e5ad80 | bellard | static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, |
1963 | e6e5ad80 | bellard | unsigned mode,
|
1964 | e6e5ad80 | bellard | unsigned offset,
|
1965 | e6e5ad80 | bellard | uint32_t mem_value) |
1966 | e6e5ad80 | bellard | { |
1967 | e6e5ad80 | bellard | int x;
|
1968 | e6e5ad80 | bellard | unsigned val = mem_value;
|
1969 | e6e5ad80 | bellard | uint8_t *dst; |
1970 | e6e5ad80 | bellard | |
1971 | 4e12cd94 | Avi Kivity | dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); |
1972 | e6e5ad80 | bellard | for (x = 0; x < 8; x++) { |
1973 | e6e5ad80 | bellard | if (val & 0x80) { |
1974 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr1; |
1975 | 4e12cd94 | Avi Kivity | *(dst + 1) = s->vga.gr[0x11]; |
1976 | e6e5ad80 | bellard | } else if (mode == 5) { |
1977 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr0; |
1978 | 4e12cd94 | Avi Kivity | *(dst + 1) = s->vga.gr[0x10]; |
1979 | e6e5ad80 | bellard | } |
1980 | e6e5ad80 | bellard | val <<= 1;
|
1981 | 0b74ed78 | bellard | dst += 2;
|
1982 | e6e5ad80 | bellard | } |
1983 | 4e12cd94 | Avi Kivity | cpu_physical_memory_set_dirty(s->vga.vram_offset + offset); |
1984 | 4e12cd94 | Avi Kivity | cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 15);
|
1985 | e6e5ad80 | bellard | } |
1986 | e6e5ad80 | bellard | |
1987 | e6e5ad80 | bellard | /***************************************
|
1988 | e6e5ad80 | bellard | *
|
1989 | e6e5ad80 | bellard | * memory access between 0xa0000-0xbffff
|
1990 | e6e5ad80 | bellard | *
|
1991 | e6e5ad80 | bellard | ***************************************/
|
1992 | e6e5ad80 | bellard | |
1993 | c227f099 | Anthony Liguori | static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr) |
1994 | e6e5ad80 | bellard | { |
1995 | e6e5ad80 | bellard | CirrusVGAState *s = opaque; |
1996 | e6e5ad80 | bellard | unsigned bank_index;
|
1997 | e6e5ad80 | bellard | unsigned bank_offset;
|
1998 | e6e5ad80 | bellard | uint32_t val; |
1999 | e6e5ad80 | bellard | |
2000 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x07] & 0x01) == 0) { |
2001 | e6e5ad80 | bellard | return vga_mem_readb(s, addr);
|
2002 | e6e5ad80 | bellard | } |
2003 | e6e5ad80 | bellard | |
2004 | aeb3c85f | bellard | addr &= 0x1ffff;
|
2005 | aeb3c85f | bellard | |
2006 | e6e5ad80 | bellard | if (addr < 0x10000) { |
2007 | e6e5ad80 | bellard | /* XXX handle bitblt */
|
2008 | e6e5ad80 | bellard | /* video memory */
|
2009 | e6e5ad80 | bellard | bank_index = addr >> 15;
|
2010 | e6e5ad80 | bellard | bank_offset = addr & 0x7fff;
|
2011 | e6e5ad80 | bellard | if (bank_offset < s->cirrus_bank_limit[bank_index]) {
|
2012 | e6e5ad80 | bellard | bank_offset += s->cirrus_bank_base[bank_index]; |
2013 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
2014 | e6e5ad80 | bellard | bank_offset <<= 4;
|
2015 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
2016 | e6e5ad80 | bellard | bank_offset <<= 3;
|
2017 | e6e5ad80 | bellard | } |
2018 | e6e5ad80 | bellard | bank_offset &= s->cirrus_addr_mask; |
2019 | 4e12cd94 | Avi Kivity | val = *(s->vga.vram_ptr + bank_offset); |
2020 | e6e5ad80 | bellard | } else
|
2021 | e6e5ad80 | bellard | val = 0xff;
|
2022 | e6e5ad80 | bellard | } else if (addr >= 0x18000 && addr < 0x18100) { |
2023 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2024 | e6e5ad80 | bellard | val = 0xff;
|
2025 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x17] & 0x44) == 0x04) { |
2026 | e6e5ad80 | bellard | val = cirrus_mmio_blt_read(s, addr & 0xff);
|
2027 | e6e5ad80 | bellard | } |
2028 | e6e5ad80 | bellard | } else {
|
2029 | e6e5ad80 | bellard | val = 0xff;
|
2030 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
2031 | 0bf9e31a | Blue Swirl | printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr); |
2032 | e6e5ad80 | bellard | #endif
|
2033 | e6e5ad80 | bellard | } |
2034 | e6e5ad80 | bellard | return val;
|
2035 | e6e5ad80 | bellard | } |
2036 | e6e5ad80 | bellard | |
2037 | c227f099 | Anthony Liguori | static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr) |
2038 | e6e5ad80 | bellard | { |
2039 | e6e5ad80 | bellard | uint32_t v; |
2040 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2041 | e6e5ad80 | bellard | v = cirrus_vga_mem_readb(opaque, addr) << 8;
|
2042 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 1);
|
2043 | e6e5ad80 | bellard | #else
|
2044 | e6e5ad80 | bellard | v = cirrus_vga_mem_readb(opaque, addr); |
2045 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8; |
2046 | e6e5ad80 | bellard | #endif
|
2047 | e6e5ad80 | bellard | return v;
|
2048 | e6e5ad80 | bellard | } |
2049 | e6e5ad80 | bellard | |
2050 | c227f099 | Anthony Liguori | static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr) |
2051 | e6e5ad80 | bellard | { |
2052 | e6e5ad80 | bellard | uint32_t v; |
2053 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2054 | e6e5ad80 | bellard | v = cirrus_vga_mem_readb(opaque, addr) << 24;
|
2055 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16; |
2056 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8; |
2057 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 3);
|
2058 | e6e5ad80 | bellard | #else
|
2059 | e6e5ad80 | bellard | v = cirrus_vga_mem_readb(opaque, addr); |
2060 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8; |
2061 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16; |
2062 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24; |
2063 | e6e5ad80 | bellard | #endif
|
2064 | e6e5ad80 | bellard | return v;
|
2065 | e6e5ad80 | bellard | } |
2066 | e6e5ad80 | bellard | |
2067 | c227f099 | Anthony Liguori | static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr, |
2068 | e6e5ad80 | bellard | uint32_t mem_value) |
2069 | e6e5ad80 | bellard | { |
2070 | e6e5ad80 | bellard | CirrusVGAState *s = opaque; |
2071 | e6e5ad80 | bellard | unsigned bank_index;
|
2072 | e6e5ad80 | bellard | unsigned bank_offset;
|
2073 | e6e5ad80 | bellard | unsigned mode;
|
2074 | e6e5ad80 | bellard | |
2075 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x07] & 0x01) == 0) { |
2076 | e6e5ad80 | bellard | vga_mem_writeb(s, addr, mem_value); |
2077 | e6e5ad80 | bellard | return;
|
2078 | e6e5ad80 | bellard | } |
2079 | e6e5ad80 | bellard | |
2080 | aeb3c85f | bellard | addr &= 0x1ffff;
|
2081 | aeb3c85f | bellard | |
2082 | e6e5ad80 | bellard | if (addr < 0x10000) { |
2083 | e6e5ad80 | bellard | if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
|
2084 | e6e5ad80 | bellard | /* bitblt */
|
2085 | e6e5ad80 | bellard | *s->cirrus_srcptr++ = (uint8_t) mem_value; |
2086 | a5082316 | bellard | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
2087 | e6e5ad80 | bellard | cirrus_bitblt_cputovideo_next(s); |
2088 | e6e5ad80 | bellard | } |
2089 | e6e5ad80 | bellard | } else {
|
2090 | e6e5ad80 | bellard | /* video memory */
|
2091 | e6e5ad80 | bellard | bank_index = addr >> 15;
|
2092 | e6e5ad80 | bellard | bank_offset = addr & 0x7fff;
|
2093 | e6e5ad80 | bellard | if (bank_offset < s->cirrus_bank_limit[bank_index]) {
|
2094 | e6e5ad80 | bellard | bank_offset += s->cirrus_bank_base[bank_index]; |
2095 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
2096 | e6e5ad80 | bellard | bank_offset <<= 4;
|
2097 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
2098 | e6e5ad80 | bellard | bank_offset <<= 3;
|
2099 | e6e5ad80 | bellard | } |
2100 | e6e5ad80 | bellard | bank_offset &= s->cirrus_addr_mask; |
2101 | 4e12cd94 | Avi Kivity | mode = s->vga.gr[0x05] & 0x7; |
2102 | 4e12cd94 | Avi Kivity | if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { |
2103 | 4e12cd94 | Avi Kivity | *(s->vga.vram_ptr + bank_offset) = mem_value; |
2104 | 4e12cd94 | Avi Kivity | cpu_physical_memory_set_dirty(s->vga.vram_offset + |
2105 | e6e5ad80 | bellard | bank_offset); |
2106 | e6e5ad80 | bellard | } else {
|
2107 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) != 0x14) { |
2108 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_8bpp(s, mode, |
2109 | e6e5ad80 | bellard | bank_offset, |
2110 | e6e5ad80 | bellard | mem_value); |
2111 | e6e5ad80 | bellard | } else {
|
2112 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_16bpp(s, mode, |
2113 | e6e5ad80 | bellard | bank_offset, |
2114 | e6e5ad80 | bellard | mem_value); |
2115 | e6e5ad80 | bellard | } |
2116 | e6e5ad80 | bellard | } |
2117 | e6e5ad80 | bellard | } |
2118 | e6e5ad80 | bellard | } |
2119 | e6e5ad80 | bellard | } else if (addr >= 0x18000 && addr < 0x18100) { |
2120 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2121 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x17] & 0x44) == 0x04) { |
2122 | e6e5ad80 | bellard | cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
|
2123 | e6e5ad80 | bellard | } |
2124 | e6e5ad80 | bellard | } else {
|
2125 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
2126 | 0bf9e31a | Blue Swirl | printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr, |
2127 | 0bf9e31a | Blue Swirl | mem_value); |
2128 | e6e5ad80 | bellard | #endif
|
2129 | e6e5ad80 | bellard | } |
2130 | e6e5ad80 | bellard | } |
2131 | e6e5ad80 | bellard | |
2132 | c227f099 | Anthony Liguori | static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
2133 | e6e5ad80 | bellard | { |
2134 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2135 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff); |
2136 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff); |
2137 | e6e5ad80 | bellard | #else
|
2138 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
|
2139 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2140 | e6e5ad80 | bellard | #endif
|
2141 | e6e5ad80 | bellard | } |
2142 | e6e5ad80 | bellard | |
2143 | c227f099 | Anthony Liguori | static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
2144 | e6e5ad80 | bellard | { |
2145 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2146 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff); |
2147 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
2148 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
2149 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff); |
2150 | e6e5ad80 | bellard | #else
|
2151 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
|
2152 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2153 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2154 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2155 | e6e5ad80 | bellard | #endif
|
2156 | e6e5ad80 | bellard | } |
2157 | e6e5ad80 | bellard | |
2158 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const cirrus_vga_mem_read[3] = { |
2159 | e6e5ad80 | bellard | cirrus_vga_mem_readb, |
2160 | e6e5ad80 | bellard | cirrus_vga_mem_readw, |
2161 | e6e5ad80 | bellard | cirrus_vga_mem_readl, |
2162 | e6e5ad80 | bellard | }; |
2163 | e6e5ad80 | bellard | |
2164 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const cirrus_vga_mem_write[3] = { |
2165 | e6e5ad80 | bellard | cirrus_vga_mem_writeb, |
2166 | e6e5ad80 | bellard | cirrus_vga_mem_writew, |
2167 | e6e5ad80 | bellard | cirrus_vga_mem_writel, |
2168 | e6e5ad80 | bellard | }; |
2169 | e6e5ad80 | bellard | |
2170 | e6e5ad80 | bellard | /***************************************
|
2171 | e6e5ad80 | bellard | *
|
2172 | a5082316 | bellard | * hardware cursor
|
2173 | a5082316 | bellard | *
|
2174 | a5082316 | bellard | ***************************************/
|
2175 | a5082316 | bellard | |
2176 | a5082316 | bellard | static inline void invalidate_cursor1(CirrusVGAState *s) |
2177 | a5082316 | bellard | { |
2178 | a5082316 | bellard | if (s->last_hw_cursor_size) {
|
2179 | 4e12cd94 | Avi Kivity | vga_invalidate_scanlines(&s->vga, |
2180 | a5082316 | bellard | s->last_hw_cursor_y + s->last_hw_cursor_y_start, |
2181 | a5082316 | bellard | s->last_hw_cursor_y + s->last_hw_cursor_y_end); |
2182 | a5082316 | bellard | } |
2183 | a5082316 | bellard | } |
2184 | a5082316 | bellard | |
2185 | a5082316 | bellard | static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s) |
2186 | a5082316 | bellard | { |
2187 | a5082316 | bellard | const uint8_t *src;
|
2188 | a5082316 | bellard | uint32_t content; |
2189 | a5082316 | bellard | int y, y_min, y_max;
|
2190 | a5082316 | bellard | |
2191 | 4e12cd94 | Avi Kivity | src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; |
2192 | 4e12cd94 | Avi Kivity | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { |
2193 | 4e12cd94 | Avi Kivity | src += (s->vga.sr[0x13] & 0x3c) * 256; |
2194 | a5082316 | bellard | y_min = 64;
|
2195 | a5082316 | bellard | y_max = -1;
|
2196 | a5082316 | bellard | for(y = 0; y < 64; y++) { |
2197 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2198 | a5082316 | bellard | ((uint32_t *)src)[1] |
|
2199 | a5082316 | bellard | ((uint32_t *)src)[2] |
|
2200 | a5082316 | bellard | ((uint32_t *)src)[3];
|
2201 | a5082316 | bellard | if (content) {
|
2202 | a5082316 | bellard | if (y < y_min)
|
2203 | a5082316 | bellard | y_min = y; |
2204 | a5082316 | bellard | if (y > y_max)
|
2205 | a5082316 | bellard | y_max = y; |
2206 | a5082316 | bellard | } |
2207 | a5082316 | bellard | src += 16;
|
2208 | a5082316 | bellard | } |
2209 | a5082316 | bellard | } else {
|
2210 | 4e12cd94 | Avi Kivity | src += (s->vga.sr[0x13] & 0x3f) * 256; |
2211 | a5082316 | bellard | y_min = 32;
|
2212 | a5082316 | bellard | y_max = -1;
|
2213 | a5082316 | bellard | for(y = 0; y < 32; y++) { |
2214 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2215 | a5082316 | bellard | ((uint32_t *)(src + 128))[0]; |
2216 | a5082316 | bellard | if (content) {
|
2217 | a5082316 | bellard | if (y < y_min)
|
2218 | a5082316 | bellard | y_min = y; |
2219 | a5082316 | bellard | if (y > y_max)
|
2220 | a5082316 | bellard | y_max = y; |
2221 | a5082316 | bellard | } |
2222 | a5082316 | bellard | src += 4;
|
2223 | a5082316 | bellard | } |
2224 | a5082316 | bellard | } |
2225 | a5082316 | bellard | if (y_min > y_max) {
|
2226 | a5082316 | bellard | s->last_hw_cursor_y_start = 0;
|
2227 | a5082316 | bellard | s->last_hw_cursor_y_end = 0;
|
2228 | a5082316 | bellard | } else {
|
2229 | a5082316 | bellard | s->last_hw_cursor_y_start = y_min; |
2230 | a5082316 | bellard | s->last_hw_cursor_y_end = y_max + 1;
|
2231 | a5082316 | bellard | } |
2232 | a5082316 | bellard | } |
2233 | a5082316 | bellard | |
2234 | a5082316 | bellard | /* NOTE: we do not currently handle the cursor bitmap change, so we
|
2235 | a5082316 | bellard | update the cursor only if it moves. */
|
2236 | a4a2f59c | Juan Quintela | static void cirrus_cursor_invalidate(VGACommonState *s1) |
2237 | a5082316 | bellard | { |
2238 | 4e12cd94 | Avi Kivity | CirrusVGAState *s = container_of(s1, CirrusVGAState, vga); |
2239 | a5082316 | bellard | int size;
|
2240 | a5082316 | bellard | |
2241 | 4e12cd94 | Avi Kivity | if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) { |
2242 | a5082316 | bellard | size = 0;
|
2243 | a5082316 | bellard | } else {
|
2244 | 4e12cd94 | Avi Kivity | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) |
2245 | a5082316 | bellard | size = 64;
|
2246 | a5082316 | bellard | else
|
2247 | a5082316 | bellard | size = 32;
|
2248 | a5082316 | bellard | } |
2249 | a5082316 | bellard | /* invalidate last cursor and new cursor if any change */
|
2250 | a5082316 | bellard | if (s->last_hw_cursor_size != size ||
|
2251 | a5082316 | bellard | s->last_hw_cursor_x != s->hw_cursor_x || |
2252 | a5082316 | bellard | s->last_hw_cursor_y != s->hw_cursor_y) { |
2253 | a5082316 | bellard | |
2254 | a5082316 | bellard | invalidate_cursor1(s); |
2255 | 3b46e624 | ths | |
2256 | a5082316 | bellard | s->last_hw_cursor_size = size; |
2257 | a5082316 | bellard | s->last_hw_cursor_x = s->hw_cursor_x; |
2258 | a5082316 | bellard | s->last_hw_cursor_y = s->hw_cursor_y; |
2259 | a5082316 | bellard | /* compute the real cursor min and max y */
|
2260 | a5082316 | bellard | cirrus_cursor_compute_yrange(s); |
2261 | a5082316 | bellard | invalidate_cursor1(s); |
2262 | a5082316 | bellard | } |
2263 | a5082316 | bellard | } |
2264 | a5082316 | bellard | |
2265 | a4a2f59c | Juan Quintela | static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y) |
2266 | a5082316 | bellard | { |
2267 | 4e12cd94 | Avi Kivity | CirrusVGAState *s = container_of(s1, CirrusVGAState, vga); |
2268 | a5082316 | bellard | int w, h, bpp, x1, x2, poffset;
|
2269 | a5082316 | bellard | unsigned int color0, color1; |
2270 | a5082316 | bellard | const uint8_t *palette, *src;
|
2271 | a5082316 | bellard | uint32_t content; |
2272 | 3b46e624 | ths | |
2273 | 4e12cd94 | Avi Kivity | if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) |
2274 | a5082316 | bellard | return;
|
2275 | a5082316 | bellard | /* fast test to see if the cursor intersects with the scan line */
|
2276 | 4e12cd94 | Avi Kivity | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { |
2277 | a5082316 | bellard | h = 64;
|
2278 | a5082316 | bellard | } else {
|
2279 | a5082316 | bellard | h = 32;
|
2280 | a5082316 | bellard | } |
2281 | a5082316 | bellard | if (scr_y < s->hw_cursor_y ||
|
2282 | a5082316 | bellard | scr_y >= (s->hw_cursor_y + h)) |
2283 | a5082316 | bellard | return;
|
2284 | 3b46e624 | ths | |
2285 | 4e12cd94 | Avi Kivity | src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; |
2286 | 4e12cd94 | Avi Kivity | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { |
2287 | 4e12cd94 | Avi Kivity | src += (s->vga.sr[0x13] & 0x3c) * 256; |
2288 | a5082316 | bellard | src += (scr_y - s->hw_cursor_y) * 16;
|
2289 | a5082316 | bellard | poffset = 8;
|
2290 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2291 | a5082316 | bellard | ((uint32_t *)src)[1] |
|
2292 | a5082316 | bellard | ((uint32_t *)src)[2] |
|
2293 | a5082316 | bellard | ((uint32_t *)src)[3];
|
2294 | a5082316 | bellard | } else {
|
2295 | 4e12cd94 | Avi Kivity | src += (s->vga.sr[0x13] & 0x3f) * 256; |
2296 | a5082316 | bellard | src += (scr_y - s->hw_cursor_y) * 4;
|
2297 | a5082316 | bellard | poffset = 128;
|
2298 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2299 | a5082316 | bellard | ((uint32_t *)(src + 128))[0]; |
2300 | a5082316 | bellard | } |
2301 | a5082316 | bellard | /* if nothing to draw, no need to continue */
|
2302 | a5082316 | bellard | if (!content)
|
2303 | a5082316 | bellard | return;
|
2304 | a5082316 | bellard | w = h; |
2305 | a5082316 | bellard | |
2306 | a5082316 | bellard | x1 = s->hw_cursor_x; |
2307 | 4e12cd94 | Avi Kivity | if (x1 >= s->vga.last_scr_width)
|
2308 | a5082316 | bellard | return;
|
2309 | a5082316 | bellard | x2 = s->hw_cursor_x + w; |
2310 | 4e12cd94 | Avi Kivity | if (x2 > s->vga.last_scr_width)
|
2311 | 4e12cd94 | Avi Kivity | x2 = s->vga.last_scr_width; |
2312 | a5082316 | bellard | w = x2 - x1; |
2313 | a5082316 | bellard | palette = s->cirrus_hidden_palette; |
2314 | 4e12cd94 | Avi Kivity | color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]), |
2315 | 4e12cd94 | Avi Kivity | c6_to_8(palette[0x0 * 3 + 1]), |
2316 | 4e12cd94 | Avi Kivity | c6_to_8(palette[0x0 * 3 + 2])); |
2317 | 4e12cd94 | Avi Kivity | color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]), |
2318 | 4e12cd94 | Avi Kivity | c6_to_8(palette[0xf * 3 + 1]), |
2319 | 4e12cd94 | Avi Kivity | c6_to_8(palette[0xf * 3 + 2])); |
2320 | 4e12cd94 | Avi Kivity | bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3); |
2321 | a5082316 | bellard | d1 += x1 * bpp; |
2322 | 4e12cd94 | Avi Kivity | switch(ds_get_bits_per_pixel(s->vga.ds)) {
|
2323 | a5082316 | bellard | default:
|
2324 | a5082316 | bellard | break;
|
2325 | a5082316 | bellard | case 8: |
2326 | a5082316 | bellard | vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
|
2327 | a5082316 | bellard | break;
|
2328 | a5082316 | bellard | case 15: |
2329 | a5082316 | bellard | vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
|
2330 | a5082316 | bellard | break;
|
2331 | a5082316 | bellard | case 16: |
2332 | a5082316 | bellard | vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
|
2333 | a5082316 | bellard | break;
|
2334 | a5082316 | bellard | case 32: |
2335 | a5082316 | bellard | vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
|
2336 | a5082316 | bellard | break;
|
2337 | a5082316 | bellard | } |
2338 | a5082316 | bellard | } |
2339 | a5082316 | bellard | |
2340 | a5082316 | bellard | /***************************************
|
2341 | a5082316 | bellard | *
|
2342 | e6e5ad80 | bellard | * LFB memory access
|
2343 | e6e5ad80 | bellard | *
|
2344 | e6e5ad80 | bellard | ***************************************/
|
2345 | e6e5ad80 | bellard | |
2346 | c227f099 | Anthony Liguori | static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr) |
2347 | e6e5ad80 | bellard | { |
2348 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2349 | e6e5ad80 | bellard | uint32_t ret; |
2350 | e6e5ad80 | bellard | |
2351 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2352 | e6e5ad80 | bellard | |
2353 | 4e12cd94 | Avi Kivity | if (((s->vga.sr[0x17] & 0x44) == 0x44) && |
2354 | 78e127ef | bellard | ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { |
2355 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2356 | e6e5ad80 | bellard | ret = cirrus_mmio_blt_read(s, addr & 0xff);
|
2357 | e6e5ad80 | bellard | } else if (0) { |
2358 | e6e5ad80 | bellard | /* XXX handle bitblt */
|
2359 | e6e5ad80 | bellard | ret = 0xff;
|
2360 | e6e5ad80 | bellard | } else {
|
2361 | e6e5ad80 | bellard | /* video memory */
|
2362 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
2363 | e6e5ad80 | bellard | addr <<= 4;
|
2364 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
2365 | e6e5ad80 | bellard | addr <<= 3;
|
2366 | e6e5ad80 | bellard | } |
2367 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2368 | 4e12cd94 | Avi Kivity | ret = *(s->vga.vram_ptr + addr); |
2369 | e6e5ad80 | bellard | } |
2370 | e6e5ad80 | bellard | |
2371 | e6e5ad80 | bellard | return ret;
|
2372 | e6e5ad80 | bellard | } |
2373 | e6e5ad80 | bellard | |
2374 | c227f099 | Anthony Liguori | static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr) |
2375 | e6e5ad80 | bellard | { |
2376 | e6e5ad80 | bellard | uint32_t v; |
2377 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2378 | e6e5ad80 | bellard | v = cirrus_linear_readb(opaque, addr) << 8;
|
2379 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 1);
|
2380 | e6e5ad80 | bellard | #else
|
2381 | e6e5ad80 | bellard | v = cirrus_linear_readb(opaque, addr); |
2382 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 1) << 8; |
2383 | e6e5ad80 | bellard | #endif
|
2384 | e6e5ad80 | bellard | return v;
|
2385 | e6e5ad80 | bellard | } |
2386 | e6e5ad80 | bellard | |
2387 | c227f099 | Anthony Liguori | static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr) |
2388 | e6e5ad80 | bellard | { |
2389 | e6e5ad80 | bellard | uint32_t v; |
2390 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2391 | e6e5ad80 | bellard | v = cirrus_linear_readb(opaque, addr) << 24;
|
2392 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 1) << 16; |
2393 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 2) << 8; |
2394 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 3);
|
2395 | e6e5ad80 | bellard | #else
|
2396 | e6e5ad80 | bellard | v = cirrus_linear_readb(opaque, addr); |
2397 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 1) << 8; |
2398 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 2) << 16; |
2399 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 3) << 24; |
2400 | e6e5ad80 | bellard | #endif
|
2401 | e6e5ad80 | bellard | return v;
|
2402 | e6e5ad80 | bellard | } |
2403 | e6e5ad80 | bellard | |
2404 | c227f099 | Anthony Liguori | static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr, |
2405 | e6e5ad80 | bellard | uint32_t val) |
2406 | e6e5ad80 | bellard | { |
2407 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2408 | e6e5ad80 | bellard | unsigned mode;
|
2409 | e6e5ad80 | bellard | |
2410 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2411 | 3b46e624 | ths | |
2412 | 4e12cd94 | Avi Kivity | if (((s->vga.sr[0x17] & 0x44) == 0x44) && |
2413 | 78e127ef | bellard | ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { |
2414 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2415 | e6e5ad80 | bellard | cirrus_mmio_blt_write(s, addr & 0xff, val);
|
2416 | e6e5ad80 | bellard | } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { |
2417 | e6e5ad80 | bellard | /* bitblt */
|
2418 | e6e5ad80 | bellard | *s->cirrus_srcptr++ = (uint8_t) val; |
2419 | a5082316 | bellard | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
2420 | e6e5ad80 | bellard | cirrus_bitblt_cputovideo_next(s); |
2421 | e6e5ad80 | bellard | } |
2422 | e6e5ad80 | bellard | } else {
|
2423 | e6e5ad80 | bellard | /* video memory */
|
2424 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
2425 | e6e5ad80 | bellard | addr <<= 4;
|
2426 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
2427 | e6e5ad80 | bellard | addr <<= 3;
|
2428 | e6e5ad80 | bellard | } |
2429 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2430 | e6e5ad80 | bellard | |
2431 | 4e12cd94 | Avi Kivity | mode = s->vga.gr[0x05] & 0x7; |
2432 | 4e12cd94 | Avi Kivity | if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { |
2433 | 4e12cd94 | Avi Kivity | *(s->vga.vram_ptr + addr) = (uint8_t) val; |
2434 | 4e12cd94 | Avi Kivity | cpu_physical_memory_set_dirty(s->vga.vram_offset + addr); |
2435 | e6e5ad80 | bellard | } else {
|
2436 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) != 0x14) { |
2437 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val); |
2438 | e6e5ad80 | bellard | } else {
|
2439 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val); |
2440 | e6e5ad80 | bellard | } |
2441 | e6e5ad80 | bellard | } |
2442 | e6e5ad80 | bellard | } |
2443 | e6e5ad80 | bellard | } |
2444 | e6e5ad80 | bellard | |
2445 | c227f099 | Anthony Liguori | static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr, |
2446 | e6e5ad80 | bellard | uint32_t val) |
2447 | e6e5ad80 | bellard | { |
2448 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2449 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff); |
2450 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 1, val & 0xff); |
2451 | e6e5ad80 | bellard | #else
|
2452 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr, val & 0xff);
|
2453 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2454 | e6e5ad80 | bellard | #endif
|
2455 | e6e5ad80 | bellard | } |
2456 | e6e5ad80 | bellard | |
2457 | c227f099 | Anthony Liguori | static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr, |
2458 | e6e5ad80 | bellard | uint32_t val) |
2459 | e6e5ad80 | bellard | { |
2460 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2461 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff); |
2462 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
2463 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
2464 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 3, val & 0xff); |
2465 | e6e5ad80 | bellard | #else
|
2466 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr, val & 0xff);
|
2467 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2468 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2469 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2470 | e6e5ad80 | bellard | #endif
|
2471 | e6e5ad80 | bellard | } |
2472 | e6e5ad80 | bellard | |
2473 | e6e5ad80 | bellard | |
2474 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const cirrus_linear_read[3] = { |
2475 | e6e5ad80 | bellard | cirrus_linear_readb, |
2476 | e6e5ad80 | bellard | cirrus_linear_readw, |
2477 | e6e5ad80 | bellard | cirrus_linear_readl, |
2478 | e6e5ad80 | bellard | }; |
2479 | e6e5ad80 | bellard | |
2480 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const cirrus_linear_write[3] = { |
2481 | e6e5ad80 | bellard | cirrus_linear_writeb, |
2482 | e6e5ad80 | bellard | cirrus_linear_writew, |
2483 | e6e5ad80 | bellard | cirrus_linear_writel, |
2484 | e6e5ad80 | bellard | }; |
2485 | e6e5ad80 | bellard | |
2486 | a5082316 | bellard | /***************************************
|
2487 | a5082316 | bellard | *
|
2488 | a5082316 | bellard | * system to screen memory access
|
2489 | a5082316 | bellard | *
|
2490 | a5082316 | bellard | ***************************************/
|
2491 | a5082316 | bellard | |
2492 | a5082316 | bellard | |
2493 | c227f099 | Anthony Liguori | static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr) |
2494 | a5082316 | bellard | { |
2495 | a5082316 | bellard | uint32_t ret; |
2496 | a5082316 | bellard | |
2497 | a5082316 | bellard | /* XXX handle bitblt */
|
2498 | a5082316 | bellard | ret = 0xff;
|
2499 | a5082316 | bellard | return ret;
|
2500 | a5082316 | bellard | } |
2501 | a5082316 | bellard | |
2502 | c227f099 | Anthony Liguori | static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr) |
2503 | a5082316 | bellard | { |
2504 | a5082316 | bellard | uint32_t v; |
2505 | a5082316 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2506 | a5082316 | bellard | v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
|
2507 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
|
2508 | a5082316 | bellard | #else
|
2509 | a5082316 | bellard | v = cirrus_linear_bitblt_readb(opaque, addr); |
2510 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8; |
2511 | a5082316 | bellard | #endif
|
2512 | a5082316 | bellard | return v;
|
2513 | a5082316 | bellard | } |
2514 | a5082316 | bellard | |
2515 | c227f099 | Anthony Liguori | static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr) |
2516 | a5082316 | bellard | { |
2517 | a5082316 | bellard | uint32_t v; |
2518 | a5082316 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2519 | a5082316 | bellard | v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
|
2520 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16; |
2521 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8; |
2522 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
|
2523 | a5082316 | bellard | #else
|
2524 | a5082316 | bellard | v = cirrus_linear_bitblt_readb(opaque, addr); |
2525 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8; |
2526 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16; |
2527 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24; |
2528 | a5082316 | bellard | #endif
|
2529 | a5082316 | bellard | return v;
|
2530 | a5082316 | bellard | } |
2531 | a5082316 | bellard | |
2532 | c227f099 | Anthony Liguori | static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr, |
2533 | a5082316 | bellard | uint32_t val) |
2534 | a5082316 | bellard | { |
2535 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2536 | a5082316 | bellard | |
2537 | a5082316 | bellard | if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
|
2538 | a5082316 | bellard | /* bitblt */
|
2539 | a5082316 | bellard | *s->cirrus_srcptr++ = (uint8_t) val; |
2540 | a5082316 | bellard | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
2541 | a5082316 | bellard | cirrus_bitblt_cputovideo_next(s); |
2542 | a5082316 | bellard | } |
2543 | a5082316 | bellard | } |
2544 | a5082316 | bellard | } |
2545 | a5082316 | bellard | |
2546 | c227f099 | Anthony Liguori | static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr, |
2547 | a5082316 | bellard | uint32_t val) |
2548 | a5082316 | bellard | { |
2549 | a5082316 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2550 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff); |
2551 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff); |
2552 | a5082316 | bellard | #else
|
2553 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
|
2554 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2555 | a5082316 | bellard | #endif
|
2556 | a5082316 | bellard | } |
2557 | a5082316 | bellard | |
2558 | c227f099 | Anthony Liguori | static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr, |
2559 | a5082316 | bellard | uint32_t val) |
2560 | a5082316 | bellard | { |
2561 | a5082316 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2562 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff); |
2563 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
2564 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
2565 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff); |
2566 | a5082316 | bellard | #else
|
2567 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
|
2568 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2569 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2570 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2571 | a5082316 | bellard | #endif
|
2572 | a5082316 | bellard | } |
2573 | a5082316 | bellard | |
2574 | a5082316 | bellard | |
2575 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const cirrus_linear_bitblt_read[3] = { |
2576 | a5082316 | bellard | cirrus_linear_bitblt_readb, |
2577 | a5082316 | bellard | cirrus_linear_bitblt_readw, |
2578 | a5082316 | bellard | cirrus_linear_bitblt_readl, |
2579 | a5082316 | bellard | }; |
2580 | a5082316 | bellard | |
2581 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const cirrus_linear_bitblt_write[3] = { |
2582 | a5082316 | bellard | cirrus_linear_bitblt_writeb, |
2583 | a5082316 | bellard | cirrus_linear_bitblt_writew, |
2584 | a5082316 | bellard | cirrus_linear_bitblt_writel, |
2585 | a5082316 | bellard | }; |
2586 | a5082316 | bellard | |
2587 | 2bec46dc | aliguori | static void map_linear_vram(CirrusVGAState *s) |
2588 | 2bec46dc | aliguori | { |
2589 | 4e12cd94 | Avi Kivity | if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
|
2590 | 4e12cd94 | Avi Kivity | s->vga.map_addr = s->vga.lfb_addr; |
2591 | 4e12cd94 | Avi Kivity | s->vga.map_end = s->vga.lfb_end; |
2592 | 4e12cd94 | Avi Kivity | cpu_register_physical_memory(s->vga.map_addr, s->vga.map_end - s->vga.map_addr, s->vga.vram_offset); |
2593 | 2bec46dc | aliguori | } |
2594 | 2bec46dc | aliguori | |
2595 | 4e12cd94 | Avi Kivity | if (!s->vga.map_addr)
|
2596 | 2bec46dc | aliguori | return;
|
2597 | 2bec46dc | aliguori | |
2598 | 4e12cd94 | Avi Kivity | s->vga.lfb_vram_mapped = 0;
|
2599 | 2bec46dc | aliguori | |
2600 | 2bec46dc | aliguori | if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
|
2601 | 4e12cd94 | Avi Kivity | && !((s->vga.sr[0x07] & 0x01) == 0) |
2602 | 4e12cd94 | Avi Kivity | && !((s->vga.gr[0x0B] & 0x14) == 0x14) |
2603 | 4e12cd94 | Avi Kivity | && !(s->vga.gr[0x0B] & 0x02)) { |
2604 | 2bec46dc | aliguori | |
2605 | 2bec46dc | aliguori | cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000, |
2606 | 4e12cd94 | Avi Kivity | (s->vga.vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
|
2607 | 2bec46dc | aliguori | cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000, |
2608 | 4e12cd94 | Avi Kivity | (s->vga.vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
|
2609 | 2bec46dc | aliguori | |
2610 | 4e12cd94 | Avi Kivity | s->vga.lfb_vram_mapped = 1;
|
2611 | 2bec46dc | aliguori | } |
2612 | 2bec46dc | aliguori | else {
|
2613 | 7cff316e | aliguori | cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000, |
2614 | 4e12cd94 | Avi Kivity | s->vga.vga_io_memory); |
2615 | 2bec46dc | aliguori | } |
2616 | 2bec46dc | aliguori | |
2617 | 4e12cd94 | Avi Kivity | vga_dirty_log_start(&s->vga); |
2618 | 2bec46dc | aliguori | } |
2619 | 2bec46dc | aliguori | |
2620 | 2bec46dc | aliguori | static void unmap_linear_vram(CirrusVGAState *s) |
2621 | 2bec46dc | aliguori | { |
2622 | 4e12cd94 | Avi Kivity | if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end)
|
2623 | 4e12cd94 | Avi Kivity | s->vga.map_addr = s->vga.map_end = 0;
|
2624 | 2bec46dc | aliguori | |
2625 | 2bec46dc | aliguori | cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000, |
2626 | 4e12cd94 | Avi Kivity | s->vga.vga_io_memory); |
2627 | 2bec46dc | aliguori | } |
2628 | 2bec46dc | aliguori | |
2629 | 8926b517 | bellard | /* Compute the memory access functions */
|
2630 | 8926b517 | bellard | static void cirrus_update_memory_access(CirrusVGAState *s) |
2631 | 8926b517 | bellard | { |
2632 | 8926b517 | bellard | unsigned mode;
|
2633 | 8926b517 | bellard | |
2634 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x17] & 0x44) == 0x44) { |
2635 | 8926b517 | bellard | goto generic_io;
|
2636 | 8926b517 | bellard | } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { |
2637 | 8926b517 | bellard | goto generic_io;
|
2638 | 8926b517 | bellard | } else {
|
2639 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
2640 | 8926b517 | bellard | goto generic_io;
|
2641 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
2642 | 8926b517 | bellard | goto generic_io;
|
2643 | 8926b517 | bellard | } |
2644 | 3b46e624 | ths | |
2645 | 4e12cd94 | Avi Kivity | mode = s->vga.gr[0x05] & 0x7; |
2646 | 4e12cd94 | Avi Kivity | if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { |
2647 | 2bec46dc | aliguori | map_linear_vram(s); |
2648 | 8926b517 | bellard | } else {
|
2649 | 8926b517 | bellard | generic_io:
|
2650 | 2bec46dc | aliguori | unmap_linear_vram(s); |
2651 | 8926b517 | bellard | } |
2652 | 8926b517 | bellard | } |
2653 | 8926b517 | bellard | } |
2654 | 8926b517 | bellard | |
2655 | 8926b517 | bellard | |
2656 | e6e5ad80 | bellard | /* I/O ports */
|
2657 | e6e5ad80 | bellard | |
2658 | 0ceac75b | Juan Quintela | static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr) |
2659 | e6e5ad80 | bellard | { |
2660 | b6343073 | Juan Quintela | CirrusVGAState *c = opaque; |
2661 | b6343073 | Juan Quintela | VGACommonState *s = &c->vga; |
2662 | e6e5ad80 | bellard | int val, index;
|
2663 | e6e5ad80 | bellard | |
2664 | b6343073 | Juan Quintela | if (vga_ioport_invalid(s, addr)) {
|
2665 | e6e5ad80 | bellard | val = 0xff;
|
2666 | e6e5ad80 | bellard | } else {
|
2667 | e6e5ad80 | bellard | switch (addr) {
|
2668 | e6e5ad80 | bellard | case 0x3c0: |
2669 | b6343073 | Juan Quintela | if (s->ar_flip_flop == 0) { |
2670 | b6343073 | Juan Quintela | val = s->ar_index; |
2671 | e6e5ad80 | bellard | } else {
|
2672 | e6e5ad80 | bellard | val = 0;
|
2673 | e6e5ad80 | bellard | } |
2674 | e6e5ad80 | bellard | break;
|
2675 | e6e5ad80 | bellard | case 0x3c1: |
2676 | b6343073 | Juan Quintela | index = s->ar_index & 0x1f;
|
2677 | e6e5ad80 | bellard | if (index < 21) |
2678 | b6343073 | Juan Quintela | val = s->ar[index]; |
2679 | e6e5ad80 | bellard | else
|
2680 | e6e5ad80 | bellard | val = 0;
|
2681 | e6e5ad80 | bellard | break;
|
2682 | e6e5ad80 | bellard | case 0x3c2: |
2683 | b6343073 | Juan Quintela | val = s->st00; |
2684 | e6e5ad80 | bellard | break;
|
2685 | e6e5ad80 | bellard | case 0x3c4: |
2686 | b6343073 | Juan Quintela | val = s->sr_index; |
2687 | e6e5ad80 | bellard | break;
|
2688 | e6e5ad80 | bellard | case 0x3c5: |
2689 | 8a82c322 | Juan Quintela | val = cirrus_vga_read_sr(c); |
2690 | 8a82c322 | Juan Quintela | break;
|
2691 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2692 | b6343073 | Juan Quintela | printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
|
2693 | e6e5ad80 | bellard | #endif
|
2694 | e6e5ad80 | bellard | break;
|
2695 | e6e5ad80 | bellard | case 0x3c6: |
2696 | 957c9db5 | Juan Quintela | val = cirrus_read_hidden_dac(c); |
2697 | e6e5ad80 | bellard | break;
|
2698 | e6e5ad80 | bellard | case 0x3c7: |
2699 | b6343073 | Juan Quintela | val = s->dac_state; |
2700 | e6e5ad80 | bellard | break;
|
2701 | ae184e4a | bellard | case 0x3c8: |
2702 | b6343073 | Juan Quintela | val = s->dac_write_index; |
2703 | b6343073 | Juan Quintela | c->cirrus_hidden_dac_lockindex = 0;
|
2704 | ae184e4a | bellard | break;
|
2705 | ae184e4a | bellard | case 0x3c9: |
2706 | 5deaeee3 | Juan Quintela | val = cirrus_vga_read_palette(c); |
2707 | 5deaeee3 | Juan Quintela | break;
|
2708 | e6e5ad80 | bellard | case 0x3ca: |
2709 | b6343073 | Juan Quintela | val = s->fcr; |
2710 | e6e5ad80 | bellard | break;
|
2711 | e6e5ad80 | bellard | case 0x3cc: |
2712 | b6343073 | Juan Quintela | val = s->msr; |
2713 | e6e5ad80 | bellard | break;
|
2714 | e6e5ad80 | bellard | case 0x3ce: |
2715 | b6343073 | Juan Quintela | val = s->gr_index; |
2716 | e6e5ad80 | bellard | break;
|
2717 | e6e5ad80 | bellard | case 0x3cf: |
2718 | f705db9d | Juan Quintela | val = cirrus_vga_read_gr(c, s->gr_index); |
2719 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2720 | b6343073 | Juan Quintela | printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
|
2721 | e6e5ad80 | bellard | #endif
|
2722 | e6e5ad80 | bellard | break;
|
2723 | e6e5ad80 | bellard | case 0x3b4: |
2724 | e6e5ad80 | bellard | case 0x3d4: |
2725 | b6343073 | Juan Quintela | val = s->cr_index; |
2726 | e6e5ad80 | bellard | break;
|
2727 | e6e5ad80 | bellard | case 0x3b5: |
2728 | e6e5ad80 | bellard | case 0x3d5: |
2729 | b863d514 | Juan Quintela | val = cirrus_vga_read_cr(c, s->cr_index); |
2730 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2731 | b6343073 | Juan Quintela | printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
|
2732 | e6e5ad80 | bellard | #endif
|
2733 | e6e5ad80 | bellard | break;
|
2734 | e6e5ad80 | bellard | case 0x3ba: |
2735 | e6e5ad80 | bellard | case 0x3da: |
2736 | e6e5ad80 | bellard | /* just toggle to fool polling */
|
2737 | b6343073 | Juan Quintela | val = s->st01 = s->retrace(s); |
2738 | b6343073 | Juan Quintela | s->ar_flip_flop = 0;
|
2739 | e6e5ad80 | bellard | break;
|
2740 | e6e5ad80 | bellard | default:
|
2741 | e6e5ad80 | bellard | val = 0x00;
|
2742 | e6e5ad80 | bellard | break;
|
2743 | e6e5ad80 | bellard | } |
2744 | e6e5ad80 | bellard | } |
2745 | e6e5ad80 | bellard | #if defined(DEBUG_VGA)
|
2746 | e6e5ad80 | bellard | printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
|
2747 | e6e5ad80 | bellard | #endif
|
2748 | e6e5ad80 | bellard | return val;
|
2749 | e6e5ad80 | bellard | } |
2750 | e6e5ad80 | bellard | |
2751 | 0ceac75b | Juan Quintela | static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
2752 | e6e5ad80 | bellard | { |
2753 | b6343073 | Juan Quintela | CirrusVGAState *c = opaque; |
2754 | b6343073 | Juan Quintela | VGACommonState *s = &c->vga; |
2755 | e6e5ad80 | bellard | int index;
|
2756 | e6e5ad80 | bellard | |
2757 | e6e5ad80 | bellard | /* check port range access depending on color/monochrome mode */
|
2758 | b6343073 | Juan Quintela | if (vga_ioport_invalid(s, addr)) {
|
2759 | e6e5ad80 | bellard | return;
|
2760 | 25a18cbd | Juan Quintela | } |
2761 | e6e5ad80 | bellard | #ifdef DEBUG_VGA
|
2762 | e6e5ad80 | bellard | printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
|
2763 | e6e5ad80 | bellard | #endif
|
2764 | e6e5ad80 | bellard | |
2765 | e6e5ad80 | bellard | switch (addr) {
|
2766 | e6e5ad80 | bellard | case 0x3c0: |
2767 | b6343073 | Juan Quintela | if (s->ar_flip_flop == 0) { |
2768 | e6e5ad80 | bellard | val &= 0x3f;
|
2769 | b6343073 | Juan Quintela | s->ar_index = val; |
2770 | e6e5ad80 | bellard | } else {
|
2771 | b6343073 | Juan Quintela | index = s->ar_index & 0x1f;
|
2772 | e6e5ad80 | bellard | switch (index) {
|
2773 | e6e5ad80 | bellard | case 0x00 ... 0x0f: |
2774 | b6343073 | Juan Quintela | s->ar[index] = val & 0x3f;
|
2775 | e6e5ad80 | bellard | break;
|
2776 | e6e5ad80 | bellard | case 0x10: |
2777 | b6343073 | Juan Quintela | s->ar[index] = val & ~0x10;
|
2778 | e6e5ad80 | bellard | break;
|
2779 | e6e5ad80 | bellard | case 0x11: |
2780 | b6343073 | Juan Quintela | s->ar[index] = val; |
2781 | e6e5ad80 | bellard | break;
|
2782 | e6e5ad80 | bellard | case 0x12: |
2783 | b6343073 | Juan Quintela | s->ar[index] = val & ~0xc0;
|
2784 | e6e5ad80 | bellard | break;
|
2785 | e6e5ad80 | bellard | case 0x13: |
2786 | b6343073 | Juan Quintela | s->ar[index] = val & ~0xf0;
|
2787 | e6e5ad80 | bellard | break;
|
2788 | e6e5ad80 | bellard | case 0x14: |
2789 | b6343073 | Juan Quintela | s->ar[index] = val & ~0xf0;
|
2790 | e6e5ad80 | bellard | break;
|
2791 | e6e5ad80 | bellard | default:
|
2792 | e6e5ad80 | bellard | break;
|
2793 | e6e5ad80 | bellard | } |
2794 | e6e5ad80 | bellard | } |
2795 | b6343073 | Juan Quintela | s->ar_flip_flop ^= 1;
|
2796 | e6e5ad80 | bellard | break;
|
2797 | e6e5ad80 | bellard | case 0x3c2: |
2798 | b6343073 | Juan Quintela | s->msr = val & ~0x10;
|
2799 | b6343073 | Juan Quintela | s->update_retrace_info(s); |
2800 | e6e5ad80 | bellard | break;
|
2801 | e6e5ad80 | bellard | case 0x3c4: |
2802 | b6343073 | Juan Quintela | s->sr_index = val; |
2803 | e6e5ad80 | bellard | break;
|
2804 | e6e5ad80 | bellard | case 0x3c5: |
2805 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2806 | b6343073 | Juan Quintela | printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
|
2807 | e6e5ad80 | bellard | #endif
|
2808 | 31c63201 | Juan Quintela | cirrus_vga_write_sr(c, val); |
2809 | 31c63201 | Juan Quintela | break;
|
2810 | e6e5ad80 | bellard | break;
|
2811 | e6e5ad80 | bellard | case 0x3c6: |
2812 | b6343073 | Juan Quintela | cirrus_write_hidden_dac(c, val); |
2813 | e6e5ad80 | bellard | break;
|
2814 | e6e5ad80 | bellard | case 0x3c7: |
2815 | b6343073 | Juan Quintela | s->dac_read_index = val; |
2816 | b6343073 | Juan Quintela | s->dac_sub_index = 0;
|
2817 | b6343073 | Juan Quintela | s->dac_state = 3;
|
2818 | e6e5ad80 | bellard | break;
|
2819 | e6e5ad80 | bellard | case 0x3c8: |
2820 | b6343073 | Juan Quintela | s->dac_write_index = val; |
2821 | b6343073 | Juan Quintela | s->dac_sub_index = 0;
|
2822 | b6343073 | Juan Quintela | s->dac_state = 0;
|
2823 | e6e5ad80 | bellard | break;
|
2824 | e6e5ad80 | bellard | case 0x3c9: |
2825 | 86948bb1 | Juan Quintela | cirrus_vga_write_palette(c, val); |
2826 | 86948bb1 | Juan Quintela | break;
|
2827 | e6e5ad80 | bellard | case 0x3ce: |
2828 | b6343073 | Juan Quintela | s->gr_index = val; |
2829 | e6e5ad80 | bellard | break;
|
2830 | e6e5ad80 | bellard | case 0x3cf: |
2831 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2832 | b6343073 | Juan Quintela | printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
|
2833 | e6e5ad80 | bellard | #endif
|
2834 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(c, s->gr_index, val); |
2835 | e6e5ad80 | bellard | break;
|
2836 | e6e5ad80 | bellard | case 0x3b4: |
2837 | e6e5ad80 | bellard | case 0x3d4: |
2838 | b6343073 | Juan Quintela | s->cr_index = val; |
2839 | e6e5ad80 | bellard | break;
|
2840 | e6e5ad80 | bellard | case 0x3b5: |
2841 | e6e5ad80 | bellard | case 0x3d5: |
2842 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2843 | b6343073 | Juan Quintela | printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
|
2844 | e6e5ad80 | bellard | #endif
|
2845 | 4ec1ce04 | Juan Quintela | cirrus_vga_write_cr(c, val); |
2846 | e6e5ad80 | bellard | break;
|
2847 | e6e5ad80 | bellard | case 0x3ba: |
2848 | e6e5ad80 | bellard | case 0x3da: |
2849 | b6343073 | Juan Quintela | s->fcr = val & 0x10;
|
2850 | e6e5ad80 | bellard | break;
|
2851 | e6e5ad80 | bellard | } |
2852 | e6e5ad80 | bellard | } |
2853 | e6e5ad80 | bellard | |
2854 | e6e5ad80 | bellard | /***************************************
|
2855 | e6e5ad80 | bellard | *
|
2856 | e36f36e1 | bellard | * memory-mapped I/O access
|
2857 | e36f36e1 | bellard | *
|
2858 | e36f36e1 | bellard | ***************************************/
|
2859 | e36f36e1 | bellard | |
2860 | c227f099 | Anthony Liguori | static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr) |
2861 | e36f36e1 | bellard | { |
2862 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2863 | e36f36e1 | bellard | |
2864 | e36f36e1 | bellard | addr &= CIRRUS_PNPMMIO_SIZE - 1;
|
2865 | e36f36e1 | bellard | |
2866 | e36f36e1 | bellard | if (addr >= 0x100) { |
2867 | e36f36e1 | bellard | return cirrus_mmio_blt_read(s, addr - 0x100); |
2868 | e36f36e1 | bellard | } else {
|
2869 | 0ceac75b | Juan Quintela | return cirrus_vga_ioport_read(s, addr + 0x3c0); |
2870 | e36f36e1 | bellard | } |
2871 | e36f36e1 | bellard | } |
2872 | e36f36e1 | bellard | |
2873 | c227f099 | Anthony Liguori | static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr) |
2874 | e36f36e1 | bellard | { |
2875 | e36f36e1 | bellard | uint32_t v; |
2876 | e36f36e1 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2877 | e36f36e1 | bellard | v = cirrus_mmio_readb(opaque, addr) << 8;
|
2878 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 1);
|
2879 | e36f36e1 | bellard | #else
|
2880 | e36f36e1 | bellard | v = cirrus_mmio_readb(opaque, addr); |
2881 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 1) << 8; |
2882 | e36f36e1 | bellard | #endif
|
2883 | e36f36e1 | bellard | return v;
|
2884 | e36f36e1 | bellard | } |
2885 | e36f36e1 | bellard | |
2886 | c227f099 | Anthony Liguori | static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr) |
2887 | e36f36e1 | bellard | { |
2888 | e36f36e1 | bellard | uint32_t v; |
2889 | e36f36e1 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2890 | e36f36e1 | bellard | v = cirrus_mmio_readb(opaque, addr) << 24;
|
2891 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 1) << 16; |
2892 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 2) << 8; |
2893 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 3);
|
2894 | e36f36e1 | bellard | #else
|
2895 | e36f36e1 | bellard | v = cirrus_mmio_readb(opaque, addr); |
2896 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 1) << 8; |
2897 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 2) << 16; |
2898 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 3) << 24; |
2899 | e36f36e1 | bellard | #endif
|
2900 | e36f36e1 | bellard | return v;
|
2901 | e36f36e1 | bellard | } |
2902 | e36f36e1 | bellard | |
2903 | c227f099 | Anthony Liguori | static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr, |
2904 | e36f36e1 | bellard | uint32_t val) |
2905 | e36f36e1 | bellard | { |
2906 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2907 | e36f36e1 | bellard | |
2908 | e36f36e1 | bellard | addr &= CIRRUS_PNPMMIO_SIZE - 1;
|
2909 | e36f36e1 | bellard | |
2910 | e36f36e1 | bellard | if (addr >= 0x100) { |
2911 | e36f36e1 | bellard | cirrus_mmio_blt_write(s, addr - 0x100, val);
|
2912 | e36f36e1 | bellard | } else {
|
2913 | 0ceac75b | Juan Quintela | cirrus_vga_ioport_write(s, addr + 0x3c0, val);
|
2914 | e36f36e1 | bellard | } |
2915 | e36f36e1 | bellard | } |
2916 | e36f36e1 | bellard | |
2917 | c227f099 | Anthony Liguori | static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr, |
2918 | e36f36e1 | bellard | uint32_t val) |
2919 | e36f36e1 | bellard | { |
2920 | e36f36e1 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2921 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff); |
2922 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 1, val & 0xff); |
2923 | e36f36e1 | bellard | #else
|
2924 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr, val & 0xff);
|
2925 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2926 | e36f36e1 | bellard | #endif
|
2927 | e36f36e1 | bellard | } |
2928 | e36f36e1 | bellard | |
2929 | c227f099 | Anthony Liguori | static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr, |
2930 | e36f36e1 | bellard | uint32_t val) |
2931 | e36f36e1 | bellard | { |
2932 | e36f36e1 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2933 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff); |
2934 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
2935 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
2936 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 3, val & 0xff); |
2937 | e36f36e1 | bellard | #else
|
2938 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr, val & 0xff);
|
2939 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2940 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2941 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2942 | e36f36e1 | bellard | #endif
|
2943 | e36f36e1 | bellard | } |
2944 | e36f36e1 | bellard | |
2945 | e36f36e1 | bellard | |
2946 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const cirrus_mmio_read[3] = { |
2947 | e36f36e1 | bellard | cirrus_mmio_readb, |
2948 | e36f36e1 | bellard | cirrus_mmio_readw, |
2949 | e36f36e1 | bellard | cirrus_mmio_readl, |
2950 | e36f36e1 | bellard | }; |
2951 | e36f36e1 | bellard | |
2952 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const cirrus_mmio_write[3] = { |
2953 | e36f36e1 | bellard | cirrus_mmio_writeb, |
2954 | e36f36e1 | bellard | cirrus_mmio_writew, |
2955 | e36f36e1 | bellard | cirrus_mmio_writel, |
2956 | e36f36e1 | bellard | }; |
2957 | e36f36e1 | bellard | |
2958 | 2c6ab832 | bellard | /* load/save state */
|
2959 | 2c6ab832 | bellard | |
2960 | e59fb374 | Juan Quintela | static int cirrus_post_load(void *opaque, int version_id) |
2961 | 2c6ab832 | bellard | { |
2962 | 2c6ab832 | bellard | CirrusVGAState *s = opaque; |
2963 | 2c6ab832 | bellard | |
2964 | 4e12cd94 | Avi Kivity | s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f; |
2965 | 4e12cd94 | Avi Kivity | s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f; |
2966 | 2c6ab832 | bellard | |
2967 | 2bec46dc | aliguori | cirrus_update_memory_access(s); |
2968 | 2c6ab832 | bellard | /* force refresh */
|
2969 | 4e12cd94 | Avi Kivity | s->vga.graphic_mode = -1;
|
2970 | 2c6ab832 | bellard | cirrus_update_bank_ptr(s, 0);
|
2971 | 2c6ab832 | bellard | cirrus_update_bank_ptr(s, 1);
|
2972 | 2c6ab832 | bellard | return 0; |
2973 | 2c6ab832 | bellard | } |
2974 | 2c6ab832 | bellard | |
2975 | 7e72abc3 | Juan Quintela | static const VMStateDescription vmstate_cirrus_vga = { |
2976 | 7e72abc3 | Juan Quintela | .name = "cirrus_vga",
|
2977 | 7e72abc3 | Juan Quintela | .version_id = 2,
|
2978 | 7e72abc3 | Juan Quintela | .minimum_version_id = 1,
|
2979 | 7e72abc3 | Juan Quintela | .minimum_version_id_old = 1,
|
2980 | 7e72abc3 | Juan Quintela | .post_load = cirrus_post_load, |
2981 | 7e72abc3 | Juan Quintela | .fields = (VMStateField []) { |
2982 | 7e72abc3 | Juan Quintela | VMSTATE_UINT32(vga.latch, CirrusVGAState), |
2983 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.sr_index, CirrusVGAState), |
2984 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.sr, CirrusVGAState), |
2985 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.gr_index, CirrusVGAState), |
2986 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState), |
2987 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState), |
2988 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
|
2989 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.ar_index, CirrusVGAState), |
2990 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.ar, CirrusVGAState), |
2991 | 7e72abc3 | Juan Quintela | VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState), |
2992 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.cr_index, CirrusVGAState), |
2993 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.cr, CirrusVGAState), |
2994 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.msr, CirrusVGAState), |
2995 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.fcr, CirrusVGAState), |
2996 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.st00, CirrusVGAState), |
2997 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.st01, CirrusVGAState), |
2998 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.dac_state, CirrusVGAState), |
2999 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState), |
3000 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState), |
3001 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState), |
3002 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState), |
3003 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.palette, CirrusVGAState), |
3004 | 7e72abc3 | Juan Quintela | VMSTATE_INT32(vga.bank_offset, CirrusVGAState), |
3005 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState), |
3006 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState), |
3007 | 7e72abc3 | Juan Quintela | VMSTATE_UINT32(hw_cursor_x, CirrusVGAState), |
3008 | 7e72abc3 | Juan Quintela | VMSTATE_UINT32(hw_cursor_y, CirrusVGAState), |
3009 | 7e72abc3 | Juan Quintela | /* XXX: we do not save the bitblt state - we assume we do not save
|
3010 | 7e72abc3 | Juan Quintela | the state when the blitter is active */
|
3011 | 7e72abc3 | Juan Quintela | VMSTATE_END_OF_LIST() |
3012 | 4f335feb | Juan Quintela | } |
3013 | 7e72abc3 | Juan Quintela | }; |
3014 | 4f335feb | Juan Quintela | |
3015 | 7e72abc3 | Juan Quintela | static const VMStateDescription vmstate_pci_cirrus_vga = { |
3016 | 7e72abc3 | Juan Quintela | .name = "cirrus_vga",
|
3017 | 7e72abc3 | Juan Quintela | .version_id = 2,
|
3018 | 7e72abc3 | Juan Quintela | .minimum_version_id = 2,
|
3019 | 7e72abc3 | Juan Quintela | .minimum_version_id_old = 2,
|
3020 | 7e72abc3 | Juan Quintela | .post_load = cirrus_post_load, |
3021 | 7e72abc3 | Juan Quintela | .fields = (VMStateField []) { |
3022 | 7e72abc3 | Juan Quintela | VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState), |
3023 | 7e72abc3 | Juan Quintela | VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
|
3024 | 7e72abc3 | Juan Quintela | vmstate_cirrus_vga, CirrusVGAState), |
3025 | 7e72abc3 | Juan Quintela | VMSTATE_END_OF_LIST() |
3026 | 7e72abc3 | Juan Quintela | } |
3027 | 7e72abc3 | Juan Quintela | }; |
3028 | 4f335feb | Juan Quintela | |
3029 | e36f36e1 | bellard | /***************************************
|
3030 | e36f36e1 | bellard | *
|
3031 | e6e5ad80 | bellard | * initialize
|
3032 | e6e5ad80 | bellard | *
|
3033 | e6e5ad80 | bellard | ***************************************/
|
3034 | e6e5ad80 | bellard | |
3035 | 4abc796d | blueswir1 | static void cirrus_reset(void *opaque) |
3036 | e6e5ad80 | bellard | { |
3037 | 4abc796d | blueswir1 | CirrusVGAState *s = opaque; |
3038 | e6e5ad80 | bellard | |
3039 | 03a3e7ba | Juan Quintela | vga_common_reset(&s->vga); |
3040 | ee50c6bc | aliguori | unmap_linear_vram(s); |
3041 | 4e12cd94 | Avi Kivity | s->vga.sr[0x06] = 0x0f; |
3042 | 4abc796d | blueswir1 | if (s->device_id == CIRRUS_ID_CLGD5446) {
|
3043 | 78e127ef | bellard | /* 4MB 64 bit memory config, always PCI */
|
3044 | 4e12cd94 | Avi Kivity | s->vga.sr[0x1F] = 0x2d; // MemClock |
3045 | 4e12cd94 | Avi Kivity | s->vga.gr[0x18] = 0x0f; // fastest memory configuration |
3046 | 4e12cd94 | Avi Kivity | s->vga.sr[0x0f] = 0x98; |
3047 | 4e12cd94 | Avi Kivity | s->vga.sr[0x17] = 0x20; |
3048 | 4e12cd94 | Avi Kivity | s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */ |
3049 | 78e127ef | bellard | } else {
|
3050 | 4e12cd94 | Avi Kivity | s->vga.sr[0x1F] = 0x22; // MemClock |
3051 | 4e12cd94 | Avi Kivity | s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
|
3052 | 4e12cd94 | Avi Kivity | s->vga.sr[0x17] = s->bustype;
|
3053 | 4e12cd94 | Avi Kivity | s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */ |
3054 | 78e127ef | bellard | } |
3055 | 4e12cd94 | Avi Kivity | s->vga.cr[0x27] = s->device_id;
|
3056 | e6e5ad80 | bellard | |
3057 | 78e127ef | bellard | /* Win2K seems to assume that the pattern buffer is at 0xff
|
3058 | 78e127ef | bellard | initially ! */
|
3059 | 4e12cd94 | Avi Kivity | memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
|
3060 | 78e127ef | bellard | |
3061 | e6e5ad80 | bellard | s->cirrus_hidden_dac_lockindex = 5;
|
3062 | e6e5ad80 | bellard | s->cirrus_hidden_dac_data = 0;
|
3063 | 4abc796d | blueswir1 | } |
3064 | 4abc796d | blueswir1 | |
3065 | 4abc796d | blueswir1 | static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci) |
3066 | 4abc796d | blueswir1 | { |
3067 | 4abc796d | blueswir1 | int i;
|
3068 | 4abc796d | blueswir1 | static int inited; |
3069 | 4abc796d | blueswir1 | |
3070 | 4abc796d | blueswir1 | if (!inited) {
|
3071 | 4abc796d | blueswir1 | inited = 1;
|
3072 | 4abc796d | blueswir1 | for(i = 0;i < 256; i++) |
3073 | 4abc796d | blueswir1 | rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
|
3074 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_0] = 0;
|
3075 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
|
3076 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOP] = 2;
|
3077 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
|
3078 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTDST] = 4;
|
3079 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC] = 5;
|
3080 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_1] = 6;
|
3081 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
|
3082 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
|
3083 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
|
3084 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
|
3085 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
|
3086 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
|
3087 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
|
3088 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
|
3089 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
|
3090 | 4abc796d | blueswir1 | s->device_id = device_id; |
3091 | 4abc796d | blueswir1 | if (is_pci)
|
3092 | 4abc796d | blueswir1 | s->bustype = CIRRUS_BUSTYPE_PCI; |
3093 | 4abc796d | blueswir1 | else
|
3094 | 4abc796d | blueswir1 | s->bustype = CIRRUS_BUSTYPE_ISA; |
3095 | 4abc796d | blueswir1 | } |
3096 | 4abc796d | blueswir1 | |
3097 | 0ceac75b | Juan Quintela | register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s); |
3098 | 4abc796d | blueswir1 | |
3099 | 0ceac75b | Juan Quintela | register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s); |
3100 | 0ceac75b | Juan Quintela | register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s); |
3101 | 0ceac75b | Juan Quintela | register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s); |
3102 | 0ceac75b | Juan Quintela | register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s); |
3103 | 4abc796d | blueswir1 | |
3104 | 0ceac75b | Juan Quintela | register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s); |
3105 | 4abc796d | blueswir1 | |
3106 | 0ceac75b | Juan Quintela | register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s); |
3107 | 0ceac75b | Juan Quintela | register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s); |
3108 | 0ceac75b | Juan Quintela | register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s); |
3109 | 0ceac75b | Juan Quintela | register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s); |
3110 | 4abc796d | blueswir1 | |
3111 | 1eed09cb | Avi Kivity | s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read, |
3112 | 4e12cd94 | Avi Kivity | cirrus_vga_mem_write, s); |
3113 | 4abc796d | blueswir1 | cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000, |
3114 | 4e12cd94 | Avi Kivity | s->vga.vga_io_memory); |
3115 | 4abc796d | blueswir1 | qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000); |
3116 | 2c6ab832 | bellard | |
3117 | fefe54e3 | aliguori | /* I/O handler for LFB */
|
3118 | fefe54e3 | aliguori | s->cirrus_linear_io_addr = |
3119 | 1eed09cb | Avi Kivity | cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s); |
3120 | fefe54e3 | aliguori | |
3121 | fefe54e3 | aliguori | /* I/O handler for LFB */
|
3122 | fefe54e3 | aliguori | s->cirrus_linear_bitblt_io_addr = |
3123 | 1eed09cb | Avi Kivity | cpu_register_io_memory(cirrus_linear_bitblt_read, |
3124 | fefe54e3 | aliguori | cirrus_linear_bitblt_write, s); |
3125 | fefe54e3 | aliguori | |
3126 | fefe54e3 | aliguori | /* I/O handler for memory-mapped I/O */
|
3127 | fefe54e3 | aliguori | s->cirrus_mmio_io_addr = |
3128 | 1eed09cb | Avi Kivity | cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s); |
3129 | fefe54e3 | aliguori | |
3130 | fefe54e3 | aliguori | s->real_vram_size = |
3131 | fefe54e3 | aliguori | (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; |
3132 | fefe54e3 | aliguori | |
3133 | 4e12cd94 | Avi Kivity | /* XXX: s->vga.vram_size must be a power of two */
|
3134 | fefe54e3 | aliguori | s->cirrus_addr_mask = s->real_vram_size - 1;
|
3135 | fefe54e3 | aliguori | s->linear_mmio_mask = s->real_vram_size - 256;
|
3136 | fefe54e3 | aliguori | |
3137 | 4e12cd94 | Avi Kivity | s->vga.get_bpp = cirrus_get_bpp; |
3138 | 4e12cd94 | Avi Kivity | s->vga.get_offsets = cirrus_get_offsets; |
3139 | 4e12cd94 | Avi Kivity | s->vga.get_resolution = cirrus_get_resolution; |
3140 | 4e12cd94 | Avi Kivity | s->vga.cursor_invalidate = cirrus_cursor_invalidate; |
3141 | 4e12cd94 | Avi Kivity | s->vga.cursor_draw_line = cirrus_cursor_draw_line; |
3142 | fefe54e3 | aliguori | |
3143 | a08d4367 | Jan Kiszka | qemu_register_reset(cirrus_reset, s); |
3144 | 4abc796d | blueswir1 | cirrus_reset(s); |
3145 | e6e5ad80 | bellard | } |
3146 | e6e5ad80 | bellard | |
3147 | e6e5ad80 | bellard | /***************************************
|
3148 | e6e5ad80 | bellard | *
|
3149 | e6e5ad80 | bellard | * ISA bus support
|
3150 | e6e5ad80 | bellard | *
|
3151 | e6e5ad80 | bellard | ***************************************/
|
3152 | e6e5ad80 | bellard | |
3153 | fbe1b595 | Paul Brook | void isa_cirrus_vga_init(void) |
3154 | e6e5ad80 | bellard | { |
3155 | e6e5ad80 | bellard | CirrusVGAState *s; |
3156 | e6e5ad80 | bellard | |
3157 | e6e5ad80 | bellard | s = qemu_mallocz(sizeof(CirrusVGAState));
|
3158 | 3b46e624 | ths | |
3159 | fbe1b595 | Paul Brook | vga_common_init(&s->vga, VGA_RAM_SIZE); |
3160 | 78e127ef | bellard | cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
|
3161 | 4e12cd94 | Avi Kivity | s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate, |
3162 | 4e12cd94 | Avi Kivity | s->vga.screen_dump, s->vga.text_update, |
3163 | 4e12cd94 | Avi Kivity | &s->vga); |
3164 | 7e72abc3 | Juan Quintela | vmstate_register(0, &vmstate_cirrus_vga, s);
|
3165 | 5245d57a | Gerd Hoffmann | rom_add_vga(VGABIOS_CIRRUS_FILENAME); |
3166 | e6e5ad80 | bellard | /* XXX ISA-LFB support */
|
3167 | e6e5ad80 | bellard | } |
3168 | e6e5ad80 | bellard | |
3169 | e6e5ad80 | bellard | /***************************************
|
3170 | e6e5ad80 | bellard | *
|
3171 | e6e5ad80 | bellard | * PCI bus support
|
3172 | e6e5ad80 | bellard | *
|
3173 | e6e5ad80 | bellard | ***************************************/
|
3174 | e6e5ad80 | bellard | |
3175 | e6e5ad80 | bellard | static void cirrus_pci_lfb_map(PCIDevice *d, int region_num, |
3176 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
|
3177 | e6e5ad80 | bellard | { |
3178 | f3566bf9 | Juan Quintela | CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga; |
3179 | e6e5ad80 | bellard | |
3180 | a5082316 | bellard | /* XXX: add byte swapping apertures */
|
3181 | 4e12cd94 | Avi Kivity | cpu_register_physical_memory(addr, s->vga.vram_size, |
3182 | e6e5ad80 | bellard | s->cirrus_linear_io_addr); |
3183 | a5082316 | bellard | cpu_register_physical_memory(addr + 0x1000000, 0x400000, |
3184 | a5082316 | bellard | s->cirrus_linear_bitblt_io_addr); |
3185 | 2bec46dc | aliguori | |
3186 | 4e12cd94 | Avi Kivity | s->vga.map_addr = s->vga.map_end = 0;
|
3187 | 4e12cd94 | Avi Kivity | s->vga.lfb_addr = addr & TARGET_PAGE_MASK; |
3188 | 4e12cd94 | Avi Kivity | s->vga.lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
3189 | 2bec46dc | aliguori | /* account for overflow */
|
3190 | 4e12cd94 | Avi Kivity | if (s->vga.lfb_end < addr + VGA_RAM_SIZE)
|
3191 | 4e12cd94 | Avi Kivity | s->vga.lfb_end = addr + VGA_RAM_SIZE; |
3192 | ba7349cd | aliguori | |
3193 | 4e12cd94 | Avi Kivity | vga_dirty_log_start(&s->vga); |
3194 | e6e5ad80 | bellard | } |
3195 | e6e5ad80 | bellard | |
3196 | e6e5ad80 | bellard | static void cirrus_pci_mmio_map(PCIDevice *d, int region_num, |
3197 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
|
3198 | e6e5ad80 | bellard | { |
3199 | f3566bf9 | Juan Quintela | CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga; |
3200 | e6e5ad80 | bellard | |
3201 | e6e5ad80 | bellard | cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE, |
3202 | e6e5ad80 | bellard | s->cirrus_mmio_io_addr); |
3203 | e6e5ad80 | bellard | } |
3204 | e6e5ad80 | bellard | |
3205 | ba7349cd | aliguori | static void pci_cirrus_write_config(PCIDevice *d, |
3206 | ba7349cd | aliguori | uint32_t address, uint32_t val, int len)
|
3207 | ba7349cd | aliguori | { |
3208 | f3566bf9 | Juan Quintela | PCICirrusVGAState *pvs = DO_UPCAST(PCICirrusVGAState, dev, d); |
3209 | ba7349cd | aliguori | CirrusVGAState *s = &pvs->cirrus_vga; |
3210 | ba7349cd | aliguori | |
3211 | ba7349cd | aliguori | pci_default_write_config(d, address, val, len); |
3212 | 182f9c8a | Isaku Yamahata | if (s->vga.map_addr && d->io_regions[0].addr == PCI_BAR_UNMAPPED) |
3213 | 4e12cd94 | Avi Kivity | s->vga.map_addr = 0;
|
3214 | ba7349cd | aliguori | cirrus_update_memory_access(s); |
3215 | ba7349cd | aliguori | } |
3216 | ba7349cd | aliguori | |
3217 | 81a322d4 | Gerd Hoffmann | static int pci_cirrus_vga_initfn(PCIDevice *dev) |
3218 | a414c306 | Gerd Hoffmann | { |
3219 | a414c306 | Gerd Hoffmann | PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev); |
3220 | a414c306 | Gerd Hoffmann | CirrusVGAState *s = &d->cirrus_vga; |
3221 | a414c306 | Gerd Hoffmann | uint8_t *pci_conf = d->dev.config; |
3222 | a414c306 | Gerd Hoffmann | int device_id = CIRRUS_ID_CLGD5446;
|
3223 | a414c306 | Gerd Hoffmann | |
3224 | a414c306 | Gerd Hoffmann | /* setup VGA */
|
3225 | a414c306 | Gerd Hoffmann | vga_common_init(&s->vga, VGA_RAM_SIZE); |
3226 | a414c306 | Gerd Hoffmann | cirrus_init_common(s, device_id, 1);
|
3227 | a414c306 | Gerd Hoffmann | s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate, |
3228 | a414c306 | Gerd Hoffmann | s->vga.screen_dump, s->vga.text_update, |
3229 | a414c306 | Gerd Hoffmann | &s->vga); |
3230 | a414c306 | Gerd Hoffmann | |
3231 | a414c306 | Gerd Hoffmann | /* setup PCI */
|
3232 | a414c306 | Gerd Hoffmann | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS); |
3233 | a414c306 | Gerd Hoffmann | pci_config_set_device_id(pci_conf, device_id); |
3234 | a414c306 | Gerd Hoffmann | pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
|
3235 | a414c306 | Gerd Hoffmann | pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA); |
3236 | a414c306 | Gerd Hoffmann | pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; |
3237 | a414c306 | Gerd Hoffmann | |
3238 | a414c306 | Gerd Hoffmann | /* setup memory space */
|
3239 | a414c306 | Gerd Hoffmann | /* memory #0 LFB */
|
3240 | a414c306 | Gerd Hoffmann | /* memory #1 memory-mapped I/O */
|
3241 | a414c306 | Gerd Hoffmann | /* XXX: s->vga.vram_size must be a power of two */
|
3242 | a414c306 | Gerd Hoffmann | pci_register_bar((PCIDevice *)d, 0, 0x2000000, |
3243 | 0392a017 | Isaku Yamahata | PCI_BASE_ADDRESS_MEM_PREFETCH, cirrus_pci_lfb_map); |
3244 | a414c306 | Gerd Hoffmann | if (device_id == CIRRUS_ID_CLGD5446) {
|
3245 | a414c306 | Gerd Hoffmann | pci_register_bar((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
|
3246 | 0392a017 | Isaku Yamahata | PCI_BASE_ADDRESS_SPACE_MEMORY, cirrus_pci_mmio_map); |
3247 | a414c306 | Gerd Hoffmann | } |
3248 | 7e72abc3 | Juan Quintela | vmstate_register(0, &vmstate_pci_cirrus_vga, d);
|
3249 | 5245d57a | Gerd Hoffmann | |
3250 | 5245d57a | Gerd Hoffmann | /* ROM BIOS */
|
3251 | 5245d57a | Gerd Hoffmann | rom_add_vga(VGABIOS_CIRRUS_FILENAME); |
3252 | 81a322d4 | Gerd Hoffmann | return 0; |
3253 | a414c306 | Gerd Hoffmann | } |
3254 | a414c306 | Gerd Hoffmann | |
3255 | fbe1b595 | Paul Brook | void pci_cirrus_vga_init(PCIBus *bus)
|
3256 | e6e5ad80 | bellard | { |
3257 | a414c306 | Gerd Hoffmann | pci_create_simple(bus, -1, "Cirrus VGA"); |
3258 | a414c306 | Gerd Hoffmann | } |
3259 | d34cab9f | ths | |
3260 | a414c306 | Gerd Hoffmann | static PCIDeviceInfo cirrus_vga_info = {
|
3261 | a414c306 | Gerd Hoffmann | .qdev.name = "Cirrus VGA",
|
3262 | a414c306 | Gerd Hoffmann | .qdev.size = sizeof(PCICirrusVGAState),
|
3263 | a414c306 | Gerd Hoffmann | .init = pci_cirrus_vga_initfn, |
3264 | a414c306 | Gerd Hoffmann | .config_write = pci_cirrus_write_config, |
3265 | a414c306 | Gerd Hoffmann | }; |
3266 | e6e5ad80 | bellard | |
3267 | a414c306 | Gerd Hoffmann | static void cirrus_vga_register(void) |
3268 | a414c306 | Gerd Hoffmann | { |
3269 | a414c306 | Gerd Hoffmann | pci_qdev_register(&cirrus_vga_info); |
3270 | e6e5ad80 | bellard | } |
3271 | a414c306 | Gerd Hoffmann | device_init(cirrus_vga_register); |