root / tcg / ia64 / tcg-target.c @ 3cf246f0
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
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* Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "tcg-be-null.h" |
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|
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/*
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* Register definitions
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*/
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
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"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", |
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"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", |
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"r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", |
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"r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", |
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}; |
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#endif
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|
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#ifdef CONFIG_USE_GUEST_BASE
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#define TCG_GUEST_BASE_REG TCG_REG_R55
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#else
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#define TCG_GUEST_BASE_REG TCG_REG_R0
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#endif
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#ifndef GUEST_BASE
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#define GUEST_BASE 0 |
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#endif
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|
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/* Branch registers */
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enum {
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TCG_REG_B0 = 0,
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TCG_REG_B1, |
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TCG_REG_B2, |
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TCG_REG_B3, |
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TCG_REG_B4, |
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TCG_REG_B5, |
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TCG_REG_B6, |
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TCG_REG_B7, |
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}; |
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|
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/* Floating point registers */
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enum {
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TCG_REG_F0 = 0,
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TCG_REG_F1, |
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TCG_REG_F2, |
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TCG_REG_F3, |
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TCG_REG_F4, |
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TCG_REG_F5, |
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TCG_REG_F6, |
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TCG_REG_F7, |
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TCG_REG_F8, |
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TCG_REG_F9, |
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TCG_REG_F10, |
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TCG_REG_F11, |
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TCG_REG_F12, |
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TCG_REG_F13, |
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TCG_REG_F14, |
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TCG_REG_F15, |
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}; |
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|
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/* Predicate registers */
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enum {
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TCG_REG_P0 = 0,
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TCG_REG_P1, |
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TCG_REG_P2, |
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TCG_REG_P3, |
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TCG_REG_P4, |
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TCG_REG_P5, |
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TCG_REG_P6, |
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TCG_REG_P7, |
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TCG_REG_P8, |
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TCG_REG_P9, |
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TCG_REG_P10, |
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TCG_REG_P11, |
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TCG_REG_P12, |
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TCG_REG_P13, |
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TCG_REG_P14, |
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TCG_REG_P15, |
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}; |
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|
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/* Application registers */
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enum {
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TCG_REG_PFS = 64,
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}; |
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|
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static const int tcg_target_reg_alloc_order[] = { |
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TCG_REG_R33, |
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TCG_REG_R35, |
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TCG_REG_R36, |
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TCG_REG_R37, |
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TCG_REG_R38, |
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TCG_REG_R39, |
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TCG_REG_R40, |
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TCG_REG_R41, |
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TCG_REG_R42, |
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TCG_REG_R43, |
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TCG_REG_R44, |
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TCG_REG_R45, |
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TCG_REG_R46, |
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TCG_REG_R47, |
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TCG_REG_R48, |
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TCG_REG_R49, |
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TCG_REG_R50, |
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TCG_REG_R51, |
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TCG_REG_R52, |
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TCG_REG_R53, |
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TCG_REG_R54, |
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TCG_REG_R55, |
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TCG_REG_R14, |
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TCG_REG_R15, |
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TCG_REG_R16, |
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TCG_REG_R17, |
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TCG_REG_R18, |
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TCG_REG_R19, |
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TCG_REG_R20, |
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TCG_REG_R21, |
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TCG_REG_R22, |
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TCG_REG_R23, |
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TCG_REG_R24, |
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TCG_REG_R25, |
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TCG_REG_R26, |
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TCG_REG_R27, |
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TCG_REG_R28, |
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TCG_REG_R29, |
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TCG_REG_R30, |
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TCG_REG_R31, |
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TCG_REG_R56, |
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TCG_REG_R57, |
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TCG_REG_R58, |
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TCG_REG_R59, |
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TCG_REG_R60, |
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TCG_REG_R61, |
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TCG_REG_R62, |
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TCG_REG_R63, |
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TCG_REG_R8, |
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TCG_REG_R9, |
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TCG_REG_R10, |
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TCG_REG_R11 |
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}; |
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|
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static const int tcg_target_call_iarg_regs[8] = { |
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TCG_REG_R56, |
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TCG_REG_R57, |
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TCG_REG_R58, |
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TCG_REG_R59, |
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TCG_REG_R60, |
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TCG_REG_R61, |
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TCG_REG_R62, |
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TCG_REG_R63, |
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}; |
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|
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static const int tcg_target_call_oarg_regs[] = { |
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TCG_REG_R8 |
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}; |
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|
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/*
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* opcode formation
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*/
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|
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/* bundle templates: stops (double bar in the IA64 manual) are marked with
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an uppercase letter. */
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enum {
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mii = 0x00,
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miI = 0x01,
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mIi = 0x02,
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mII = 0x03,
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mlx = 0x04,
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mLX = 0x05,
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mmi = 0x08,
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mmI = 0x09,
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Mmi = 0x0a,
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MmI = 0x0b,
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mfi = 0x0c,
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mfI = 0x0d,
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mmf = 0x0e,
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mmF = 0x0f,
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mib = 0x10,
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miB = 0x11,
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mbb = 0x12,
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mbB = 0x13,
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bbb = 0x16,
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bbB = 0x17,
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mmb = 0x18,
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mmB = 0x19,
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mfb = 0x1c,
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mfB = 0x1d,
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}; |
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enum {
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OPC_ADD_A1 = 0x10000000000ull,
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OPC_AND_A1 = 0x10060000000ull,
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OPC_AND_A3 = 0x10160000000ull,
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OPC_ANDCM_A1 = 0x10068000000ull,
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OPC_ANDCM_A3 = 0x10168000000ull,
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OPC_ADDS_A4 = 0x10800000000ull,
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OPC_ADDL_A5 = 0x12000000000ull,
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OPC_ALLOC_M34 = 0x02c00000000ull,
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OPC_BR_DPTK_FEW_B1 = 0x08400000000ull,
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OPC_BR_SPTK_MANY_B1 = 0x08000001000ull,
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OPC_BR_SPTK_MANY_B4 = 0x00100001000ull,
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OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull,
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OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull,
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OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull,
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OPC_CMP_LT_A6 = 0x18000000000ull,
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OPC_CMP_LTU_A6 = 0x1a000000000ull,
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OPC_CMP_EQ_A6 = 0x1c000000000ull,
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OPC_CMP4_LT_A6 = 0x18400000000ull,
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OPC_CMP4_LTU_A6 = 0x1a400000000ull,
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OPC_CMP4_EQ_A6 = 0x1c400000000ull,
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OPC_DEP_I14 = 0x0ae00000000ull,
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OPC_DEP_I15 = 0x08000000000ull,
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OPC_DEP_Z_I12 = 0x0a600000000ull,
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OPC_EXTR_I11 = 0x0a400002000ull,
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OPC_EXTR_U_I11 = 0x0a400000000ull,
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OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull,
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OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
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OPC_FCVT_XF_F11 = 0x000e0000000ull,
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OPC_FMA_S1_F1 = 0x10400000000ull,
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OPC_FNMA_S1_F1 = 0x18400000000ull,
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OPC_FRCPA_S1_F6 = 0x00600000000ull,
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OPC_GETF_SIG_M19 = 0x08708000000ull,
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OPC_LD1_M1 = 0x08000000000ull,
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OPC_LD1_M3 = 0x0a000000000ull,
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OPC_LD2_M1 = 0x08040000000ull,
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OPC_LD2_M3 = 0x0a040000000ull,
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OPC_LD4_M1 = 0x08080000000ull,
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OPC_LD4_M3 = 0x0a080000000ull,
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OPC_LD8_M1 = 0x080c0000000ull,
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OPC_LD8_M3 = 0x0a0c0000000ull,
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OPC_MUX1_I3 = 0x0eca0000000ull,
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OPC_NOP_B9 = 0x04008000000ull,
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OPC_NOP_F16 = 0x00008000000ull,
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OPC_NOP_I18 = 0x00008000000ull,
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OPC_NOP_M48 = 0x00008000000ull,
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OPC_MOV_I21 = 0x00e00100000ull,
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OPC_MOV_RET_I21 = 0x00e00500000ull,
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OPC_MOV_I22 = 0x00188000000ull,
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OPC_MOV_I_I26 = 0x00150000000ull,
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OPC_MOVL_X2 = 0x0c000000000ull,
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OPC_OR_A1 = 0x10070000000ull,
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OPC_SETF_EXP_M18 = 0x0c748000000ull,
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OPC_SETF_SIG_M18 = 0x0c708000000ull,
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OPC_SHL_I7 = 0x0f240000000ull,
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OPC_SHR_I5 = 0x0f220000000ull,
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OPC_SHR_U_I5 = 0x0f200000000ull,
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OPC_SHRP_I10 = 0x0ac00000000ull,
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OPC_SXT1_I29 = 0x000a0000000ull,
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OPC_SXT2_I29 = 0x000a8000000ull,
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OPC_SXT4_I29 = 0x000b0000000ull,
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OPC_ST1_M4 = 0x08c00000000ull,
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OPC_ST2_M4 = 0x08c40000000ull,
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OPC_ST4_M4 = 0x08c80000000ull,
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OPC_ST8_M4 = 0x08cc0000000ull,
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OPC_SUB_A1 = 0x10028000000ull,
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OPC_SUB_A3 = 0x10128000000ull,
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OPC_UNPACK4_L_I2 = 0x0f860000000ull,
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OPC_XMA_L_F2 = 0x1d000000000ull,
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OPC_XOR_A1 = 0x10078000000ull,
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OPC_ZXT1_I29 = 0x00080000000ull,
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OPC_ZXT2_I29 = 0x00088000000ull,
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OPC_ZXT4_I29 = 0x00090000000ull,
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}; |
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|
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static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1, |
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int r2, int r3) |
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{
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return opc
|
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| ((r3 & 0x7f) << 20) |
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| ((r2 & 0x7f) << 13) |
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| ((r1 & 0x7f) << 6) |
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| (qp & 0x3f);
|
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} |
| 298 |
|
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static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1, |
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uint64_t imm, int r3)
|
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{
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return opc
|
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| ((imm & 0x80) << 29) /* s */ |
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| ((imm & 0x7f) << 13) /* imm7b */ |
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| ((r3 & 0x7f) << 20) |
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| ((r1 & 0x7f) << 6) |
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| (qp & 0x3f);
|
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} |
| 309 |
|
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static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1, |
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uint64_t imm, int r3)
|
| 312 |
{
|
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return opc
|
| 314 |
| ((imm & 0x2000) << 23) /* s */ |
| 315 |
| ((imm & 0x1f80) << 20) /* imm6d */ |
| 316 |
| ((imm & 0x007f) << 13) /* imm7b */ |
| 317 |
| ((r3 & 0x7f) << 20) |
| 318 |
| ((r1 & 0x7f) << 6) |
| 319 |
| (qp & 0x3f);
|
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} |
| 321 |
|
| 322 |
static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1, |
| 323 |
uint64_t imm, int r3)
|
| 324 |
{
|
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return opc
|
| 326 |
| ((imm & 0x200000) << 15) /* s */ |
| 327 |
| ((imm & 0x1f0000) << 6) /* imm5c */ |
| 328 |
| ((imm & 0x00ff80) << 20) /* imm9d */ |
| 329 |
| ((imm & 0x00007f) << 13) /* imm7b */ |
| 330 |
| ((r3 & 0x03) << 20) |
| 331 |
| ((r1 & 0x7f) << 6) |
| 332 |
| (qp & 0x3f);
|
| 333 |
} |
| 334 |
|
| 335 |
static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1, |
| 336 |
int p2, int r2, int r3) |
| 337 |
{
|
| 338 |
return opc
|
| 339 |
| ((p2 & 0x3f) << 27) |
| 340 |
| ((r3 & 0x7f) << 20) |
| 341 |
| ((r2 & 0x7f) << 13) |
| 342 |
| ((p1 & 0x3f) << 6) |
| 343 |
| (qp & 0x3f);
|
| 344 |
} |
| 345 |
|
| 346 |
static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm) |
| 347 |
{
|
| 348 |
return opc
|
| 349 |
| ((imm & 0x100000) << 16) /* s */ |
| 350 |
| ((imm & 0x0fffff) << 13) /* imm20b */ |
| 351 |
| (qp & 0x3f);
|
| 352 |
} |
| 353 |
|
| 354 |
static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2) |
| 355 |
{
|
| 356 |
return opc
|
| 357 |
| ((b2 & 0x7) << 13) |
| 358 |
| (qp & 0x3f);
|
| 359 |
} |
| 360 |
|
| 361 |
static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2) |
| 362 |
{
|
| 363 |
return opc
|
| 364 |
| ((b2 & 0x7) << 13) |
| 365 |
| ((b1 & 0x7) << 6) |
| 366 |
| (qp & 0x3f);
|
| 367 |
} |
| 368 |
|
| 369 |
|
| 370 |
static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm) |
| 371 |
{
|
| 372 |
return opc
|
| 373 |
| ((imm & 0x100000) << 16) /* i */ |
| 374 |
| ((imm & 0x0fffff) << 6) /* imm20a */ |
| 375 |
| (qp & 0x3f);
|
| 376 |
} |
| 377 |
|
| 378 |
static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1, |
| 379 |
int f3, int f4, int f2) |
| 380 |
{
|
| 381 |
return opc
|
| 382 |
| ((f4 & 0x7f) << 27) |
| 383 |
| ((f3 & 0x7f) << 20) |
| 384 |
| ((f2 & 0x7f) << 13) |
| 385 |
| ((f1 & 0x7f) << 6) |
| 386 |
| (qp & 0x3f);
|
| 387 |
} |
| 388 |
|
| 389 |
static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1, |
| 390 |
int f3, int f4, int f2) |
| 391 |
{
|
| 392 |
return opc
|
| 393 |
| ((f4 & 0x7f) << 27) |
| 394 |
| ((f3 & 0x7f) << 20) |
| 395 |
| ((f2 & 0x7f) << 13) |
| 396 |
| ((f1 & 0x7f) << 6) |
| 397 |
| (qp & 0x3f);
|
| 398 |
} |
| 399 |
|
| 400 |
static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1, |
| 401 |
int p2, int f2, int f3) |
| 402 |
{
|
| 403 |
return opc
|
| 404 |
| ((p2 & 0x3f) << 27) |
| 405 |
| ((f3 & 0x7f) << 20) |
| 406 |
| ((f2 & 0x7f) << 13) |
| 407 |
| ((f1 & 0x7f) << 6) |
| 408 |
| (qp & 0x3f);
|
| 409 |
} |
| 410 |
|
| 411 |
static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2) |
| 412 |
{
|
| 413 |
return opc
|
| 414 |
| ((f2 & 0x7f) << 13) |
| 415 |
| ((f1 & 0x7f) << 6) |
| 416 |
| (qp & 0x3f);
|
| 417 |
} |
| 418 |
|
| 419 |
static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2) |
| 420 |
{
|
| 421 |
return opc
|
| 422 |
| ((f2 & 0x7f) << 13) |
| 423 |
| ((f1 & 0x7f) << 6) |
| 424 |
| (qp & 0x3f);
|
| 425 |
} |
| 426 |
|
| 427 |
static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm) |
| 428 |
{
|
| 429 |
return opc
|
| 430 |
| ((imm & 0x100000) << 16) /* i */ |
| 431 |
| ((imm & 0x0fffff) << 6) /* imm20a */ |
| 432 |
| (qp & 0x3f);
|
| 433 |
} |
| 434 |
|
| 435 |
static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1, |
| 436 |
int r2, int r3) |
| 437 |
{
|
| 438 |
return opc
|
| 439 |
| ((r3 & 0x7f) << 20) |
| 440 |
| ((r2 & 0x7f) << 13) |
| 441 |
| ((r1 & 0x7f) << 6) |
| 442 |
| (qp & 0x3f);
|
| 443 |
} |
| 444 |
|
| 445 |
static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1, |
| 446 |
int r2, int mbtype) |
| 447 |
{
|
| 448 |
return opc
|
| 449 |
| ((mbtype & 0x0f) << 20) |
| 450 |
| ((r2 & 0x7f) << 13) |
| 451 |
| ((r1 & 0x7f) << 6) |
| 452 |
| (qp & 0x3f);
|
| 453 |
} |
| 454 |
|
| 455 |
static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1, |
| 456 |
int r3, int r2) |
| 457 |
{
|
| 458 |
return opc
|
| 459 |
| ((r3 & 0x7f) << 20) |
| 460 |
| ((r2 & 0x7f) << 13) |
| 461 |
| ((r1 & 0x7f) << 6) |
| 462 |
| (qp & 0x3f);
|
| 463 |
} |
| 464 |
|
| 465 |
static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1, |
| 466 |
int r2, int r3) |
| 467 |
{
|
| 468 |
return opc
|
| 469 |
| ((r3 & 0x7f) << 20) |
| 470 |
| ((r2 & 0x7f) << 13) |
| 471 |
| ((r1 & 0x7f) << 6) |
| 472 |
| (qp & 0x3f);
|
| 473 |
} |
| 474 |
|
| 475 |
static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1, |
| 476 |
int r2, int r3, uint64_t count) |
| 477 |
{
|
| 478 |
return opc
|
| 479 |
| ((count & 0x3f) << 27) |
| 480 |
| ((r3 & 0x7f) << 20) |
| 481 |
| ((r2 & 0x7f) << 13) |
| 482 |
| ((r1 & 0x7f) << 6) |
| 483 |
| (qp & 0x3f);
|
| 484 |
} |
| 485 |
|
| 486 |
static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1, |
| 487 |
int r3, uint64_t pos, uint64_t len)
|
| 488 |
{
|
| 489 |
return opc
|
| 490 |
| ((len & 0x3f) << 27) |
| 491 |
| ((r3 & 0x7f) << 20) |
| 492 |
| ((pos & 0x3f) << 14) |
| 493 |
| ((r1 & 0x7f) << 6) |
| 494 |
| (qp & 0x3f);
|
| 495 |
} |
| 496 |
|
| 497 |
static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1, |
| 498 |
int r2, uint64_t pos, uint64_t len)
|
| 499 |
{
|
| 500 |
return opc
|
| 501 |
| ((len & 0x3f) << 27) |
| 502 |
| ((pos & 0x3f) << 20) |
| 503 |
| ((r2 & 0x7f) << 13) |
| 504 |
| ((r1 & 0x7f) << 6) |
| 505 |
| (qp & 0x3f);
|
| 506 |
} |
| 507 |
|
| 508 |
static inline uint64_t tcg_opc_i14(int qp, uint64_t opc, int r1, uint64_t imm, |
| 509 |
int r3, uint64_t pos, uint64_t len)
|
| 510 |
{
|
| 511 |
return opc
|
| 512 |
| ((imm & 0x01) << 36) |
| 513 |
| ((len & 0x3f) << 27) |
| 514 |
| ((r3 & 0x7f) << 20) |
| 515 |
| ((pos & 0x3f) << 14) |
| 516 |
| ((r1 & 0x7f) << 6) |
| 517 |
| (qp & 0x3f);
|
| 518 |
} |
| 519 |
|
| 520 |
static inline uint64_t tcg_opc_i15(int qp, uint64_t opc, int r1, int r2, |
| 521 |
int r3, uint64_t pos, uint64_t len)
|
| 522 |
{
|
| 523 |
return opc
|
| 524 |
| ((pos & 0x3f) << 31) |
| 525 |
| ((len & 0x0f) << 27) |
| 526 |
| ((r3 & 0x7f) << 20) |
| 527 |
| ((r2 & 0x7f) << 13) |
| 528 |
| ((r1 & 0x7f) << 6) |
| 529 |
| (qp & 0x3f);
|
| 530 |
} |
| 531 |
|
| 532 |
static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm) |
| 533 |
{
|
| 534 |
return opc
|
| 535 |
| ((imm & 0x100000) << 16) /* i */ |
| 536 |
| ((imm & 0x0fffff) << 6) /* imm20a */ |
| 537 |
| (qp & 0x3f);
|
| 538 |
} |
| 539 |
|
| 540 |
static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1, |
| 541 |
int r2, uint64_t imm)
|
| 542 |
{
|
| 543 |
return opc
|
| 544 |
| ((imm & 0x1ff) << 24) |
| 545 |
| ((r2 & 0x7f) << 13) |
| 546 |
| ((b1 & 0x7) << 6) |
| 547 |
| (qp & 0x3f);
|
| 548 |
} |
| 549 |
|
| 550 |
static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2) |
| 551 |
{
|
| 552 |
return opc
|
| 553 |
| ((b2 & 0x7) << 13) |
| 554 |
| ((r1 & 0x7f) << 6) |
| 555 |
| (qp & 0x3f);
|
| 556 |
} |
| 557 |
|
| 558 |
static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2) |
| 559 |
{
|
| 560 |
return opc
|
| 561 |
| ((ar3 & 0x7f) << 20) |
| 562 |
| ((r2 & 0x7f) << 13) |
| 563 |
| (qp & 0x3f);
|
| 564 |
} |
| 565 |
|
| 566 |
static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3) |
| 567 |
{
|
| 568 |
return opc
|
| 569 |
| ((r3 & 0x7f) << 20) |
| 570 |
| ((r1 & 0x7f) << 6) |
| 571 |
| (qp & 0x3f);
|
| 572 |
} |
| 573 |
|
| 574 |
static inline uint64_t tcg_opc_l2(uint64_t imm) |
| 575 |
{
|
| 576 |
return (imm & 0x7fffffffffc00000ull) >> 22; |
| 577 |
} |
| 578 |
|
| 579 |
static inline uint64_t tcg_opc_l3(uint64_t imm) |
| 580 |
{
|
| 581 |
return (imm & 0x07fffffffff00000ull) >> 18; |
| 582 |
} |
| 583 |
|
| 584 |
static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3) |
| 585 |
{
|
| 586 |
return opc
|
| 587 |
| ((r3 & 0x7f) << 20) |
| 588 |
| ((r1 & 0x7f) << 6) |
| 589 |
| (qp & 0x3f);
|
| 590 |
} |
| 591 |
|
| 592 |
static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1, |
| 593 |
int r3, uint64_t imm)
|
| 594 |
{
|
| 595 |
return opc
|
| 596 |
| ((imm & 0x100) << 28) /* s */ |
| 597 |
| ((imm & 0x080) << 20) /* i */ |
| 598 |
| ((imm & 0x07f) << 13) /* imm7b */ |
| 599 |
| ((r3 & 0x7f) << 20) |
| 600 |
| ((r1 & 0x7f) << 6) |
| 601 |
| (qp & 0x3f);
|
| 602 |
} |
| 603 |
|
| 604 |
static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3) |
| 605 |
{
|
| 606 |
return opc
|
| 607 |
| ((r3 & 0x7f) << 20) |
| 608 |
| ((r2 & 0x7f) << 13) |
| 609 |
| (qp & 0x3f);
|
| 610 |
} |
| 611 |
|
| 612 |
static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2) |
| 613 |
{
|
| 614 |
return opc
|
| 615 |
| ((r2 & 0x7f) << 13) |
| 616 |
| ((f1 & 0x7f) << 6) |
| 617 |
| (qp & 0x3f);
|
| 618 |
} |
| 619 |
|
| 620 |
static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2) |
| 621 |
{
|
| 622 |
return opc
|
| 623 |
| ((f2 & 0x7f) << 13) |
| 624 |
| ((r1 & 0x7f) << 6) |
| 625 |
| (qp & 0x3f);
|
| 626 |
} |
| 627 |
|
| 628 |
static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1, |
| 629 |
int sof, int sol, int sor) |
| 630 |
{
|
| 631 |
return opc
|
| 632 |
| ((sor & 0x0f) << 27) |
| 633 |
| ((sol & 0x7f) << 20) |
| 634 |
| ((sof & 0x7f) << 13) |
| 635 |
| ((r1 & 0x7f) << 6) |
| 636 |
| (qp & 0x3f);
|
| 637 |
} |
| 638 |
|
| 639 |
static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm) |
| 640 |
{
|
| 641 |
return opc
|
| 642 |
| ((imm & 0x100000) << 16) /* i */ |
| 643 |
| ((imm & 0x0fffff) << 6) /* imm20a */ |
| 644 |
| (qp & 0x3f);
|
| 645 |
} |
| 646 |
|
| 647 |
static inline uint64_t tcg_opc_x2(int qp, uint64_t opc, |
| 648 |
int r1, uint64_t imm)
|
| 649 |
{
|
| 650 |
return opc
|
| 651 |
| ((imm & 0x8000000000000000ull) >> 27) /* i */ |
| 652 |
| (imm & 0x0000000000200000ull) /* ic */ |
| 653 |
| ((imm & 0x00000000001f0000ull) << 6) /* imm5c */ |
| 654 |
| ((imm & 0x000000000000ff80ull) << 20) /* imm9d */ |
| 655 |
| ((imm & 0x000000000000007full) << 13) /* imm7b */ |
| 656 |
| ((r1 & 0x7f) << 6) |
| 657 |
| (qp & 0x3f);
|
| 658 |
} |
| 659 |
|
| 660 |
static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm) |
| 661 |
{
|
| 662 |
return opc
|
| 663 |
| ((imm & 0x0800000000000000ull) >> 23) /* i */ |
| 664 |
| ((imm & 0x00000000000fffffull) << 13) /* imm20b */ |
| 665 |
| (qp & 0x3f);
|
| 666 |
} |
| 667 |
|
| 668 |
|
| 669 |
/*
|
| 670 |
* Relocations
|
| 671 |
*/
|
| 672 |
|
| 673 |
static inline void reloc_pcrel21b(void *pc, intptr_t target) |
| 674 |
{
|
| 675 |
uint64_t imm; |
| 676 |
int64_t disp; |
| 677 |
int slot;
|
| 678 |
|
| 679 |
slot = (intptr_t)pc & 3;
|
| 680 |
pc = (void *)((intptr_t)pc & ~3); |
| 681 |
|
| 682 |
disp = target - (intptr_t)pc; |
| 683 |
imm = (uint64_t) disp >> 4;
|
| 684 |
|
| 685 |
switch(slot) {
|
| 686 |
case 0: |
| 687 |
*(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull) |
| 688 |
| ((imm & 0x100000) << 21) /* s */ |
| 689 |
| ((imm & 0x0fffff) << 18); /* imm20b */ |
| 690 |
break;
|
| 691 |
case 1: |
| 692 |
*(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull) |
| 693 |
| ((imm & 0x100000) >> 2) /* s */ |
| 694 |
| ((imm & 0x0fffe0) >> 5); /* imm20b */ |
| 695 |
*(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull) |
| 696 |
| ((imm & 0x00001f) << 59); /* imm20b */ |
| 697 |
break;
|
| 698 |
case 2: |
| 699 |
*(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull) |
| 700 |
| ((imm & 0x100000) << 39) /* s */ |
| 701 |
| ((imm & 0x0fffff) << 36); /* imm20b */ |
| 702 |
break;
|
| 703 |
} |
| 704 |
} |
| 705 |
|
| 706 |
static inline uint64_t get_reloc_pcrel21b (void *pc) |
| 707 |
{
|
| 708 |
int64_t low, high; |
| 709 |
int slot;
|
| 710 |
|
| 711 |
slot = (tcg_target_long) pc & 3;
|
| 712 |
pc = (void *)((tcg_target_long) pc & ~3); |
| 713 |
|
| 714 |
low = (*(uint64_t *)(pc + 0));
|
| 715 |
high = (*(uint64_t *)(pc + 8));
|
| 716 |
|
| 717 |
switch(slot) {
|
| 718 |
case 0: |
| 719 |
return ((low >> 21) & 0x100000) + /* s */ |
| 720 |
((low >> 18) & 0x0fffff); /* imm20b */ |
| 721 |
case 1: |
| 722 |
return ((high << 2) & 0x100000) + /* s */ |
| 723 |
((high << 5) & 0x0fffe0) + /* imm20b */ |
| 724 |
((low >> 59) & 0x00001f); /* imm20b */ |
| 725 |
case 2: |
| 726 |
return ((high >> 39) & 0x100000) + /* s */ |
| 727 |
((high >> 36) & 0x0fffff); /* imm20b */ |
| 728 |
default:
|
| 729 |
tcg_abort(); |
| 730 |
} |
| 731 |
} |
| 732 |
|
| 733 |
static inline void reloc_pcrel60b(void *pc, intptr_t target) |
| 734 |
{
|
| 735 |
int64_t disp; |
| 736 |
uint64_t imm; |
| 737 |
|
| 738 |
disp = target - (intptr_t)pc; |
| 739 |
imm = (uint64_t) disp >> 4;
|
| 740 |
|
| 741 |
*(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull) |
| 742 |
| (imm & 0x0800000000000000ull) /* s */ |
| 743 |
| ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */ |
| 744 |
| ((imm & 0x00000000000fffffull) << 36); /* imm20b */ |
| 745 |
*(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull) |
| 746 |
| ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */ |
| 747 |
} |
| 748 |
|
| 749 |
static inline uint64_t get_reloc_pcrel60b (void *pc) |
| 750 |
{
|
| 751 |
int64_t low, high; |
| 752 |
|
| 753 |
low = (*(uint64_t *)(pc + 0));
|
| 754 |
high = (*(uint64_t *)(pc + 8));
|
| 755 |
|
| 756 |
return ((high) & 0x0800000000000000ull) + /* s */ |
| 757 |
((high >> 36) & 0x00000000000fffffull) + /* imm20b */ |
| 758 |
((high << 36) & 0x07fffff000000000ull) + /* imm39 */ |
| 759 |
((low >> 28) & 0x0000000ffff00000ull); /* imm39 */ |
| 760 |
} |
| 761 |
|
| 762 |
|
| 763 |
static void patch_reloc(uint8_t *code_ptr, int type, |
| 764 |
intptr_t value, intptr_t addend) |
| 765 |
{
|
| 766 |
value += addend; |
| 767 |
switch (type) {
|
| 768 |
case R_IA64_PCREL21B:
|
| 769 |
reloc_pcrel21b(code_ptr, value); |
| 770 |
break;
|
| 771 |
case R_IA64_PCREL60B:
|
| 772 |
reloc_pcrel60b(code_ptr, value); |
| 773 |
default:
|
| 774 |
tcg_abort(); |
| 775 |
} |
| 776 |
} |
| 777 |
|
| 778 |
/*
|
| 779 |
* Constraints
|
| 780 |
*/
|
| 781 |
|
| 782 |
/* parse target specific constraints */
|
| 783 |
static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
| 784 |
{
|
| 785 |
const char *ct_str; |
| 786 |
|
| 787 |
ct_str = *pct_str; |
| 788 |
switch(ct_str[0]) { |
| 789 |
case 'r': |
| 790 |
ct->ct |= TCG_CT_REG; |
| 791 |
tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
|
| 792 |
break;
|
| 793 |
case 'I': |
| 794 |
ct->ct |= TCG_CT_CONST_S22; |
| 795 |
break;
|
| 796 |
case 'S': |
| 797 |
ct->ct |= TCG_CT_REG; |
| 798 |
tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
|
| 799 |
#if defined(CONFIG_SOFTMMU)
|
| 800 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56); |
| 801 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57); |
| 802 |
#endif
|
| 803 |
break;
|
| 804 |
case 'Z': |
| 805 |
/* We are cheating a bit here, using the fact that the register
|
| 806 |
r0 is also the register number 0. Hence there is no need
|
| 807 |
to check for const_args in each instruction. */
|
| 808 |
ct->ct |= TCG_CT_CONST_ZERO; |
| 809 |
break;
|
| 810 |
default:
|
| 811 |
return -1; |
| 812 |
} |
| 813 |
ct_str++; |
| 814 |
*pct_str = ct_str; |
| 815 |
return 0; |
| 816 |
} |
| 817 |
|
| 818 |
/* test if a constant matches the constraint */
|
| 819 |
static inline int tcg_target_const_match(tcg_target_long val, |
| 820 |
const TCGArgConstraint *arg_ct)
|
| 821 |
{
|
| 822 |
int ct;
|
| 823 |
ct = arg_ct->ct; |
| 824 |
if (ct & TCG_CT_CONST)
|
| 825 |
return 1; |
| 826 |
else if ((ct & TCG_CT_CONST_ZERO) && val == 0) |
| 827 |
return 1; |
| 828 |
else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10) |
| 829 |
return 1; |
| 830 |
else
|
| 831 |
return 0; |
| 832 |
} |
| 833 |
|
| 834 |
/*
|
| 835 |
* Code generation
|
| 836 |
*/
|
| 837 |
|
| 838 |
static uint8_t *tb_ret_addr;
|
| 839 |
|
| 840 |
static inline void tcg_out_bundle(TCGContext *s, int template, |
| 841 |
uint64_t slot0, uint64_t slot1, |
| 842 |
uint64_t slot2) |
| 843 |
{
|
| 844 |
template &= 0x1f; /* 5 bits */ |
| 845 |
slot0 &= 0x1ffffffffffull; /* 41 bits */ |
| 846 |
slot1 &= 0x1ffffffffffull; /* 41 bits */ |
| 847 |
slot2 &= 0x1ffffffffffull; /* 41 bits */ |
| 848 |
|
| 849 |
*(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template; |
| 850 |
*(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18); |
| 851 |
s->code_ptr += 16;
|
| 852 |
} |
| 853 |
|
| 854 |
static inline void tcg_out_mov(TCGContext *s, TCGType type, |
| 855 |
TCGReg ret, TCGReg arg) |
| 856 |
{
|
| 857 |
tcg_out_bundle(s, mmI, |
| 858 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 859 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 860 |
tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));
|
| 861 |
} |
| 862 |
|
| 863 |
static inline void tcg_out_movi(TCGContext *s, TCGType type, |
| 864 |
TCGReg reg, tcg_target_long arg) |
| 865 |
{
|
| 866 |
tcg_out_bundle(s, mLX, |
| 867 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 868 |
tcg_opc_l2 (arg), |
| 869 |
tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg)); |
| 870 |
} |
| 871 |
|
| 872 |
static void tcg_out_br(TCGContext *s, int label_index) |
| 873 |
{
|
| 874 |
TCGLabel *l = &s->labels[label_index]; |
| 875 |
|
| 876 |
/* We pay attention here to not modify the branch target by reading
|
| 877 |
the existing value and using it again. This ensure that caches and
|
| 878 |
memory are kept coherent during retranslation. */
|
| 879 |
tcg_out_bundle(s, mmB, |
| 880 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 881 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 882 |
tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1, |
| 883 |
get_reloc_pcrel21b(s->code_ptr + 2)));
|
| 884 |
|
| 885 |
if (l->has_value) {
|
| 886 |
reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value); |
| 887 |
} else {
|
| 888 |
tcg_out_reloc(s, (s->code_ptr - 16) + 2, |
| 889 |
R_IA64_PCREL21B, label_index, 0);
|
| 890 |
} |
| 891 |
} |
| 892 |
|
| 893 |
static inline void tcg_out_call(TCGContext *s, TCGArg addr) |
| 894 |
{
|
| 895 |
tcg_out_bundle(s, MmI, |
| 896 |
tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr), |
| 897 |
tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
|
| 898 |
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, |
| 899 |
TCG_REG_B6, TCG_REG_R2, 0));
|
| 900 |
tcg_out_bundle(s, mmB, |
| 901 |
tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3), |
| 902 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 903 |
tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5, |
| 904 |
TCG_REG_B0, TCG_REG_B6)); |
| 905 |
} |
| 906 |
|
| 907 |
static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg) |
| 908 |
{
|
| 909 |
int64_t disp; |
| 910 |
uint64_t imm; |
| 911 |
|
| 912 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg); |
| 913 |
|
| 914 |
disp = tb_ret_addr - s->code_ptr; |
| 915 |
imm = (uint64_t)disp >> 4;
|
| 916 |
|
| 917 |
tcg_out_bundle(s, mLX, |
| 918 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 919 |
tcg_opc_l3 (imm), |
| 920 |
tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm)); |
| 921 |
} |
| 922 |
|
| 923 |
static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg) |
| 924 |
{
|
| 925 |
if (s->tb_jmp_offset) {
|
| 926 |
/* direct jump method */
|
| 927 |
tcg_abort(); |
| 928 |
} else {
|
| 929 |
/* indirect jump method */
|
| 930 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, |
| 931 |
(tcg_target_long)(s->tb_next + arg)); |
| 932 |
tcg_out_bundle(s, MmI, |
| 933 |
tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, |
| 934 |
TCG_REG_R2, TCG_REG_R2), |
| 935 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 936 |
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, |
| 937 |
TCG_REG_R2, 0));
|
| 938 |
tcg_out_bundle(s, mmB, |
| 939 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 940 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 941 |
tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, |
| 942 |
TCG_REG_B6)); |
| 943 |
} |
| 944 |
s->tb_next_offset[arg] = s->code_ptr - s->code_buf; |
| 945 |
} |
| 946 |
|
| 947 |
static inline void tcg_out_jmp(TCGContext *s, TCGArg addr) |
| 948 |
{
|
| 949 |
tcg_out_bundle(s, mmI, |
| 950 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 951 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 952 |
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
|
| 953 |
tcg_out_bundle(s, mmB, |
| 954 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 955 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 956 |
tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6)); |
| 957 |
} |
| 958 |
|
| 959 |
static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg, |
| 960 |
TCGArg arg1, tcg_target_long arg2) |
| 961 |
{
|
| 962 |
if (arg2 == ((int16_t)arg2 >> 2) << 2) { |
| 963 |
tcg_out_bundle(s, MmI, |
| 964 |
tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, |
| 965 |
TCG_REG_R2, arg2, arg1), |
| 966 |
tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), |
| 967 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 968 |
} else {
|
| 969 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2); |
| 970 |
tcg_out_bundle(s, MmI, |
| 971 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, |
| 972 |
TCG_REG_R2, TCG_REG_R2, arg1), |
| 973 |
tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), |
| 974 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 975 |
} |
| 976 |
} |
| 977 |
|
| 978 |
static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg, |
| 979 |
TCGArg arg1, tcg_target_long arg2) |
| 980 |
{
|
| 981 |
if (arg2 == ((int16_t)arg2 >> 2) << 2) { |
| 982 |
tcg_out_bundle(s, MmI, |
| 983 |
tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, |
| 984 |
TCG_REG_R2, arg2, arg1), |
| 985 |
tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), |
| 986 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 987 |
} else {
|
| 988 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2); |
| 989 |
tcg_out_bundle(s, MmI, |
| 990 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, |
| 991 |
TCG_REG_R2, TCG_REG_R2, arg1), |
| 992 |
tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), |
| 993 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 994 |
} |
| 995 |
} |
| 996 |
|
| 997 |
static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, |
| 998 |
TCGReg arg1, intptr_t arg2) |
| 999 |
{
|
| 1000 |
if (type == TCG_TYPE_I32) {
|
| 1001 |
tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2); |
| 1002 |
} else {
|
| 1003 |
tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2); |
| 1004 |
} |
| 1005 |
} |
| 1006 |
|
| 1007 |
static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, |
| 1008 |
TCGReg arg1, intptr_t arg2) |
| 1009 |
{
|
| 1010 |
if (type == TCG_TYPE_I32) {
|
| 1011 |
tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2); |
| 1012 |
} else {
|
| 1013 |
tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2); |
| 1014 |
} |
| 1015 |
} |
| 1016 |
|
| 1017 |
static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGArg ret, |
| 1018 |
TCGArg arg1, int const_arg1,
|
| 1019 |
TCGArg arg2, int const_arg2)
|
| 1020 |
{
|
| 1021 |
uint64_t opc1, opc2; |
| 1022 |
|
| 1023 |
if (const_arg1 && arg1 != 0) { |
| 1024 |
opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, |
| 1025 |
TCG_REG_R2, arg1, TCG_REG_R0); |
| 1026 |
arg1 = TCG_REG_R2; |
| 1027 |
} else {
|
| 1028 |
opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
|
| 1029 |
} |
| 1030 |
|
| 1031 |
if (const_arg2 && arg2 != 0) { |
| 1032 |
opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, |
| 1033 |
TCG_REG_R3, arg2, TCG_REG_R0); |
| 1034 |
arg2 = TCG_REG_R3; |
| 1035 |
} else {
|
| 1036 |
opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
|
| 1037 |
} |
| 1038 |
|
| 1039 |
tcg_out_bundle(s, mII, |
| 1040 |
opc1, |
| 1041 |
opc2, |
| 1042 |
tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2)); |
| 1043 |
} |
| 1044 |
|
| 1045 |
static inline void tcg_out_eqv(TCGContext *s, TCGArg ret, |
| 1046 |
TCGArg arg1, int const_arg1,
|
| 1047 |
TCGArg arg2, int const_arg2)
|
| 1048 |
{
|
| 1049 |
tcg_out_bundle(s, mII, |
| 1050 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1051 |
tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2), |
| 1052 |
tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
|
| 1053 |
} |
| 1054 |
|
| 1055 |
static inline void tcg_out_nand(TCGContext *s, TCGArg ret, |
| 1056 |
TCGArg arg1, int const_arg1,
|
| 1057 |
TCGArg arg2, int const_arg2)
|
| 1058 |
{
|
| 1059 |
tcg_out_bundle(s, mII, |
| 1060 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1061 |
tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2), |
| 1062 |
tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
|
| 1063 |
} |
| 1064 |
|
| 1065 |
static inline void tcg_out_nor(TCGContext *s, TCGArg ret, |
| 1066 |
TCGArg arg1, int const_arg1,
|
| 1067 |
TCGArg arg2, int const_arg2)
|
| 1068 |
{
|
| 1069 |
tcg_out_bundle(s, mII, |
| 1070 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1071 |
tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2), |
| 1072 |
tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
|
| 1073 |
} |
| 1074 |
|
| 1075 |
static inline void tcg_out_orc(TCGContext *s, TCGArg ret, |
| 1076 |
TCGArg arg1, int const_arg1,
|
| 1077 |
TCGArg arg2, int const_arg2)
|
| 1078 |
{
|
| 1079 |
tcg_out_bundle(s, mII, |
| 1080 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1081 |
tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
|
| 1082 |
tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2)); |
| 1083 |
} |
| 1084 |
|
| 1085 |
static inline void tcg_out_mul(TCGContext *s, TCGArg ret, |
| 1086 |
TCGArg arg1, TCGArg arg2) |
| 1087 |
{
|
| 1088 |
tcg_out_bundle(s, mmI, |
| 1089 |
tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1), |
| 1090 |
tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2), |
| 1091 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 1092 |
tcg_out_bundle(s, mmF, |
| 1093 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1094 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1095 |
tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6, |
| 1096 |
TCG_REG_F7, TCG_REG_F0)); |
| 1097 |
tcg_out_bundle(s, miI, |
| 1098 |
tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6), |
| 1099 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1100 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 1101 |
} |
| 1102 |
|
| 1103 |
static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
| 1104 |
TCGArg arg2, int const_arg2)
|
| 1105 |
{
|
| 1106 |
if (const_arg2) {
|
| 1107 |
tcg_out_bundle(s, miI, |
| 1108 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1109 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1110 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11, |
| 1111 |
ret, arg1, arg2, 31 - arg2));
|
| 1112 |
} else {
|
| 1113 |
tcg_out_bundle(s, mII, |
| 1114 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, |
| 1115 |
TCG_REG_R3, 0x1f, arg2),
|
| 1116 |
tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1), |
| 1117 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, |
| 1118 |
TCG_REG_R2, TCG_REG_R3)); |
| 1119 |
} |
| 1120 |
} |
| 1121 |
|
| 1122 |
static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
| 1123 |
TCGArg arg2, int const_arg2)
|
| 1124 |
{
|
| 1125 |
if (const_arg2) {
|
| 1126 |
tcg_out_bundle(s, miI, |
| 1127 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1128 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1129 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11, |
| 1130 |
ret, arg1, arg2, 63 - arg2));
|
| 1131 |
} else {
|
| 1132 |
tcg_out_bundle(s, miI, |
| 1133 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1134 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1135 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2)); |
| 1136 |
} |
| 1137 |
} |
| 1138 |
|
| 1139 |
static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
| 1140 |
TCGArg arg2, int const_arg2)
|
| 1141 |
{
|
| 1142 |
if (const_arg2) {
|
| 1143 |
tcg_out_bundle(s, miI, |
| 1144 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1145 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1146 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, |
| 1147 |
arg1, 63 - arg2, 31 - arg2)); |
| 1148 |
} else {
|
| 1149 |
tcg_out_bundle(s, mII, |
| 1150 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1151 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2, |
| 1152 |
0x1f, arg2),
|
| 1153 |
tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret, |
| 1154 |
arg1, TCG_REG_R2)); |
| 1155 |
} |
| 1156 |
} |
| 1157 |
|
| 1158 |
static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
| 1159 |
TCGArg arg2, int const_arg2)
|
| 1160 |
{
|
| 1161 |
if (const_arg2) {
|
| 1162 |
tcg_out_bundle(s, miI, |
| 1163 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1164 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1165 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, |
| 1166 |
arg1, 63 - arg2, 63 - arg2)); |
| 1167 |
} else {
|
| 1168 |
tcg_out_bundle(s, miI, |
| 1169 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1170 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1171 |
tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret, |
| 1172 |
arg1, arg2)); |
| 1173 |
} |
| 1174 |
} |
| 1175 |
|
| 1176 |
static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
| 1177 |
TCGArg arg2, int const_arg2)
|
| 1178 |
{
|
| 1179 |
if (const_arg2) {
|
| 1180 |
tcg_out_bundle(s, miI, |
| 1181 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1182 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1183 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, |
| 1184 |
arg1, arg2, 31 - arg2));
|
| 1185 |
} else {
|
| 1186 |
tcg_out_bundle(s, mII, |
| 1187 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, |
| 1188 |
0x1f, arg2),
|
| 1189 |
tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1), |
| 1190 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, |
| 1191 |
TCG_REG_R2, TCG_REG_R3)); |
| 1192 |
} |
| 1193 |
} |
| 1194 |
|
| 1195 |
static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
| 1196 |
TCGArg arg2, int const_arg2)
|
| 1197 |
{
|
| 1198 |
if (const_arg2) {
|
| 1199 |
tcg_out_bundle(s, miI, |
| 1200 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1201 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1202 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, |
| 1203 |
arg1, arg2, 63 - arg2));
|
| 1204 |
} else {
|
| 1205 |
tcg_out_bundle(s, miI, |
| 1206 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1207 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1208 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, |
| 1209 |
arg1, arg2)); |
| 1210 |
} |
| 1211 |
} |
| 1212 |
|
| 1213 |
static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
| 1214 |
TCGArg arg2, int const_arg2)
|
| 1215 |
{
|
| 1216 |
if (const_arg2) {
|
| 1217 |
tcg_out_bundle(s, mII, |
| 1218 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1219 |
tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
| 1220 |
TCG_REG_R2, arg1, arg1), |
| 1221 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, |
| 1222 |
TCG_REG_R2, 32 - arg2, 31)); |
| 1223 |
} else {
|
| 1224 |
tcg_out_bundle(s, miI, |
| 1225 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1226 |
tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
| 1227 |
TCG_REG_R2, arg1, arg1), |
| 1228 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, |
| 1229 |
0x1f, arg2));
|
| 1230 |
tcg_out_bundle(s, mII, |
| 1231 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1232 |
tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3, |
| 1233 |
0x20, TCG_REG_R3),
|
| 1234 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, |
| 1235 |
TCG_REG_R2, TCG_REG_R3)); |
| 1236 |
} |
| 1237 |
} |
| 1238 |
|
| 1239 |
static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
| 1240 |
TCGArg arg2, int const_arg2)
|
| 1241 |
{
|
| 1242 |
if (const_arg2) {
|
| 1243 |
tcg_out_bundle(s, miI, |
| 1244 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1245 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1246 |
tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1, |
| 1247 |
arg1, 0x40 - arg2));
|
| 1248 |
} else {
|
| 1249 |
tcg_out_bundle(s, mII, |
| 1250 |
tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2, |
| 1251 |
0x40, arg2),
|
| 1252 |
tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3, |
| 1253 |
arg1, arg2), |
| 1254 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2, |
| 1255 |
arg1, TCG_REG_R2)); |
| 1256 |
tcg_out_bundle(s, miI, |
| 1257 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1258 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1259 |
tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, |
| 1260 |
TCG_REG_R2, TCG_REG_R3)); |
| 1261 |
} |
| 1262 |
} |
| 1263 |
|
| 1264 |
static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
| 1265 |
TCGArg arg2, int const_arg2)
|
| 1266 |
{
|
| 1267 |
if (const_arg2) {
|
| 1268 |
tcg_out_bundle(s, mII, |
| 1269 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1270 |
tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
| 1271 |
TCG_REG_R2, arg1, arg1), |
| 1272 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, |
| 1273 |
TCG_REG_R2, arg2, 31));
|
| 1274 |
} else {
|
| 1275 |
tcg_out_bundle(s, mII, |
| 1276 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, |
| 1277 |
0x1f, arg2),
|
| 1278 |
tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
| 1279 |
TCG_REG_R2, arg1, arg1), |
| 1280 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, |
| 1281 |
TCG_REG_R2, TCG_REG_R3)); |
| 1282 |
} |
| 1283 |
} |
| 1284 |
|
| 1285 |
static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
| 1286 |
TCGArg arg2, int const_arg2)
|
| 1287 |
{
|
| 1288 |
if (const_arg2) {
|
| 1289 |
tcg_out_bundle(s, miI, |
| 1290 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1291 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1292 |
tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1, |
| 1293 |
arg1, arg2)); |
| 1294 |
} else {
|
| 1295 |
tcg_out_bundle(s, mII, |
| 1296 |
tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2, |
| 1297 |
0x40, arg2),
|
| 1298 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3, |
| 1299 |
arg1, arg2), |
| 1300 |
tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2, |
| 1301 |
arg1, TCG_REG_R2)); |
| 1302 |
tcg_out_bundle(s, miI, |
| 1303 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1304 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1305 |
tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, |
| 1306 |
TCG_REG_R2, TCG_REG_R3)); |
| 1307 |
} |
| 1308 |
} |
| 1309 |
|
| 1310 |
static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29, |
| 1311 |
TCGArg ret, TCGArg arg) |
| 1312 |
{
|
| 1313 |
tcg_out_bundle(s, miI, |
| 1314 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1315 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1316 |
tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg)); |
| 1317 |
} |
| 1318 |
|
| 1319 |
static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg) |
| 1320 |
{
|
| 1321 |
tcg_out_bundle(s, mII, |
| 1322 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1323 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15), |
| 1324 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
|
| 1325 |
} |
| 1326 |
|
| 1327 |
static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg) |
| 1328 |
{
|
| 1329 |
tcg_out_bundle(s, mII, |
| 1330 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1331 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31), |
| 1332 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
|
| 1333 |
} |
| 1334 |
|
| 1335 |
static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg) |
| 1336 |
{
|
| 1337 |
tcg_out_bundle(s, miI, |
| 1338 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1339 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1340 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
|
| 1341 |
} |
| 1342 |
|
| 1343 |
static inline void tcg_out_deposit(TCGContext *s, TCGArg ret, TCGArg a1, |
| 1344 |
TCGArg a2, int const_a2, int pos, int len) |
| 1345 |
{
|
| 1346 |
uint64_t i1 = 0, i2 = 0; |
| 1347 |
int cpos = 63 - pos, lm1 = len - 1; |
| 1348 |
|
| 1349 |
if (const_a2) {
|
| 1350 |
/* Truncate the value of a constant a2 to the width of the field. */
|
| 1351 |
int mask = (1u << len) - 1; |
| 1352 |
a2 &= mask; |
| 1353 |
|
| 1354 |
if (a2 == 0 || a2 == mask) { |
| 1355 |
/* 1-bit signed constant inserted into register. */
|
| 1356 |
i2 = tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, ret, a2, a1, cpos, lm1); |
| 1357 |
} else {
|
| 1358 |
/* Otherwise, load any constant into a temporary. Do this into
|
| 1359 |
the first I slot to help out with cross-unit delays. */
|
| 1360 |
i1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, |
| 1361 |
TCG_REG_R2, a2, TCG_REG_R0); |
| 1362 |
a2 = TCG_REG_R2; |
| 1363 |
} |
| 1364 |
} |
| 1365 |
if (i2 == 0) { |
| 1366 |
i2 = tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, ret, a2, a1, cpos, lm1); |
| 1367 |
} |
| 1368 |
tcg_out_bundle(s, (i1 ? mII : miI), |
| 1369 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1370 |
i1 ? i1 : tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1371 |
i2); |
| 1372 |
} |
| 1373 |
|
| 1374 |
static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1, |
| 1375 |
TCGArg arg2, int cmp4)
|
| 1376 |
{
|
| 1377 |
uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6; |
| 1378 |
|
| 1379 |
if (cmp4) {
|
| 1380 |
opc_eq_a6 = OPC_CMP4_EQ_A6; |
| 1381 |
opc_lt_a6 = OPC_CMP4_LT_A6; |
| 1382 |
opc_ltu_a6 = OPC_CMP4_LTU_A6; |
| 1383 |
} else {
|
| 1384 |
opc_eq_a6 = OPC_CMP_EQ_A6; |
| 1385 |
opc_lt_a6 = OPC_CMP_LT_A6; |
| 1386 |
opc_ltu_a6 = OPC_CMP_LTU_A6; |
| 1387 |
} |
| 1388 |
|
| 1389 |
switch (cond) {
|
| 1390 |
case TCG_COND_EQ:
|
| 1391 |
return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
|
| 1392 |
case TCG_COND_NE:
|
| 1393 |
return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
|
| 1394 |
case TCG_COND_LT:
|
| 1395 |
return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
|
| 1396 |
case TCG_COND_LTU:
|
| 1397 |
return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
|
| 1398 |
case TCG_COND_GE:
|
| 1399 |
return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
|
| 1400 |
case TCG_COND_GEU:
|
| 1401 |
return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
|
| 1402 |
case TCG_COND_LE:
|
| 1403 |
return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
|
| 1404 |
case TCG_COND_LEU:
|
| 1405 |
return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
|
| 1406 |
case TCG_COND_GT:
|
| 1407 |
return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
|
| 1408 |
case TCG_COND_GTU:
|
| 1409 |
return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
|
| 1410 |
default:
|
| 1411 |
tcg_abort(); |
| 1412 |
break;
|
| 1413 |
} |
| 1414 |
} |
| 1415 |
|
| 1416 |
static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGArg arg1, |
| 1417 |
int const_arg1, TCGArg arg2, int const_arg2, |
| 1418 |
int label_index, int cmp4) |
| 1419 |
{
|
| 1420 |
TCGLabel *l = &s->labels[label_index]; |
| 1421 |
uint64_t opc1, opc2; |
| 1422 |
|
| 1423 |
if (const_arg1 && arg1 != 0) { |
| 1424 |
opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2, |
| 1425 |
arg1, TCG_REG_R0); |
| 1426 |
arg1 = TCG_REG_R2; |
| 1427 |
} else {
|
| 1428 |
opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
|
| 1429 |
} |
| 1430 |
|
| 1431 |
if (const_arg2 && arg2 != 0) { |
| 1432 |
opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3, |
| 1433 |
arg2, TCG_REG_R0); |
| 1434 |
arg2 = TCG_REG_R3; |
| 1435 |
} else {
|
| 1436 |
opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
|
| 1437 |
} |
| 1438 |
|
| 1439 |
tcg_out_bundle(s, mII, |
| 1440 |
opc1, |
| 1441 |
opc2, |
| 1442 |
tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4)); |
| 1443 |
tcg_out_bundle(s, mmB, |
| 1444 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1445 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1446 |
tcg_opc_b1 (TCG_REG_P6, OPC_BR_DPTK_FEW_B1, |
| 1447 |
get_reloc_pcrel21b(s->code_ptr + 2)));
|
| 1448 |
|
| 1449 |
if (l->has_value) {
|
| 1450 |
reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value); |
| 1451 |
} else {
|
| 1452 |
tcg_out_reloc(s, (s->code_ptr - 16) + 2, |
| 1453 |
R_IA64_PCREL21B, label_index, 0);
|
| 1454 |
} |
| 1455 |
} |
| 1456 |
|
| 1457 |
static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret, |
| 1458 |
TCGArg arg1, TCGArg arg2, int cmp4)
|
| 1459 |
{
|
| 1460 |
tcg_out_bundle(s, MmI, |
| 1461 |
tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4), |
| 1462 |
tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0),
|
| 1463 |
tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
|
| 1464 |
} |
| 1465 |
|
| 1466 |
static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret, |
| 1467 |
TCGArg c1, TCGArg c2, |
| 1468 |
TCGArg v1, int const_v1,
|
| 1469 |
TCGArg v2, int const_v2, int cmp4) |
| 1470 |
{
|
| 1471 |
uint64_t opc1, opc2; |
| 1472 |
|
| 1473 |
if (const_v1) {
|
| 1474 |
opc1 = tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, v1, TCG_REG_R0); |
| 1475 |
} else if (ret == v1) { |
| 1476 |
opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
|
| 1477 |
} else {
|
| 1478 |
opc1 = tcg_opc_a4(TCG_REG_P6, OPC_ADDS_A4, ret, 0, v1);
|
| 1479 |
} |
| 1480 |
if (const_v2) {
|
| 1481 |
opc2 = tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, v2, TCG_REG_R0); |
| 1482 |
} else if (ret == v2) { |
| 1483 |
opc2 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
|
| 1484 |
} else {
|
| 1485 |
opc2 = tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, ret, 0, v2);
|
| 1486 |
} |
| 1487 |
|
| 1488 |
tcg_out_bundle(s, MmI, |
| 1489 |
tcg_opc_cmp_a(TCG_REG_P0, cond, c1, c2, cmp4), |
| 1490 |
opc1, |
| 1491 |
opc2); |
| 1492 |
} |
| 1493 |
|
| 1494 |
#if defined(CONFIG_SOFTMMU)
|
| 1495 |
/* Load and compare a TLB entry, and return the result in (p6, p7).
|
| 1496 |
R2 is loaded with the address of the addend TLB entry.
|
| 1497 |
R57 is loaded with the address, zero extented on 32-bit targets. */
|
| 1498 |
static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg, |
| 1499 |
int s_bits, uint64_t offset_rw,
|
| 1500 |
uint64_t offset_addend) |
| 1501 |
{
|
| 1502 |
tcg_out_bundle(s, mII, |
| 1503 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1504 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2, |
| 1505 |
addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
|
| 1506 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2, |
| 1507 |
TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS,
|
| 1508 |
63 - CPU_TLB_ENTRY_BITS));
|
| 1509 |
tcg_out_bundle(s, mII, |
| 1510 |
tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2, |
| 1511 |
offset_rw, TCG_REG_R2), |
| 1512 |
#if TARGET_LONG_BITS == 32 |
| 1513 |
tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R57, addr_reg), |
| 1514 |
#else
|
| 1515 |
tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R57, |
| 1516 |
0, addr_reg),
|
| 1517 |
#endif
|
| 1518 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
| 1519 |
TCG_REG_R2, TCG_AREG0)); |
| 1520 |
tcg_out_bundle(s, mII, |
| 1521 |
tcg_opc_m3 (TCG_REG_P0, |
| 1522 |
(TARGET_LONG_BITS == 32
|
| 1523 |
? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R56, |
| 1524 |
TCG_REG_R2, offset_addend - offset_rw), |
| 1525 |
tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, TCG_REG_R3, 0,
|
| 1526 |
TCG_REG_R57, 63 - s_bits,
|
| 1527 |
TARGET_PAGE_BITS - s_bits - 1),
|
| 1528 |
tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6, |
| 1529 |
TCG_REG_P7, TCG_REG_R3, TCG_REG_R56)); |
| 1530 |
} |
| 1531 |
|
| 1532 |
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
|
| 1533 |
int mmu_idx) */
|
| 1534 |
static const void * const qemu_ld_helpers[4] = { |
| 1535 |
helper_ldb_mmu, |
| 1536 |
helper_ldw_mmu, |
| 1537 |
helper_ldl_mmu, |
| 1538 |
helper_ldq_mmu, |
| 1539 |
}; |
| 1540 |
|
| 1541 |
static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) |
| 1542 |
{
|
| 1543 |
int addr_reg, data_reg, mem_index, s_bits, bswap;
|
| 1544 |
uint64_t opc_ld_m1[4] = { OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 };
|
| 1545 |
uint64_t opc_ext_i29[8] = { OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0, |
| 1546 |
OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 };
|
| 1547 |
|
| 1548 |
data_reg = *args++; |
| 1549 |
addr_reg = *args++; |
| 1550 |
mem_index = *args; |
| 1551 |
s_bits = opc & 3;
|
| 1552 |
|
| 1553 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 1554 |
bswap = 1;
|
| 1555 |
#else
|
| 1556 |
bswap = 0;
|
| 1557 |
#endif
|
| 1558 |
|
| 1559 |
/* Read the TLB entry */
|
| 1560 |
tcg_out_qemu_tlb(s, addr_reg, s_bits, |
| 1561 |
offsetof(CPUArchState, tlb_table[mem_index][0].addr_read),
|
| 1562 |
offsetof(CPUArchState, tlb_table[mem_index][0].addend));
|
| 1563 |
|
| 1564 |
/* P6 is the fast path, and P7 the slow path */
|
| 1565 |
tcg_out_bundle(s, mLX, |
| 1566 |
tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, |
| 1567 |
TCG_REG_R56, 0, TCG_AREG0),
|
| 1568 |
tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]), |
| 1569 |
tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2, |
| 1570 |
(tcg_target_long) qemu_ld_helpers[s_bits])); |
| 1571 |
tcg_out_bundle(s, MmI, |
| 1572 |
tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3, |
| 1573 |
TCG_REG_R2, 8),
|
| 1574 |
tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3, |
| 1575 |
TCG_REG_R3, TCG_REG_R57), |
| 1576 |
tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, |
| 1577 |
TCG_REG_R3, 0));
|
| 1578 |
if (bswap && s_bits == 1) { |
| 1579 |
tcg_out_bundle(s, MmI, |
| 1580 |
tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], |
| 1581 |
TCG_REG_R8, TCG_REG_R3), |
| 1582 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), |
| 1583 |
tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, |
| 1584 |
TCG_REG_R8, TCG_REG_R8, 15, 15)); |
| 1585 |
} else if (bswap && s_bits == 2) { |
| 1586 |
tcg_out_bundle(s, MmI, |
| 1587 |
tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], |
| 1588 |
TCG_REG_R8, TCG_REG_R3), |
| 1589 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), |
| 1590 |
tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, |
| 1591 |
TCG_REG_R8, TCG_REG_R8, 31, 31)); |
| 1592 |
} else {
|
| 1593 |
tcg_out_bundle(s, mmI, |
| 1594 |
tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], |
| 1595 |
TCG_REG_R8, TCG_REG_R3), |
| 1596 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), |
| 1597 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 1598 |
} |
| 1599 |
if (!bswap || s_bits == 0) { |
| 1600 |
tcg_out_bundle(s, miB, |
| 1601 |
tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58, |
| 1602 |
mem_index, TCG_REG_R0), |
| 1603 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1604 |
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, |
| 1605 |
TCG_REG_B0, TCG_REG_B6)); |
| 1606 |
} else {
|
| 1607 |
tcg_out_bundle(s, miB, |
| 1608 |
tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58, |
| 1609 |
mem_index, TCG_REG_R0), |
| 1610 |
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
| 1611 |
TCG_REG_R8, TCG_REG_R8, 0xb),
|
| 1612 |
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, |
| 1613 |
TCG_REG_B0, TCG_REG_B6)); |
| 1614 |
} |
| 1615 |
|
| 1616 |
if (opc == 3) { |
| 1617 |
tcg_out_bundle(s, miI, |
| 1618 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1619 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1620 |
tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, |
| 1621 |
data_reg, 0, TCG_REG_R8));
|
| 1622 |
} else {
|
| 1623 |
tcg_out_bundle(s, miI, |
| 1624 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1625 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1626 |
tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc], |
| 1627 |
data_reg, TCG_REG_R8)); |
| 1628 |
} |
| 1629 |
} |
| 1630 |
|
| 1631 |
/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
|
| 1632 |
uintxx_t val, int mmu_idx) */
|
| 1633 |
static const void * const qemu_st_helpers[4] = { |
| 1634 |
helper_stb_mmu, |
| 1635 |
helper_stw_mmu, |
| 1636 |
helper_stl_mmu, |
| 1637 |
helper_stq_mmu, |
| 1638 |
}; |
| 1639 |
|
| 1640 |
static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) |
| 1641 |
{
|
| 1642 |
int addr_reg, data_reg, mem_index, bswap;
|
| 1643 |
uint64_t opc_st_m4[4] = { OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 };
|
| 1644 |
|
| 1645 |
data_reg = *args++; |
| 1646 |
addr_reg = *args++; |
| 1647 |
mem_index = *args; |
| 1648 |
|
| 1649 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 1650 |
bswap = 1;
|
| 1651 |
#else
|
| 1652 |
bswap = 0;
|
| 1653 |
#endif
|
| 1654 |
|
| 1655 |
tcg_out_qemu_tlb(s, addr_reg, opc, |
| 1656 |
offsetof(CPUArchState, tlb_table[mem_index][0].addr_write),
|
| 1657 |
offsetof(CPUArchState, tlb_table[mem_index][0].addend));
|
| 1658 |
|
| 1659 |
/* P6 is the fast path, and P7 the slow path */
|
| 1660 |
tcg_out_bundle(s, mLX, |
| 1661 |
tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, |
| 1662 |
TCG_REG_R56, 0, TCG_AREG0),
|
| 1663 |
tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[opc]), |
| 1664 |
tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2, |
| 1665 |
(tcg_target_long) qemu_st_helpers[opc])); |
| 1666 |
tcg_out_bundle(s, MmI, |
| 1667 |
tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3, |
| 1668 |
TCG_REG_R2, 8),
|
| 1669 |
tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3, |
| 1670 |
TCG_REG_R3, TCG_REG_R57), |
| 1671 |
tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, |
| 1672 |
TCG_REG_R3, 0));
|
| 1673 |
|
| 1674 |
if (!bswap || opc == 0) { |
| 1675 |
tcg_out_bundle(s, mii, |
| 1676 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
| 1677 |
TCG_REG_R1, TCG_REG_R2), |
| 1678 |
tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58, |
| 1679 |
0, data_reg),
|
| 1680 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 1681 |
} else if (opc == 1) { |
| 1682 |
tcg_out_bundle(s, miI, |
| 1683 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
| 1684 |
TCG_REG_R1, TCG_REG_R2), |
| 1685 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1686 |
tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, |
| 1687 |
TCG_REG_R2, data_reg, 15, 15)); |
| 1688 |
tcg_out_bundle(s, miI, |
| 1689 |
tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58, |
| 1690 |
0, data_reg),
|
| 1691 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1692 |
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
| 1693 |
TCG_REG_R2, TCG_REG_R2, 0xb));
|
| 1694 |
data_reg = TCG_REG_R2; |
| 1695 |
} else if (opc == 2) { |
| 1696 |
tcg_out_bundle(s, miI, |
| 1697 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
| 1698 |
TCG_REG_R1, TCG_REG_R2), |
| 1699 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1700 |
tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, |
| 1701 |
TCG_REG_R2, data_reg, 31, 31)); |
| 1702 |
tcg_out_bundle(s, miI, |
| 1703 |
tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58, |
| 1704 |
0, data_reg),
|
| 1705 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1706 |
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
| 1707 |
TCG_REG_R2, TCG_REG_R2, 0xb));
|
| 1708 |
data_reg = TCG_REG_R2; |
| 1709 |
} else if (opc == 3) { |
| 1710 |
tcg_out_bundle(s, miI, |
| 1711 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
| 1712 |
TCG_REG_R1, TCG_REG_R2), |
| 1713 |
tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58, |
| 1714 |
0, data_reg),
|
| 1715 |
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
| 1716 |
TCG_REG_R2, data_reg, 0xb));
|
| 1717 |
data_reg = TCG_REG_R2; |
| 1718 |
} |
| 1719 |
|
| 1720 |
tcg_out_bundle(s, miB, |
| 1721 |
tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc], |
| 1722 |
data_reg, TCG_REG_R3), |
| 1723 |
tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59, |
| 1724 |
mem_index, TCG_REG_R0), |
| 1725 |
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, |
| 1726 |
TCG_REG_B0, TCG_REG_B6)); |
| 1727 |
} |
| 1728 |
|
| 1729 |
#else /* !CONFIG_SOFTMMU */ |
| 1730 |
|
| 1731 |
static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) |
| 1732 |
{
|
| 1733 |
static uint64_t const opc_ld_m1[4] = { |
| 1734 |
OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 |
| 1735 |
}; |
| 1736 |
static uint64_t const opc_sxt_i29[4] = { |
| 1737 |
OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
|
| 1738 |
}; |
| 1739 |
int addr_reg, data_reg, s_bits, bswap;
|
| 1740 |
|
| 1741 |
data_reg = *args++; |
| 1742 |
addr_reg = *args++; |
| 1743 |
s_bits = opc & 3;
|
| 1744 |
|
| 1745 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 1746 |
bswap = 1;
|
| 1747 |
#else
|
| 1748 |
bswap = 0;
|
| 1749 |
#endif
|
| 1750 |
|
| 1751 |
#if TARGET_LONG_BITS == 32 |
| 1752 |
if (GUEST_BASE != 0) { |
| 1753 |
tcg_out_bundle(s, mII, |
| 1754 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1755 |
tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, |
| 1756 |
TCG_REG_R3, addr_reg), |
| 1757 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
| 1758 |
TCG_GUEST_BASE_REG, TCG_REG_R3)); |
| 1759 |
} else {
|
| 1760 |
tcg_out_bundle(s, miI, |
| 1761 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1762 |
tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, |
| 1763 |
TCG_REG_R2, addr_reg), |
| 1764 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 1765 |
} |
| 1766 |
|
| 1767 |
if (!bswap || s_bits == 0) { |
| 1768 |
if (s_bits == opc) {
|
| 1769 |
tcg_out_bundle(s, miI, |
| 1770 |
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
| 1771 |
data_reg, TCG_REG_R2), |
| 1772 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1773 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 1774 |
} else {
|
| 1775 |
tcg_out_bundle(s, mII, |
| 1776 |
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
| 1777 |
data_reg, TCG_REG_R2), |
| 1778 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1779 |
tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], |
| 1780 |
data_reg, data_reg)); |
| 1781 |
} |
| 1782 |
} else if (s_bits == 3) { |
| 1783 |
tcg_out_bundle(s, mII, |
| 1784 |
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
| 1785 |
data_reg, TCG_REG_R2), |
| 1786 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1787 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
| 1788 |
data_reg, data_reg, 0xb));
|
| 1789 |
} else {
|
| 1790 |
if (s_bits == 1) { |
| 1791 |
tcg_out_bundle(s, mII, |
| 1792 |
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
| 1793 |
data_reg, TCG_REG_R2), |
| 1794 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1795 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
| 1796 |
data_reg, data_reg, 15, 15)); |
| 1797 |
} else {
|
| 1798 |
tcg_out_bundle(s, mII, |
| 1799 |
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
| 1800 |
data_reg, TCG_REG_R2), |
| 1801 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1802 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
| 1803 |
data_reg, data_reg, 31, 31)); |
| 1804 |
} |
| 1805 |
if (opc == s_bits) {
|
| 1806 |
tcg_out_bundle(s, miI, |
| 1807 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1808 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1809 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
| 1810 |
data_reg, data_reg, 0xb));
|
| 1811 |
} else {
|
| 1812 |
tcg_out_bundle(s, mII, |
| 1813 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1814 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
| 1815 |
data_reg, data_reg, 0xb),
|
| 1816 |
tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], |
| 1817 |
data_reg, data_reg)); |
| 1818 |
} |
| 1819 |
} |
| 1820 |
#else
|
| 1821 |
if (GUEST_BASE != 0) { |
| 1822 |
tcg_out_bundle(s, MmI, |
| 1823 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
| 1824 |
TCG_GUEST_BASE_REG, addr_reg), |
| 1825 |
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
| 1826 |
data_reg, TCG_REG_R2), |
| 1827 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 1828 |
} else {
|
| 1829 |
tcg_out_bundle(s, mmI, |
| 1830 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1831 |
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
| 1832 |
data_reg, addr_reg), |
| 1833 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 1834 |
} |
| 1835 |
|
| 1836 |
if (bswap && s_bits == 1) { |
| 1837 |
tcg_out_bundle(s, mII, |
| 1838 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1839 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
| 1840 |
data_reg, data_reg, 15, 15), |
| 1841 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
| 1842 |
data_reg, data_reg, 0xb));
|
| 1843 |
} else if (bswap && s_bits == 2) { |
| 1844 |
tcg_out_bundle(s, mII, |
| 1845 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1846 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
| 1847 |
data_reg, data_reg, 31, 31), |
| 1848 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
| 1849 |
data_reg, data_reg, 0xb));
|
| 1850 |
} else if (bswap && s_bits == 3) { |
| 1851 |
tcg_out_bundle(s, miI, |
| 1852 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1853 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1854 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
| 1855 |
data_reg, data_reg, 0xb));
|
| 1856 |
} |
| 1857 |
if (s_bits != opc) {
|
| 1858 |
tcg_out_bundle(s, miI, |
| 1859 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1860 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1861 |
tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], |
| 1862 |
data_reg, data_reg)); |
| 1863 |
} |
| 1864 |
#endif
|
| 1865 |
} |
| 1866 |
|
| 1867 |
static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) |
| 1868 |
{
|
| 1869 |
static uint64_t const opc_st_m4[4] = { |
| 1870 |
OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 |
| 1871 |
}; |
| 1872 |
int addr_reg, data_reg, bswap;
|
| 1873 |
#if TARGET_LONG_BITS == 64 |
| 1874 |
uint64_t add_guest_base; |
| 1875 |
#endif
|
| 1876 |
|
| 1877 |
data_reg = *args++; |
| 1878 |
addr_reg = *args++; |
| 1879 |
|
| 1880 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 1881 |
bswap = 1;
|
| 1882 |
#else
|
| 1883 |
bswap = 0;
|
| 1884 |
#endif
|
| 1885 |
|
| 1886 |
#if TARGET_LONG_BITS == 32 |
| 1887 |
if (GUEST_BASE != 0) { |
| 1888 |
tcg_out_bundle(s, mII, |
| 1889 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1890 |
tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, |
| 1891 |
TCG_REG_R3, addr_reg), |
| 1892 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
| 1893 |
TCG_GUEST_BASE_REG, TCG_REG_R3)); |
| 1894 |
} else {
|
| 1895 |
tcg_out_bundle(s, miI, |
| 1896 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1897 |
tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, |
| 1898 |
TCG_REG_R2, addr_reg), |
| 1899 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 1900 |
} |
| 1901 |
|
| 1902 |
if (bswap) {
|
| 1903 |
if (opc == 1) { |
| 1904 |
tcg_out_bundle(s, mII, |
| 1905 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1906 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
| 1907 |
TCG_REG_R3, data_reg, 15, 15), |
| 1908 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
| 1909 |
TCG_REG_R3, TCG_REG_R3, 0xb));
|
| 1910 |
data_reg = TCG_REG_R3; |
| 1911 |
} else if (opc == 2) { |
| 1912 |
tcg_out_bundle(s, mII, |
| 1913 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1914 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
| 1915 |
TCG_REG_R3, data_reg, 31, 31), |
| 1916 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
| 1917 |
TCG_REG_R3, TCG_REG_R3, 0xb));
|
| 1918 |
data_reg = TCG_REG_R3; |
| 1919 |
} else if (opc == 3) { |
| 1920 |
tcg_out_bundle(s, miI, |
| 1921 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1922 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1923 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
| 1924 |
TCG_REG_R3, data_reg, 0xb));
|
| 1925 |
data_reg = TCG_REG_R3; |
| 1926 |
} |
| 1927 |
} |
| 1928 |
tcg_out_bundle(s, mmI, |
| 1929 |
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], |
| 1930 |
data_reg, TCG_REG_R2), |
| 1931 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 1932 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 1933 |
#else
|
| 1934 |
if (GUEST_BASE != 0) { |
| 1935 |
add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
| 1936 |
TCG_GUEST_BASE_REG, addr_reg); |
| 1937 |
addr_reg = TCG_REG_R2; |
| 1938 |
} else {
|
| 1939 |
add_guest_base = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
|
| 1940 |
} |
| 1941 |
|
| 1942 |
if (!bswap || opc == 0) { |
| 1943 |
tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI), |
| 1944 |
add_guest_base, |
| 1945 |
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], |
| 1946 |
data_reg, addr_reg), |
| 1947 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 1948 |
} else {
|
| 1949 |
if (opc == 1) { |
| 1950 |
tcg_out_bundle(s, mII, |
| 1951 |
add_guest_base, |
| 1952 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
| 1953 |
TCG_REG_R3, data_reg, 15, 15), |
| 1954 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
| 1955 |
TCG_REG_R3, TCG_REG_R3, 0xb));
|
| 1956 |
data_reg = TCG_REG_R3; |
| 1957 |
} else if (opc == 2) { |
| 1958 |
tcg_out_bundle(s, mII, |
| 1959 |
add_guest_base, |
| 1960 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
| 1961 |
TCG_REG_R3, data_reg, 31, 31), |
| 1962 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
| 1963 |
TCG_REG_R3, TCG_REG_R3, 0xb));
|
| 1964 |
data_reg = TCG_REG_R3; |
| 1965 |
} else if (opc == 3) { |
| 1966 |
tcg_out_bundle(s, miI, |
| 1967 |
add_guest_base, |
| 1968 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1969 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
| 1970 |
TCG_REG_R3, data_reg, 0xb));
|
| 1971 |
data_reg = TCG_REG_R3; |
| 1972 |
} |
| 1973 |
tcg_out_bundle(s, miI, |
| 1974 |
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], |
| 1975 |
data_reg, addr_reg), |
| 1976 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
| 1977 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
| 1978 |
} |
| 1979 |
#endif
|
| 1980 |
} |
| 1981 |
|
| 1982 |
#endif
|
| 1983 |
|
| 1984 |
static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, |
| 1985 |
const TCGArg *args, const int *const_args) |
| 1986 |
{
|
| 1987 |
switch(opc) {
|
| 1988 |
case INDEX_op_exit_tb:
|
| 1989 |
tcg_out_exit_tb(s, args[0]);
|
| 1990 |
break;
|
| 1991 |
case INDEX_op_br:
|
| 1992 |
tcg_out_br(s, args[0]);
|
| 1993 |
break;
|
| 1994 |
case INDEX_op_call:
|
| 1995 |
tcg_out_call(s, args[0]);
|
| 1996 |
break;
|
| 1997 |
case INDEX_op_goto_tb:
|
| 1998 |
tcg_out_goto_tb(s, args[0]);
|
| 1999 |
break;
|
| 2000 |
|
| 2001 |
case INDEX_op_movi_i32:
|
| 2002 |
tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]); |
| 2003 |
break;
|
| 2004 |
case INDEX_op_movi_i64:
|
| 2005 |
tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
| 2006 |
break;
|
| 2007 |
|
| 2008 |
case INDEX_op_ld8u_i32:
|
| 2009 |
case INDEX_op_ld8u_i64:
|
| 2010 |
tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]); |
| 2011 |
break;
|
| 2012 |
case INDEX_op_ld8s_i32:
|
| 2013 |
case INDEX_op_ld8s_i64:
|
| 2014 |
tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]); |
| 2015 |
tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]); |
| 2016 |
break;
|
| 2017 |
case INDEX_op_ld16u_i32:
|
| 2018 |
case INDEX_op_ld16u_i64:
|
| 2019 |
tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]); |
| 2020 |
break;
|
| 2021 |
case INDEX_op_ld16s_i32:
|
| 2022 |
case INDEX_op_ld16s_i64:
|
| 2023 |
tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]); |
| 2024 |
tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]); |
| 2025 |
break;
|
| 2026 |
case INDEX_op_ld_i32:
|
| 2027 |
case INDEX_op_ld32u_i64:
|
| 2028 |
tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]); |
| 2029 |
break;
|
| 2030 |
case INDEX_op_ld32s_i64:
|
| 2031 |
tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]); |
| 2032 |
tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]); |
| 2033 |
break;
|
| 2034 |
case INDEX_op_ld_i64:
|
| 2035 |
tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]); |
| 2036 |
break;
|
| 2037 |
case INDEX_op_st8_i32:
|
| 2038 |
case INDEX_op_st8_i64:
|
| 2039 |
tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]); |
| 2040 |
break;
|
| 2041 |
case INDEX_op_st16_i32:
|
| 2042 |
case INDEX_op_st16_i64:
|
| 2043 |
tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]); |
| 2044 |
break;
|
| 2045 |
case INDEX_op_st_i32:
|
| 2046 |
case INDEX_op_st32_i64:
|
| 2047 |
tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]); |
| 2048 |
break;
|
| 2049 |
case INDEX_op_st_i64:
|
| 2050 |
tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]); |
| 2051 |
break;
|
| 2052 |
|
| 2053 |
case INDEX_op_add_i32:
|
| 2054 |
case INDEX_op_add_i64:
|
| 2055 |
tcg_out_alu(s, OPC_ADD_A1, args[0], args[1], const_args[1], |
| 2056 |
args[2], const_args[2]); |
| 2057 |
break;
|
| 2058 |
case INDEX_op_sub_i32:
|
| 2059 |
case INDEX_op_sub_i64:
|
| 2060 |
tcg_out_alu(s, OPC_SUB_A1, args[0], args[1], const_args[1], |
| 2061 |
args[2], const_args[2]); |
| 2062 |
break;
|
| 2063 |
|
| 2064 |
case INDEX_op_and_i32:
|
| 2065 |
case INDEX_op_and_i64:
|
| 2066 |
tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1], |
| 2067 |
args[2], const_args[2]); |
| 2068 |
break;
|
| 2069 |
case INDEX_op_andc_i32:
|
| 2070 |
case INDEX_op_andc_i64:
|
| 2071 |
tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1], |
| 2072 |
args[2], const_args[2]); |
| 2073 |
break;
|
| 2074 |
case INDEX_op_eqv_i32:
|
| 2075 |
case INDEX_op_eqv_i64:
|
| 2076 |
tcg_out_eqv(s, args[0], args[1], const_args[1], |
| 2077 |
args[2], const_args[2]); |
| 2078 |
break;
|
| 2079 |
case INDEX_op_nand_i32:
|
| 2080 |
case INDEX_op_nand_i64:
|
| 2081 |
tcg_out_nand(s, args[0], args[1], const_args[1], |
| 2082 |
args[2], const_args[2]); |
| 2083 |
break;
|
| 2084 |
case INDEX_op_nor_i32:
|
| 2085 |
case INDEX_op_nor_i64:
|
| 2086 |
tcg_out_nor(s, args[0], args[1], const_args[1], |
| 2087 |
args[2], const_args[2]); |
| 2088 |
break;
|
| 2089 |
case INDEX_op_or_i32:
|
| 2090 |
case INDEX_op_or_i64:
|
| 2091 |
tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1], |
| 2092 |
args[2], const_args[2]); |
| 2093 |
break;
|
| 2094 |
case INDEX_op_orc_i32:
|
| 2095 |
case INDEX_op_orc_i64:
|
| 2096 |
tcg_out_orc(s, args[0], args[1], const_args[1], |
| 2097 |
args[2], const_args[2]); |
| 2098 |
break;
|
| 2099 |
case INDEX_op_xor_i32:
|
| 2100 |
case INDEX_op_xor_i64:
|
| 2101 |
tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1], |
| 2102 |
args[2], const_args[2]); |
| 2103 |
break;
|
| 2104 |
|
| 2105 |
case INDEX_op_mul_i32:
|
| 2106 |
case INDEX_op_mul_i64:
|
| 2107 |
tcg_out_mul(s, args[0], args[1], args[2]); |
| 2108 |
break;
|
| 2109 |
|
| 2110 |
case INDEX_op_sar_i32:
|
| 2111 |
tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]); |
| 2112 |
break;
|
| 2113 |
case INDEX_op_sar_i64:
|
| 2114 |
tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]); |
| 2115 |
break;
|
| 2116 |
case INDEX_op_shl_i32:
|
| 2117 |
tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]); |
| 2118 |
break;
|
| 2119 |
case INDEX_op_shl_i64:
|
| 2120 |
tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]); |
| 2121 |
break;
|
| 2122 |
case INDEX_op_shr_i32:
|
| 2123 |
tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]); |
| 2124 |
break;
|
| 2125 |
case INDEX_op_shr_i64:
|
| 2126 |
tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]); |
| 2127 |
break;
|
| 2128 |
case INDEX_op_rotl_i32:
|
| 2129 |
tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]); |
| 2130 |
break;
|
| 2131 |
case INDEX_op_rotl_i64:
|
| 2132 |
tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]); |
| 2133 |
break;
|
| 2134 |
case INDEX_op_rotr_i32:
|
| 2135 |
tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]); |
| 2136 |
break;
|
| 2137 |
case INDEX_op_rotr_i64:
|
| 2138 |
tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]); |
| 2139 |
break;
|
| 2140 |
|
| 2141 |
case INDEX_op_ext8s_i32:
|
| 2142 |
case INDEX_op_ext8s_i64:
|
| 2143 |
tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]); |
| 2144 |
break;
|
| 2145 |
case INDEX_op_ext8u_i32:
|
| 2146 |
case INDEX_op_ext8u_i64:
|
| 2147 |
tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]); |
| 2148 |
break;
|
| 2149 |
case INDEX_op_ext16s_i32:
|
| 2150 |
case INDEX_op_ext16s_i64:
|
| 2151 |
tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]); |
| 2152 |
break;
|
| 2153 |
case INDEX_op_ext16u_i32:
|
| 2154 |
case INDEX_op_ext16u_i64:
|
| 2155 |
tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]); |
| 2156 |
break;
|
| 2157 |
case INDEX_op_ext32s_i64:
|
| 2158 |
tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]); |
| 2159 |
break;
|
| 2160 |
case INDEX_op_ext32u_i64:
|
| 2161 |
tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]); |
| 2162 |
break;
|
| 2163 |
|
| 2164 |
case INDEX_op_bswap16_i32:
|
| 2165 |
case INDEX_op_bswap16_i64:
|
| 2166 |
tcg_out_bswap16(s, args[0], args[1]); |
| 2167 |
break;
|
| 2168 |
case INDEX_op_bswap32_i32:
|
| 2169 |
case INDEX_op_bswap32_i64:
|
| 2170 |
tcg_out_bswap32(s, args[0], args[1]); |
| 2171 |
break;
|
| 2172 |
case INDEX_op_bswap64_i64:
|
| 2173 |
tcg_out_bswap64(s, args[0], args[1]); |
| 2174 |
break;
|
| 2175 |
|
| 2176 |
case INDEX_op_deposit_i32:
|
| 2177 |
case INDEX_op_deposit_i64:
|
| 2178 |
tcg_out_deposit(s, args[0], args[1], args[2], const_args[2], |
| 2179 |
args[3], args[4]); |
| 2180 |
break;
|
| 2181 |
|
| 2182 |
case INDEX_op_brcond_i32:
|
| 2183 |
tcg_out_brcond(s, args[2], args[0], const_args[0], |
| 2184 |
args[1], const_args[1], args[3], 1); |
| 2185 |
break;
|
| 2186 |
case INDEX_op_brcond_i64:
|
| 2187 |
tcg_out_brcond(s, args[2], args[0], const_args[0], |
| 2188 |
args[1], const_args[1], args[3], 0); |
| 2189 |
break;
|
| 2190 |
case INDEX_op_setcond_i32:
|
| 2191 |
tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1); |
| 2192 |
break;
|
| 2193 |
case INDEX_op_setcond_i64:
|
| 2194 |
tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0); |
| 2195 |
break;
|
| 2196 |
case INDEX_op_movcond_i32:
|
| 2197 |
tcg_out_movcond(s, args[5], args[0], args[1], args[2], |
| 2198 |
args[3], const_args[3], args[4], const_args[4], 1); |
| 2199 |
break;
|
| 2200 |
case INDEX_op_movcond_i64:
|
| 2201 |
tcg_out_movcond(s, args[5], args[0], args[1], args[2], |
| 2202 |
args[3], const_args[3], args[4], const_args[4], 0); |
| 2203 |
break;
|
| 2204 |
|
| 2205 |
case INDEX_op_qemu_ld8u:
|
| 2206 |
tcg_out_qemu_ld(s, args, 0);
|
| 2207 |
break;
|
| 2208 |
case INDEX_op_qemu_ld8s:
|
| 2209 |
tcg_out_qemu_ld(s, args, 0 | 4); |
| 2210 |
break;
|
| 2211 |
case INDEX_op_qemu_ld16u:
|
| 2212 |
tcg_out_qemu_ld(s, args, 1);
|
| 2213 |
break;
|
| 2214 |
case INDEX_op_qemu_ld16s:
|
| 2215 |
tcg_out_qemu_ld(s, args, 1 | 4); |
| 2216 |
break;
|
| 2217 |
case INDEX_op_qemu_ld32:
|
| 2218 |
case INDEX_op_qemu_ld32u:
|
| 2219 |
tcg_out_qemu_ld(s, args, 2);
|
| 2220 |
break;
|
| 2221 |
case INDEX_op_qemu_ld32s:
|
| 2222 |
tcg_out_qemu_ld(s, args, 2 | 4); |
| 2223 |
break;
|
| 2224 |
case INDEX_op_qemu_ld64:
|
| 2225 |
tcg_out_qemu_ld(s, args, 3);
|
| 2226 |
break;
|
| 2227 |
|
| 2228 |
case INDEX_op_qemu_st8:
|
| 2229 |
tcg_out_qemu_st(s, args, 0);
|
| 2230 |
break;
|
| 2231 |
case INDEX_op_qemu_st16:
|
| 2232 |
tcg_out_qemu_st(s, args, 1);
|
| 2233 |
break;
|
| 2234 |
case INDEX_op_qemu_st32:
|
| 2235 |
tcg_out_qemu_st(s, args, 2);
|
| 2236 |
break;
|
| 2237 |
case INDEX_op_qemu_st64:
|
| 2238 |
tcg_out_qemu_st(s, args, 3);
|
| 2239 |
break;
|
| 2240 |
|
| 2241 |
default:
|
| 2242 |
tcg_abort(); |
| 2243 |
} |
| 2244 |
} |
| 2245 |
|
| 2246 |
static const TCGTargetOpDef ia64_op_defs[] = { |
| 2247 |
{ INDEX_op_br, { } },
|
| 2248 |
{ INDEX_op_call, { "r" } },
|
| 2249 |
{ INDEX_op_exit_tb, { } },
|
| 2250 |
{ INDEX_op_goto_tb, { } },
|
| 2251 |
|
| 2252 |
{ INDEX_op_mov_i32, { "r", "r" } },
|
| 2253 |
{ INDEX_op_movi_i32, { "r" } },
|
| 2254 |
|
| 2255 |
{ INDEX_op_ld8u_i32, { "r", "r" } },
|
| 2256 |
{ INDEX_op_ld8s_i32, { "r", "r" } },
|
| 2257 |
{ INDEX_op_ld16u_i32, { "r", "r" } },
|
| 2258 |
{ INDEX_op_ld16s_i32, { "r", "r" } },
|
| 2259 |
{ INDEX_op_ld_i32, { "r", "r" } },
|
| 2260 |
{ INDEX_op_st8_i32, { "rZ", "r" } },
|
| 2261 |
{ INDEX_op_st16_i32, { "rZ", "r" } },
|
| 2262 |
{ INDEX_op_st_i32, { "rZ", "r" } },
|
| 2263 |
|
| 2264 |
{ INDEX_op_add_i32, { "r", "rI", "rI" } },
|
| 2265 |
{ INDEX_op_sub_i32, { "r", "rI", "rI" } },
|
| 2266 |
|
| 2267 |
{ INDEX_op_and_i32, { "r", "rI", "rI" } },
|
| 2268 |
{ INDEX_op_andc_i32, { "r", "rI", "rI" } },
|
| 2269 |
{ INDEX_op_eqv_i32, { "r", "rZ", "rZ" } },
|
| 2270 |
{ INDEX_op_nand_i32, { "r", "rZ", "rZ" } },
|
| 2271 |
{ INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
|
| 2272 |
{ INDEX_op_or_i32, { "r", "rI", "rI" } },
|
| 2273 |
{ INDEX_op_orc_i32, { "r", "rZ", "rZ" } },
|
| 2274 |
{ INDEX_op_xor_i32, { "r", "rI", "rI" } },
|
| 2275 |
|
| 2276 |
{ INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
|
| 2277 |
|
| 2278 |
{ INDEX_op_sar_i32, { "r", "rZ", "ri" } },
|
| 2279 |
{ INDEX_op_shl_i32, { "r", "rZ", "ri" } },
|
| 2280 |
{ INDEX_op_shr_i32, { "r", "rZ", "ri" } },
|
| 2281 |
{ INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
|
| 2282 |
{ INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
|
| 2283 |
|
| 2284 |
{ INDEX_op_ext8s_i32, { "r", "rZ"} },
|
| 2285 |
{ INDEX_op_ext8u_i32, { "r", "rZ"} },
|
| 2286 |
{ INDEX_op_ext16s_i32, { "r", "rZ"} },
|
| 2287 |
{ INDEX_op_ext16u_i32, { "r", "rZ"} },
|
| 2288 |
|
| 2289 |
{ INDEX_op_bswap16_i32, { "r", "rZ" } },
|
| 2290 |
{ INDEX_op_bswap32_i32, { "r", "rZ" } },
|
| 2291 |
|
| 2292 |
{ INDEX_op_brcond_i32, { "rI", "rI" } },
|
| 2293 |
{ INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
|
| 2294 |
{ INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } },
|
| 2295 |
|
| 2296 |
{ INDEX_op_mov_i64, { "r", "r" } },
|
| 2297 |
{ INDEX_op_movi_i64, { "r" } },
|
| 2298 |
|
| 2299 |
{ INDEX_op_ld8u_i64, { "r", "r" } },
|
| 2300 |
{ INDEX_op_ld8s_i64, { "r", "r" } },
|
| 2301 |
{ INDEX_op_ld16u_i64, { "r", "r" } },
|
| 2302 |
{ INDEX_op_ld16s_i64, { "r", "r" } },
|
| 2303 |
{ INDEX_op_ld32u_i64, { "r", "r" } },
|
| 2304 |
{ INDEX_op_ld32s_i64, { "r", "r" } },
|
| 2305 |
{ INDEX_op_ld_i64, { "r", "r" } },
|
| 2306 |
{ INDEX_op_st8_i64, { "rZ", "r" } },
|
| 2307 |
{ INDEX_op_st16_i64, { "rZ", "r" } },
|
| 2308 |
{ INDEX_op_st32_i64, { "rZ", "r" } },
|
| 2309 |
{ INDEX_op_st_i64, { "rZ", "r" } },
|
| 2310 |
|
| 2311 |
{ INDEX_op_add_i64, { "r", "rI", "rI" } },
|
| 2312 |
{ INDEX_op_sub_i64, { "r", "rI", "rI" } },
|
| 2313 |
|
| 2314 |
{ INDEX_op_and_i64, { "r", "rI", "rI" } },
|
| 2315 |
{ INDEX_op_andc_i64, { "r", "rI", "rI" } },
|
| 2316 |
{ INDEX_op_eqv_i64, { "r", "rZ", "rZ" } },
|
| 2317 |
{ INDEX_op_nand_i64, { "r", "rZ", "rZ" } },
|
| 2318 |
{ INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
|
| 2319 |
{ INDEX_op_or_i64, { "r", "rI", "rI" } },
|
| 2320 |
{ INDEX_op_orc_i64, { "r", "rZ", "rZ" } },
|
| 2321 |
{ INDEX_op_xor_i64, { "r", "rI", "rI" } },
|
| 2322 |
|
| 2323 |
{ INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
|
| 2324 |
|
| 2325 |
{ INDEX_op_sar_i64, { "r", "rZ", "ri" } },
|
| 2326 |
{ INDEX_op_shl_i64, { "r", "rZ", "ri" } },
|
| 2327 |
{ INDEX_op_shr_i64, { "r", "rZ", "ri" } },
|
| 2328 |
{ INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
|
| 2329 |
{ INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
|
| 2330 |
|
| 2331 |
{ INDEX_op_ext8s_i64, { "r", "rZ"} },
|
| 2332 |
{ INDEX_op_ext8u_i64, { "r", "rZ"} },
|
| 2333 |
{ INDEX_op_ext16s_i64, { "r", "rZ"} },
|
| 2334 |
{ INDEX_op_ext16u_i64, { "r", "rZ"} },
|
| 2335 |
{ INDEX_op_ext32s_i64, { "r", "rZ"} },
|
| 2336 |
{ INDEX_op_ext32u_i64, { "r", "rZ"} },
|
| 2337 |
|
| 2338 |
{ INDEX_op_bswap16_i64, { "r", "rZ" } },
|
| 2339 |
{ INDEX_op_bswap32_i64, { "r", "rZ" } },
|
| 2340 |
{ INDEX_op_bswap64_i64, { "r", "rZ" } },
|
| 2341 |
|
| 2342 |
{ INDEX_op_brcond_i64, { "rI", "rI" } },
|
| 2343 |
{ INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
|
| 2344 |
{ INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } },
|
| 2345 |
|
| 2346 |
{ INDEX_op_deposit_i32, { "r", "rZ", "ri" } },
|
| 2347 |
{ INDEX_op_deposit_i64, { "r", "rZ", "ri" } },
|
| 2348 |
|
| 2349 |
{ INDEX_op_qemu_ld8u, { "r", "r" } },
|
| 2350 |
{ INDEX_op_qemu_ld8s, { "r", "r" } },
|
| 2351 |
{ INDEX_op_qemu_ld16u, { "r", "r" } },
|
| 2352 |
{ INDEX_op_qemu_ld16s, { "r", "r" } },
|
| 2353 |
{ INDEX_op_qemu_ld32, { "r", "r" } },
|
| 2354 |
{ INDEX_op_qemu_ld32u, { "r", "r" } },
|
| 2355 |
{ INDEX_op_qemu_ld32s, { "r", "r" } },
|
| 2356 |
{ INDEX_op_qemu_ld64, { "r", "r" } },
|
| 2357 |
|
| 2358 |
{ INDEX_op_qemu_st8, { "SZ", "r" } },
|
| 2359 |
{ INDEX_op_qemu_st16, { "SZ", "r" } },
|
| 2360 |
{ INDEX_op_qemu_st32, { "SZ", "r" } },
|
| 2361 |
{ INDEX_op_qemu_st64, { "SZ", "r" } },
|
| 2362 |
|
| 2363 |
{ -1 },
|
| 2364 |
}; |
| 2365 |
|
| 2366 |
/* Generate global QEMU prologue and epilogue code */
|
| 2367 |
static void tcg_target_qemu_prologue(TCGContext *s) |
| 2368 |
{
|
| 2369 |
int frame_size;
|
| 2370 |
|
| 2371 |
/* reserve some stack space */
|
| 2372 |
frame_size = TCG_STATIC_CALL_ARGS_SIZE + |
| 2373 |
CPU_TEMP_BUF_NLONGS * sizeof(long); |
| 2374 |
frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
|
| 2375 |
~(TCG_TARGET_STACK_ALIGN - 1);
|
| 2376 |
tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, |
| 2377 |
CPU_TEMP_BUF_NLONGS * sizeof(long)); |
| 2378 |
|
| 2379 |
/* First emit adhoc function descriptor */
|
| 2380 |
*(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */ |
| 2381 |
s->code_ptr += 16; /* skip GP */ |
| 2382 |
|
| 2383 |
/* prologue */
|
| 2384 |
tcg_out_bundle(s, miI, |
| 2385 |
tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34, |
| 2386 |
TCG_REG_R34, 32, 24, 0), |
| 2387 |
tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, |
| 2388 |
TCG_AREG0, 0, TCG_REG_R32),
|
| 2389 |
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, |
| 2390 |
TCG_REG_B6, TCG_REG_R33, 0));
|
| 2391 |
|
| 2392 |
/* ??? If GUEST_BASE < 0x200000, we could load the register via
|
| 2393 |
an ADDL in the M slot of the next bundle. */
|
| 2394 |
if (GUEST_BASE != 0) { |
| 2395 |
tcg_out_bundle(s, mlx, |
| 2396 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 2397 |
tcg_opc_l2 (GUEST_BASE), |
| 2398 |
tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, |
| 2399 |
TCG_GUEST_BASE_REG, GUEST_BASE)); |
| 2400 |
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); |
| 2401 |
} |
| 2402 |
|
| 2403 |
tcg_out_bundle(s, miB, |
| 2404 |
tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, |
| 2405 |
TCG_REG_R12, -frame_size, TCG_REG_R12), |
| 2406 |
tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22, |
| 2407 |
TCG_REG_R32, TCG_REG_B0), |
| 2408 |
tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6)); |
| 2409 |
|
| 2410 |
/* epilogue */
|
| 2411 |
tb_ret_addr = s->code_ptr; |
| 2412 |
tcg_out_bundle(s, miI, |
| 2413 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 2414 |
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, |
| 2415 |
TCG_REG_B0, TCG_REG_R32, 0),
|
| 2416 |
tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, |
| 2417 |
TCG_REG_R12, frame_size, TCG_REG_R12)); |
| 2418 |
tcg_out_bundle(s, miB, |
| 2419 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
| 2420 |
tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26, |
| 2421 |
TCG_REG_PFS, TCG_REG_R34), |
| 2422 |
tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4, |
| 2423 |
TCG_REG_B0)); |
| 2424 |
} |
| 2425 |
|
| 2426 |
static void tcg_target_init(TCGContext *s) |
| 2427 |
{
|
| 2428 |
tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], |
| 2429 |
0xffffffffffffffffull);
|
| 2430 |
tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64], |
| 2431 |
0xffffffffffffffffull);
|
| 2432 |
|
| 2433 |
tcg_regset_clear(tcg_target_call_clobber_regs); |
| 2434 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); |
| 2435 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); |
| 2436 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); |
| 2437 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); |
| 2438 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); |
| 2439 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15); |
| 2440 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16); |
| 2441 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17); |
| 2442 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18); |
| 2443 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19); |
| 2444 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20); |
| 2445 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21); |
| 2446 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22); |
| 2447 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23); |
| 2448 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24); |
| 2449 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25); |
| 2450 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26); |
| 2451 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27); |
| 2452 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28); |
| 2453 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29); |
| 2454 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30); |
| 2455 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31); |
| 2456 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56); |
| 2457 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57); |
| 2458 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58); |
| 2459 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59); |
| 2460 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60); |
| 2461 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61); |
| 2462 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62); |
| 2463 |
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63); |
| 2464 |
|
| 2465 |
tcg_regset_clear(s->reserved_regs); |
| 2466 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */
|
| 2467 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */
|
| 2468 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */
|
| 2469 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */
|
| 2470 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */
|
| 2471 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
|
| 2472 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R32); /* return address */
|
| 2473 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R34); /* PFS */
|
| 2474 |
|
| 2475 |
/* The following 3 are not in use, are call-saved, but *not* saved
|
| 2476 |
by the prologue. Therefore we cannot use them without modifying
|
| 2477 |
the prologue. There doesn't seem to be any good reason to use
|
| 2478 |
these as opposed to the windowed registers. */
|
| 2479 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4); |
| 2480 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5); |
| 2481 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6); |
| 2482 |
|
| 2483 |
tcg_add_target_add_op_defs(ia64_op_defs); |
| 2484 |
} |