root / tcg / tci / tcg-target.c @ 3cf246f0
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2009, 2011 Stefan Weil
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "tcg-be-null.h" |
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/* TODO list:
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* - See TODO comments in code.
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*/
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|
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/* Marker for missing code. */
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#define TODO() \
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do { \
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fprintf(stderr, "TODO %s:%u: %s()\n", \
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__FILE__, __LINE__, __func__); \ |
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tcg_abort(); \ |
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} while (0) |
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/* Bitfield n...m (in 32 bit value). */
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#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) |
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/* Macros used in tcg_target_op_defs. */
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#define R "r" |
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#define RI "ri" |
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#if TCG_TARGET_REG_BITS == 32 |
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# define R64 "r", "r" |
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#else
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# define R64 "r" |
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#endif
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#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
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# define L "L", "L" |
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# define S "S", "S" |
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#else
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# define L "L" |
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# define S "S" |
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#endif
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/* TODO: documentation. */
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static const TCGTargetOpDef tcg_target_op_defs[] = { |
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{ INDEX_op_exit_tb, { NULL } },
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{ INDEX_op_goto_tb, { NULL } },
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{ INDEX_op_call, { RI } }, |
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{ INDEX_op_br, { NULL } },
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{ INDEX_op_mov_i32, { R, R } }, |
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{ INDEX_op_movi_i32, { R } }, |
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{ INDEX_op_ld8u_i32, { R, R } }, |
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{ INDEX_op_ld8s_i32, { R, R } }, |
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{ INDEX_op_ld16u_i32, { R, R } }, |
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{ INDEX_op_ld16s_i32, { R, R } }, |
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{ INDEX_op_ld_i32, { R, R } }, |
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{ INDEX_op_st8_i32, { R, R } }, |
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{ INDEX_op_st16_i32, { R, R } }, |
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{ INDEX_op_st_i32, { R, R } }, |
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{ INDEX_op_add_i32, { R, RI, RI } }, |
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{ INDEX_op_sub_i32, { R, RI, RI } }, |
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{ INDEX_op_mul_i32, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_div_i32
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{ INDEX_op_div_i32, { R, R, R } }, |
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{ INDEX_op_divu_i32, { R, R, R } }, |
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{ INDEX_op_rem_i32, { R, R, R } }, |
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{ INDEX_op_remu_i32, { R, R, R } }, |
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#elif TCG_TARGET_HAS_div2_i32
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{ INDEX_op_div2_i32, { R, R, "0", "1", R } }, |
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{ INDEX_op_divu2_i32, { R, R, "0", "1", R } }, |
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#endif
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/* TODO: Does R, RI, RI result in faster code than R, R, RI?
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If both operands are constants, we can optimize. */
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{ INDEX_op_and_i32, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_andc_i32
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{ INDEX_op_andc_i32, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_eqv_i32
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{ INDEX_op_eqv_i32, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_nand_i32
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{ INDEX_op_nand_i32, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_nor_i32
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{ INDEX_op_nor_i32, { R, RI, RI } }, |
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#endif
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{ INDEX_op_or_i32, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_orc_i32
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{ INDEX_op_orc_i32, { R, RI, RI } }, |
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#endif
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{ INDEX_op_xor_i32, { R, RI, RI } }, |
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{ INDEX_op_shl_i32, { R, RI, RI } }, |
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{ INDEX_op_shr_i32, { R, RI, RI } }, |
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{ INDEX_op_sar_i32, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_rot_i32
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{ INDEX_op_rotl_i32, { R, RI, RI } }, |
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{ INDEX_op_rotr_i32, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_deposit_i32
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{ INDEX_op_deposit_i32, { R, "0", R } },
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#endif
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{ INDEX_op_brcond_i32, { R, RI } }, |
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{ INDEX_op_setcond_i32, { R, R, RI } }, |
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#if TCG_TARGET_REG_BITS == 64 |
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{ INDEX_op_setcond_i64, { R, R, RI } }, |
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#endif /* TCG_TARGET_REG_BITS == 64 */ |
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#if TCG_TARGET_REG_BITS == 32 |
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/* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
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{ INDEX_op_add2_i32, { R, R, R, R, R, R } }, |
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{ INDEX_op_sub2_i32, { R, R, R, R, R, R } }, |
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{ INDEX_op_brcond2_i32, { R, R, RI, RI } }, |
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{ INDEX_op_mulu2_i32, { R, R, R, R } }, |
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{ INDEX_op_setcond2_i32, { R, R, R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_not_i32
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{ INDEX_op_not_i32, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_neg_i32
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{ INDEX_op_neg_i32, { R, R } }, |
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#endif
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#if TCG_TARGET_REG_BITS == 64 |
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{ INDEX_op_mov_i64, { R, R } }, |
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{ INDEX_op_movi_i64, { R } }, |
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{ INDEX_op_ld8u_i64, { R, R } }, |
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{ INDEX_op_ld8s_i64, { R, R } }, |
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{ INDEX_op_ld16u_i64, { R, R } }, |
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{ INDEX_op_ld16s_i64, { R, R } }, |
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{ INDEX_op_ld32u_i64, { R, R } }, |
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{ INDEX_op_ld32s_i64, { R, R } }, |
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{ INDEX_op_ld_i64, { R, R } }, |
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{ INDEX_op_st8_i64, { R, R } }, |
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{ INDEX_op_st16_i64, { R, R } }, |
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{ INDEX_op_st32_i64, { R, R } }, |
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{ INDEX_op_st_i64, { R, R } }, |
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{ INDEX_op_add_i64, { R, RI, RI } }, |
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{ INDEX_op_sub_i64, { R, RI, RI } }, |
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{ INDEX_op_mul_i64, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_div_i64
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{ INDEX_op_div_i64, { R, R, R } }, |
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{ INDEX_op_divu_i64, { R, R, R } }, |
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{ INDEX_op_rem_i64, { R, R, R } }, |
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{ INDEX_op_remu_i64, { R, R, R } }, |
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#elif TCG_TARGET_HAS_div2_i64
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{ INDEX_op_div2_i64, { R, R, "0", "1", R } }, |
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{ INDEX_op_divu2_i64, { R, R, "0", "1", R } }, |
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#endif
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{ INDEX_op_and_i64, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_andc_i64
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{ INDEX_op_andc_i64, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_eqv_i64
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{ INDEX_op_eqv_i64, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_nand_i64
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{ INDEX_op_nand_i64, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_nor_i64
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{ INDEX_op_nor_i64, { R, RI, RI } }, |
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#endif
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{ INDEX_op_or_i64, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_orc_i64
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{ INDEX_op_orc_i64, { R, RI, RI } }, |
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#endif
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{ INDEX_op_xor_i64, { R, RI, RI } }, |
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{ INDEX_op_shl_i64, { R, RI, RI } }, |
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{ INDEX_op_shr_i64, { R, RI, RI } }, |
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{ INDEX_op_sar_i64, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_rot_i64
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{ INDEX_op_rotl_i64, { R, RI, RI } }, |
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{ INDEX_op_rotr_i64, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_deposit_i64
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{ INDEX_op_deposit_i64, { R, "0", R } },
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#endif
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{ INDEX_op_brcond_i64, { R, RI } }, |
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#if TCG_TARGET_HAS_ext8s_i64
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{ INDEX_op_ext8s_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext16s_i64
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{ INDEX_op_ext16s_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext32s_i64
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{ INDEX_op_ext32s_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext8u_i64
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{ INDEX_op_ext8u_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext16u_i64
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{ INDEX_op_ext16u_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext32u_i64
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{ INDEX_op_ext32u_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_bswap16_i64
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{ INDEX_op_bswap16_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_bswap32_i64
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{ INDEX_op_bswap32_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_bswap64_i64
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{ INDEX_op_bswap64_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_not_i64
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{ INDEX_op_not_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_neg_i64
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{ INDEX_op_neg_i64, { R, R } }, |
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#endif
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#endif /* TCG_TARGET_REG_BITS == 64 */ |
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{ INDEX_op_qemu_ld8u, { R, L } }, |
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{ INDEX_op_qemu_ld8s, { R, L } }, |
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{ INDEX_op_qemu_ld16u, { R, L } }, |
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{ INDEX_op_qemu_ld16s, { R, L } }, |
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{ INDEX_op_qemu_ld32, { R, L } }, |
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#if TCG_TARGET_REG_BITS == 64 |
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{ INDEX_op_qemu_ld32u, { R, L } }, |
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{ INDEX_op_qemu_ld32s, { R, L } }, |
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#endif
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{ INDEX_op_qemu_ld64, { R64, L } }, |
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|
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{ INDEX_op_qemu_st8, { R, S } }, |
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{ INDEX_op_qemu_st16, { R, S } }, |
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{ INDEX_op_qemu_st32, { R, S } }, |
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{ INDEX_op_qemu_st64, { R64, S } }, |
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|
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#if TCG_TARGET_HAS_ext8s_i32
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{ INDEX_op_ext8s_i32, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext16s_i32
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{ INDEX_op_ext16s_i32, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext8u_i32
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{ INDEX_op_ext8u_i32, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext16u_i32
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{ INDEX_op_ext16u_i32, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_bswap16_i32
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{ INDEX_op_bswap16_i32, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_bswap32_i32
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{ INDEX_op_bswap32_i32, { R, R } }, |
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#endif
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{ -1 },
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}; |
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|
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static const int tcg_target_reg_alloc_order[] = { |
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TCG_REG_R0, |
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TCG_REG_R1, |
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TCG_REG_R2, |
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TCG_REG_R3, |
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#if 0 /* used for TCG_REG_CALL_STACK */
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TCG_REG_R4,
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#endif
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TCG_REG_R5, |
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TCG_REG_R6, |
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TCG_REG_R7, |
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#if TCG_TARGET_NB_REGS >= 16 |
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TCG_REG_R8, |
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TCG_REG_R9, |
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TCG_REG_R10, |
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TCG_REG_R11, |
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TCG_REG_R12, |
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TCG_REG_R13, |
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TCG_REG_R14, |
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TCG_REG_R15, |
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#endif
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}; |
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|
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#if MAX_OPC_PARAM_IARGS != 5 |
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# error Fix needed, number of supported input arguments changed!
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#endif
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|
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static const int tcg_target_call_iarg_regs[] = { |
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TCG_REG_R0, |
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TCG_REG_R1, |
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TCG_REG_R2, |
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TCG_REG_R3, |
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#if 0 /* used for TCG_REG_CALL_STACK */
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TCG_REG_R4,
|
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#endif
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TCG_REG_R5, |
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#if TCG_TARGET_REG_BITS == 32 |
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/* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
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TCG_REG_R6, |
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TCG_REG_R7, |
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#if TCG_TARGET_NB_REGS >= 16 |
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TCG_REG_R8, |
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TCG_REG_R9, |
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TCG_REG_R10, |
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#else
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# error Too few input registers available
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#endif
|
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#endif
|
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}; |
325 |
|
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static const int tcg_target_call_oarg_regs[] = { |
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TCG_REG_R0, |
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#if TCG_TARGET_REG_BITS == 32 |
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TCG_REG_R1 |
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#endif
|
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}; |
332 |
|
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#ifndef NDEBUG
|
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static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
335 |
"r00",
|
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"r01",
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"r02",
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"r03",
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"r04",
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"r05",
|
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"r06",
|
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"r07",
|
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#if TCG_TARGET_NB_REGS >= 16 |
344 |
"r08",
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"r09",
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"r10",
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"r11",
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"r12",
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"r13",
|
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"r14",
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"r15",
|
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#if TCG_TARGET_NB_REGS >= 32 |
353 |
"r16",
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"r17",
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"r18",
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"r19",
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"r20",
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"r21",
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"r22",
|
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"r23",
|
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"r24",
|
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"r25",
|
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"r26",
|
364 |
"r27",
|
365 |
"r28",
|
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"r29",
|
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"r30",
|
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"r31"
|
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#endif
|
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#endif
|
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}; |
372 |
#endif
|
373 |
|
374 |
static void patch_reloc(uint8_t *code_ptr, int type, |
375 |
intptr_t value, intptr_t addend) |
376 |
{ |
377 |
/* tcg_out_reloc always uses the same type, addend. */
|
378 |
assert(type == sizeof(tcg_target_long));
|
379 |
assert(addend == 0);
|
380 |
assert(value != 0);
|
381 |
*(tcg_target_long *)code_ptr = value; |
382 |
} |
383 |
|
384 |
/* Parse target specific constraints. */
|
385 |
static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
386 |
{ |
387 |
const char *ct_str = *pct_str; |
388 |
switch (ct_str[0]) { |
389 |
case 'r': |
390 |
case 'L': /* qemu_ld constraint */ |
391 |
case 'S': /* qemu_st constraint */ |
392 |
ct->ct |= TCG_CT_REG; |
393 |
tcg_regset_set32(ct->u.regs, 0, BIT(TCG_TARGET_NB_REGS) - 1); |
394 |
break;
|
395 |
default:
|
396 |
return -1; |
397 |
} |
398 |
ct_str++; |
399 |
*pct_str = ct_str; |
400 |
return 0; |
401 |
} |
402 |
|
403 |
#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
|
404 |
/* Show current bytecode. Used by tcg interpreter. */
|
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void tci_disas(uint8_t opc)
|
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{ |
407 |
const TCGOpDef *def = &tcg_op_defs[opc];
|
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fprintf(stderr, "TCG %s %u, %u, %u\n",
|
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def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs); |
410 |
} |
411 |
#endif
|
412 |
|
413 |
/* Write value (native size). */
|
414 |
static void tcg_out_i(TCGContext *s, tcg_target_ulong v) |
415 |
{ |
416 |
*(tcg_target_ulong *)s->code_ptr = v; |
417 |
s->code_ptr += sizeof(tcg_target_ulong);
|
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} |
419 |
|
420 |
/* Write opcode. */
|
421 |
static void tcg_out_op_t(TCGContext *s, TCGOpcode op) |
422 |
{ |
423 |
tcg_out8(s, op); |
424 |
tcg_out8(s, 0);
|
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} |
426 |
|
427 |
/* Write register. */
|
428 |
static void tcg_out_r(TCGContext *s, TCGArg t0) |
429 |
{ |
430 |
assert(t0 < TCG_TARGET_NB_REGS); |
431 |
tcg_out8(s, t0); |
432 |
} |
433 |
|
434 |
/* Write register or constant (native size). */
|
435 |
static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg) |
436 |
{ |
437 |
if (const_arg) {
|
438 |
assert(const_arg == 1);
|
439 |
tcg_out8(s, TCG_CONST); |
440 |
tcg_out_i(s, arg); |
441 |
} else {
|
442 |
tcg_out_r(s, arg); |
443 |
} |
444 |
} |
445 |
|
446 |
/* Write register or constant (32 bit). */
|
447 |
static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg) |
448 |
{ |
449 |
if (const_arg) {
|
450 |
assert(const_arg == 1);
|
451 |
tcg_out8(s, TCG_CONST); |
452 |
tcg_out32(s, arg); |
453 |
} else {
|
454 |
tcg_out_r(s, arg); |
455 |
} |
456 |
} |
457 |
|
458 |
#if TCG_TARGET_REG_BITS == 64 |
459 |
/* Write register or constant (64 bit). */
|
460 |
static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg) |
461 |
{ |
462 |
if (const_arg) {
|
463 |
assert(const_arg == 1);
|
464 |
tcg_out8(s, TCG_CONST); |
465 |
tcg_out64(s, arg); |
466 |
} else {
|
467 |
tcg_out_r(s, arg); |
468 |
} |
469 |
} |
470 |
#endif
|
471 |
|
472 |
/* Write label. */
|
473 |
static void tci_out_label(TCGContext *s, TCGArg arg) |
474 |
{ |
475 |
TCGLabel *label = &s->labels[arg]; |
476 |
if (label->has_value) {
|
477 |
tcg_out_i(s, label->u.value); |
478 |
assert(label->u.value); |
479 |
} else {
|
480 |
tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), arg, 0); |
481 |
s->code_ptr += sizeof(tcg_target_ulong);
|
482 |
} |
483 |
} |
484 |
|
485 |
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, |
486 |
intptr_t arg2) |
487 |
{ |
488 |
uint8_t *old_code_ptr = s->code_ptr; |
489 |
if (type == TCG_TYPE_I32) {
|
490 |
tcg_out_op_t(s, INDEX_op_ld_i32); |
491 |
tcg_out_r(s, ret); |
492 |
tcg_out_r(s, arg1); |
493 |
tcg_out32(s, arg2); |
494 |
} else {
|
495 |
assert(type == TCG_TYPE_I64); |
496 |
#if TCG_TARGET_REG_BITS == 64 |
497 |
tcg_out_op_t(s, INDEX_op_ld_i64); |
498 |
tcg_out_r(s, ret); |
499 |
tcg_out_r(s, arg1); |
500 |
assert(arg2 == (int32_t)arg2); |
501 |
tcg_out32(s, arg2); |
502 |
#else
|
503 |
TODO(); |
504 |
#endif
|
505 |
} |
506 |
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
507 |
} |
508 |
|
509 |
static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) |
510 |
{ |
511 |
uint8_t *old_code_ptr = s->code_ptr; |
512 |
assert(ret != arg); |
513 |
#if TCG_TARGET_REG_BITS == 32 |
514 |
tcg_out_op_t(s, INDEX_op_mov_i32); |
515 |
#else
|
516 |
tcg_out_op_t(s, INDEX_op_mov_i64); |
517 |
#endif
|
518 |
tcg_out_r(s, ret); |
519 |
tcg_out_r(s, arg); |
520 |
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
521 |
} |
522 |
|
523 |
static void tcg_out_movi(TCGContext *s, TCGType type, |
524 |
TCGReg t0, tcg_target_long arg) |
525 |
{ |
526 |
uint8_t *old_code_ptr = s->code_ptr; |
527 |
uint32_t arg32 = arg; |
528 |
if (type == TCG_TYPE_I32 || arg == arg32) {
|
529 |
tcg_out_op_t(s, INDEX_op_movi_i32); |
530 |
tcg_out_r(s, t0); |
531 |
tcg_out32(s, arg32); |
532 |
} else {
|
533 |
assert(type == TCG_TYPE_I64); |
534 |
#if TCG_TARGET_REG_BITS == 64 |
535 |
tcg_out_op_t(s, INDEX_op_movi_i64); |
536 |
tcg_out_r(s, t0); |
537 |
tcg_out64(s, arg); |
538 |
#else
|
539 |
TODO(); |
540 |
#endif
|
541 |
} |
542 |
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
543 |
} |
544 |
|
545 |
static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, |
546 |
const int *const_args) |
547 |
{ |
548 |
uint8_t *old_code_ptr = s->code_ptr; |
549 |
|
550 |
tcg_out_op_t(s, opc); |
551 |
|
552 |
switch (opc) {
|
553 |
case INDEX_op_exit_tb:
|
554 |
tcg_out64(s, args[0]);
|
555 |
break;
|
556 |
case INDEX_op_goto_tb:
|
557 |
if (s->tb_jmp_offset) {
|
558 |
/* Direct jump method. */
|
559 |
assert(args[0] < ARRAY_SIZE(s->tb_jmp_offset));
|
560 |
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
561 |
tcg_out32(s, 0);
|
562 |
} else {
|
563 |
/* Indirect jump method. */
|
564 |
TODO(); |
565 |
} |
566 |
assert(args[0] < ARRAY_SIZE(s->tb_next_offset));
|
567 |
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
568 |
break;
|
569 |
case INDEX_op_br:
|
570 |
tci_out_label(s, args[0]);
|
571 |
break;
|
572 |
case INDEX_op_call:
|
573 |
tcg_out_ri(s, const_args[0], args[0]); |
574 |
break;
|
575 |
case INDEX_op_setcond_i32:
|
576 |
tcg_out_r(s, args[0]);
|
577 |
tcg_out_r(s, args[1]);
|
578 |
tcg_out_ri32(s, const_args[2], args[2]); |
579 |
tcg_out8(s, args[3]); /* condition */ |
580 |
break;
|
581 |
#if TCG_TARGET_REG_BITS == 32 |
582 |
case INDEX_op_setcond2_i32:
|
583 |
/* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
|
584 |
tcg_out_r(s, args[0]);
|
585 |
tcg_out_r(s, args[1]);
|
586 |
tcg_out_r(s, args[2]);
|
587 |
tcg_out_ri32(s, const_args[3], args[3]); |
588 |
tcg_out_ri32(s, const_args[4], args[4]); |
589 |
tcg_out8(s, args[5]); /* condition */ |
590 |
break;
|
591 |
#elif TCG_TARGET_REG_BITS == 64 |
592 |
case INDEX_op_setcond_i64:
|
593 |
tcg_out_r(s, args[0]);
|
594 |
tcg_out_r(s, args[1]);
|
595 |
tcg_out_ri64(s, const_args[2], args[2]); |
596 |
tcg_out8(s, args[3]); /* condition */ |
597 |
break;
|
598 |
#endif
|
599 |
case INDEX_op_movi_i32:
|
600 |
TODO(); /* Handled by tcg_out_movi? */
|
601 |
break;
|
602 |
case INDEX_op_ld8u_i32:
|
603 |
case INDEX_op_ld8s_i32:
|
604 |
case INDEX_op_ld16u_i32:
|
605 |
case INDEX_op_ld16s_i32:
|
606 |
case INDEX_op_ld_i32:
|
607 |
case INDEX_op_st8_i32:
|
608 |
case INDEX_op_st16_i32:
|
609 |
case INDEX_op_st_i32:
|
610 |
case INDEX_op_ld8u_i64:
|
611 |
case INDEX_op_ld8s_i64:
|
612 |
case INDEX_op_ld16u_i64:
|
613 |
case INDEX_op_ld16s_i64:
|
614 |
case INDEX_op_ld32u_i64:
|
615 |
case INDEX_op_ld32s_i64:
|
616 |
case INDEX_op_ld_i64:
|
617 |
case INDEX_op_st8_i64:
|
618 |
case INDEX_op_st16_i64:
|
619 |
case INDEX_op_st32_i64:
|
620 |
case INDEX_op_st_i64:
|
621 |
tcg_out_r(s, args[0]);
|
622 |
tcg_out_r(s, args[1]);
|
623 |
assert(args[2] == (int32_t)args[2]); |
624 |
tcg_out32(s, args[2]);
|
625 |
break;
|
626 |
case INDEX_op_add_i32:
|
627 |
case INDEX_op_sub_i32:
|
628 |
case INDEX_op_mul_i32:
|
629 |
case INDEX_op_and_i32:
|
630 |
case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */ |
631 |
case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */ |
632 |
case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */ |
633 |
case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */ |
634 |
case INDEX_op_or_i32:
|
635 |
case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */ |
636 |
case INDEX_op_xor_i32:
|
637 |
case INDEX_op_shl_i32:
|
638 |
case INDEX_op_shr_i32:
|
639 |
case INDEX_op_sar_i32:
|
640 |
case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ |
641 |
case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ |
642 |
tcg_out_r(s, args[0]);
|
643 |
tcg_out_ri32(s, const_args[1], args[1]); |
644 |
tcg_out_ri32(s, const_args[2], args[2]); |
645 |
break;
|
646 |
case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */ |
647 |
tcg_out_r(s, args[0]);
|
648 |
tcg_out_r(s, args[1]);
|
649 |
tcg_out_r(s, args[2]);
|
650 |
assert(args[3] <= UINT8_MAX);
|
651 |
tcg_out8(s, args[3]);
|
652 |
assert(args[4] <= UINT8_MAX);
|
653 |
tcg_out8(s, args[4]);
|
654 |
break;
|
655 |
|
656 |
#if TCG_TARGET_REG_BITS == 64 |
657 |
case INDEX_op_mov_i64:
|
658 |
case INDEX_op_movi_i64:
|
659 |
TODO(); |
660 |
break;
|
661 |
case INDEX_op_add_i64:
|
662 |
case INDEX_op_sub_i64:
|
663 |
case INDEX_op_mul_i64:
|
664 |
case INDEX_op_and_i64:
|
665 |
case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */ |
666 |
case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */ |
667 |
case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */ |
668 |
case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */ |
669 |
case INDEX_op_or_i64:
|
670 |
case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */ |
671 |
case INDEX_op_xor_i64:
|
672 |
case INDEX_op_shl_i64:
|
673 |
case INDEX_op_shr_i64:
|
674 |
case INDEX_op_sar_i64:
|
675 |
case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ |
676 |
case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ |
677 |
tcg_out_r(s, args[0]);
|
678 |
tcg_out_ri64(s, const_args[1], args[1]); |
679 |
tcg_out_ri64(s, const_args[2], args[2]); |
680 |
break;
|
681 |
case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */ |
682 |
tcg_out_r(s, args[0]);
|
683 |
tcg_out_r(s, args[1]);
|
684 |
tcg_out_r(s, args[2]);
|
685 |
assert(args[3] <= UINT8_MAX);
|
686 |
tcg_out8(s, args[3]);
|
687 |
assert(args[4] <= UINT8_MAX);
|
688 |
tcg_out8(s, args[4]);
|
689 |
break;
|
690 |
case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ |
691 |
case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ |
692 |
case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ |
693 |
case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ |
694 |
TODO(); |
695 |
break;
|
696 |
case INDEX_op_div2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ |
697 |
case INDEX_op_divu2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ |
698 |
TODO(); |
699 |
break;
|
700 |
case INDEX_op_brcond_i64:
|
701 |
tcg_out_r(s, args[0]);
|
702 |
tcg_out_ri64(s, const_args[1], args[1]); |
703 |
tcg_out8(s, args[2]); /* condition */ |
704 |
tci_out_label(s, args[3]);
|
705 |
break;
|
706 |
case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). */ |
707 |
case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */ |
708 |
case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */ |
709 |
case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */ |
710 |
case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */ |
711 |
case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */ |
712 |
case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */ |
713 |
case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */ |
714 |
case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */ |
715 |
case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */ |
716 |
case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */ |
717 |
#endif /* TCG_TARGET_REG_BITS == 64 */ |
718 |
case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */ |
719 |
case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */ |
720 |
case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */ |
721 |
case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */ |
722 |
case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */ |
723 |
case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */ |
724 |
case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). */ |
725 |
case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */ |
726 |
tcg_out_r(s, args[0]);
|
727 |
tcg_out_r(s, args[1]);
|
728 |
break;
|
729 |
case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ |
730 |
case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ |
731 |
case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ |
732 |
case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ |
733 |
tcg_out_r(s, args[0]);
|
734 |
tcg_out_ri32(s, const_args[1], args[1]); |
735 |
tcg_out_ri32(s, const_args[2], args[2]); |
736 |
break;
|
737 |
case INDEX_op_div2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ |
738 |
case INDEX_op_divu2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ |
739 |
TODO(); |
740 |
break;
|
741 |
#if TCG_TARGET_REG_BITS == 32 |
742 |
case INDEX_op_add2_i32:
|
743 |
case INDEX_op_sub2_i32:
|
744 |
tcg_out_r(s, args[0]);
|
745 |
tcg_out_r(s, args[1]);
|
746 |
tcg_out_r(s, args[2]);
|
747 |
tcg_out_r(s, args[3]);
|
748 |
tcg_out_r(s, args[4]);
|
749 |
tcg_out_r(s, args[5]);
|
750 |
break;
|
751 |
case INDEX_op_brcond2_i32:
|
752 |
tcg_out_r(s, args[0]);
|
753 |
tcg_out_r(s, args[1]);
|
754 |
tcg_out_ri32(s, const_args[2], args[2]); |
755 |
tcg_out_ri32(s, const_args[3], args[3]); |
756 |
tcg_out8(s, args[4]); /* condition */ |
757 |
tci_out_label(s, args[5]);
|
758 |
break;
|
759 |
case INDEX_op_mulu2_i32:
|
760 |
tcg_out_r(s, args[0]);
|
761 |
tcg_out_r(s, args[1]);
|
762 |
tcg_out_r(s, args[2]);
|
763 |
tcg_out_r(s, args[3]);
|
764 |
break;
|
765 |
#endif
|
766 |
case INDEX_op_brcond_i32:
|
767 |
tcg_out_r(s, args[0]);
|
768 |
tcg_out_ri32(s, const_args[1], args[1]); |
769 |
tcg_out8(s, args[2]); /* condition */ |
770 |
tci_out_label(s, args[3]);
|
771 |
break;
|
772 |
case INDEX_op_qemu_ld8u:
|
773 |
case INDEX_op_qemu_ld8s:
|
774 |
case INDEX_op_qemu_ld16u:
|
775 |
case INDEX_op_qemu_ld16s:
|
776 |
case INDEX_op_qemu_ld32:
|
777 |
#if TCG_TARGET_REG_BITS == 64 |
778 |
case INDEX_op_qemu_ld32s:
|
779 |
case INDEX_op_qemu_ld32u:
|
780 |
#endif
|
781 |
tcg_out_r(s, *args++); |
782 |
tcg_out_r(s, *args++); |
783 |
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
784 |
tcg_out_r(s, *args++); |
785 |
#endif
|
786 |
#ifdef CONFIG_SOFTMMU
|
787 |
tcg_out_i(s, *args); |
788 |
#endif
|
789 |
break;
|
790 |
case INDEX_op_qemu_ld64:
|
791 |
tcg_out_r(s, *args++); |
792 |
#if TCG_TARGET_REG_BITS == 32 |
793 |
tcg_out_r(s, *args++); |
794 |
#endif
|
795 |
tcg_out_r(s, *args++); |
796 |
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
797 |
tcg_out_r(s, *args++); |
798 |
#endif
|
799 |
#ifdef CONFIG_SOFTMMU
|
800 |
tcg_out_i(s, *args); |
801 |
#endif
|
802 |
break;
|
803 |
case INDEX_op_qemu_st8:
|
804 |
case INDEX_op_qemu_st16:
|
805 |
case INDEX_op_qemu_st32:
|
806 |
tcg_out_r(s, *args++); |
807 |
tcg_out_r(s, *args++); |
808 |
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
809 |
tcg_out_r(s, *args++); |
810 |
#endif
|
811 |
#ifdef CONFIG_SOFTMMU
|
812 |
tcg_out_i(s, *args); |
813 |
#endif
|
814 |
break;
|
815 |
case INDEX_op_qemu_st64:
|
816 |
tcg_out_r(s, *args++); |
817 |
#if TCG_TARGET_REG_BITS == 32 |
818 |
tcg_out_r(s, *args++); |
819 |
#endif
|
820 |
tcg_out_r(s, *args++); |
821 |
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
822 |
tcg_out_r(s, *args++); |
823 |
#endif
|
824 |
#ifdef CONFIG_SOFTMMU
|
825 |
tcg_out_i(s, *args); |
826 |
#endif
|
827 |
break;
|
828 |
case INDEX_op_end:
|
829 |
TODO(); |
830 |
break;
|
831 |
default:
|
832 |
fprintf(stderr, "Missing: %s\n", tcg_op_defs[opc].name);
|
833 |
tcg_abort(); |
834 |
} |
835 |
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
836 |
} |
837 |
|
838 |
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, |
839 |
intptr_t arg2) |
840 |
{ |
841 |
uint8_t *old_code_ptr = s->code_ptr; |
842 |
if (type == TCG_TYPE_I32) {
|
843 |
tcg_out_op_t(s, INDEX_op_st_i32); |
844 |
tcg_out_r(s, arg); |
845 |
tcg_out_r(s, arg1); |
846 |
tcg_out32(s, arg2); |
847 |
} else {
|
848 |
assert(type == TCG_TYPE_I64); |
849 |
#if TCG_TARGET_REG_BITS == 64 |
850 |
tcg_out_op_t(s, INDEX_op_st_i64); |
851 |
tcg_out_r(s, arg); |
852 |
tcg_out_r(s, arg1); |
853 |
tcg_out32(s, arg2); |
854 |
#else
|
855 |
TODO(); |
856 |
#endif
|
857 |
} |
858 |
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
859 |
} |
860 |
|
861 |
/* Test if a constant matches the constraint. */
|
862 |
static int tcg_target_const_match(tcg_target_long val, |
863 |
const TCGArgConstraint *arg_ct)
|
864 |
{ |
865 |
/* No need to return 0 or 1, 0 or != 0 is good enough. */
|
866 |
return arg_ct->ct & TCG_CT_CONST;
|
867 |
} |
868 |
|
869 |
static void tcg_target_init(TCGContext *s) |
870 |
{ |
871 |
#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
|
872 |
const char *envval = getenv("DEBUG_TCG"); |
873 |
if (envval) {
|
874 |
qemu_set_log(strtol(envval, NULL, 0)); |
875 |
} |
876 |
#endif
|
877 |
|
878 |
/* The current code uses uint8_t for tcg operations. */
|
879 |
assert(ARRAY_SIZE(tcg_op_defs) <= UINT8_MAX); |
880 |
|
881 |
/* Registers available for 32 bit operations. */
|
882 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
|
883 |
BIT(TCG_TARGET_NB_REGS) - 1);
|
884 |
/* Registers available for 64 bit operations. */
|
885 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0,
|
886 |
BIT(TCG_TARGET_NB_REGS) - 1);
|
887 |
/* TODO: Which registers should be set here? */
|
888 |
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
889 |
BIT(TCG_TARGET_NB_REGS) - 1);
|
890 |
|
891 |
tcg_regset_clear(s->reserved_regs); |
892 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); |
893 |
tcg_add_target_add_op_defs(tcg_target_op_defs); |
894 |
|
895 |
/* We use negative offsets from "sp" so that we can distinguish
|
896 |
stores that might pretend to be call arguments. */
|
897 |
tcg_set_frame(s, TCG_REG_CALL_STACK, |
898 |
-CPU_TEMP_BUF_NLONGS * sizeof(long), |
899 |
CPU_TEMP_BUF_NLONGS * sizeof(long)); |
900 |
} |
901 |
|
902 |
/* Generate global QEMU prologue and epilogue code. */
|
903 |
static inline void tcg_target_qemu_prologue(TCGContext *s) |
904 |
{ |
905 |
} |