root / hw / cs4231.c @ 3d53f5c3
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1 | b8174937 | bellard | /*
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2 | b8174937 | bellard | * QEMU Crystal CS4231 audio chip emulation
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3 | b8174937 | bellard | *
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4 | b8174937 | bellard | * Copyright (c) 2006 Fabrice Bellard
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5 | b8174937 | bellard | *
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6 | b8174937 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | b8174937 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | b8174937 | bellard | * in the Software without restriction, including without limitation the rights
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9 | b8174937 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | b8174937 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | b8174937 | bellard | * furnished to do so, subject to the following conditions:
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12 | b8174937 | bellard | *
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13 | b8174937 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | b8174937 | bellard | * all copies or substantial portions of the Software.
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15 | b8174937 | bellard | *
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16 | b8174937 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | b8174937 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | b8174937 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | b8174937 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | b8174937 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | b8174937 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | b8174937 | bellard | * THE SOFTWARE.
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23 | b8174937 | bellard | */
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24 | fa28ec52 | Blue Swirl | |
25 | fa28ec52 | Blue Swirl | #include "sysbus.h" |
26 | b8174937 | bellard | |
27 | b8174937 | bellard | /* debug CS4231 */
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28 | b8174937 | bellard | //#define DEBUG_CS
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29 | b8174937 | bellard | |
30 | b8174937 | bellard | /*
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31 | b8174937 | bellard | * In addition to Crystal CS4231 there is a DMA controller on Sparc.
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32 | b8174937 | bellard | */
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33 | e64d7d59 | blueswir1 | #define CS_SIZE 0x40 |
34 | b8174937 | bellard | #define CS_REGS 16 |
35 | b8174937 | bellard | #define CS_DREGS 32 |
36 | b8174937 | bellard | #define CS_MAXDREG (CS_DREGS - 1) |
37 | b8174937 | bellard | |
38 | b8174937 | bellard | typedef struct CSState { |
39 | fa28ec52 | Blue Swirl | SysBusDevice busdev; |
40 | fa28ec52 | Blue Swirl | qemu_irq irq; |
41 | b8174937 | bellard | uint32_t regs[CS_REGS]; |
42 | b8174937 | bellard | uint8_t dregs[CS_DREGS]; |
43 | b8174937 | bellard | } CSState; |
44 | b8174937 | bellard | |
45 | b8174937 | bellard | #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG) |
46 | b8174937 | bellard | #define CS_VER 0xa0 |
47 | b8174937 | bellard | #define CS_CDC_VER 0x8a |
48 | b8174937 | bellard | |
49 | b8174937 | bellard | #ifdef DEBUG_CS
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50 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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51 | 001faf32 | Blue Swirl | do { printf("CS: " fmt , ## __VA_ARGS__); } while (0) |
52 | b8174937 | bellard | #else
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53 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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54 | b8174937 | bellard | #endif
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55 | b8174937 | bellard | |
56 | 82d4c6e6 | Blue Swirl | static void cs_reset(DeviceState *d) |
57 | b8174937 | bellard | { |
58 | 82d4c6e6 | Blue Swirl | CSState *s = container_of(d, CSState, busdev.qdev); |
59 | b8174937 | bellard | |
60 | b8174937 | bellard | memset(s->regs, 0, CS_REGS * 4); |
61 | b8174937 | bellard | memset(s->dregs, 0, CS_DREGS);
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62 | b8174937 | bellard | s->dregs[12] = CS_CDC_VER;
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63 | b8174937 | bellard | s->dregs[25] = CS_VER;
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64 | b8174937 | bellard | } |
65 | b8174937 | bellard | |
66 | c227f099 | Anthony Liguori | static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) |
67 | b8174937 | bellard | { |
68 | b8174937 | bellard | CSState *s = opaque; |
69 | b8174937 | bellard | uint32_t saddr, ret; |
70 | b8174937 | bellard | |
71 | e64d7d59 | blueswir1 | saddr = addr >> 2;
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72 | b8174937 | bellard | switch (saddr) {
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73 | b8174937 | bellard | case 1: |
74 | b8174937 | bellard | switch (CS_RAP(s)) {
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75 | b8174937 | bellard | case 3: // Write only |
76 | b8174937 | bellard | ret = 0;
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77 | b8174937 | bellard | break;
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78 | b8174937 | bellard | default:
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79 | b8174937 | bellard | ret = s->dregs[CS_RAP(s)]; |
80 | b8174937 | bellard | break;
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81 | b8174937 | bellard | } |
82 | b8174937 | bellard | DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
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83 | f930d07e | blueswir1 | break;
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84 | b8174937 | bellard | default:
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85 | b8174937 | bellard | ret = s->regs[saddr]; |
86 | b8174937 | bellard | DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
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87 | f930d07e | blueswir1 | break;
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88 | b8174937 | bellard | } |
89 | b8174937 | bellard | return ret;
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90 | b8174937 | bellard | } |
91 | b8174937 | bellard | |
92 | c227f099 | Anthony Liguori | static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
93 | b8174937 | bellard | { |
94 | b8174937 | bellard | CSState *s = opaque; |
95 | b8174937 | bellard | uint32_t saddr; |
96 | b8174937 | bellard | |
97 | e64d7d59 | blueswir1 | saddr = addr >> 2;
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98 | b8174937 | bellard | DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
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99 | b8174937 | bellard | switch (saddr) {
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100 | b8174937 | bellard | case 1: |
101 | 77f193da | blueswir1 | DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s),
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102 | 77f193da | blueswir1 | s->dregs[CS_RAP(s)], val); |
103 | b8174937 | bellard | switch(CS_RAP(s)) {
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104 | b8174937 | bellard | case 11: |
105 | b8174937 | bellard | case 25: // Read only |
106 | b8174937 | bellard | break;
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107 | b8174937 | bellard | case 12: |
108 | b8174937 | bellard | val &= 0x40;
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109 | b8174937 | bellard | val |= CS_CDC_VER; // Codec version
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110 | b8174937 | bellard | s->dregs[CS_RAP(s)] = val; |
111 | b8174937 | bellard | break;
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112 | b8174937 | bellard | default:
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113 | b8174937 | bellard | s->dregs[CS_RAP(s)] = val; |
114 | b8174937 | bellard | break;
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115 | b8174937 | bellard | } |
116 | b8174937 | bellard | break;
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117 | b8174937 | bellard | case 2: // Read only |
118 | b8174937 | bellard | break;
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119 | b8174937 | bellard | case 4: |
120 | 82d4c6e6 | Blue Swirl | if (val & 1) { |
121 | 82d4c6e6 | Blue Swirl | cs_reset(&s->busdev.qdev); |
122 | 82d4c6e6 | Blue Swirl | } |
123 | b8174937 | bellard | val &= 0x7f;
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124 | b8174937 | bellard | s->regs[saddr] = val; |
125 | b8174937 | bellard | break;
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126 | b8174937 | bellard | default:
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127 | b8174937 | bellard | s->regs[saddr] = val; |
128 | f930d07e | blueswir1 | break;
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129 | b8174937 | bellard | } |
130 | b8174937 | bellard | } |
131 | b8174937 | bellard | |
132 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const cs_mem_read[3] = { |
133 | b8174937 | bellard | cs_mem_readl, |
134 | b8174937 | bellard | cs_mem_readl, |
135 | b8174937 | bellard | cs_mem_readl, |
136 | b8174937 | bellard | }; |
137 | b8174937 | bellard | |
138 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const cs_mem_write[3] = { |
139 | b8174937 | bellard | cs_mem_writel, |
140 | b8174937 | bellard | cs_mem_writel, |
141 | b8174937 | bellard | cs_mem_writel, |
142 | b8174937 | bellard | }; |
143 | b8174937 | bellard | |
144 | 82d4c6e6 | Blue Swirl | static const VMStateDescription vmstate_cs4231 = { |
145 | 82d4c6e6 | Blue Swirl | .name ="cs4231",
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146 | 82d4c6e6 | Blue Swirl | .version_id = 1,
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147 | 82d4c6e6 | Blue Swirl | .minimum_version_id = 1,
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148 | 82d4c6e6 | Blue Swirl | .minimum_version_id_old = 1,
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149 | 82d4c6e6 | Blue Swirl | .fields = (VMStateField []) { |
150 | 82d4c6e6 | Blue Swirl | VMSTATE_UINT32_ARRAY(regs, CSState, CS_REGS), |
151 | 82d4c6e6 | Blue Swirl | VMSTATE_UINT8_ARRAY(dregs, CSState, CS_DREGS), |
152 | 82d4c6e6 | Blue Swirl | VMSTATE_END_OF_LIST() |
153 | 82d4c6e6 | Blue Swirl | } |
154 | 82d4c6e6 | Blue Swirl | }; |
155 | b8174937 | bellard | |
156 | 81a322d4 | Gerd Hoffmann | static int cs4231_init1(SysBusDevice *dev) |
157 | b8174937 | bellard | { |
158 | fa28ec52 | Blue Swirl | int io;
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159 | fa28ec52 | Blue Swirl | CSState *s = FROM_SYSBUS(CSState, dev); |
160 | b8174937 | bellard | |
161 | fa28ec52 | Blue Swirl | io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s); |
162 | fa28ec52 | Blue Swirl | sysbus_init_mmio(dev, CS_SIZE, io); |
163 | fa28ec52 | Blue Swirl | sysbus_init_irq(dev, &s->irq); |
164 | b8174937 | bellard | |
165 | 81a322d4 | Gerd Hoffmann | return 0; |
166 | b8174937 | bellard | } |
167 | fa28ec52 | Blue Swirl | |
168 | fa28ec52 | Blue Swirl | static SysBusDeviceInfo cs4231_info = {
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169 | fa28ec52 | Blue Swirl | .init = cs4231_init1, |
170 | fa28ec52 | Blue Swirl | .qdev.name = "SUNW,CS4231",
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171 | fa28ec52 | Blue Swirl | .qdev.size = sizeof(CSState),
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172 | 82d4c6e6 | Blue Swirl | .qdev.vmsd = &vmstate_cs4231, |
173 | 82d4c6e6 | Blue Swirl | .qdev.reset = cs_reset, |
174 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
175 | fa28ec52 | Blue Swirl | {.name = NULL}
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176 | fa28ec52 | Blue Swirl | } |
177 | fa28ec52 | Blue Swirl | }; |
178 | fa28ec52 | Blue Swirl | |
179 | fa28ec52 | Blue Swirl | static void cs4231_register_devices(void) |
180 | fa28ec52 | Blue Swirl | { |
181 | fa28ec52 | Blue Swirl | sysbus_register_withprop(&cs4231_info); |
182 | fa28ec52 | Blue Swirl | } |
183 | fa28ec52 | Blue Swirl | |
184 | fa28ec52 | Blue Swirl | device_init(cs4231_register_devices) |