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/*
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* QEMU PC System Emulator
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "apic.h" |
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#include "fdc.h" |
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#include "pci.h" |
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#include "vmware_vga.h" |
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#include "usb-uhci.h" |
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#include "usb-ohci.h" |
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#include "prep_pci.h" |
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#include "apb_pci.h" |
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#include "block.h" |
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#include "sysemu.h" |
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#include "audio/audio.h" |
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#include "net.h" |
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#include "smbus.h" |
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#include "boards.h" |
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#include "monitor.h" |
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#include "fw_cfg.h" |
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#include "hpet_emul.h" |
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#include "watchdog.h" |
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#include "smbios.h" |
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#include "ide.h" |
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#include "loader.h" |
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#include "elf.h" |
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#include "multiboot.h" |
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#include "kvm.h" |
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|
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/* output Bochs bios info messages */
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//#define DEBUG_BIOS
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|
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#define BIOS_FILENAME "bios.bin" |
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#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
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/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
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#define ACPI_DATA_SIZE 0x10000 |
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#define BIOS_CFG_IOPORT 0x510 |
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#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
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#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
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#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
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#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
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|
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#define MAX_IDE_BUS 2 |
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|
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#define E820_NR_ENTRIES 16 |
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|
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struct e820_entry {
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uint64_t address; |
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uint64_t length; |
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uint32_t type; |
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}; |
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|
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struct e820_table {
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uint32_t count; |
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struct e820_entry entry[E820_NR_ENTRIES];
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}; |
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static struct e820_table e820_table; |
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|
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typedef struct isa_irq_state { |
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qemu_irq *i8259; |
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qemu_irq *ioapic; |
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} IsaIrqState; |
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static void isa_irq_handler(void *opaque, int n, int level) |
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{ |
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IsaIrqState *isa = (IsaIrqState *)opaque; |
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if (n < 16) { |
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qemu_set_irq(isa->i8259[n], level); |
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} |
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if (isa->ioapic)
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qemu_set_irq(isa->ioapic[n], level); |
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}; |
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|
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static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
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{ |
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} |
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|
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/* MSDOS compatibility mode FPU exception support */
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static qemu_irq ferr_irq;
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|
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void pc_register_ferr_irq(qemu_irq irq)
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{ |
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ferr_irq = irq; |
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} |
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|
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/* XXX: add IGNNE support */
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void cpu_set_ferr(CPUX86State *s)
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{ |
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qemu_irq_raise(ferr_irq); |
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} |
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static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) |
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{ |
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qemu_irq_lower(ferr_irq); |
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} |
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|
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/* TSC handling */
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uint64_t cpu_get_tsc(CPUX86State *env) |
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{ |
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return cpu_get_ticks();
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} |
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|
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/* SMM support */
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|
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static cpu_set_smm_t smm_set;
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static void *smm_arg; |
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|
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void cpu_smm_register(cpu_set_smm_t callback, void *arg) |
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{ |
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assert(smm_set == NULL);
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assert(smm_arg == NULL);
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smm_set = callback; |
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smm_arg = arg; |
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} |
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void cpu_smm_update(CPUState *env)
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{ |
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if (smm_set && smm_arg && env == first_cpu)
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smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); |
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} |
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/* IRQ handling */
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int cpu_get_pic_interrupt(CPUState *env)
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{ |
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int intno;
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intno = apic_get_interrupt(env); |
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if (intno >= 0) { |
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/* set irq request if a PIC irq is still pending */
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/* XXX: improve that */
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pic_update_irq(isa_pic); |
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return intno;
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} |
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/* read the irq from the PIC */
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if (!apic_accept_pic_intr(env))
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return -1; |
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intno = pic_read_irq(isa_pic); |
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return intno;
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} |
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static void pic_irq_request(void *opaque, int irq, int level) |
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{ |
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CPUState *env = first_cpu; |
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if (env->apic_state) {
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while (env) {
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if (apic_accept_pic_intr(env))
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apic_deliver_pic_intr(env, level); |
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env = env->next_cpu; |
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} |
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} else {
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if (level)
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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else
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} |
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/* PC cmos mappings */
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#define REG_EQUIPMENT_BYTE 0x14 |
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static int cmos_get_fd_drive_type(int fd0) |
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{ |
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int val;
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switch (fd0) {
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case 0: |
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/* 1.44 Mb 3"5 drive */
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val = 4;
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break;
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case 1: |
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/* 2.88 Mb 3"5 drive */
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val = 5;
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break;
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case 2: |
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/* 1.2 Mb 5"5 drive */
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val = 2;
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break;
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default:
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val = 0;
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break;
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} |
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return val;
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} |
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static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd, |
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RTCState *s) |
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{ |
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int cylinders, heads, sectors;
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bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); |
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rtc_set_memory(s, type_ofs, 47);
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rtc_set_memory(s, info_ofs, cylinders); |
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rtc_set_memory(s, info_ofs + 1, cylinders >> 8); |
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rtc_set_memory(s, info_ofs + 2, heads);
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rtc_set_memory(s, info_ofs + 3, 0xff); |
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rtc_set_memory(s, info_ofs + 4, 0xff); |
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rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); |
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rtc_set_memory(s, info_ofs + 6, cylinders);
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rtc_set_memory(s, info_ofs + 7, cylinders >> 8); |
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rtc_set_memory(s, info_ofs + 8, sectors);
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} |
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/* convert boot_device letter to something recognizable by the bios */
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static int boot_device2nibble(char boot_device) |
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{ |
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switch(boot_device) {
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case 'a': |
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case 'b': |
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return 0x01; /* floppy boot */ |
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case 'c': |
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return 0x02; /* hard drive boot */ |
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case 'd': |
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return 0x03; /* CD-ROM boot */ |
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case 'n': |
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return 0x04; /* Network boot */ |
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} |
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return 0; |
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} |
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static int set_boot_dev(RTCState *s, const char *boot_device, int fd_bootchk) |
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{ |
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#define PC_MAX_BOOT_DEVICES 3 |
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int nbds, bds[3] = { 0, }; |
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int i;
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nbds = strlen(boot_device); |
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if (nbds > PC_MAX_BOOT_DEVICES) {
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error_report("Too many boot devices for PC");
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return(1); |
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} |
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for (i = 0; i < nbds; i++) { |
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bds[i] = boot_device2nibble(boot_device[i]); |
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if (bds[i] == 0) { |
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error_report("Invalid boot device for PC: '%c'",
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boot_device[i]); |
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return(1); |
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} |
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} |
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rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
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rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
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return(0); |
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} |
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static int pc_boot_set(void *opaque, const char *boot_device) |
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{ |
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return set_boot_dev(opaque, boot_device, 0); |
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} |
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|
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/* hd_table must contain 4 block drivers */
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static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
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const char *boot_device, DriveInfo **hd_table, |
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FDCtrl *floppy_controller, RTCState *s) |
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{ |
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int val;
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int fd0, fd1, nb;
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int i;
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/* various important CMOS locations needed by PC/Bochs bios */
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/* memory size */
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val = 640; /* base memory in K */ |
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rtc_set_memory(s, 0x15, val);
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rtc_set_memory(s, 0x16, val >> 8); |
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val = (ram_size / 1024) - 1024; |
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if (val > 65535) |
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val = 65535;
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rtc_set_memory(s, 0x17, val);
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rtc_set_memory(s, 0x18, val >> 8); |
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rtc_set_memory(s, 0x30, val);
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rtc_set_memory(s, 0x31, val >> 8); |
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if (above_4g_mem_size) {
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rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); |
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rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); |
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rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); |
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} |
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|
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if (ram_size > (16 * 1024 * 1024)) |
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val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); |
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else
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val = 0;
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if (val > 65535) |
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val = 65535;
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rtc_set_memory(s, 0x34, val);
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rtc_set_memory(s, 0x35, val >> 8); |
315 |
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/* set the number of CPU */
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rtc_set_memory(s, 0x5f, smp_cpus - 1); |
318 |
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/* set boot devices, and disable floppy signature check if requested */
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if (set_boot_dev(s, boot_device, fd_bootchk)) {
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exit(1);
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} |
323 |
|
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/* floppy type */
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fd0 = fdctrl_get_drive_type(floppy_controller, 0);
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fd1 = fdctrl_get_drive_type(floppy_controller, 1);
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val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
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rtc_set_memory(s, 0x10, val);
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val = 0;
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nb = 0;
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if (fd0 < 3) |
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nb++; |
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if (fd1 < 3) |
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nb++; |
338 |
switch (nb) {
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case 0: |
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break;
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case 1: |
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val |= 0x01; /* 1 drive, ready for boot */ |
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break;
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case 2: |
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val |= 0x41; /* 2 drives, ready for boot */ |
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break;
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} |
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val |= 0x02; /* FPU is there */ |
349 |
val |= 0x04; /* PS/2 mouse installed */ |
350 |
rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); |
351 |
|
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/* hard drives */
|
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|
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rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); |
355 |
if (hd_table[0]) |
356 |
cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv, s); |
357 |
if (hd_table[1]) |
358 |
cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv, s); |
359 |
|
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val = 0;
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for (i = 0; i < 4; i++) { |
362 |
if (hd_table[i]) {
|
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int cylinders, heads, sectors, translation;
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/* NOTE: bdrv_get_geometry_hint() returns the physical
|
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geometry. It is always such that: 1 <= sects <= 63, 1
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<= heads <= 16, 1 <= cylinders <= 16383. The BIOS
|
367 |
geometry can be different if a translation is done. */
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translation = bdrv_get_translation_hint(hd_table[i]->bdrv); |
369 |
if (translation == BIOS_ATA_TRANSLATION_AUTO) {
|
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bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, §ors); |
371 |
if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { |
372 |
/* No translation. */
|
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translation = 0;
|
374 |
} else {
|
375 |
/* LBA translation. */
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376 |
translation = 1;
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377 |
} |
378 |
} else {
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379 |
translation--; |
380 |
} |
381 |
val |= translation << (i * 2);
|
382 |
} |
383 |
} |
384 |
rtc_set_memory(s, 0x39, val);
|
385 |
} |
386 |
|
387 |
void ioport_set_a20(int enable) |
388 |
{ |
389 |
/* XXX: send to all CPUs ? */
|
390 |
cpu_x86_set_a20(first_cpu, enable); |
391 |
} |
392 |
|
393 |
int ioport_get_a20(void) |
394 |
{ |
395 |
return ((first_cpu->a20_mask >> 20) & 1); |
396 |
} |
397 |
|
398 |
static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) |
399 |
{ |
400 |
ioport_set_a20((val >> 1) & 1); |
401 |
/* XXX: bit 0 is fast reset */
|
402 |
} |
403 |
|
404 |
static uint32_t ioport92_read(void *opaque, uint32_t addr) |
405 |
{ |
406 |
return ioport_get_a20() << 1; |
407 |
} |
408 |
|
409 |
/***********************************************************/
|
410 |
/* Bochs BIOS debug ports */
|
411 |
|
412 |
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
413 |
{ |
414 |
static const char shutdown_str[8] = "Shutdown"; |
415 |
static int shutdown_index = 0; |
416 |
|
417 |
switch(addr) {
|
418 |
/* Bochs BIOS messages */
|
419 |
case 0x400: |
420 |
case 0x401: |
421 |
fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
|
422 |
exit(1);
|
423 |
case 0x402: |
424 |
case 0x403: |
425 |
#ifdef DEBUG_BIOS
|
426 |
fprintf(stderr, "%c", val);
|
427 |
#endif
|
428 |
break;
|
429 |
case 0x8900: |
430 |
/* same as Bochs power off */
|
431 |
if (val == shutdown_str[shutdown_index]) {
|
432 |
shutdown_index++; |
433 |
if (shutdown_index == 8) { |
434 |
shutdown_index = 0;
|
435 |
qemu_system_shutdown_request(); |
436 |
} |
437 |
} else {
|
438 |
shutdown_index = 0;
|
439 |
} |
440 |
break;
|
441 |
|
442 |
/* LGPL'ed VGA BIOS messages */
|
443 |
case 0x501: |
444 |
case 0x502: |
445 |
fprintf(stderr, "VGA BIOS panic, line %d\n", val);
|
446 |
exit(1);
|
447 |
case 0x500: |
448 |
case 0x503: |
449 |
#ifdef DEBUG_BIOS
|
450 |
fprintf(stderr, "%c", val);
|
451 |
#endif
|
452 |
break;
|
453 |
} |
454 |
} |
455 |
|
456 |
int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
|
457 |
{ |
458 |
int index = e820_table.count;
|
459 |
struct e820_entry *entry;
|
460 |
|
461 |
if (index >= E820_NR_ENTRIES)
|
462 |
return -EBUSY;
|
463 |
entry = &e820_table.entry[index]; |
464 |
|
465 |
entry->address = address; |
466 |
entry->length = length; |
467 |
entry->type = type; |
468 |
|
469 |
e820_table.count++; |
470 |
return e820_table.count;
|
471 |
} |
472 |
|
473 |
static void *bochs_bios_init(void) |
474 |
{ |
475 |
void *fw_cfg;
|
476 |
uint8_t *smbios_table; |
477 |
size_t smbios_len; |
478 |
uint64_t *numa_fw_cfg; |
479 |
int i, j;
|
480 |
|
481 |
register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
482 |
register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); |
483 |
register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); |
484 |
register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); |
485 |
register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
486 |
|
487 |
register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
488 |
register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); |
489 |
register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); |
490 |
register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); |
491 |
|
492 |
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
493 |
|
494 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
495 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
496 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
497 |
acpi_tables_len); |
498 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
|
499 |
|
500 |
smbios_table = smbios_get_table(&smbios_len); |
501 |
if (smbios_table)
|
502 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
503 |
smbios_table, smbios_len); |
504 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table, |
505 |
sizeof(struct e820_table)); |
506 |
|
507 |
/* allocate memory for the NUMA channel: one (64bit) word for the number
|
508 |
* of nodes, one word for each VCPU->node and one word for each node to
|
509 |
* hold the amount of memory.
|
510 |
*/
|
511 |
numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); |
512 |
numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
|
513 |
for (i = 0; i < smp_cpus; i++) { |
514 |
for (j = 0; j < nb_numa_nodes; j++) { |
515 |
if (node_cpumask[j] & (1 << i)) { |
516 |
numa_fw_cfg[i + 1] = cpu_to_le64(j);
|
517 |
break;
|
518 |
} |
519 |
} |
520 |
} |
521 |
for (i = 0; i < nb_numa_nodes; i++) { |
522 |
numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
|
523 |
} |
524 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, |
525 |
(1 + smp_cpus + nb_numa_nodes) * 8); |
526 |
|
527 |
return fw_cfg;
|
528 |
} |
529 |
|
530 |
static long get_file_size(FILE *f) |
531 |
{ |
532 |
long where, size;
|
533 |
|
534 |
/* XXX: on Unix systems, using fstat() probably makes more sense */
|
535 |
|
536 |
where = ftell(f); |
537 |
fseek(f, 0, SEEK_END);
|
538 |
size = ftell(f); |
539 |
fseek(f, where, SEEK_SET); |
540 |
|
541 |
return size;
|
542 |
} |
543 |
|
544 |
static void load_linux(void *fw_cfg, |
545 |
const char *kernel_filename, |
546 |
const char *initrd_filename, |
547 |
const char *kernel_cmdline, |
548 |
target_phys_addr_t max_ram_size) |
549 |
{ |
550 |
uint16_t protocol; |
551 |
int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
552 |
uint32_t initrd_max; |
553 |
uint8_t header[8192], *setup, *kernel, *initrd_data;
|
554 |
target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
|
555 |
FILE *f; |
556 |
char *vmode;
|
557 |
|
558 |
/* Align to 16 bytes as a paranoia measure */
|
559 |
cmdline_size = (strlen(kernel_cmdline)+16) & ~15; |
560 |
|
561 |
/* load the kernel header */
|
562 |
f = fopen(kernel_filename, "rb");
|
563 |
if (!f || !(kernel_size = get_file_size(f)) ||
|
564 |
fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
|
565 |
MIN(ARRAY_SIZE(header), kernel_size)) { |
566 |
fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
|
567 |
kernel_filename, strerror(errno)); |
568 |
exit(1);
|
569 |
} |
570 |
|
571 |
/* kernel protocol version */
|
572 |
#if 0
|
573 |
fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
|
574 |
#endif
|
575 |
if (ldl_p(header+0x202) == 0x53726448) |
576 |
protocol = lduw_p(header+0x206);
|
577 |
else {
|
578 |
/* This looks like a multiboot kernel. If it is, let's stop
|
579 |
treating it like a Linux kernel. */
|
580 |
if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
|
581 |
kernel_cmdline, kernel_size, header)) |
582 |
return;
|
583 |
protocol = 0;
|
584 |
} |
585 |
|
586 |
if (protocol < 0x200 || !(header[0x211] & 0x01)) { |
587 |
/* Low kernel */
|
588 |
real_addr = 0x90000;
|
589 |
cmdline_addr = 0x9a000 - cmdline_size;
|
590 |
prot_addr = 0x10000;
|
591 |
} else if (protocol < 0x202) { |
592 |
/* High but ancient kernel */
|
593 |
real_addr = 0x90000;
|
594 |
cmdline_addr = 0x9a000 - cmdline_size;
|
595 |
prot_addr = 0x100000;
|
596 |
} else {
|
597 |
/* High and recent kernel */
|
598 |
real_addr = 0x10000;
|
599 |
cmdline_addr = 0x20000;
|
600 |
prot_addr = 0x100000;
|
601 |
} |
602 |
|
603 |
#if 0
|
604 |
fprintf(stderr,
|
605 |
"qemu: real_addr = 0x" TARGET_FMT_plx "\n"
|
606 |
"qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
|
607 |
"qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
|
608 |
real_addr,
|
609 |
cmdline_addr,
|
610 |
prot_addr);
|
611 |
#endif
|
612 |
|
613 |
/* highest address for loading the initrd */
|
614 |
if (protocol >= 0x203) |
615 |
initrd_max = ldl_p(header+0x22c);
|
616 |
else
|
617 |
initrd_max = 0x37ffffff;
|
618 |
|
619 |
if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
|
620 |
initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
|
621 |
|
622 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
623 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
|
624 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
625 |
(uint8_t*)strdup(kernel_cmdline), |
626 |
strlen(kernel_cmdline)+1);
|
627 |
|
628 |
if (protocol >= 0x202) { |
629 |
stl_p(header+0x228, cmdline_addr);
|
630 |
} else {
|
631 |
stw_p(header+0x20, 0xA33F); |
632 |
stw_p(header+0x22, cmdline_addr-real_addr);
|
633 |
} |
634 |
|
635 |
/* handle vga= parameter */
|
636 |
vmode = strstr(kernel_cmdline, "vga=");
|
637 |
if (vmode) {
|
638 |
unsigned int video_mode; |
639 |
/* skip "vga=" */
|
640 |
vmode += 4;
|
641 |
if (!strncmp(vmode, "normal", 6)) { |
642 |
video_mode = 0xffff;
|
643 |
} else if (!strncmp(vmode, "ext", 3)) { |
644 |
video_mode = 0xfffe;
|
645 |
} else if (!strncmp(vmode, "ask", 3)) { |
646 |
video_mode = 0xfffd;
|
647 |
} else {
|
648 |
video_mode = strtol(vmode, NULL, 0); |
649 |
} |
650 |
stw_p(header+0x1fa, video_mode);
|
651 |
} |
652 |
|
653 |
/* loader type */
|
654 |
/* High nybble = B reserved for Qemu; low nybble is revision number.
|
655 |
If this code is substantially changed, you may want to consider
|
656 |
incrementing the revision. */
|
657 |
if (protocol >= 0x200) |
658 |
header[0x210] = 0xB0; |
659 |
|
660 |
/* heap */
|
661 |
if (protocol >= 0x201) { |
662 |
header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
663 |
stw_p(header+0x224, cmdline_addr-real_addr-0x200); |
664 |
} |
665 |
|
666 |
/* load initrd */
|
667 |
if (initrd_filename) {
|
668 |
if (protocol < 0x200) { |
669 |
fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
|
670 |
exit(1);
|
671 |
} |
672 |
|
673 |
initrd_size = get_image_size(initrd_filename); |
674 |
if (initrd_size < 0) { |
675 |
fprintf(stderr, "qemu: error reading initrd %s\n",
|
676 |
initrd_filename); |
677 |
exit(1);
|
678 |
} |
679 |
|
680 |
initrd_addr = (initrd_max-initrd_size) & ~4095;
|
681 |
|
682 |
initrd_data = qemu_malloc(initrd_size); |
683 |
load_image(initrd_filename, initrd_data); |
684 |
|
685 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
686 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
687 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); |
688 |
|
689 |
stl_p(header+0x218, initrd_addr);
|
690 |
stl_p(header+0x21c, initrd_size);
|
691 |
} |
692 |
|
693 |
/* load kernel and setup */
|
694 |
setup_size = header[0x1f1];
|
695 |
if (setup_size == 0) |
696 |
setup_size = 4;
|
697 |
setup_size = (setup_size+1)*512; |
698 |
kernel_size -= setup_size; |
699 |
|
700 |
setup = qemu_malloc(setup_size); |
701 |
kernel = qemu_malloc(kernel_size); |
702 |
fseek(f, 0, SEEK_SET);
|
703 |
if (fread(setup, 1, setup_size, f) != setup_size) { |
704 |
fprintf(stderr, "fread() failed\n");
|
705 |
exit(1);
|
706 |
} |
707 |
if (fread(kernel, 1, kernel_size, f) != kernel_size) { |
708 |
fprintf(stderr, "fread() failed\n");
|
709 |
exit(1);
|
710 |
} |
711 |
fclose(f); |
712 |
memcpy(setup, header, MIN(sizeof(header), setup_size));
|
713 |
|
714 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); |
715 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
716 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); |
717 |
|
718 |
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); |
719 |
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); |
720 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); |
721 |
|
722 |
option_rom[nb_option_roms] = "linuxboot.bin";
|
723 |
nb_option_roms++; |
724 |
} |
725 |
|
726 |
static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
727 |
static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
728 |
static const int ide_irq[2] = { 14, 15 }; |
729 |
|
730 |
#define NE2000_NB_MAX 6 |
731 |
|
732 |
static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
733 |
0x280, 0x380 }; |
734 |
static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
735 |
|
736 |
static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
737 |
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
738 |
|
739 |
#ifdef HAS_AUDIO
|
740 |
static void audio_init (PCIBus *pci_bus, qemu_irq *pic) |
741 |
{ |
742 |
struct soundhw *c;
|
743 |
|
744 |
for (c = soundhw; c->name; ++c) {
|
745 |
if (c->enabled) {
|
746 |
if (c->isa) {
|
747 |
c->init.init_isa(pic); |
748 |
} else {
|
749 |
if (pci_bus) {
|
750 |
c->init.init_pci(pci_bus); |
751 |
} |
752 |
} |
753 |
} |
754 |
} |
755 |
} |
756 |
#endif
|
757 |
|
758 |
static void pc_init_ne2k_isa(NICInfo *nd) |
759 |
{ |
760 |
static int nb_ne2k = 0; |
761 |
|
762 |
if (nb_ne2k == NE2000_NB_MAX)
|
763 |
return;
|
764 |
isa_ne2000_init(ne2000_io[nb_ne2k], |
765 |
ne2000_irq[nb_ne2k], nd); |
766 |
nb_ne2k++; |
767 |
} |
768 |
|
769 |
int cpu_is_bsp(CPUState *env)
|
770 |
{ |
771 |
/* We hard-wire the BSP to the first CPU. */
|
772 |
return env->cpu_index == 0; |
773 |
} |
774 |
|
775 |
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
|
776 |
BIOS will read it and start S3 resume at POST Entry */
|
777 |
static void cmos_set_s3_resume(void *opaque, int irq, int level) |
778 |
{ |
779 |
RTCState *s = opaque; |
780 |
|
781 |
if (level) {
|
782 |
rtc_set_memory(s, 0xF, 0xFE); |
783 |
} |
784 |
} |
785 |
|
786 |
static void acpi_smi_interrupt(void *opaque, int irq, int level) |
787 |
{ |
788 |
CPUState *s = opaque; |
789 |
|
790 |
if (level) {
|
791 |
cpu_interrupt(s, CPU_INTERRUPT_SMI); |
792 |
} |
793 |
} |
794 |
|
795 |
static CPUState *pc_new_cpu(const char *cpu_model) |
796 |
{ |
797 |
CPUState *env; |
798 |
|
799 |
env = cpu_init(cpu_model); |
800 |
if (!env) {
|
801 |
fprintf(stderr, "Unable to find x86 CPU definition\n");
|
802 |
exit(1);
|
803 |
} |
804 |
if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { |
805 |
env->cpuid_apic_id = env->cpu_index; |
806 |
/* APIC reset callback resets cpu */
|
807 |
apic_init(env); |
808 |
} else {
|
809 |
qemu_register_reset((QEMUResetHandler*)cpu_reset, env); |
810 |
} |
811 |
return env;
|
812 |
} |
813 |
|
814 |
static void pc_cpus_init(const char *cpu_model) |
815 |
{ |
816 |
int i;
|
817 |
|
818 |
/* init CPUs */
|
819 |
if (cpu_model == NULL) { |
820 |
#ifdef TARGET_X86_64
|
821 |
cpu_model = "qemu64";
|
822 |
#else
|
823 |
cpu_model = "qemu32";
|
824 |
#endif
|
825 |
} |
826 |
|
827 |
for(i = 0; i < smp_cpus; i++) { |
828 |
pc_new_cpu(cpu_model); |
829 |
} |
830 |
} |
831 |
|
832 |
static qemu_irq *pc_allocate_cpu_irq(void) |
833 |
{ |
834 |
return qemu_allocate_irqs(pic_irq_request, NULL, 1); |
835 |
} |
836 |
|
837 |
static void pc_memory_init(ram_addr_t ram_size, |
838 |
const char *kernel_filename, |
839 |
const char *kernel_cmdline, |
840 |
const char *initrd_filename, |
841 |
ram_addr_t *below_4g_mem_size_p, |
842 |
ram_addr_t *above_4g_mem_size_p) |
843 |
{ |
844 |
char *filename;
|
845 |
int ret, linux_boot, i;
|
846 |
ram_addr_t ram_addr, bios_offset, option_rom_offset; |
847 |
ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
|
848 |
int bios_size, isa_bios_size;
|
849 |
void **fw_cfg;
|
850 |
|
851 |
if (ram_size >= 0xe0000000 ) { |
852 |
above_4g_mem_size = ram_size - 0xe0000000;
|
853 |
below_4g_mem_size = 0xe0000000;
|
854 |
} else {
|
855 |
below_4g_mem_size = ram_size; |
856 |
} |
857 |
*above_4g_mem_size_p = above_4g_mem_size; |
858 |
*below_4g_mem_size_p = below_4g_mem_size; |
859 |
|
860 |
linux_boot = (kernel_filename != NULL);
|
861 |
|
862 |
/* allocate RAM */
|
863 |
ram_addr = qemu_ram_alloc(below_4g_mem_size); |
864 |
cpu_register_physical_memory(0, 0xa0000, ram_addr); |
865 |
cpu_register_physical_memory(0x100000,
|
866 |
below_4g_mem_size - 0x100000,
|
867 |
ram_addr + 0x100000);
|
868 |
|
869 |
/* above 4giga memory allocation */
|
870 |
if (above_4g_mem_size > 0) { |
871 |
#if TARGET_PHYS_ADDR_BITS == 32 |
872 |
hw_error("To much RAM for 32-bit physical address");
|
873 |
#else
|
874 |
ram_addr = qemu_ram_alloc(above_4g_mem_size); |
875 |
cpu_register_physical_memory(0x100000000ULL,
|
876 |
above_4g_mem_size, |
877 |
ram_addr); |
878 |
#endif
|
879 |
} |
880 |
|
881 |
|
882 |
/* BIOS load */
|
883 |
if (bios_name == NULL) |
884 |
bios_name = BIOS_FILENAME; |
885 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
886 |
if (filename) {
|
887 |
bios_size = get_image_size(filename); |
888 |
} else {
|
889 |
bios_size = -1;
|
890 |
} |
891 |
if (bios_size <= 0 || |
892 |
(bios_size % 65536) != 0) { |
893 |
goto bios_error;
|
894 |
} |
895 |
bios_offset = qemu_ram_alloc(bios_size); |
896 |
ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size)); |
897 |
if (ret != 0) { |
898 |
bios_error:
|
899 |
fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
|
900 |
exit(1);
|
901 |
} |
902 |
if (filename) {
|
903 |
qemu_free(filename); |
904 |
} |
905 |
/* map the last 128KB of the BIOS in ISA space */
|
906 |
isa_bios_size = bios_size; |
907 |
if (isa_bios_size > (128 * 1024)) |
908 |
isa_bios_size = 128 * 1024; |
909 |
cpu_register_physical_memory(0x100000 - isa_bios_size,
|
910 |
isa_bios_size, |
911 |
(bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
912 |
|
913 |
option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE); |
914 |
cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset); |
915 |
|
916 |
/* map all the bios at the top of memory */
|
917 |
cpu_register_physical_memory((uint32_t)(-bios_size), |
918 |
bios_size, bios_offset | IO_MEM_ROM); |
919 |
|
920 |
fw_cfg = bochs_bios_init(); |
921 |
rom_set_fw(fw_cfg); |
922 |
|
923 |
if (linux_boot) {
|
924 |
load_linux(*fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
925 |
} |
926 |
|
927 |
for (i = 0; i < nb_option_roms; i++) { |
928 |
rom_add_option(option_rom[i]); |
929 |
} |
930 |
} |
931 |
|
932 |
/* PC hardware initialisation */
|
933 |
static void pc_init1(ram_addr_t ram_size, |
934 |
const char *boot_device, |
935 |
const char *kernel_filename, |
936 |
const char *kernel_cmdline, |
937 |
const char *initrd_filename, |
938 |
const char *cpu_model, |
939 |
int pci_enabled)
|
940 |
{ |
941 |
int i;
|
942 |
ram_addr_t below_4g_mem_size, above_4g_mem_size; |
943 |
PCIBus *pci_bus; |
944 |
PCII440FXState *i440fx_state; |
945 |
int piix3_devfn = -1; |
946 |
qemu_irq *cpu_irq; |
947 |
qemu_irq *isa_irq; |
948 |
qemu_irq *i8259; |
949 |
qemu_irq *cmos_s3; |
950 |
qemu_irq *smi_irq; |
951 |
IsaIrqState *isa_irq_state; |
952 |
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
953 |
DriveInfo *fd[MAX_FD]; |
954 |
FDCtrl *floppy_controller; |
955 |
RTCState *rtc_state; |
956 |
PITState *pit; |
957 |
|
958 |
pc_cpus_init(cpu_model); |
959 |
|
960 |
vmport_init(); |
961 |
|
962 |
/* allocate ram and load rom/bios */
|
963 |
pc_memory_init(ram_size, kernel_filename, kernel_cmdline, initrd_filename, |
964 |
&below_4g_mem_size, &above_4g_mem_size); |
965 |
|
966 |
cpu_irq = pc_allocate_cpu_irq(); |
967 |
i8259 = i8259_init(cpu_irq[0]);
|
968 |
isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
|
969 |
isa_irq_state->i8259 = i8259; |
970 |
if (pci_enabled) {
|
971 |
isa_irq_state->ioapic = ioapic_init(); |
972 |
} |
973 |
isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
|
974 |
|
975 |
if (pci_enabled) {
|
976 |
pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq, ram_size); |
977 |
} else {
|
978 |
pci_bus = NULL;
|
979 |
isa_bus_new(NULL);
|
980 |
} |
981 |
isa_bus_irqs(isa_irq); |
982 |
|
983 |
pc_register_ferr_irq(isa_reserve_irq(13));
|
984 |
|
985 |
/* init basic PC hardware */
|
986 |
register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
987 |
|
988 |
register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
989 |
|
990 |
if (cirrus_vga_enabled) {
|
991 |
if (pci_enabled) {
|
992 |
pci_cirrus_vga_init(pci_bus); |
993 |
} else {
|
994 |
isa_cirrus_vga_init(); |
995 |
} |
996 |
} else if (vmsvga_enabled) { |
997 |
if (pci_enabled)
|
998 |
pci_vmsvga_init(pci_bus); |
999 |
else
|
1000 |
fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
|
1001 |
} else if (std_vga_enabled) { |
1002 |
if (pci_enabled) {
|
1003 |
pci_vga_init(pci_bus, 0, 0); |
1004 |
} else {
|
1005 |
isa_vga_init(); |
1006 |
} |
1007 |
} |
1008 |
|
1009 |
rtc_state = rtc_init(2000);
|
1010 |
|
1011 |
qemu_register_boot_set(pc_boot_set, rtc_state); |
1012 |
|
1013 |
register_ioport_read(0x92, 1, 1, ioport92_read, NULL); |
1014 |
register_ioport_write(0x92, 1, 1, ioport92_write, NULL); |
1015 |
|
1016 |
pit = pit_init(0x40, isa_reserve_irq(0)); |
1017 |
pcspk_init(pit); |
1018 |
if (!no_hpet) {
|
1019 |
hpet_init(isa_irq); |
1020 |
} |
1021 |
|
1022 |
for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
1023 |
if (serial_hds[i]) {
|
1024 |
serial_isa_init(i, serial_hds[i]); |
1025 |
} |
1026 |
} |
1027 |
|
1028 |
for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
1029 |
if (parallel_hds[i]) {
|
1030 |
parallel_init(i, parallel_hds[i]); |
1031 |
} |
1032 |
} |
1033 |
|
1034 |
for(i = 0; i < nb_nics; i++) { |
1035 |
NICInfo *nd = &nd_table[i]; |
1036 |
|
1037 |
if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) |
1038 |
pc_init_ne2k_isa(nd); |
1039 |
else
|
1040 |
pci_nic_init_nofail(nd, "e1000", NULL); |
1041 |
} |
1042 |
|
1043 |
if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
1044 |
fprintf(stderr, "qemu: too many IDE bus\n");
|
1045 |
exit(1);
|
1046 |
} |
1047 |
|
1048 |
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
1049 |
hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
1050 |
} |
1051 |
|
1052 |
if (pci_enabled) {
|
1053 |
pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
|
1054 |
} else {
|
1055 |
for(i = 0; i < MAX_IDE_BUS; i++) { |
1056 |
isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
1057 |
hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
|
1058 |
} |
1059 |
} |
1060 |
|
1061 |
isa_create_simple("i8042");
|
1062 |
DMA_init(0);
|
1063 |
#ifdef HAS_AUDIO
|
1064 |
audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
|
1065 |
#endif
|
1066 |
|
1067 |
for(i = 0; i < MAX_FD; i++) { |
1068 |
fd[i] = drive_get(IF_FLOPPY, 0, i);
|
1069 |
} |
1070 |
floppy_controller = fdctrl_init_isa(fd); |
1071 |
|
1072 |
cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd, |
1073 |
floppy_controller, rtc_state); |
1074 |
|
1075 |
if (pci_enabled && usb_enabled) {
|
1076 |
usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
|
1077 |
} |
1078 |
|
1079 |
if (pci_enabled && acpi_enabled) {
|
1080 |
uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ |
1081 |
i2c_bus *smbus; |
1082 |
|
1083 |
cmos_s3 = qemu_allocate_irqs(cmos_set_s3_resume, rtc_state, 1);
|
1084 |
smi_irq = qemu_allocate_irqs(acpi_smi_interrupt, first_cpu, 1);
|
1085 |
/* TODO: Populate SPD eeprom data. */
|
1086 |
smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, |
1087 |
isa_reserve_irq(9), *cmos_s3, *smi_irq,
|
1088 |
kvm_enabled()); |
1089 |
for (i = 0; i < 8; i++) { |
1090 |
DeviceState *eeprom; |
1091 |
eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
|
1092 |
qdev_prop_set_uint8(eeprom, "address", 0x50 + i); |
1093 |
qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256)); |
1094 |
qdev_init_nofail(eeprom); |
1095 |
} |
1096 |
piix4_acpi_system_hot_add_init(pci_bus); |
1097 |
} |
1098 |
|
1099 |
if (i440fx_state) {
|
1100 |
i440fx_init_memory_mappings(i440fx_state); |
1101 |
} |
1102 |
|
1103 |
if (pci_enabled) {
|
1104 |
int max_bus;
|
1105 |
int bus;
|
1106 |
|
1107 |
max_bus = drive_get_max_bus(IF_SCSI); |
1108 |
for (bus = 0; bus <= max_bus; bus++) { |
1109 |
pci_create_simple(pci_bus, -1, "lsi53c895a"); |
1110 |
} |
1111 |
} |
1112 |
} |
1113 |
|
1114 |
static void pc_init_pci(ram_addr_t ram_size, |
1115 |
const char *boot_device, |
1116 |
const char *kernel_filename, |
1117 |
const char *kernel_cmdline, |
1118 |
const char *initrd_filename, |
1119 |
const char *cpu_model) |
1120 |
{ |
1121 |
pc_init1(ram_size, boot_device, |
1122 |
kernel_filename, kernel_cmdline, |
1123 |
initrd_filename, cpu_model, 1);
|
1124 |
} |
1125 |
|
1126 |
static void pc_init_isa(ram_addr_t ram_size, |
1127 |
const char *boot_device, |
1128 |
const char *kernel_filename, |
1129 |
const char *kernel_cmdline, |
1130 |
const char *initrd_filename, |
1131 |
const char *cpu_model) |
1132 |
{ |
1133 |
if (cpu_model == NULL) |
1134 |
cpu_model = "486";
|
1135 |
pc_init1(ram_size, boot_device, |
1136 |
kernel_filename, kernel_cmdline, |
1137 |
initrd_filename, cpu_model, 0);
|
1138 |
} |
1139 |
|
1140 |
static QEMUMachine pc_machine = {
|
1141 |
.name = "pc-0.13",
|
1142 |
.alias = "pc",
|
1143 |
.desc = "Standard PC",
|
1144 |
.init = pc_init_pci, |
1145 |
.max_cpus = 255,
|
1146 |
.is_default = 1,
|
1147 |
}; |
1148 |
|
1149 |
static QEMUMachine pc_machine_v0_12 = {
|
1150 |
.name = "pc-0.12",
|
1151 |
.desc = "Standard PC",
|
1152 |
.init = pc_init_pci, |
1153 |
.max_cpus = 255,
|
1154 |
.compat_props = (GlobalProperty[]) { |
1155 |
{ |
1156 |
.driver = "virtio-serial-pci",
|
1157 |
.property = "max_nr_ports",
|
1158 |
.value = stringify(1),
|
1159 |
},{ |
1160 |
.driver = "virtio-serial-pci",
|
1161 |
.property = "vectors",
|
1162 |
.value = stringify(0),
|
1163 |
}, |
1164 |
{ /* end of list */ }
|
1165 |
} |
1166 |
}; |
1167 |
|
1168 |
static QEMUMachine pc_machine_v0_11 = {
|
1169 |
.name = "pc-0.11",
|
1170 |
.desc = "Standard PC, qemu 0.11",
|
1171 |
.init = pc_init_pci, |
1172 |
.max_cpus = 255,
|
1173 |
.compat_props = (GlobalProperty[]) { |
1174 |
{ |
1175 |
.driver = "virtio-blk-pci",
|
1176 |
.property = "vectors",
|
1177 |
.value = stringify(0),
|
1178 |
},{ |
1179 |
.driver = "virtio-serial-pci",
|
1180 |
.property = "max_nr_ports",
|
1181 |
.value = stringify(1),
|
1182 |
},{ |
1183 |
.driver = "virtio-serial-pci",
|
1184 |
.property = "vectors",
|
1185 |
.value = stringify(0),
|
1186 |
},{ |
1187 |
.driver = "ide-drive",
|
1188 |
.property = "ver",
|
1189 |
.value = "0.11",
|
1190 |
},{ |
1191 |
.driver = "scsi-disk",
|
1192 |
.property = "ver",
|
1193 |
.value = "0.11",
|
1194 |
},{ |
1195 |
.driver = "PCI",
|
1196 |
.property = "rombar",
|
1197 |
.value = stringify(0),
|
1198 |
}, |
1199 |
{ /* end of list */ }
|
1200 |
} |
1201 |
}; |
1202 |
|
1203 |
static QEMUMachine pc_machine_v0_10 = {
|
1204 |
.name = "pc-0.10",
|
1205 |
.desc = "Standard PC, qemu 0.10",
|
1206 |
.init = pc_init_pci, |
1207 |
.max_cpus = 255,
|
1208 |
.compat_props = (GlobalProperty[]) { |
1209 |
{ |
1210 |
.driver = "virtio-blk-pci",
|
1211 |
.property = "class",
|
1212 |
.value = stringify(PCI_CLASS_STORAGE_OTHER), |
1213 |
},{ |
1214 |
.driver = "virtio-serial-pci",
|
1215 |
.property = "class",
|
1216 |
.value = stringify(PCI_CLASS_DISPLAY_OTHER), |
1217 |
},{ |
1218 |
.driver = "virtio-serial-pci",
|
1219 |
.property = "max_nr_ports",
|
1220 |
.value = stringify(1),
|
1221 |
},{ |
1222 |
.driver = "virtio-serial-pci",
|
1223 |
.property = "vectors",
|
1224 |
.value = stringify(0),
|
1225 |
},{ |
1226 |
.driver = "virtio-net-pci",
|
1227 |
.property = "vectors",
|
1228 |
.value = stringify(0),
|
1229 |
},{ |
1230 |
.driver = "virtio-blk-pci",
|
1231 |
.property = "vectors",
|
1232 |
.value = stringify(0),
|
1233 |
},{ |
1234 |
.driver = "ide-drive",
|
1235 |
.property = "ver",
|
1236 |
.value = "0.10",
|
1237 |
},{ |
1238 |
.driver = "scsi-disk",
|
1239 |
.property = "ver",
|
1240 |
.value = "0.10",
|
1241 |
},{ |
1242 |
.driver = "PCI",
|
1243 |
.property = "rombar",
|
1244 |
.value = stringify(0),
|
1245 |
}, |
1246 |
{ /* end of list */ }
|
1247 |
}, |
1248 |
}; |
1249 |
|
1250 |
static QEMUMachine isapc_machine = {
|
1251 |
.name = "isapc",
|
1252 |
.desc = "ISA-only PC",
|
1253 |
.init = pc_init_isa, |
1254 |
.max_cpus = 1,
|
1255 |
}; |
1256 |
|
1257 |
static void pc_machine_init(void) |
1258 |
{ |
1259 |
qemu_register_machine(&pc_machine); |
1260 |
qemu_register_machine(&pc_machine_v0_12); |
1261 |
qemu_register_machine(&pc_machine_v0_11); |
1262 |
qemu_register_machine(&pc_machine_v0_10); |
1263 |
qemu_register_machine(&isapc_machine); |
1264 |
} |
1265 |
|
1266 |
machine_init(pc_machine_init); |