Revision 3dd3a2b9 target-lm32/cpu.h
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/* debug registers */ |
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uint32_t dc; /* debug control */ |
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uint32_t bp[4]; /* breakpoint addresses */ |
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uint32_t wp[4]; /* watchpoint addresses */ |
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uint32_t bp[4]; /* breakpoints */ |
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uint32_t wp[4]; /* watchpoints */ |
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CPUBreakpoint * cpu_breakpoint[4]; |
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CPUWatchpoint * cpu_watchpoint[4]; |
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CPU_COMMON |
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}; |
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typedef enum {
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LM32_WP_DISABLED = 0, |
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LM32_WP_READ, |
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LM32_WP_WRITE, |
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LM32_WP_READ_WRITE, |
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} lm32_wp_t; |
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static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx) |
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{
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assert(idx < 4); |
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return (dc >> (idx+1)*2) & 0x3; |
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} |
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#include "cpu-qom.h" |
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LM32CPU *cpu_lm32_init(const char *cpu_model); |
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void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
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void lm32_translate_init(void); |
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void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value); |
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void QEMU_NORETURN raise_exception(CPULM32State *env, int index); |
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void lm32_debug_excp_handler(CPULM32State *env); |
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void lm32_breakpoint_insert(CPULM32State *env, int index, target_ulong address); |
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void lm32_breakpoint_remove(CPULM32State *env, int index); |
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void lm32_watchpoint_insert(CPULM32State *env, int index, target_ulong address, |
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lm32_wp_t wp_type); |
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void lm32_watchpoint_remove(CPULM32State *env, int index); |
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static inline CPULM32State *cpu_init(const char *cpu_model) |
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{
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