Revision 3deaeab7 target-sparc/op_helper.c
b/target-sparc/op_helper.c | ||
---|---|---|
591 | 591 |
|
592 | 592 |
oldreg = env->mmuregs[reg]; |
593 | 593 |
switch(reg) { |
594 |
case 0: |
|
594 |
case 0: // Control Register
|
|
595 | 595 |
env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | |
596 | 596 |
(T1 & 0x00ffffff); |
597 | 597 |
// Mappings generated during no-fault mode or MMU |
... | ... | |
600 | 600 |
(env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm))) |
601 | 601 |
tlb_flush(env, 1); |
602 | 602 |
break; |
603 |
case 2: |
|
604 |
env->mmuregs[reg] = T1; |
|
603 |
case 1: // Context Table Pointer Register |
|
604 |
env->mmuregs[reg] = T1 & env->mmu_ctpr_mask; |
|
605 |
break; |
|
606 |
case 2: // Context Register |
|
607 |
env->mmuregs[reg] = T1 & env->mmu_cxr_mask; |
|
605 | 608 |
if (oldreg != env->mmuregs[reg]) { |
606 | 609 |
/* we flush when the MMU context changes because |
607 | 610 |
QEMU has no MMU context support */ |
608 | 611 |
tlb_flush(env, 1); |
609 | 612 |
} |
610 | 613 |
break; |
611 |
case 3: |
|
612 |
case 4: |
|
614 |
case 3: // Synchronous Fault Status Register with Clear |
|
615 |
case 4: // Synchronous Fault Address Register |
|
616 |
break; |
|
617 |
case 0x10: // TLB Replacement Control Register |
|
618 |
env->mmuregs[reg] = T1 & env->mmu_trcr_mask; |
|
613 | 619 |
break; |
614 |
case 0x13: |
|
615 |
env->mmuregs[3] = T1; |
|
620 |
case 0x13: // Synchronous Fault Status Register with Read and Clear
|
|
621 |
env->mmuregs[3] = T1 & env->mmu_sfsr_mask;
|
|
616 | 622 |
break; |
617 |
case 0x14: |
|
623 |
case 0x14: // Synchronous Fault Address Register
|
|
618 | 624 |
env->mmuregs[4] = T1; |
619 | 625 |
break; |
620 | 626 |
default: |
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