root / hw / dma.c @ 3df3f6fd
History | View | Annotate | Download (10.8 kB)
1 | 27503323 | bellard | /*
|
---|---|---|---|
2 | 27503323 | bellard | * QEMU DMA emulation
|
3 | 27503323 | bellard | *
|
4 | 27503323 | bellard | * Copyright (c) 2003 Vassili Karpov (malc)
|
5 | 27503323 | bellard | *
|
6 | 27503323 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 27503323 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | 27503323 | bellard | * in the Software without restriction, including without limitation the rights
|
9 | 27503323 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 27503323 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | 27503323 | bellard | * furnished to do so, subject to the following conditions:
|
12 | 27503323 | bellard | *
|
13 | 27503323 | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | 27503323 | bellard | * all copies or substantial portions of the Software.
|
15 | 27503323 | bellard | *
|
16 | 27503323 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 27503323 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 27503323 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 27503323 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 27503323 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 27503323 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 27503323 | bellard | * THE SOFTWARE.
|
23 | 27503323 | bellard | */
|
24 | 16d17fdb | bellard | #include "vl.h" |
25 | 27503323 | bellard | |
26 | 7ebb5e41 | bellard | //#define DEBUG_DMA
|
27 | 7ebb5e41 | bellard | |
28 | 27503323 | bellard | #define log(...) fprintf (stderr, "dma: " __VA_ARGS__) |
29 | 27503323 | bellard | #ifdef DEBUG_DMA
|
30 | 27503323 | bellard | #define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__) |
31 | 27503323 | bellard | #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) |
32 | 27503323 | bellard | #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) |
33 | 27503323 | bellard | #else
|
34 | 27503323 | bellard | #define lwarn(...)
|
35 | 27503323 | bellard | #define linfo(...)
|
36 | 27503323 | bellard | #define ldebug(...)
|
37 | 27503323 | bellard | #endif
|
38 | 27503323 | bellard | |
39 | 27503323 | bellard | #define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0]))) |
40 | 27503323 | bellard | |
41 | 27503323 | bellard | struct dma_regs {
|
42 | 27503323 | bellard | int now[2]; |
43 | 27503323 | bellard | uint16_t base[2];
|
44 | 27503323 | bellard | uint8_t mode; |
45 | 27503323 | bellard | uint8_t page; |
46 | b0bda528 | bellard | uint8_t pageh; |
47 | 27503323 | bellard | uint8_t dack; |
48 | 27503323 | bellard | uint8_t eop; |
49 | 16f62432 | bellard | DMA_transfer_handler transfer_handler; |
50 | 16f62432 | bellard | void *opaque;
|
51 | 27503323 | bellard | }; |
52 | 27503323 | bellard | |
53 | 27503323 | bellard | #define ADDR 0 |
54 | 27503323 | bellard | #define COUNT 1 |
55 | 27503323 | bellard | |
56 | 27503323 | bellard | static struct dma_cont { |
57 | 27503323 | bellard | uint8_t status; |
58 | 27503323 | bellard | uint8_t command; |
59 | 27503323 | bellard | uint8_t mask; |
60 | 27503323 | bellard | uint8_t flip_flop; |
61 | 9eb153f1 | bellard | int dshift;
|
62 | 27503323 | bellard | struct dma_regs regs[4]; |
63 | 27503323 | bellard | } dma_controllers[2];
|
64 | 27503323 | bellard | |
65 | 27503323 | bellard | enum {
|
66 | 27503323 | bellard | CMD_MEMORY_TO_MEMORY = 0x01,
|
67 | 27503323 | bellard | CMD_FIXED_ADDRESS = 0x02,
|
68 | 27503323 | bellard | CMD_BLOCK_CONTROLLER = 0x04,
|
69 | 27503323 | bellard | CMD_COMPRESSED_TIME = 0x08,
|
70 | 27503323 | bellard | CMD_CYCLIC_PRIORITY = 0x10,
|
71 | 27503323 | bellard | CMD_EXTENDED_WRITE = 0x20,
|
72 | 27503323 | bellard | CMD_LOW_DREQ = 0x40,
|
73 | 27503323 | bellard | CMD_LOW_DACK = 0x80,
|
74 | 27503323 | bellard | CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS |
75 | 27503323 | bellard | | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE |
76 | 27503323 | bellard | | CMD_LOW_DREQ | CMD_LOW_DACK |
77 | 27503323 | bellard | |
78 | 27503323 | bellard | }; |
79 | 27503323 | bellard | |
80 | 9eb153f1 | bellard | static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; |
81 | 9eb153f1 | bellard | |
82 | 7d977de7 | bellard | static void write_page (void *opaque, uint32_t nport, uint32_t data) |
83 | 27503323 | bellard | { |
84 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
|
85 | 27503323 | bellard | int ichan;
|
86 | 27503323 | bellard | |
87 | 9eb153f1 | bellard | ichan = channels[nport & 7];
|
88 | 27503323 | bellard | if (-1 == ichan) { |
89 | 27503323 | bellard | log ("invalid channel %#x %#x\n", nport, data);
|
90 | 27503323 | bellard | return;
|
91 | 27503323 | bellard | } |
92 | 9eb153f1 | bellard | d->regs[ichan].page = data; |
93 | 9eb153f1 | bellard | } |
94 | 9eb153f1 | bellard | |
95 | b0bda528 | bellard | static void write_pageh (void *opaque, uint32_t nport, uint32_t data) |
96 | 9eb153f1 | bellard | { |
97 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
|
98 | 9eb153f1 | bellard | int ichan;
|
99 | 27503323 | bellard | |
100 | 9eb153f1 | bellard | ichan = channels[nport & 7];
|
101 | b0bda528 | bellard | if (-1 == ichan) { |
102 | b0bda528 | bellard | log ("invalid channel %#x %#x\n", nport, data);
|
103 | b0bda528 | bellard | return;
|
104 | b0bda528 | bellard | } |
105 | b0bda528 | bellard | d->regs[ichan].pageh = data; |
106 | b0bda528 | bellard | } |
107 | 9eb153f1 | bellard | |
108 | b0bda528 | bellard | static uint32_t read_page (void *opaque, uint32_t nport) |
109 | b0bda528 | bellard | { |
110 | b0bda528 | bellard | struct dma_cont *d = opaque;
|
111 | b0bda528 | bellard | int ichan;
|
112 | b0bda528 | bellard | |
113 | b0bda528 | bellard | ichan = channels[nport & 7];
|
114 | 9eb153f1 | bellard | if (-1 == ichan) { |
115 | 9eb153f1 | bellard | log ("invalid channel read %#x\n", nport);
|
116 | 9eb153f1 | bellard | return 0; |
117 | 9eb153f1 | bellard | } |
118 | 9eb153f1 | bellard | return d->regs[ichan].page;
|
119 | 27503323 | bellard | } |
120 | 27503323 | bellard | |
121 | b0bda528 | bellard | static uint32_t read_pageh (void *opaque, uint32_t nport) |
122 | b0bda528 | bellard | { |
123 | b0bda528 | bellard | struct dma_cont *d = opaque;
|
124 | b0bda528 | bellard | int ichan;
|
125 | b0bda528 | bellard | |
126 | b0bda528 | bellard | ichan = channels[nport & 7];
|
127 | b0bda528 | bellard | if (-1 == ichan) { |
128 | b0bda528 | bellard | log ("invalid channel read %#x\n", nport);
|
129 | b0bda528 | bellard | return 0; |
130 | b0bda528 | bellard | } |
131 | b0bda528 | bellard | return d->regs[ichan].pageh;
|
132 | b0bda528 | bellard | } |
133 | b0bda528 | bellard | |
134 | 9eb153f1 | bellard | static inline void init_chan (struct dma_cont *d, int ichan) |
135 | 27503323 | bellard | { |
136 | 27503323 | bellard | struct dma_regs *r;
|
137 | 27503323 | bellard | |
138 | 9eb153f1 | bellard | r = d->regs + ichan; |
139 | 9eb153f1 | bellard | r->now[ADDR] = r->base[0] << d->dshift;
|
140 | 27503323 | bellard | r->now[COUNT] = 0;
|
141 | 27503323 | bellard | } |
142 | 27503323 | bellard | |
143 | 9eb153f1 | bellard | static inline int getff (struct dma_cont *d) |
144 | 27503323 | bellard | { |
145 | 27503323 | bellard | int ff;
|
146 | 27503323 | bellard | |
147 | 9eb153f1 | bellard | ff = d->flip_flop; |
148 | 9eb153f1 | bellard | d->flip_flop = !ff; |
149 | 27503323 | bellard | return ff;
|
150 | 27503323 | bellard | } |
151 | 27503323 | bellard | |
152 | 7d977de7 | bellard | static uint32_t read_chan (void *opaque, uint32_t nport) |
153 | 27503323 | bellard | { |
154 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
|
155 | 9eb153f1 | bellard | int ichan, nreg, iport, ff, val;
|
156 | 27503323 | bellard | struct dma_regs *r;
|
157 | 27503323 | bellard | |
158 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
|
159 | 9eb153f1 | bellard | ichan = iport >> 1;
|
160 | 9eb153f1 | bellard | nreg = iport & 1;
|
161 | 9eb153f1 | bellard | r = d->regs + ichan; |
162 | 27503323 | bellard | |
163 | 9eb153f1 | bellard | ff = getff (d); |
164 | 27503323 | bellard | if (nreg)
|
165 | 9eb153f1 | bellard | val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; |
166 | 27503323 | bellard | else
|
167 | 27503323 | bellard | val = r->now[ADDR] + r->now[COUNT]; |
168 | 27503323 | bellard | |
169 | 9eb153f1 | bellard | return (val >> (d->dshift + (ff << 3))) & 0xff; |
170 | 27503323 | bellard | } |
171 | 27503323 | bellard | |
172 | 7d977de7 | bellard | static void write_chan (void *opaque, uint32_t nport, uint32_t data) |
173 | 27503323 | bellard | { |
174 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
|
175 | 9eb153f1 | bellard | int iport, ichan, nreg;
|
176 | 27503323 | bellard | struct dma_regs *r;
|
177 | 27503323 | bellard | |
178 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
|
179 | 9eb153f1 | bellard | ichan = iport >> 1;
|
180 | 9eb153f1 | bellard | nreg = iport & 1;
|
181 | 9eb153f1 | bellard | r = d->regs + ichan; |
182 | 9eb153f1 | bellard | if (getff (d)) {
|
183 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
184 | 9eb153f1 | bellard | init_chan (d, ichan); |
185 | 3504fe17 | bellard | } else {
|
186 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); |
187 | 27503323 | bellard | } |
188 | 27503323 | bellard | } |
189 | 27503323 | bellard | |
190 | 7d977de7 | bellard | static void write_cont (void *opaque, uint32_t nport, uint32_t data) |
191 | 27503323 | bellard | { |
192 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
|
193 | 9eb153f1 | bellard | int iport, ichan;
|
194 | 27503323 | bellard | |
195 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
|
196 | 27503323 | bellard | switch (iport) {
|
197 | 27503323 | bellard | case 8: /* command */ |
198 | df475d18 | bellard | if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { |
199 | 27503323 | bellard | log ("command %#x not supported\n", data);
|
200 | df475d18 | bellard | return;
|
201 | 27503323 | bellard | } |
202 | 27503323 | bellard | d->command = data; |
203 | 27503323 | bellard | break;
|
204 | 27503323 | bellard | |
205 | 27503323 | bellard | case 9: |
206 | 27503323 | bellard | ichan = data & 3;
|
207 | 27503323 | bellard | if (data & 4) { |
208 | 27503323 | bellard | d->status |= 1 << (ichan + 4); |
209 | 27503323 | bellard | } |
210 | 27503323 | bellard | else {
|
211 | 27503323 | bellard | d->status &= ~(1 << (ichan + 4)); |
212 | 27503323 | bellard | } |
213 | 27503323 | bellard | d->status &= ~(1 << ichan);
|
214 | 27503323 | bellard | break;
|
215 | 27503323 | bellard | |
216 | 27503323 | bellard | case 0xa: /* single mask */ |
217 | 27503323 | bellard | if (data & 4) |
218 | 27503323 | bellard | d->mask |= 1 << (data & 3); |
219 | 27503323 | bellard | else
|
220 | 27503323 | bellard | d->mask &= ~(1 << (data & 3)); |
221 | 27503323 | bellard | break;
|
222 | 27503323 | bellard | |
223 | 27503323 | bellard | case 0xb: /* mode */ |
224 | 27503323 | bellard | { |
225 | 16d17fdb | bellard | ichan = data & 3;
|
226 | 16d17fdb | bellard | #ifdef DEBUG_DMA
|
227 | 27503323 | bellard | int op;
|
228 | 27503323 | bellard | int ai;
|
229 | 27503323 | bellard | int dir;
|
230 | 27503323 | bellard | int opmode;
|
231 | 27503323 | bellard | |
232 | 16d17fdb | bellard | op = (data >> 2) & 3; |
233 | 16d17fdb | bellard | ai = (data >> 4) & 1; |
234 | 16d17fdb | bellard | dir = (data >> 5) & 1; |
235 | 16d17fdb | bellard | opmode = (data >> 6) & 3; |
236 | 27503323 | bellard | |
237 | 27503323 | bellard | linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
|
238 | 27503323 | bellard | ichan, op, ai, dir, opmode); |
239 | 27503323 | bellard | #endif
|
240 | 27503323 | bellard | |
241 | 27503323 | bellard | d->regs[ichan].mode = data; |
242 | 27503323 | bellard | break;
|
243 | 27503323 | bellard | } |
244 | 27503323 | bellard | |
245 | 27503323 | bellard | case 0xc: /* clear flip flop */ |
246 | 27503323 | bellard | d->flip_flop = 0;
|
247 | 27503323 | bellard | break;
|
248 | 27503323 | bellard | |
249 | 27503323 | bellard | case 0xd: /* reset */ |
250 | 27503323 | bellard | d->flip_flop = 0;
|
251 | 27503323 | bellard | d->mask = ~0;
|
252 | 27503323 | bellard | d->status = 0;
|
253 | 27503323 | bellard | d->command = 0;
|
254 | 27503323 | bellard | break;
|
255 | 27503323 | bellard | |
256 | 27503323 | bellard | case 0xe: /* clear mask for all channels */ |
257 | 27503323 | bellard | d->mask = 0;
|
258 | 27503323 | bellard | break;
|
259 | 27503323 | bellard | |
260 | 27503323 | bellard | case 0xf: /* write mask for all channels */ |
261 | 27503323 | bellard | d->mask = data; |
262 | 27503323 | bellard | break;
|
263 | 27503323 | bellard | |
264 | 27503323 | bellard | default:
|
265 | 27503323 | bellard | log ("dma: unknown iport %#x\n", iport);
|
266 | df475d18 | bellard | break;
|
267 | 27503323 | bellard | } |
268 | 27503323 | bellard | |
269 | 16d17fdb | bellard | #ifdef DEBUG_DMA
|
270 | 27503323 | bellard | if (0xc != iport) { |
271 | 9eb153f1 | bellard | linfo ("nport %#06x, ichan % 2d, val %#06x\n",
|
272 | 9eb153f1 | bellard | nport, ichan, data); |
273 | 27503323 | bellard | } |
274 | 27503323 | bellard | #endif
|
275 | 27503323 | bellard | } |
276 | 27503323 | bellard | |
277 | 9eb153f1 | bellard | static uint32_t read_cont (void *opaque, uint32_t nport) |
278 | 9eb153f1 | bellard | { |
279 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
|
280 | 9eb153f1 | bellard | int iport, val;
|
281 | 9eb153f1 | bellard | |
282 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
|
283 | 9eb153f1 | bellard | switch (iport) {
|
284 | 9eb153f1 | bellard | case 0x08: /* status */ |
285 | 9eb153f1 | bellard | val = d->status; |
286 | 9eb153f1 | bellard | d->status &= 0xf0;
|
287 | 9eb153f1 | bellard | break;
|
288 | 9eb153f1 | bellard | case 0x0f: /* mask */ |
289 | 9eb153f1 | bellard | val = d->mask; |
290 | 9eb153f1 | bellard | break;
|
291 | 9eb153f1 | bellard | default:
|
292 | 9eb153f1 | bellard | val = 0;
|
293 | 9eb153f1 | bellard | break;
|
294 | 9eb153f1 | bellard | } |
295 | 9eb153f1 | bellard | return val;
|
296 | 9eb153f1 | bellard | } |
297 | 9eb153f1 | bellard | |
298 | 27503323 | bellard | int DMA_get_channel_mode (int nchan) |
299 | 27503323 | bellard | { |
300 | 27503323 | bellard | return dma_controllers[nchan > 3].regs[nchan & 3].mode; |
301 | 27503323 | bellard | } |
302 | 27503323 | bellard | |
303 | 27503323 | bellard | void DMA_hold_DREQ (int nchan) |
304 | 27503323 | bellard | { |
305 | 27503323 | bellard | int ncont, ichan;
|
306 | 27503323 | bellard | |
307 | 27503323 | bellard | ncont = nchan > 3;
|
308 | 27503323 | bellard | ichan = nchan & 3;
|
309 | 27503323 | bellard | linfo ("held cont=%d chan=%d\n", ncont, ichan);
|
310 | 27503323 | bellard | dma_controllers[ncont].status |= 1 << (ichan + 4); |
311 | 27503323 | bellard | } |
312 | 27503323 | bellard | |
313 | 27503323 | bellard | void DMA_release_DREQ (int nchan) |
314 | 27503323 | bellard | { |
315 | 27503323 | bellard | int ncont, ichan;
|
316 | 27503323 | bellard | |
317 | 27503323 | bellard | ncont = nchan > 3;
|
318 | 27503323 | bellard | ichan = nchan & 3;
|
319 | 27503323 | bellard | linfo ("released cont=%d chan=%d\n", ncont, ichan);
|
320 | 27503323 | bellard | dma_controllers[ncont].status &= ~(1 << (ichan + 4)); |
321 | 27503323 | bellard | } |
322 | 27503323 | bellard | |
323 | 27503323 | bellard | static void channel_run (int ncont, int ichan) |
324 | 27503323 | bellard | { |
325 | 27503323 | bellard | struct dma_regs *r;
|
326 | 27503323 | bellard | int n;
|
327 | 16f62432 | bellard | target_ulong addr; |
328 | 27503323 | bellard | /* int ai, dir; */
|
329 | 27503323 | bellard | |
330 | 27503323 | bellard | r = dma_controllers[ncont].regs + ichan; |
331 | 27503323 | bellard | /* ai = r->mode & 16; */
|
332 | 27503323 | bellard | /* dir = r->mode & 32 ? -1 : 1; */
|
333 | 27503323 | bellard | |
334 | b0bda528 | bellard | /* NOTE: pageh is only used by PPC PREP */
|
335 | b0bda528 | bellard | addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
336 | 16f62432 | bellard | n = r->transfer_handler (r->opaque, addr, |
337 | 16f62432 | bellard | (r->base[COUNT] << ncont) + (1 << ncont));
|
338 | 27503323 | bellard | r->now[COUNT] = n; |
339 | 27503323 | bellard | |
340 | 16f62432 | bellard | ldebug ("dma_pos %d size %d\n",
|
341 | 16f62432 | bellard | n, (r->base[1] << ncont) + (1 << ncont)); |
342 | 27503323 | bellard | } |
343 | 27503323 | bellard | |
344 | 27503323 | bellard | void DMA_run (void) |
345 | 27503323 | bellard | { |
346 | 27503323 | bellard | struct dma_cont *d;
|
347 | 27503323 | bellard | int icont, ichan;
|
348 | 27503323 | bellard | |
349 | 27503323 | bellard | d = dma_controllers; |
350 | 27503323 | bellard | |
351 | 27503323 | bellard | for (icont = 0; icont < 2; icont++, d++) { |
352 | 27503323 | bellard | for (ichan = 0; ichan < 4; ichan++) { |
353 | 27503323 | bellard | int mask;
|
354 | 27503323 | bellard | |
355 | 27503323 | bellard | mask = 1 << ichan;
|
356 | 27503323 | bellard | |
357 | 27503323 | bellard | if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) |
358 | 27503323 | bellard | channel_run (icont, ichan); |
359 | 27503323 | bellard | } |
360 | 27503323 | bellard | } |
361 | 27503323 | bellard | } |
362 | 27503323 | bellard | |
363 | 27503323 | bellard | void DMA_register_channel (int nchan, |
364 | 16f62432 | bellard | DMA_transfer_handler transfer_handler, |
365 | 16f62432 | bellard | void *opaque)
|
366 | 27503323 | bellard | { |
367 | 27503323 | bellard | struct dma_regs *r;
|
368 | 27503323 | bellard | int ichan, ncont;
|
369 | 27503323 | bellard | |
370 | 27503323 | bellard | ncont = nchan > 3;
|
371 | 27503323 | bellard | ichan = nchan & 3;
|
372 | 27503323 | bellard | |
373 | 27503323 | bellard | r = dma_controllers[ncont].regs + ichan; |
374 | 16f62432 | bellard | r->transfer_handler = transfer_handler; |
375 | 16f62432 | bellard | r->opaque = opaque; |
376 | 16f62432 | bellard | } |
377 | 16f62432 | bellard | |
378 | 16f62432 | bellard | /* request the emulator to transfer a new DMA memory block ASAP */
|
379 | 16f62432 | bellard | void DMA_schedule(int nchan) |
380 | 16f62432 | bellard | { |
381 | 16f62432 | bellard | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT); |
382 | 27503323 | bellard | } |
383 | 27503323 | bellard | |
384 | d7d02e3c | bellard | static void dma_reset(void *opaque) |
385 | d7d02e3c | bellard | { |
386 | d7d02e3c | bellard | struct dma_cont *d = opaque;
|
387 | d7d02e3c | bellard | write_cont (d, (0x0d << d->dshift), 0); |
388 | d7d02e3c | bellard | } |
389 | d7d02e3c | bellard | |
390 | 9eb153f1 | bellard | /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
|
391 | b0bda528 | bellard | static void dma_init2(struct dma_cont *d, int base, int dshift, |
392 | b0bda528 | bellard | int page_base, int pageh_base) |
393 | 27503323 | bellard | { |
394 | 9eb153f1 | bellard | const static int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; |
395 | 27503323 | bellard | int i;
|
396 | 27503323 | bellard | |
397 | 9eb153f1 | bellard | d->dshift = dshift; |
398 | 27503323 | bellard | for (i = 0; i < 8; i++) { |
399 | 9eb153f1 | bellard | register_ioport_write (base + (i << dshift), 1, 1, write_chan, d); |
400 | 9eb153f1 | bellard | register_ioport_read (base + (i << dshift), 1, 1, read_chan, d); |
401 | 27503323 | bellard | } |
402 | 27503323 | bellard | for (i = 0; i < LENOFA (page_port_list); i++) { |
403 | 9eb153f1 | bellard | register_ioport_write (page_base + page_port_list[i], 1, 1, |
404 | 9eb153f1 | bellard | write_page, d); |
405 | 9eb153f1 | bellard | register_ioport_read (page_base + page_port_list[i], 1, 1, |
406 | 9eb153f1 | bellard | read_page, d); |
407 | b0bda528 | bellard | if (pageh_base >= 0) { |
408 | b0bda528 | bellard | register_ioport_write (pageh_base + page_port_list[i], 1, 1, |
409 | b0bda528 | bellard | write_pageh, d); |
410 | b0bda528 | bellard | register_ioport_read (pageh_base + page_port_list[i], 1, 1, |
411 | b0bda528 | bellard | read_pageh, d); |
412 | b0bda528 | bellard | } |
413 | 27503323 | bellard | } |
414 | 27503323 | bellard | for (i = 0; i < 8; i++) { |
415 | 9eb153f1 | bellard | register_ioport_write (base + ((i + 8) << dshift), 1, 1, |
416 | 9eb153f1 | bellard | write_cont, d); |
417 | 9eb153f1 | bellard | register_ioport_read (base + ((i + 8) << dshift), 1, 1, |
418 | 9eb153f1 | bellard | read_cont, d); |
419 | 27503323 | bellard | } |
420 | d7d02e3c | bellard | qemu_register_reset(dma_reset, d); |
421 | d7d02e3c | bellard | dma_reset(d); |
422 | 9eb153f1 | bellard | } |
423 | 27503323 | bellard | |
424 | b0bda528 | bellard | void DMA_init (int high_page_enable) |
425 | 9eb153f1 | bellard | { |
426 | b0bda528 | bellard | dma_init2(&dma_controllers[0], 0x00, 0, 0x80, |
427 | b0bda528 | bellard | high_page_enable ? 0x480 : -1); |
428 | b0bda528 | bellard | dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, |
429 | b0bda528 | bellard | high_page_enable ? 0x488 : -1); |
430 | 27503323 | bellard | } |