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/*
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* i386 emulator main execution loop
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "config.h" |
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#include "exec.h" |
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#include "disas.h" |
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#if !defined(CONFIG_SOFTMMU)
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#undef EAX
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#undef ECX
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#undef EDX
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#undef EBX
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#undef ESP
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#undef EBP
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#undef ESI
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#undef EDI
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#undef EIP
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#include <signal.h> |
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#include <sys/ucontext.h> |
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#endif
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int tb_invalidated_flag;
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//#define DEBUG_EXEC
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//#define DEBUG_SIGNAL
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#if defined(TARGET_ARM) || defined(TARGET_SPARC)
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/* XXX: unify with i386 target */
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void cpu_loop_exit(void) |
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{ |
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longjmp(env->jmp_env, 1);
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} |
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#endif
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/* exit the current TB from a signal handler. The host registers are
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restored in a state compatible with the CPU emulator
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*/
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void cpu_resume_from_signal(CPUState *env1, void *puc) |
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{ |
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#if !defined(CONFIG_SOFTMMU)
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struct ucontext *uc = puc;
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#endif
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env = env1; |
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/* XXX: restore cpu registers saved in host registers */
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#if !defined(CONFIG_SOFTMMU)
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if (puc) {
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/* XXX: use siglongjmp ? */
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sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
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} |
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#endif
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longjmp(env->jmp_env, 1);
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} |
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/* main execution loop */
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int cpu_exec(CPUState *env1)
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{ |
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int saved_T0, saved_T1, saved_T2;
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CPUState *saved_env; |
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#ifdef reg_EAX
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int saved_EAX;
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#endif
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#ifdef reg_ECX
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int saved_ECX;
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#endif
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#ifdef reg_EDX
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int saved_EDX;
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#endif
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#ifdef reg_EBX
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int saved_EBX;
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#endif
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#ifdef reg_ESP
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int saved_ESP;
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#endif
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#ifdef reg_EBP
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int saved_EBP;
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#endif
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#ifdef reg_ESI
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int saved_ESI;
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#endif
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#ifdef reg_EDI
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int saved_EDI;
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#endif
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#ifdef __sparc__
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int saved_i7, tmp_T0;
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#endif
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int code_gen_size, ret, interrupt_request;
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void (*gen_func)(void); |
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TranslationBlock *tb, **ptb; |
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uint8_t *tc_ptr, *cs_base, *pc; |
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unsigned int flags; |
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/* first we save global registers */
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saved_T0 = T0; |
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saved_T1 = T1; |
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saved_T2 = T2; |
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saved_env = env; |
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env = env1; |
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#ifdef __sparc__
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/* we also save i7 because longjmp may not restore it */
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asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
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#endif
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#if defined(TARGET_I386)
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#ifdef reg_EAX
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saved_EAX = EAX; |
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EAX = env->regs[R_EAX]; |
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#endif
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#ifdef reg_ECX
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saved_ECX = ECX; |
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ECX = env->regs[R_ECX]; |
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#endif
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#ifdef reg_EDX
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saved_EDX = EDX; |
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EDX = env->regs[R_EDX]; |
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#endif
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#ifdef reg_EBX
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saved_EBX = EBX; |
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EBX = env->regs[R_EBX]; |
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#endif
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#ifdef reg_ESP
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saved_ESP = ESP; |
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ESP = env->regs[R_ESP]; |
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#endif
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#ifdef reg_EBP
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saved_EBP = EBP; |
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EBP = env->regs[R_EBP]; |
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#endif
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#ifdef reg_ESI
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saved_ESI = ESI; |
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ESI = env->regs[R_ESI]; |
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#endif
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#ifdef reg_EDI
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saved_EDI = EDI; |
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EDI = env->regs[R_EDI]; |
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#endif
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/* put eflags in CPU temporary format */
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
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DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
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CC_OP = CC_OP_EFLAGS; |
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
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#elif defined(TARGET_ARM)
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{ |
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unsigned int psr; |
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psr = env->cpsr; |
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env->CF = (psr >> 29) & 1; |
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env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
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env->VF = (psr << 3) & 0x80000000; |
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env->cpsr = psr & ~0xf0000000;
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} |
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#elif defined(TARGET_SPARC)
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#elif defined(TARGET_PPC)
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#else
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#error unsupported target CPU
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#endif
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env->exception_index = -1;
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/* prepare setjmp context for exception handling */
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for(;;) {
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if (setjmp(env->jmp_env) == 0) { |
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env->current_tb = NULL;
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/* if an exception is pending, we execute it here */
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if (env->exception_index >= 0) { |
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if (env->exception_index >= EXCP_INTERRUPT) {
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/* exit request from the cpu execution loop */
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ret = env->exception_index; |
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break;
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} else if (env->user_mode_only) { |
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/* if user mode only, we simulate a fake exception
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which will be hanlded outside the cpu execution
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loop */
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#if defined(TARGET_I386)
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do_interrupt_user(env->exception_index, |
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env->exception_is_int, |
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env->error_code, |
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env->exception_next_eip); |
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#endif
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ret = env->exception_index; |
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break;
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} else {
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#if defined(TARGET_I386)
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/* simulate a real cpu exception. On i386, it can
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trigger new exceptions, but we do not handle
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double or triple faults yet. */
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do_interrupt(env->exception_index, |
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env->exception_is_int, |
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env->error_code, |
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env->exception_next_eip, 0);
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#elif defined(TARGET_PPC)
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do_interrupt(env); |
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#endif
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} |
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env->exception_index = -1;
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} |
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T0 = 0; /* force lookup of first TB */ |
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for(;;) {
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#ifdef __sparc__
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/* g1 can be modified by some libc? functions */
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tmp_T0 = T0; |
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#endif
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interrupt_request = env->interrupt_request; |
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if (__builtin_expect(interrupt_request, 0)) { |
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#if defined(TARGET_I386)
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/* if hardware interrupt pending, we execute it */
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if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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(env->eflags & IF_MASK) && |
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!(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
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int intno;
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env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
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intno = cpu_get_pic_interrupt(env); |
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
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} |
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do_interrupt(intno, 0, 0, 0, 1); |
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/* ensure that no TB jump will be modified as
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the program flow was changed */
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#ifdef __sparc__
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tmp_T0 = 0;
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#else
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T0 = 0;
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#endif
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} |
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#elif defined(TARGET_PPC)
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#if 0
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if ((interrupt_request & CPU_INTERRUPT_RESET)) {
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cpu_ppc_reset(env);
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}
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#endif
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if (msr_ee != 0) { |
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if ((interrupt_request & CPU_INTERRUPT_HARD)) {
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/* Raise it */
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env->exception_index = EXCP_EXTERNAL; |
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env->error_code = 0;
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do_interrupt(env); |
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env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
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} else if ((interrupt_request & CPU_INTERRUPT_TIMER)) { |
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/* Raise it */
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env->exception_index = EXCP_DECR; |
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env->error_code = 0;
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do_interrupt(env); |
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env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
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} |
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} |
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#endif
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if (interrupt_request & CPU_INTERRUPT_EXITTB) {
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env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
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/* ensure that no TB jump will be modified as
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the program flow was changed */
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#ifdef __sparc__
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tmp_T0 = 0;
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#else
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T0 = 0;
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#endif
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} |
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if (interrupt_request & CPU_INTERRUPT_EXIT) {
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env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
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env->exception_index = EXCP_INTERRUPT; |
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cpu_loop_exit(); |
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} |
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} |
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#ifdef DEBUG_EXEC
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if (loglevel & CPU_LOG_EXEC) {
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#if defined(TARGET_I386)
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/* restore flags in standard format */
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env->regs[R_EAX] = EAX; |
286 |
env->regs[R_EBX] = EBX; |
287 |
env->regs[R_ECX] = ECX; |
288 |
env->regs[R_EDX] = EDX; |
289 |
env->regs[R_ESI] = ESI; |
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env->regs[R_EDI] = EDI; |
291 |
env->regs[R_EBP] = EBP; |
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env->regs[R_ESP] = ESP; |
293 |
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
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cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP); |
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
296 |
#elif defined(TARGET_ARM)
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env->cpsr = compute_cpsr(); |
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cpu_arm_dump_state(env, logfile, 0);
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env->cpsr &= ~0xf0000000;
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#elif defined(TARGET_SPARC)
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cpu_sparc_dump_state (env, logfile, 0);
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#elif defined(TARGET_PPC)
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cpu_ppc_dump_state(env, logfile, 0);
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#else
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#error unsupported target CPU
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#endif
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} |
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#endif
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/* we record a subset of the CPU state. It will
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always be the same before a given translated block
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is executed. */
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#if defined(TARGET_I386)
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flags = env->hflags; |
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flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
315 |
cs_base = env->segs[R_CS].base; |
316 |
pc = cs_base + env->eip; |
317 |
#elif defined(TARGET_ARM)
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flags = 0;
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cs_base = 0;
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pc = (uint8_t *)env->regs[15];
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#elif defined(TARGET_SPARC)
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flags = 0;
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cs_base = (uint8_t *)env->npc; |
324 |
pc = (uint8_t *) env->pc; |
325 |
#elif defined(TARGET_PPC)
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flags = 0;
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cs_base = 0;
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pc = (uint8_t *)env->nip; |
329 |
#else
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#error unsupported CPU
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#endif
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tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, |
333 |
flags); |
334 |
if (!tb) {
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TranslationBlock **ptb1; |
336 |
unsigned int h; |
337 |
target_ulong phys_pc, phys_page1, phys_page2, virt_page2; |
338 |
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339 |
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spin_lock(&tb_lock); |
341 |
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342 |
tb_invalidated_flag = 0;
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343 |
|
344 |
/* find translated block using physical mappings */
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phys_pc = get_phys_addr_code(env, (unsigned long)pc); |
346 |
phys_page1 = phys_pc & TARGET_PAGE_MASK; |
347 |
phys_page2 = -1;
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348 |
h = tb_phys_hash_func(phys_pc); |
349 |
ptb1 = &tb_phys_hash[h]; |
350 |
for(;;) {
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tb = *ptb1; |
352 |
if (!tb)
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goto not_found;
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354 |
if (tb->pc == (unsigned long)pc && |
355 |
tb->page_addr[0] == phys_page1 &&
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356 |
tb->cs_base == (unsigned long)cs_base && |
357 |
tb->flags == flags) { |
358 |
/* check next page if needed */
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359 |
if (tb->page_addr[1] != -1) { |
360 |
virt_page2 = ((unsigned long)pc & TARGET_PAGE_MASK) + |
361 |
TARGET_PAGE_SIZE; |
362 |
phys_page2 = get_phys_addr_code(env, virt_page2); |
363 |
if (tb->page_addr[1] == phys_page2) |
364 |
goto found;
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} else {
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goto found;
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367 |
} |
368 |
} |
369 |
ptb1 = &tb->phys_hash_next; |
370 |
} |
371 |
not_found:
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372 |
/* if no translated code available, then translate it now */
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tb = tb_alloc((unsigned long)pc); |
374 |
if (!tb) {
|
375 |
/* flush must be done */
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376 |
tb_flush(env); |
377 |
/* cannot fail at this point */
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378 |
tb = tb_alloc((unsigned long)pc); |
379 |
/* don't forget to invalidate previous TB info */
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380 |
ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; |
381 |
T0 = 0;
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382 |
} |
383 |
tc_ptr = code_gen_ptr; |
384 |
tb->tc_ptr = tc_ptr; |
385 |
tb->cs_base = (unsigned long)cs_base; |
386 |
tb->flags = flags; |
387 |
cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
388 |
code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
389 |
|
390 |
/* check next page if needed */
|
391 |
virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK; |
392 |
phys_page2 = -1;
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393 |
if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) { |
394 |
phys_page2 = get_phys_addr_code(env, virt_page2); |
395 |
} |
396 |
tb_link_phys(tb, phys_pc, phys_page2); |
397 |
|
398 |
found:
|
399 |
if (tb_invalidated_flag) {
|
400 |
/* as some TB could have been invalidated because
|
401 |
of memory exceptions while generating the code, we
|
402 |
must recompute the hash index here */
|
403 |
ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; |
404 |
while (*ptb != NULL) |
405 |
ptb = &(*ptb)->hash_next; |
406 |
T0 = 0;
|
407 |
} |
408 |
/* we add the TB in the virtual pc hash table */
|
409 |
*ptb = tb; |
410 |
tb->hash_next = NULL;
|
411 |
tb_link(tb); |
412 |
spin_unlock(&tb_lock); |
413 |
} |
414 |
#ifdef DEBUG_EXEC
|
415 |
if (loglevel & CPU_LOG_EXEC) {
|
416 |
fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
|
417 |
(long)tb->tc_ptr, (long)tb->pc, |
418 |
lookup_symbol((void *)tb->pc));
|
419 |
} |
420 |
#endif
|
421 |
#ifdef __sparc__
|
422 |
T0 = tmp_T0; |
423 |
#endif
|
424 |
/* see if we can patch the calling TB. */
|
425 |
if (T0 != 0 |
426 |
#if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
427 |
&& (tb->cflags & CF_CODE_COPY) == |
428 |
(((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
|
429 |
#endif
|
430 |
) { |
431 |
spin_lock(&tb_lock); |
432 |
tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb); |
433 |
#if defined(USE_CODE_COPY)
|
434 |
/* propagates the FP use info */
|
435 |
((TranslationBlock *)(T0 & ~3))->cflags |=
|
436 |
(tb->cflags & CF_FP_USED); |
437 |
#endif
|
438 |
spin_unlock(&tb_lock); |
439 |
} |
440 |
tc_ptr = tb->tc_ptr; |
441 |
env->current_tb = tb; |
442 |
/* execute the generated code */
|
443 |
gen_func = (void *)tc_ptr;
|
444 |
#if defined(__sparc__)
|
445 |
__asm__ __volatile__("call %0\n\t"
|
446 |
"mov %%o7,%%i0"
|
447 |
: /* no outputs */
|
448 |
: "r" (gen_func)
|
449 |
: "i0", "i1", "i2", "i3", "i4", "i5"); |
450 |
#elif defined(__arm__)
|
451 |
asm volatile ("mov pc, %0\n\t" |
452 |
".global exec_loop\n\t"
|
453 |
"exec_loop:\n\t"
|
454 |
: /* no outputs */
|
455 |
: "r" (gen_func)
|
456 |
: "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
457 |
#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
|
458 |
{ |
459 |
if (!(tb->cflags & CF_CODE_COPY)) {
|
460 |
if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
|
461 |
save_native_fp_state(env); |
462 |
} |
463 |
gen_func(); |
464 |
} else {
|
465 |
if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
|
466 |
restore_native_fp_state(env); |
467 |
} |
468 |
/* we work with native eflags */
|
469 |
CC_SRC = cc_table[CC_OP].compute_all(); |
470 |
CC_OP = CC_OP_EFLAGS; |
471 |
asm(".globl exec_loop\n" |
472 |
"\n"
|
473 |
"debug1:\n"
|
474 |
" pushl %%ebp\n"
|
475 |
" fs movl %10, %9\n"
|
476 |
" fs movl %11, %%eax\n"
|
477 |
" andl $0x400, %%eax\n"
|
478 |
" fs orl %8, %%eax\n"
|
479 |
" pushl %%eax\n"
|
480 |
" popf\n"
|
481 |
" fs movl %%esp, %12\n"
|
482 |
" fs movl %0, %%eax\n"
|
483 |
" fs movl %1, %%ecx\n"
|
484 |
" fs movl %2, %%edx\n"
|
485 |
" fs movl %3, %%ebx\n"
|
486 |
" fs movl %4, %%esp\n"
|
487 |
" fs movl %5, %%ebp\n"
|
488 |
" fs movl %6, %%esi\n"
|
489 |
" fs movl %7, %%edi\n"
|
490 |
" fs jmp *%9\n"
|
491 |
"exec_loop:\n"
|
492 |
" fs movl %%esp, %4\n"
|
493 |
" fs movl %12, %%esp\n"
|
494 |
" fs movl %%eax, %0\n"
|
495 |
" fs movl %%ecx, %1\n"
|
496 |
" fs movl %%edx, %2\n"
|
497 |
" fs movl %%ebx, %3\n"
|
498 |
" fs movl %%ebp, %5\n"
|
499 |
" fs movl %%esi, %6\n"
|
500 |
" fs movl %%edi, %7\n"
|
501 |
" pushf\n"
|
502 |
" popl %%eax\n"
|
503 |
" movl %%eax, %%ecx\n"
|
504 |
" andl $0x400, %%ecx\n"
|
505 |
" shrl $9, %%ecx\n"
|
506 |
" andl $0x8d5, %%eax\n"
|
507 |
" fs movl %%eax, %8\n"
|
508 |
" movl $1, %%eax\n"
|
509 |
" subl %%ecx, %%eax\n"
|
510 |
" fs movl %%eax, %11\n"
|
511 |
" fs movl %9, %%ebx\n" /* get T0 value */ |
512 |
" popl %%ebp\n"
|
513 |
: |
514 |
: "m" (*(uint8_t *)offsetof(CPUState, regs[0])), |
515 |
"m" (*(uint8_t *)offsetof(CPUState, regs[1])), |
516 |
"m" (*(uint8_t *)offsetof(CPUState, regs[2])), |
517 |
"m" (*(uint8_t *)offsetof(CPUState, regs[3])), |
518 |
"m" (*(uint8_t *)offsetof(CPUState, regs[4])), |
519 |
"m" (*(uint8_t *)offsetof(CPUState, regs[5])), |
520 |
"m" (*(uint8_t *)offsetof(CPUState, regs[6])), |
521 |
"m" (*(uint8_t *)offsetof(CPUState, regs[7])), |
522 |
"m" (*(uint8_t *)offsetof(CPUState, cc_src)),
|
523 |
"m" (*(uint8_t *)offsetof(CPUState, tmp0)),
|
524 |
"a" (gen_func),
|
525 |
"m" (*(uint8_t *)offsetof(CPUState, df)),
|
526 |
"m" (*(uint8_t *)offsetof(CPUState, saved_esp))
|
527 |
: "%ecx", "%edx" |
528 |
); |
529 |
} |
530 |
} |
531 |
#else
|
532 |
gen_func(); |
533 |
#endif
|
534 |
env->current_tb = NULL;
|
535 |
/* reset soft MMU for next block (it can currently
|
536 |
only be set by a memory fault) */
|
537 |
#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
|
538 |
if (env->hflags & HF_SOFTMMU_MASK) {
|
539 |
env->hflags &= ~HF_SOFTMMU_MASK; |
540 |
/* do not allow linking to another block */
|
541 |
T0 = 0;
|
542 |
} |
543 |
#endif
|
544 |
} |
545 |
} else {
|
546 |
} |
547 |
} /* for(;;) */
|
548 |
|
549 |
|
550 |
#if defined(TARGET_I386)
|
551 |
#if defined(USE_CODE_COPY)
|
552 |
if (env->native_fp_regs) {
|
553 |
save_native_fp_state(env); |
554 |
} |
555 |
#endif
|
556 |
/* restore flags in standard format */
|
557 |
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
558 |
|
559 |
/* restore global registers */
|
560 |
#ifdef reg_EAX
|
561 |
EAX = saved_EAX; |
562 |
#endif
|
563 |
#ifdef reg_ECX
|
564 |
ECX = saved_ECX; |
565 |
#endif
|
566 |
#ifdef reg_EDX
|
567 |
EDX = saved_EDX; |
568 |
#endif
|
569 |
#ifdef reg_EBX
|
570 |
EBX = saved_EBX; |
571 |
#endif
|
572 |
#ifdef reg_ESP
|
573 |
ESP = saved_ESP; |
574 |
#endif
|
575 |
#ifdef reg_EBP
|
576 |
EBP = saved_EBP; |
577 |
#endif
|
578 |
#ifdef reg_ESI
|
579 |
ESI = saved_ESI; |
580 |
#endif
|
581 |
#ifdef reg_EDI
|
582 |
EDI = saved_EDI; |
583 |
#endif
|
584 |
#elif defined(TARGET_ARM)
|
585 |
env->cpsr = compute_cpsr(); |
586 |
#elif defined(TARGET_SPARC)
|
587 |
#elif defined(TARGET_PPC)
|
588 |
#else
|
589 |
#error unsupported target CPU
|
590 |
#endif
|
591 |
#ifdef __sparc__
|
592 |
asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
593 |
#endif
|
594 |
T0 = saved_T0; |
595 |
T1 = saved_T1; |
596 |
T2 = saved_T2; |
597 |
env = saved_env; |
598 |
return ret;
|
599 |
} |
600 |
|
601 |
/* must only be called from the generated code as an exception can be
|
602 |
generated */
|
603 |
void tb_invalidate_page_range(target_ulong start, target_ulong end)
|
604 |
{ |
605 |
/* XXX: cannot enable it yet because it yields to MMU exception
|
606 |
where NIP != read address on PowerPC */
|
607 |
#if 0
|
608 |
target_ulong phys_addr;
|
609 |
phys_addr = get_phys_addr_code(env, start);
|
610 |
tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
|
611 |
#endif
|
612 |
} |
613 |
|
614 |
#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
|
615 |
|
616 |
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
617 |
{ |
618 |
CPUX86State *saved_env; |
619 |
|
620 |
saved_env = env; |
621 |
env = s; |
622 |
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
623 |
selector &= 0xffff;
|
624 |
cpu_x86_load_seg_cache(env, seg_reg, selector, |
625 |
(uint8_t *)(selector << 4), 0xffff, 0); |
626 |
} else {
|
627 |
load_seg(seg_reg, selector); |
628 |
} |
629 |
env = saved_env; |
630 |
} |
631 |
|
632 |
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
633 |
{ |
634 |
CPUX86State *saved_env; |
635 |
|
636 |
saved_env = env; |
637 |
env = s; |
638 |
|
639 |
helper_fsave(ptr, data32); |
640 |
|
641 |
env = saved_env; |
642 |
} |
643 |
|
644 |
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
645 |
{ |
646 |
CPUX86State *saved_env; |
647 |
|
648 |
saved_env = env; |
649 |
env = s; |
650 |
|
651 |
helper_frstor(ptr, data32); |
652 |
|
653 |
env = saved_env; |
654 |
} |
655 |
|
656 |
#endif /* TARGET_I386 */ |
657 |
|
658 |
#if !defined(CONFIG_SOFTMMU)
|
659 |
|
660 |
#if defined(TARGET_I386)
|
661 |
|
662 |
/* 'pc' is the host PC at which the exception was raised. 'address' is
|
663 |
the effective address of the memory exception. 'is_write' is 1 if a
|
664 |
write caused the exception and otherwise 0'. 'old_set' is the
|
665 |
signal set which should be restored */
|
666 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
667 |
int is_write, sigset_t *old_set,
|
668 |
void *puc)
|
669 |
{ |
670 |
TranslationBlock *tb; |
671 |
int ret;
|
672 |
|
673 |
if (cpu_single_env)
|
674 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
675 |
#if defined(DEBUG_SIGNAL)
|
676 |
qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
677 |
pc, address, is_write, *(unsigned long *)old_set); |
678 |
#endif
|
679 |
/* XXX: locking issue */
|
680 |
if (is_write && page_unprotect(address, pc, puc)) {
|
681 |
return 1; |
682 |
} |
683 |
|
684 |
/* see if it is an MMU fault */
|
685 |
ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
686 |
((env->hflags & HF_CPL_MASK) == 3), 0); |
687 |
if (ret < 0) |
688 |
return 0; /* not an MMU fault */ |
689 |
if (ret == 0) |
690 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
691 |
/* now we have a real cpu fault */
|
692 |
tb = tb_find_pc(pc); |
693 |
if (tb) {
|
694 |
/* the PC is inside the translated code. It means that we have
|
695 |
a virtual CPU fault */
|
696 |
cpu_restore_state(tb, env, pc, puc); |
697 |
} |
698 |
if (ret == 1) { |
699 |
#if 0
|
700 |
printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
|
701 |
env->eip, env->cr[2], env->error_code);
|
702 |
#endif
|
703 |
/* we restore the process signal mask as the sigreturn should
|
704 |
do it (XXX: use sigsetjmp) */
|
705 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
706 |
raise_exception_err(EXCP0E_PAGE, env->error_code); |
707 |
} else {
|
708 |
/* activate soft MMU for this block */
|
709 |
env->hflags |= HF_SOFTMMU_MASK; |
710 |
cpu_resume_from_signal(env, puc); |
711 |
} |
712 |
/* never comes here */
|
713 |
return 1; |
714 |
} |
715 |
|
716 |
#elif defined(TARGET_ARM)
|
717 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
718 |
int is_write, sigset_t *old_set,
|
719 |
void *puc)
|
720 |
{ |
721 |
/* XXX: do more */
|
722 |
return 0; |
723 |
} |
724 |
#elif defined(TARGET_SPARC)
|
725 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
726 |
int is_write, sigset_t *old_set,
|
727 |
void *puc)
|
728 |
{ |
729 |
/* XXX: locking issue */
|
730 |
if (is_write && page_unprotect(address, pc, puc)) {
|
731 |
return 1; |
732 |
} |
733 |
return 0; |
734 |
} |
735 |
#elif defined (TARGET_PPC)
|
736 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
737 |
int is_write, sigset_t *old_set,
|
738 |
void *puc)
|
739 |
{ |
740 |
TranslationBlock *tb; |
741 |
int ret;
|
742 |
|
743 |
#if 1 |
744 |
if (cpu_single_env)
|
745 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
746 |
#endif
|
747 |
#if defined(DEBUG_SIGNAL)
|
748 |
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
749 |
pc, address, is_write, *(unsigned long *)old_set); |
750 |
#endif
|
751 |
/* XXX: locking issue */
|
752 |
if (is_write && page_unprotect(address, pc, puc)) {
|
753 |
return 1; |
754 |
} |
755 |
|
756 |
/* see if it is an MMU fault */
|
757 |
ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
|
758 |
if (ret < 0) |
759 |
return 0; /* not an MMU fault */ |
760 |
if (ret == 0) |
761 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
762 |
|
763 |
/* now we have a real cpu fault */
|
764 |
tb = tb_find_pc(pc); |
765 |
if (tb) {
|
766 |
/* the PC is inside the translated code. It means that we have
|
767 |
a virtual CPU fault */
|
768 |
cpu_restore_state(tb, env, pc, puc); |
769 |
} |
770 |
if (ret == 1) { |
771 |
#if 0
|
772 |
printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
773 |
env->nip, env->error_code, tb);
|
774 |
#endif
|
775 |
/* we restore the process signal mask as the sigreturn should
|
776 |
do it (XXX: use sigsetjmp) */
|
777 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
778 |
do_raise_exception_err(env->exception_index, env->error_code); |
779 |
} else {
|
780 |
/* activate soft MMU for this block */
|
781 |
cpu_resume_from_signal(env, puc); |
782 |
} |
783 |
/* never comes here */
|
784 |
return 1; |
785 |
} |
786 |
#else
|
787 |
#error unsupported target CPU
|
788 |
#endif
|
789 |
|
790 |
#if defined(__i386__)
|
791 |
|
792 |
#if defined(USE_CODE_COPY)
|
793 |
static void cpu_send_trap(unsigned long pc, int trap, |
794 |
struct ucontext *uc)
|
795 |
{ |
796 |
TranslationBlock *tb; |
797 |
|
798 |
if (cpu_single_env)
|
799 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
800 |
/* now we have a real cpu fault */
|
801 |
tb = tb_find_pc(pc); |
802 |
if (tb) {
|
803 |
/* the PC is inside the translated code. It means that we have
|
804 |
a virtual CPU fault */
|
805 |
cpu_restore_state(tb, env, pc, uc); |
806 |
} |
807 |
sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
|
808 |
raise_exception_err(trap, env->error_code); |
809 |
} |
810 |
#endif
|
811 |
|
812 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
813 |
void *puc)
|
814 |
{ |
815 |
struct ucontext *uc = puc;
|
816 |
unsigned long pc; |
817 |
int trapno;
|
818 |
|
819 |
#ifndef REG_EIP
|
820 |
/* for glibc 2.1 */
|
821 |
#define REG_EIP EIP
|
822 |
#define REG_ERR ERR
|
823 |
#define REG_TRAPNO TRAPNO
|
824 |
#endif
|
825 |
pc = uc->uc_mcontext.gregs[REG_EIP]; |
826 |
trapno = uc->uc_mcontext.gregs[REG_TRAPNO]; |
827 |
#if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
828 |
if (trapno == 0x00 || trapno == 0x05) { |
829 |
/* send division by zero or bound exception */
|
830 |
cpu_send_trap(pc, trapno, uc); |
831 |
return 1; |
832 |
} else
|
833 |
#endif
|
834 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
835 |
trapno == 0xe ?
|
836 |
(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
837 |
&uc->uc_sigmask, puc); |
838 |
} |
839 |
|
840 |
#elif defined(__x86_64__)
|
841 |
|
842 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
843 |
void *puc)
|
844 |
{ |
845 |
struct ucontext *uc = puc;
|
846 |
unsigned long pc; |
847 |
|
848 |
pc = uc->uc_mcontext.gregs[REG_RIP]; |
849 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
850 |
uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
|
851 |
(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
852 |
&uc->uc_sigmask, puc); |
853 |
} |
854 |
|
855 |
#elif defined(__powerpc__)
|
856 |
|
857 |
/***********************************************************************
|
858 |
* signal context platform-specific definitions
|
859 |
* From Wine
|
860 |
*/
|
861 |
#ifdef linux
|
862 |
/* All Registers access - only for local access */
|
863 |
# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
|
864 |
/* Gpr Registers access */
|
865 |
# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
|
866 |
# define IAR_sig(context) REG_sig(nip, context) /* Program counter */ |
867 |
# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ |
868 |
# define CTR_sig(context) REG_sig(ctr, context) /* Count register */ |
869 |
# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ |
870 |
# define LR_sig(context) REG_sig(link, context) /* Link register */ |
871 |
# define CR_sig(context) REG_sig(ccr, context) /* Condition register */ |
872 |
/* Float Registers access */
|
873 |
# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) |
874 |
# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) |
875 |
/* Exception Registers access */
|
876 |
# define DAR_sig(context) REG_sig(dar, context)
|
877 |
# define DSISR_sig(context) REG_sig(dsisr, context)
|
878 |
# define TRAP_sig(context) REG_sig(trap, context)
|
879 |
#endif /* linux */ |
880 |
|
881 |
#ifdef __APPLE__
|
882 |
# include <sys/ucontext.h> |
883 |
typedef struct ucontext SIGCONTEXT; |
884 |
/* All Registers access - only for local access */
|
885 |
# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
|
886 |
# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
|
887 |
# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
|
888 |
# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
|
889 |
/* Gpr Registers access */
|
890 |
# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
891 |
# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ |
892 |
# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ |
893 |
# define CTR_sig(context) REG_sig(ctr, context)
|
894 |
# define XER_sig(context) REG_sig(xer, context) /* Link register */ |
895 |
# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ |
896 |
# define CR_sig(context) REG_sig(cr, context) /* Condition register */ |
897 |
/* Float Registers access */
|
898 |
# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
|
899 |
# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) |
900 |
/* Exception Registers access */
|
901 |
# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ |
902 |
# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
|
903 |
# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ |
904 |
#endif /* __APPLE__ */ |
905 |
|
906 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
907 |
void *puc)
|
908 |
{ |
909 |
struct ucontext *uc = puc;
|
910 |
unsigned long pc; |
911 |
int is_write;
|
912 |
|
913 |
pc = IAR_sig(uc); |
914 |
is_write = 0;
|
915 |
#if 0
|
916 |
/* ppc 4xx case */
|
917 |
if (DSISR_sig(uc) & 0x00800000)
|
918 |
is_write = 1;
|
919 |
#else
|
920 |
if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
921 |
is_write = 1;
|
922 |
#endif
|
923 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
924 |
is_write, &uc->uc_sigmask, puc); |
925 |
} |
926 |
|
927 |
#elif defined(__alpha__)
|
928 |
|
929 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
930 |
void *puc)
|
931 |
{ |
932 |
struct ucontext *uc = puc;
|
933 |
uint32_t *pc = uc->uc_mcontext.sc_pc; |
934 |
uint32_t insn = *pc; |
935 |
int is_write = 0; |
936 |
|
937 |
/* XXX: need kernel patch to get write flag faster */
|
938 |
switch (insn >> 26) { |
939 |
case 0x0d: // stw |
940 |
case 0x0e: // stb |
941 |
case 0x0f: // stq_u |
942 |
case 0x24: // stf |
943 |
case 0x25: // stg |
944 |
case 0x26: // sts |
945 |
case 0x27: // stt |
946 |
case 0x2c: // stl |
947 |
case 0x2d: // stq |
948 |
case 0x2e: // stl_c |
949 |
case 0x2f: // stq_c |
950 |
is_write = 1;
|
951 |
} |
952 |
|
953 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
954 |
is_write, &uc->uc_sigmask, puc); |
955 |
} |
956 |
#elif defined(__sparc__)
|
957 |
|
958 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
959 |
void *puc)
|
960 |
{ |
961 |
uint32_t *regs = (uint32_t *)(info + 1);
|
962 |
void *sigmask = (regs + 20); |
963 |
unsigned long pc; |
964 |
int is_write;
|
965 |
uint32_t insn; |
966 |
|
967 |
/* XXX: is there a standard glibc define ? */
|
968 |
pc = regs[1];
|
969 |
/* XXX: need kernel patch to get write flag faster */
|
970 |
is_write = 0;
|
971 |
insn = *(uint32_t *)pc; |
972 |
if ((insn >> 30) == 3) { |
973 |
switch((insn >> 19) & 0x3f) { |
974 |
case 0x05: // stb |
975 |
case 0x06: // sth |
976 |
case 0x04: // st |
977 |
case 0x07: // std |
978 |
case 0x24: // stf |
979 |
case 0x27: // stdf |
980 |
case 0x25: // stfsr |
981 |
is_write = 1;
|
982 |
break;
|
983 |
} |
984 |
} |
985 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
986 |
is_write, sigmask, NULL);
|
987 |
} |
988 |
|
989 |
#elif defined(__arm__)
|
990 |
|
991 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
992 |
void *puc)
|
993 |
{ |
994 |
struct ucontext *uc = puc;
|
995 |
unsigned long pc; |
996 |
int is_write;
|
997 |
|
998 |
pc = uc->uc_mcontext.gregs[R15]; |
999 |
/* XXX: compute is_write */
|
1000 |
is_write = 0;
|
1001 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1002 |
is_write, |
1003 |
&uc->uc_sigmask); |
1004 |
} |
1005 |
|
1006 |
#elif defined(__mc68000)
|
1007 |
|
1008 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
1009 |
void *puc)
|
1010 |
{ |
1011 |
struct ucontext *uc = puc;
|
1012 |
unsigned long pc; |
1013 |
int is_write;
|
1014 |
|
1015 |
pc = uc->uc_mcontext.gregs[16];
|
1016 |
/* XXX: compute is_write */
|
1017 |
is_write = 0;
|
1018 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1019 |
is_write, |
1020 |
&uc->uc_sigmask, puc); |
1021 |
} |
1022 |
|
1023 |
#else
|
1024 |
|
1025 |
#error host CPU specific signal handler needed
|
1026 |
|
1027 |
#endif
|
1028 |
|
1029 |
#endif /* !defined(CONFIG_SOFTMMU) */ |