Archipelago » qemu

/*

 * TI OMAP processors emulation.

 *

 * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation; either version 2 or

 * (at your option) version 3 of the License.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License along

 * with this program; if not, see <http://www.gnu.org/licenses/>.

 */

#include "hw.h"

#include "arm-misc.h"

#include "omap.h"

#include "sysemu.h"

#include "qemu-timer.h"

#include "qemu-char.h"

#include "soc_dma.h"

/* We use pc-style serial ports.  */

#include "pc.h"

#include "blockdev.h"

#include "range.h"

/* Should signal the TCMI/GPMC */

uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)

{

    uint8_t ret;

    OMAP_8B_REG(addr);

    cpu_physical_memory_read(addr, (void *) &ret, 1);

    return ret;

}

void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    uint8_t val8 = value;

    OMAP_8B_REG(addr);

    cpu_physical_memory_write(addr, (void *) &val8, 1);

}

uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)

{

    uint16_t ret;

    OMAP_16B_REG(addr);

    cpu_physical_memory_read(addr, (void *) &ret, 2);

    return ret;

}

void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    uint16_t val16 = value;

    OMAP_16B_REG(addr);

    cpu_physical_memory_write(addr, (void *) &val16, 2);

}

uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)

{

    uint32_t ret;

    OMAP_32B_REG(addr);

    cpu_physical_memory_read(addr, (void *) &ret, 4);

    return ret;

}

void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    OMAP_32B_REG(addr);

    cpu_physical_memory_write(addr, (void *) &value, 4);

}

/* MPU OS timers */

struct omap_mpu_timer_s {

    qemu_irq irq;

    omap_clk clk;

    uint32_t val;

    int64_t time;

    QEMUTimer *timer;

    QEMUBH *tick;

    int64_t rate;

    int it_ena;

    int enable;

    int ptv;

    int ar;

    int st;

    uint32_t reset_val;

};

static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)

{

    uint64_t distance = qemu_get_clock_ns(vm_clock) - timer->time;

    if (timer->st && timer->enable && timer->rate)

        return timer->val - muldiv64(distance >> (timer->ptv + 1),

                                     timer->rate, get_ticks_per_sec());

    else

        return timer->val;

}

static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)

{

    timer->val = omap_timer_read(timer);

    timer->time = qemu_get_clock_ns(vm_clock);

}

static inline void omap_timer_update(struct omap_mpu_timer_s *timer)

{

    int64_t expires;

    if (timer->enable && timer->st && timer->rate) {

        timer->val = timer->reset_val;        /* Should skip this on clk enable */

        expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),

                           get_ticks_per_sec(), timer->rate);

        /* If timer expiry would be sooner than in about 1 ms and

         * auto-reload isn't set, then fire immediately.  This is a hack

         * to make systems like PalmOS run in acceptable time.  PalmOS

         * sets the interval to a very low value and polls the status bit

         * in a busy loop when it wants to sleep just a couple of CPU

         * ticks.  */

        if (expires > (get_ticks_per_sec() >> 10) || timer->ar)

            qemu_mod_timer(timer->timer, timer->time + expires);

        else

            qemu_bh_schedule(timer->tick);

    } else

        qemu_del_timer(timer->timer);

}

static void omap_timer_fire(void *opaque)

{

    struct omap_mpu_timer_s *timer = opaque;

    if (!timer->ar) {

        timer->val = 0;

        timer->st = 0;

    }

    if (timer->it_ena)

        /* Edge-triggered irq */

        qemu_irq_pulse(timer->irq);

}

static void omap_timer_tick(void *opaque)

{

    struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;

    omap_timer_sync(timer);

    omap_timer_fire(timer);

    omap_timer_update(timer);

}

static void omap_timer_clk_update(void *opaque, int line, int on)

{

    struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;

    omap_timer_sync(timer);

    timer->rate = on ? omap_clk_getrate(timer->clk) : 0;

    omap_timer_update(timer);

}

static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)

{

    omap_clk_adduser(timer->clk,

                    qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);

    timer->rate = omap_clk_getrate(timer->clk);

}

static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)

{

    struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;

    switch (addr) {

    case 0x00:        /* CNTL_TIMER */

        return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;

    case 0x04:        /* LOAD_TIM */

        break;

    case 0x08:        /* READ_TIM */

        return omap_timer_read(s);

    }

    OMAP_BAD_REG(addr);

    return 0;

}

static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;

    switch (addr) {

    case 0x00:        /* CNTL_TIMER */

        omap_timer_sync(s);

        s->enable = (value >> 5) & 1;

        s->ptv = (value >> 2) & 7;

        s->ar = (value >> 1) & 1;

        s->st = value & 1;

        omap_timer_update(s);

        return;

    case 0x04:        /* LOAD_TIM */

        s->reset_val = value;

        return;

    case 0x08:        /* READ_TIM */

        OMAP_RO_REG(addr);

        break;

    default:

        OMAP_BAD_REG(addr);

    }

}

static CPUReadMemoryFunc * const omap_mpu_timer_readfn[] = {

    omap_badwidth_read32,

    omap_badwidth_read32,

    omap_mpu_timer_read,

};

static CPUWriteMemoryFunc * const omap_mpu_timer_writefn[] = {

    omap_badwidth_write32,

    omap_badwidth_write32,

    omap_mpu_timer_write,

};

static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)

{

    qemu_del_timer(s->timer);

    s->enable = 0;

    s->reset_val = 31337;

    s->val = 0;

    s->ptv = 0;

    s->ar = 0;

    s->st = 0;

    s->it_ena = 1;

}

static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,

                qemu_irq irq, omap_clk clk)

{

    int iomemtype;

    struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)

            qemu_mallocz(sizeof(struct omap_mpu_timer_s));

    s->irq = irq;

    s->clk = clk;

    s->timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, s);

    s->tick = qemu_bh_new(omap_timer_fire, s);

    omap_mpu_timer_reset(s);

    omap_timer_clk_setup(s);

    iomemtype = cpu_register_io_memory(omap_mpu_timer_readfn,

                    omap_mpu_timer_writefn, s, DEVICE_NATIVE_ENDIAN);

    cpu_register_physical_memory(base, 0x100, iomemtype);

    return s;

}

/* Watchdog timer */

struct omap_watchdog_timer_s {

    struct omap_mpu_timer_s timer;

    uint8_t last_wr;

    int mode;

    int free;

    int reset;

};

static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)

{

    struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;

    switch (addr) {

    case 0x00:        /* CNTL_TIMER */

        return (s->timer.ptv << 9) | (s->timer.ar << 8) |

                (s->timer.st << 7) | (s->free << 1);

    case 0x04:        /* READ_TIMER */

        return omap_timer_read(&s->timer);

    case 0x08:        /* TIMER_MODE */

        return s->mode << 15;

    }

    OMAP_BAD_REG(addr);

    return 0;

}

static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;

    switch (addr) {

    case 0x00:        /* CNTL_TIMER */

        omap_timer_sync(&s->timer);

        s->timer.ptv = (value >> 9) & 7;

        s->timer.ar = (value >> 8) & 1;

        s->timer.st = (value >> 7) & 1;

        s->free = (value >> 1) & 1;

        omap_timer_update(&s->timer);

        break;

    case 0x04:        /* LOAD_TIMER */

        s->timer.reset_val = value & 0xffff;

        break;

    case 0x08:        /* TIMER_MODE */

        if (!s->mode && ((value >> 15) & 1))

            omap_clk_get(s->timer.clk);

        s->mode |= (value >> 15) & 1;

        if (s->last_wr == 0xf5) {

            if ((value & 0xff) == 0xa0) {

                if (s->mode) {

                    s->mode = 0;

                    omap_clk_put(s->timer.clk);

                }

            } else {

                /* XXX: on T|E hardware somehow this has no effect,

                 * on Zire 71 it works as specified.  */

                s->reset = 1;

                qemu_system_reset_request();

            }

        }

        s->last_wr = value & 0xff;

        break;

    default:

        OMAP_BAD_REG(addr);

    }

}

static CPUReadMemoryFunc * const omap_wd_timer_readfn[] = {

    omap_badwidth_read16,

    omap_wd_timer_read,

    omap_badwidth_read16,

};

static CPUWriteMemoryFunc * const omap_wd_timer_writefn[] = {

    omap_badwidth_write16,

    omap_wd_timer_write,

    omap_badwidth_write16,

};

static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)

{

    qemu_del_timer(s->timer.timer);

    if (!s->mode)

        omap_clk_get(s->timer.clk);

    s->mode = 1;

    s->free = 1;

    s->reset = 0;

    s->timer.enable = 1;

    s->timer.it_ena = 1;

    s->timer.reset_val = 0xffff;

    s->timer.val = 0;

    s->timer.st = 0;

    s->timer.ptv = 0;

    s->timer.ar = 0;

    omap_timer_update(&s->timer);

}

static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,

                qemu_irq irq, omap_clk clk)

{

    int iomemtype;

    struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)

            qemu_mallocz(sizeof(struct omap_watchdog_timer_s));

    s->timer.irq = irq;

    s->timer.clk = clk;

    s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);

    omap_wd_timer_reset(s);

    omap_timer_clk_setup(&s->timer);

    iomemtype = cpu_register_io_memory(omap_wd_timer_readfn,

                    omap_wd_timer_writefn, s, DEVICE_NATIVE_ENDIAN);

    cpu_register_physical_memory(base, 0x100, iomemtype);

    return s;

}

/* 32-kHz timer */

struct omap_32khz_timer_s {

    struct omap_mpu_timer_s timer;

};

static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)

{

    struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;

    switch (offset) {

    case 0x00:        /* TVR */

        return s->timer.reset_val;

    case 0x04:        /* TCR */

        return omap_timer_read(&s->timer);

    case 0x08:        /* CR */

        return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;

    default:

        break;

    }

    OMAP_BAD_REG(addr);

    return 0;

}

static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;

    switch (offset) {

    case 0x00:        /* TVR */

        s->timer.reset_val = value & 0x00ffffff;

        break;

    case 0x04:        /* TCR */

        OMAP_RO_REG(addr);

        break;

    case 0x08:        /* CR */

        s->timer.ar = (value >> 3) & 1;

        s->timer.it_ena = (value >> 2) & 1;

        if (s->timer.st != (value & 1) || (value & 2)) {

            omap_timer_sync(&s->timer);

            s->timer.enable = value & 1;

            s->timer.st = value & 1;

            omap_timer_update(&s->timer);

        }

        break;

    default:

        OMAP_BAD_REG(addr);

    }

}

static CPUReadMemoryFunc * const omap_os_timer_readfn[] = {

    omap_badwidth_read32,

    omap_badwidth_read32,

    omap_os_timer_read,

};

static CPUWriteMemoryFunc * const omap_os_timer_writefn[] = {

    omap_badwidth_write32,

    omap_badwidth_write32,

    omap_os_timer_write,

};

static void omap_os_timer_reset(struct omap_32khz_timer_s *s)

{

    qemu_del_timer(s->timer.timer);

    s->timer.enable = 0;

    s->timer.it_ena = 0;

    s->timer.reset_val = 0x00ffffff;

    s->timer.val = 0;

    s->timer.st = 0;

    s->timer.ptv = 0;

    s->timer.ar = 1;

}

static struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,

                qemu_irq irq, omap_clk clk)

{

    int iomemtype;

    struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)

            qemu_mallocz(sizeof(struct omap_32khz_timer_s));

    s->timer.irq = irq;

    s->timer.clk = clk;

    s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);

    omap_os_timer_reset(s);

    omap_timer_clk_setup(&s->timer);

    iomemtype = cpu_register_io_memory(omap_os_timer_readfn,

                    omap_os_timer_writefn, s, DEVICE_NATIVE_ENDIAN);

    cpu_register_physical_memory(base, 0x800, iomemtype);

    return s;

}

/* Ultra Low-Power Device Module */

static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    uint16_t ret;

    switch (addr) {

    case 0x14:        /* IT_STATUS */

        ret = s->ulpd_pm_regs[addr >> 2];

        s->ulpd_pm_regs[addr >> 2] = 0;

        qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);

        return ret;

    case 0x18:        /* Reserved */

    case 0x1c:        /* Reserved */

    case 0x20:        /* Reserved */

    case 0x28:        /* Reserved */

    case 0x2c:        /* Reserved */

        OMAP_BAD_REG(addr);

    case 0x00:        /* COUNTER_32_LSB */

    case 0x04:        /* COUNTER_32_MSB */

    case 0x08:        /* COUNTER_HIGH_FREQ_LSB */

    case 0x0c:        /* COUNTER_HIGH_FREQ_MSB */

    case 0x10:        /* GAUGING_CTRL */

    case 0x24:        /* SETUP_ANALOG_CELL3_ULPD1 */

    case 0x30:        /* CLOCK_CTRL */

    case 0x34:        /* SOFT_REQ */

    case 0x38:        /* COUNTER_32_FIQ */

    case 0x3c:        /* DPLL_CTRL */

    case 0x40:        /* STATUS_REQ */

        /* XXX: check clk::usecount state for every clock */

    case 0x48:        /* LOCL_TIME */

    case 0x4c:        /* APLL_CTRL */

    case 0x50:        /* POWER_CTRL */

        return s->ulpd_pm_regs[addr >> 2];

    }

    OMAP_BAD_REG(addr);

    return 0;

}

static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,

                uint16_t diff, uint16_t value)

{

    if (diff & (1 << 4))                                /* USB_MCLK_EN */

        omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);

    if (diff & (1 << 5))                                /* DIS_USB_PVCI_CLK */

        omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);

}

static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,

                uint16_t diff, uint16_t value)

{

    if (diff & (1 << 0))                                /* SOFT_DPLL_REQ */

        omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);

    if (diff & (1 << 1))                                /* SOFT_COM_REQ */

        omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);

    if (diff & (1 << 2))                                /* SOFT_SDW_REQ */

        omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);

    if (diff & (1 << 3))                                /* SOFT_USB_REQ */

        omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);

}

static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    int64_t now, ticks;

    int div, mult;

    static const int bypass_div[4] = { 1, 2, 4, 4 };

    uint16_t diff;

    switch (addr) {

    case 0x00:        /* COUNTER_32_LSB */

    case 0x04:        /* COUNTER_32_MSB */

    case 0x08:        /* COUNTER_HIGH_FREQ_LSB */

    case 0x0c:        /* COUNTER_HIGH_FREQ_MSB */

    case 0x14:        /* IT_STATUS */

    case 0x40:        /* STATUS_REQ */

        OMAP_RO_REG(addr);

        break;

    case 0x10:        /* GAUGING_CTRL */

        /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */

        if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {

            now = qemu_get_clock_ns(vm_clock);

            if (value & 1)

                s->ulpd_gauge_start = now;

            else {

                now -= s->ulpd_gauge_start;

                /* 32-kHz ticks */

                ticks = muldiv64(now, 32768, get_ticks_per_sec());

                s->ulpd_pm_regs[0x00 >> 2] = (ticks >>  0) & 0xffff;

                s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;

                if (ticks >> 32)        /* OVERFLOW_32K */

                    s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;

                /* High frequency ticks */

                ticks = muldiv64(now, 12000000, get_ticks_per_sec());

                s->ulpd_pm_regs[0x08 >> 2] = (ticks >>  0) & 0xffff;

                s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;

                if (ticks >> 32)        /* OVERFLOW_HI_FREQ */

                    s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;

                s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0;        /* IT_GAUGING */

                qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);

            }

        }

        s->ulpd_pm_regs[addr >> 2] = value;

        break;

    case 0x18:        /* Reserved */

    case 0x1c:        /* Reserved */

    case 0x20:        /* Reserved */

    case 0x28:        /* Reserved */

    case 0x2c:        /* Reserved */

        OMAP_BAD_REG(addr);

    case 0x24:        /* SETUP_ANALOG_CELL3_ULPD1 */

    case 0x38:        /* COUNTER_32_FIQ */

    case 0x48:        /* LOCL_TIME */

    case 0x50:        /* POWER_CTRL */

        s->ulpd_pm_regs[addr >> 2] = value;

        break;

    case 0x30:        /* CLOCK_CTRL */

        diff = s->ulpd_pm_regs[addr >> 2] ^ value;

        s->ulpd_pm_regs[addr >> 2] = value & 0x3f;

        omap_ulpd_clk_update(s, diff, value);

        break;

    case 0x34:        /* SOFT_REQ */

        diff = s->ulpd_pm_regs[addr >> 2] ^ value;

        s->ulpd_pm_regs[addr >> 2] = value & 0x1f;

        omap_ulpd_req_update(s, diff, value);

        break;

    case 0x3c:        /* DPLL_CTRL */

        /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is

         * omitted altogether, probably a typo.  */

        /* This register has identical semantics with DPLL(1:3) control

         * registers, see omap_dpll_write() */

        diff = s->ulpd_pm_regs[addr >> 2] & value;

        s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;

        if (diff & (0x3ff << 2)) {

            if (value & (1 << 4)) {                        /* PLL_ENABLE */

                div = ((value >> 5) & 3) + 1;                /* PLL_DIV */

                mult = MIN((value >> 7) & 0x1f, 1);        /* PLL_MULT */

            } else {

                div = bypass_div[((value >> 2) & 3)];        /* BYPASS_DIV */

                mult = 1;

            }

            omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);

        }

        /* Enter the desired mode.  */

        s->ulpd_pm_regs[addr >> 2] =

                (s->ulpd_pm_regs[addr >> 2] & 0xfffe) |

                ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);

        /* Act as if the lock is restored.  */

        s->ulpd_pm_regs[addr >> 2] |= 2;

        break;

    case 0x4c:        /* APLL_CTRL */

        diff = s->ulpd_pm_regs[addr >> 2] & value;

        s->ulpd_pm_regs[addr >> 2] = value & 0xf;

        if (diff & (1 << 0))                                /* APLL_NDPLL_SWITCH */

            omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,

                                    (value & (1 << 0)) ? "apll" : "dpll4"));

        break;

    default:

        OMAP_BAD_REG(addr);

    }

}

static CPUReadMemoryFunc * const omap_ulpd_pm_readfn[] = {

    omap_badwidth_read16,

    omap_ulpd_pm_read,

    omap_badwidth_read16,

};

static CPUWriteMemoryFunc * const omap_ulpd_pm_writefn[] = {

    omap_badwidth_write16,

    omap_ulpd_pm_write,

    omap_badwidth_write16,

};

static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)

{

    mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;

    mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;

    mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;

    mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;

    mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;

    mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;

    mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;

    mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;

    mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;

    mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;

    mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;

    omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);

    mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;

    omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);

    mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;

    mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;

    mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;

    mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */

    mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;

    mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;

    mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;

    omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);

    omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));

}

static void omap_ulpd_pm_init(target_phys_addr_t base,

                struct omap_mpu_state_s *mpu)

{

    int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn,

                    omap_ulpd_pm_writefn, mpu, DEVICE_NATIVE_ENDIAN);

    cpu_register_physical_memory(base, 0x800, iomemtype);

    omap_ulpd_pm_reset(mpu);

}

/* OMAP Pin Configuration */

static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    switch (addr) {

    case 0x00:        /* FUNC_MUX_CTRL_0 */

    case 0x04:        /* FUNC_MUX_CTRL_1 */

    case 0x08:        /* FUNC_MUX_CTRL_2 */

        return s->func_mux_ctrl[addr >> 2];

    case 0x0c:        /* COMP_MODE_CTRL_0 */

        return s->comp_mode_ctrl[0];

    case 0x10:        /* FUNC_MUX_CTRL_3 */

    case 0x14:        /* FUNC_MUX_CTRL_4 */

    case 0x18:        /* FUNC_MUX_CTRL_5 */

    case 0x1c:        /* FUNC_MUX_CTRL_6 */

    case 0x20:        /* FUNC_MUX_CTRL_7 */

    case 0x24:        /* FUNC_MUX_CTRL_8 */

    case 0x28:        /* FUNC_MUX_CTRL_9 */

    case 0x2c:        /* FUNC_MUX_CTRL_A */

    case 0x30:        /* FUNC_MUX_CTRL_B */

    case 0x34:        /* FUNC_MUX_CTRL_C */

    case 0x38:        /* FUNC_MUX_CTRL_D */

        return s->func_mux_ctrl[(addr >> 2) - 1];

    case 0x40:        /* PULL_DWN_CTRL_0 */

    case 0x44:        /* PULL_DWN_CTRL_1 */

    case 0x48:        /* PULL_DWN_CTRL_2 */

    case 0x4c:        /* PULL_DWN_CTRL_3 */

        return s->pull_dwn_ctrl[(addr & 0xf) >> 2];

    case 0x50:        /* GATE_INH_CTRL_0 */

        return s->gate_inh_ctrl[0];

    case 0x60:        /* VOLTAGE_CTRL_0 */

        return s->voltage_ctrl[0];

    case 0x70:        /* TEST_DBG_CTRL_0 */

        return s->test_dbg_ctrl[0];

    case 0x80:        /* MOD_CONF_CTRL_0 */

        return s->mod_conf_ctrl[0];

    }

    OMAP_BAD_REG(addr);

    return 0;

}

static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,

                uint32_t diff, uint32_t value)

{

    if (s->compat1509) {

        if (diff & (1 << 9))                        /* BLUETOOTH */

            omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),

                            (~value >> 9) & 1);

        if (diff & (1 << 7))                        /* USB.CLKO */

            omap_clk_onoff(omap_findclk(s, "usb.clko"),

                            (value >> 7) & 1);

    }

}

static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,

                uint32_t diff, uint32_t value)

{

    if (s->compat1509) {

        if (diff & (1 << 31))                        /* MCBSP3_CLK_HIZ_DI */

            omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),

                            (value >> 31) & 1);

        if (diff & (1 << 1))                        /* CLK32K */

            omap_clk_onoff(omap_findclk(s, "clk32k_out"),

                            (~value >> 1) & 1);

    }

}

static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,

                uint32_t diff, uint32_t value)

{

    if (diff & (1 << 31))                        /* CONF_MOD_UART3_CLK_MODE_R */

         omap_clk_reparent(omap_findclk(s, "uart3_ck"),

                         omap_findclk(s, ((value >> 31) & 1) ?

                                 "ck_48m" : "armper_ck"));

    if (diff & (1 << 30))                        /* CONF_MOD_UART2_CLK_MODE_R */

         omap_clk_reparent(omap_findclk(s, "uart2_ck"),

                         omap_findclk(s, ((value >> 30) & 1) ?

                                 "ck_48m" : "armper_ck"));

    if (diff & (1 << 29))                        /* CONF_MOD_UART1_CLK_MODE_R */

         omap_clk_reparent(omap_findclk(s, "uart1_ck"),

                         omap_findclk(s, ((value >> 29) & 1) ?

                                 "ck_48m" : "armper_ck"));

    if (diff & (1 << 23))                        /* CONF_MOD_MMC_SD_CLK_REQ_R */

         omap_clk_reparent(omap_findclk(s, "mmc_ck"),

                         omap_findclk(s, ((value >> 23) & 1) ?

                                 "ck_48m" : "armper_ck"));

    if (diff & (1 << 12))                        /* CONF_MOD_COM_MCLK_12_48_S */

         omap_clk_reparent(omap_findclk(s, "com_mclk_out"),

                         omap_findclk(s, ((value >> 12) & 1) ?

                                 "ck_48m" : "armper_ck"));

    if (diff & (1 << 9))                        /* CONF_MOD_USB_HOST_HHC_UHO */

         omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);

}

static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    uint32_t diff;

    switch (addr) {

    case 0x00:        /* FUNC_MUX_CTRL_0 */

        diff = s->func_mux_ctrl[addr >> 2] ^ value;

        s->func_mux_ctrl[addr >> 2] = value;

        omap_pin_funcmux0_update(s, diff, value);

        return;

    case 0x04:        /* FUNC_MUX_CTRL_1 */

        diff = s->func_mux_ctrl[addr >> 2] ^ value;

        s->func_mux_ctrl[addr >> 2] = value;

        omap_pin_funcmux1_update(s, diff, value);

        return;

    case 0x08:        /* FUNC_MUX_CTRL_2 */

        s->func_mux_ctrl[addr >> 2] = value;

        return;

    case 0x0c:        /* COMP_MODE_CTRL_0 */

        s->comp_mode_ctrl[0] = value;

        s->compat1509 = (value != 0x0000eaef);

        omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);