root / hw / smc91c111.c @ 3e1c0c9a
History | View | Annotate | Download (21.7 kB)
1 | 5fafdf24 | ths | /*
|
---|---|---|---|
2 | 80337b66 | bellard | * SMSC 91C111 Ethernet interface emulation
|
3 | 80337b66 | bellard | *
|
4 | 80337b66 | bellard | * Copyright (c) 2005 CodeSourcery, LLC.
|
5 | 80337b66 | bellard | * Written by Paul Brook
|
6 | 80337b66 | bellard | *
|
7 | 80337b66 | bellard | * This code is licenced under the GPL
|
8 | 80337b66 | bellard | */
|
9 | 80337b66 | bellard | |
10 | 418dcf5b | Paul Brook | #include "sysbus.h" |
11 | 87ecb68b | pbrook | #include "net.h" |
12 | 87ecb68b | pbrook | #include "devices.h" |
13 | 80337b66 | bellard | /* For crc32 */
|
14 | 80337b66 | bellard | #include <zlib.h> |
15 | 80337b66 | bellard | |
16 | 80337b66 | bellard | /* Number of 2k memory pages available. */
|
17 | 80337b66 | bellard | #define NUM_PACKETS 4 |
18 | 80337b66 | bellard | |
19 | 80337b66 | bellard | typedef struct { |
20 | 418dcf5b | Paul Brook | SysBusDevice busdev; |
21 | 42a4260f | Mark McLoughlin | NICState *nic; |
22 | 50132156 | Gerd Hoffmann | NICConf conf; |
23 | 80337b66 | bellard | uint16_t tcr; |
24 | 80337b66 | bellard | uint16_t rcr; |
25 | 80337b66 | bellard | uint16_t cr; |
26 | 80337b66 | bellard | uint16_t ctr; |
27 | 80337b66 | bellard | uint16_t gpr; |
28 | 80337b66 | bellard | uint16_t ptr; |
29 | 80337b66 | bellard | uint16_t ercv; |
30 | d537cf6c | pbrook | qemu_irq irq; |
31 | 80337b66 | bellard | int bank;
|
32 | 80337b66 | bellard | int packet_num;
|
33 | 80337b66 | bellard | int tx_alloc;
|
34 | 80337b66 | bellard | /* Bitmask of allocated packets. */
|
35 | 80337b66 | bellard | int allocated;
|
36 | 80337b66 | bellard | int tx_fifo_len;
|
37 | 80337b66 | bellard | int tx_fifo[NUM_PACKETS];
|
38 | 80337b66 | bellard | int rx_fifo_len;
|
39 | 80337b66 | bellard | int rx_fifo[NUM_PACKETS];
|
40 | 5198cfd9 | bellard | int tx_fifo_done_len;
|
41 | 5198cfd9 | bellard | int tx_fifo_done[NUM_PACKETS];
|
42 | 80337b66 | bellard | /* Packet buffer memory. */
|
43 | 5198cfd9 | bellard | uint8_t data[NUM_PACKETS][2048];
|
44 | 80337b66 | bellard | uint8_t int_level; |
45 | 80337b66 | bellard | uint8_t int_mask; |
46 | b946a153 | aliguori | int mmio_index;
|
47 | 80337b66 | bellard | } smc91c111_state; |
48 | 80337b66 | bellard | |
49 | 3ac59434 | Peter Maydell | static const VMStateDescription vmstate_smc91c111 = { |
50 | 3ac59434 | Peter Maydell | .name = "smc91c111",
|
51 | 3ac59434 | Peter Maydell | .version_id = 1,
|
52 | 3ac59434 | Peter Maydell | .minimum_version_id = 1,
|
53 | 3ac59434 | Peter Maydell | .fields = (VMStateField []) { |
54 | 3ac59434 | Peter Maydell | VMSTATE_UINT16(tcr, smc91c111_state), |
55 | 3ac59434 | Peter Maydell | VMSTATE_UINT16(rcr, smc91c111_state), |
56 | 3ac59434 | Peter Maydell | VMSTATE_UINT16(cr, smc91c111_state), |
57 | 3ac59434 | Peter Maydell | VMSTATE_UINT16(ctr, smc91c111_state), |
58 | 3ac59434 | Peter Maydell | VMSTATE_UINT16(gpr, smc91c111_state), |
59 | 3ac59434 | Peter Maydell | VMSTATE_UINT16(ptr, smc91c111_state), |
60 | 3ac59434 | Peter Maydell | VMSTATE_UINT16(ercv, smc91c111_state), |
61 | 3ac59434 | Peter Maydell | VMSTATE_INT32(bank, smc91c111_state), |
62 | 3ac59434 | Peter Maydell | VMSTATE_INT32(packet_num, smc91c111_state), |
63 | 3ac59434 | Peter Maydell | VMSTATE_INT32(tx_alloc, smc91c111_state), |
64 | 3ac59434 | Peter Maydell | VMSTATE_INT32(allocated, smc91c111_state), |
65 | 3ac59434 | Peter Maydell | VMSTATE_INT32(tx_fifo_len, smc91c111_state), |
66 | 3ac59434 | Peter Maydell | VMSTATE_INT32_ARRAY(tx_fifo, smc91c111_state, NUM_PACKETS), |
67 | 3ac59434 | Peter Maydell | VMSTATE_INT32(rx_fifo_len, smc91c111_state), |
68 | 3ac59434 | Peter Maydell | VMSTATE_INT32_ARRAY(rx_fifo, smc91c111_state, NUM_PACKETS), |
69 | 3ac59434 | Peter Maydell | VMSTATE_INT32(tx_fifo_done_len, smc91c111_state), |
70 | 3ac59434 | Peter Maydell | VMSTATE_INT32_ARRAY(tx_fifo_done, smc91c111_state, NUM_PACKETS), |
71 | 3ac59434 | Peter Maydell | VMSTATE_BUFFER_UNSAFE(data, smc91c111_state, 0, NUM_PACKETS * 2048), |
72 | 3ac59434 | Peter Maydell | VMSTATE_UINT8(int_level, smc91c111_state), |
73 | 3ac59434 | Peter Maydell | VMSTATE_UINT8(int_mask, smc91c111_state), |
74 | 3ac59434 | Peter Maydell | VMSTATE_END_OF_LIST() |
75 | 3ac59434 | Peter Maydell | } |
76 | 3ac59434 | Peter Maydell | }; |
77 | 3ac59434 | Peter Maydell | |
78 | 80337b66 | bellard | #define RCR_SOFT_RST 0x8000 |
79 | 80337b66 | bellard | #define RCR_STRIP_CRC 0x0200 |
80 | 80337b66 | bellard | #define RCR_RXEN 0x0100 |
81 | 80337b66 | bellard | |
82 | 80337b66 | bellard | #define TCR_EPH_LOOP 0x2000 |
83 | 80337b66 | bellard | #define TCR_NOCRC 0x0100 |
84 | 80337b66 | bellard | #define TCR_PAD_EN 0x0080 |
85 | 80337b66 | bellard | #define TCR_FORCOL 0x0004 |
86 | 80337b66 | bellard | #define TCR_LOOP 0x0002 |
87 | 80337b66 | bellard | #define TCR_TXEN 0x0001 |
88 | 80337b66 | bellard | |
89 | 80337b66 | bellard | #define INT_MD 0x80 |
90 | 80337b66 | bellard | #define INT_ERCV 0x40 |
91 | 80337b66 | bellard | #define INT_EPH 0x20 |
92 | 80337b66 | bellard | #define INT_RX_OVRN 0x10 |
93 | 80337b66 | bellard | #define INT_ALLOC 0x08 |
94 | 80337b66 | bellard | #define INT_TX_EMPTY 0x04 |
95 | 80337b66 | bellard | #define INT_TX 0x02 |
96 | 80337b66 | bellard | #define INT_RCV 0x01 |
97 | 80337b66 | bellard | |
98 | 80337b66 | bellard | #define CTR_AUTO_RELEASE 0x0800 |
99 | 80337b66 | bellard | #define CTR_RELOAD 0x0002 |
100 | 80337b66 | bellard | #define CTR_STORE 0x0001 |
101 | 80337b66 | bellard | |
102 | 80337b66 | bellard | #define RS_ALGNERR 0x8000 |
103 | 80337b66 | bellard | #define RS_BRODCAST 0x4000 |
104 | 80337b66 | bellard | #define RS_BADCRC 0x2000 |
105 | 80337b66 | bellard | #define RS_ODDFRAME 0x1000 |
106 | 80337b66 | bellard | #define RS_TOOLONG 0x0800 |
107 | 80337b66 | bellard | #define RS_TOOSHORT 0x0400 |
108 | 80337b66 | bellard | #define RS_MULTICAST 0x0001 |
109 | 80337b66 | bellard | |
110 | 80337b66 | bellard | /* Update interrupt status. */
|
111 | 80337b66 | bellard | static void smc91c111_update(smc91c111_state *s) |
112 | 80337b66 | bellard | { |
113 | 80337b66 | bellard | int level;
|
114 | 80337b66 | bellard | |
115 | 80337b66 | bellard | if (s->tx_fifo_len == 0) |
116 | 80337b66 | bellard | s->int_level |= INT_TX_EMPTY; |
117 | 5198cfd9 | bellard | if (s->tx_fifo_done_len != 0) |
118 | 5198cfd9 | bellard | s->int_level |= INT_TX; |
119 | 80337b66 | bellard | level = (s->int_level & s->int_mask) != 0;
|
120 | d537cf6c | pbrook | qemu_set_irq(s->irq, level); |
121 | 80337b66 | bellard | } |
122 | 80337b66 | bellard | |
123 | 80337b66 | bellard | /* Try to allocate a packet. Returns 0x80 on failure. */
|
124 | 80337b66 | bellard | static int smc91c111_allocate_packet(smc91c111_state *s) |
125 | 80337b66 | bellard | { |
126 | 80337b66 | bellard | int i;
|
127 | 80337b66 | bellard | if (s->allocated == (1 << NUM_PACKETS) - 1) { |
128 | 80337b66 | bellard | return 0x80; |
129 | 80337b66 | bellard | } |
130 | 80337b66 | bellard | |
131 | 80337b66 | bellard | for (i = 0; i < NUM_PACKETS; i++) { |
132 | 80337b66 | bellard | if ((s->allocated & (1 << i)) == 0) |
133 | 80337b66 | bellard | break;
|
134 | 80337b66 | bellard | } |
135 | 80337b66 | bellard | s->allocated |= 1 << i;
|
136 | 80337b66 | bellard | return i;
|
137 | 80337b66 | bellard | } |
138 | 80337b66 | bellard | |
139 | 80337b66 | bellard | |
140 | 80337b66 | bellard | /* Process a pending TX allocate. */
|
141 | 80337b66 | bellard | static void smc91c111_tx_alloc(smc91c111_state *s) |
142 | 80337b66 | bellard | { |
143 | 80337b66 | bellard | s->tx_alloc = smc91c111_allocate_packet(s); |
144 | 80337b66 | bellard | if (s->tx_alloc == 0x80) |
145 | 80337b66 | bellard | return;
|
146 | 80337b66 | bellard | s->int_level |= INT_ALLOC; |
147 | 80337b66 | bellard | smc91c111_update(s); |
148 | 80337b66 | bellard | } |
149 | 80337b66 | bellard | |
150 | 80337b66 | bellard | /* Remove and item from the RX FIFO. */
|
151 | 80337b66 | bellard | static void smc91c111_pop_rx_fifo(smc91c111_state *s) |
152 | 80337b66 | bellard | { |
153 | 80337b66 | bellard | int i;
|
154 | 80337b66 | bellard | |
155 | 80337b66 | bellard | s->rx_fifo_len--; |
156 | 80337b66 | bellard | if (s->rx_fifo_len) {
|
157 | 80337b66 | bellard | for (i = 0; i < s->rx_fifo_len; i++) |
158 | 80337b66 | bellard | s->rx_fifo[i] = s->rx_fifo[i + 1];
|
159 | 80337b66 | bellard | s->int_level |= INT_RCV; |
160 | 80337b66 | bellard | } else {
|
161 | 80337b66 | bellard | s->int_level &= ~INT_RCV; |
162 | 80337b66 | bellard | } |
163 | 80337b66 | bellard | smc91c111_update(s); |
164 | 80337b66 | bellard | } |
165 | 80337b66 | bellard | |
166 | 5198cfd9 | bellard | /* Remove an item from the TX completion FIFO. */
|
167 | 5198cfd9 | bellard | static void smc91c111_pop_tx_fifo_done(smc91c111_state *s) |
168 | 5198cfd9 | bellard | { |
169 | 5198cfd9 | bellard | int i;
|
170 | 5198cfd9 | bellard | |
171 | 5198cfd9 | bellard | if (s->tx_fifo_done_len == 0) |
172 | 5198cfd9 | bellard | return;
|
173 | 5198cfd9 | bellard | s->tx_fifo_done_len--; |
174 | 5198cfd9 | bellard | for (i = 0; i < s->tx_fifo_done_len; i++) |
175 | 5198cfd9 | bellard | s->tx_fifo_done[i] = s->tx_fifo_done[i + 1];
|
176 | 5198cfd9 | bellard | } |
177 | 5198cfd9 | bellard | |
178 | 80337b66 | bellard | /* Release the memory allocated to a packet. */
|
179 | 80337b66 | bellard | static void smc91c111_release_packet(smc91c111_state *s, int packet) |
180 | 80337b66 | bellard | { |
181 | 80337b66 | bellard | s->allocated &= ~(1 << packet);
|
182 | 80337b66 | bellard | if (s->tx_alloc == 0x80) |
183 | 80337b66 | bellard | smc91c111_tx_alloc(s); |
184 | 80337b66 | bellard | } |
185 | 80337b66 | bellard | |
186 | 80337b66 | bellard | /* Flush the TX FIFO. */
|
187 | 80337b66 | bellard | static void smc91c111_do_tx(smc91c111_state *s) |
188 | 80337b66 | bellard | { |
189 | 80337b66 | bellard | int i;
|
190 | 80337b66 | bellard | int len;
|
191 | 80337b66 | bellard | int control;
|
192 | 80337b66 | bellard | int packetnum;
|
193 | 80337b66 | bellard | uint8_t *p; |
194 | 80337b66 | bellard | |
195 | 80337b66 | bellard | if ((s->tcr & TCR_TXEN) == 0) |
196 | 80337b66 | bellard | return;
|
197 | 80337b66 | bellard | if (s->tx_fifo_len == 0) |
198 | 80337b66 | bellard | return;
|
199 | 80337b66 | bellard | for (i = 0; i < s->tx_fifo_len; i++) { |
200 | 80337b66 | bellard | packetnum = s->tx_fifo[i]; |
201 | 80337b66 | bellard | p = &s->data[packetnum][0];
|
202 | 80337b66 | bellard | /* Set status word. */
|
203 | 80337b66 | bellard | *(p++) = 0x01;
|
204 | 80337b66 | bellard | *(p++) = 0x40;
|
205 | 80337b66 | bellard | len = *(p++); |
206 | 80337b66 | bellard | len |= ((int)*(p++)) << 8; |
207 | 80337b66 | bellard | len -= 6;
|
208 | 80337b66 | bellard | control = p[len + 1];
|
209 | 80337b66 | bellard | if (control & 0x20) |
210 | 80337b66 | bellard | len++; |
211 | 80337b66 | bellard | /* ??? This overwrites the data following the buffer.
|
212 | 80337b66 | bellard | Don't know what real hardware does. */
|
213 | 80337b66 | bellard | if (len < 64 && (s->tcr & TCR_PAD_EN)) { |
214 | 80337b66 | bellard | memset(p + len, 0, 64 - len); |
215 | 80337b66 | bellard | len = 64;
|
216 | 80337b66 | bellard | } |
217 | 80337b66 | bellard | #if 0
|
218 | 22ed1d34 | Blue Swirl | {
|
219 | 22ed1d34 | Blue Swirl | int add_crc;
|
220 | 22ed1d34 | Blue Swirl | |
221 | 22ed1d34 | Blue Swirl | /* The card is supposed to append the CRC to the frame.
|
222 | 22ed1d34 | Blue Swirl | However none of the other network traffic has the CRC
|
223 | 22ed1d34 | Blue Swirl | appended. Suspect this is low level ethernet detail we
|
224 | 22ed1d34 | Blue Swirl | don't need to worry about. */
|
225 | 22ed1d34 | Blue Swirl | add_crc = (control & 0x10) || (s->tcr & TCR_NOCRC) == 0;
|
226 | 22ed1d34 | Blue Swirl | if (add_crc) {
|
227 | 22ed1d34 | Blue Swirl | uint32_t crc;
|
228 | 22ed1d34 | Blue Swirl | |
229 | 22ed1d34 | Blue Swirl | crc = crc32(~0, p, len);
|
230 | 22ed1d34 | Blue Swirl | memcpy(p + len, &crc, 4);
|
231 | 22ed1d34 | Blue Swirl | len += 4;
|
232 | 22ed1d34 | Blue Swirl | }
|
233 | 80337b66 | bellard | }
|
234 | 80337b66 | bellard | #endif
|
235 | 80337b66 | bellard | if (s->ctr & CTR_AUTO_RELEASE)
|
236 | 5198cfd9 | bellard | /* Race? */
|
237 | 80337b66 | bellard | smc91c111_release_packet(s, packetnum); |
238 | 5198cfd9 | bellard | else if (s->tx_fifo_done_len < NUM_PACKETS) |
239 | 5198cfd9 | bellard | s->tx_fifo_done[s->tx_fifo_done_len++] = packetnum; |
240 | 42a4260f | Mark McLoughlin | qemu_send_packet(&s->nic->nc, p, len); |
241 | 80337b66 | bellard | } |
242 | 80337b66 | bellard | s->tx_fifo_len = 0;
|
243 | 80337b66 | bellard | smc91c111_update(s); |
244 | 80337b66 | bellard | } |
245 | 80337b66 | bellard | |
246 | 80337b66 | bellard | /* Add a packet to the TX FIFO. */
|
247 | 80337b66 | bellard | static void smc91c111_queue_tx(smc91c111_state *s, int packet) |
248 | 80337b66 | bellard | { |
249 | 80337b66 | bellard | if (s->tx_fifo_len == NUM_PACKETS)
|
250 | 80337b66 | bellard | return;
|
251 | 80337b66 | bellard | s->tx_fifo[s->tx_fifo_len++] = packet; |
252 | 80337b66 | bellard | smc91c111_do_tx(s); |
253 | 80337b66 | bellard | } |
254 | 80337b66 | bellard | |
255 | 1e36f6a5 | Juha Riihimäki | static void smc91c111_reset(DeviceState *dev) |
256 | 80337b66 | bellard | { |
257 | 1e36f6a5 | Juha Riihimäki | smc91c111_state *s = FROM_SYSBUS(smc91c111_state, sysbus_from_qdev(dev)); |
258 | 80337b66 | bellard | s->bank = 0;
|
259 | 80337b66 | bellard | s->tx_fifo_len = 0;
|
260 | 5198cfd9 | bellard | s->tx_fifo_done_len = 0;
|
261 | 80337b66 | bellard | s->rx_fifo_len = 0;
|
262 | 80337b66 | bellard | s->allocated = 0;
|
263 | 80337b66 | bellard | s->packet_num = 0;
|
264 | 80337b66 | bellard | s->tx_alloc = 0;
|
265 | 80337b66 | bellard | s->tcr = 0;
|
266 | 80337b66 | bellard | s->rcr = 0;
|
267 | 80337b66 | bellard | s->cr = 0xa0b1;
|
268 | 80337b66 | bellard | s->ctr = 0x1210;
|
269 | 80337b66 | bellard | s->ptr = 0;
|
270 | 80337b66 | bellard | s->ercv = 0x1f;
|
271 | 80337b66 | bellard | s->int_level = INT_TX_EMPTY; |
272 | 80337b66 | bellard | s->int_mask = 0;
|
273 | 80337b66 | bellard | smc91c111_update(s); |
274 | 80337b66 | bellard | } |
275 | 80337b66 | bellard | |
276 | 80337b66 | bellard | #define SET_LOW(name, val) s->name = (s->name & 0xff00) | val |
277 | 80337b66 | bellard | #define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8) |
278 | 80337b66 | bellard | |
279 | c227f099 | Anthony Liguori | static void smc91c111_writeb(void *opaque, target_phys_addr_t offset, |
280 | 80337b66 | bellard | uint32_t value) |
281 | 80337b66 | bellard | { |
282 | 80337b66 | bellard | smc91c111_state *s = (smc91c111_state *)opaque; |
283 | 80337b66 | bellard | |
284 | 3b4b86aa | Lars Munch | offset = offset & 0xf;
|
285 | 80337b66 | bellard | if (offset == 14) { |
286 | 80337b66 | bellard | s->bank = value; |
287 | 80337b66 | bellard | return;
|
288 | 80337b66 | bellard | } |
289 | 80337b66 | bellard | if (offset == 15) |
290 | 80337b66 | bellard | return;
|
291 | 80337b66 | bellard | switch (s->bank) {
|
292 | 80337b66 | bellard | case 0: |
293 | 80337b66 | bellard | switch (offset) {
|
294 | 80337b66 | bellard | case 0: /* TCR */ |
295 | 80337b66 | bellard | SET_LOW(tcr, value); |
296 | 80337b66 | bellard | return;
|
297 | 80337b66 | bellard | case 1: |
298 | 80337b66 | bellard | SET_HIGH(tcr, value); |
299 | 80337b66 | bellard | return;
|
300 | 80337b66 | bellard | case 4: /* RCR */ |
301 | 80337b66 | bellard | SET_LOW(rcr, value); |
302 | 80337b66 | bellard | return;
|
303 | 80337b66 | bellard | case 5: |
304 | 80337b66 | bellard | SET_HIGH(rcr, value); |
305 | 80337b66 | bellard | if (s->rcr & RCR_SOFT_RST)
|
306 | 1e36f6a5 | Juha Riihimäki | smc91c111_reset(&s->busdev.qdev); |
307 | 80337b66 | bellard | return;
|
308 | 80337b66 | bellard | case 10: case 11: /* RPCR */ |
309 | 80337b66 | bellard | /* Ignored */
|
310 | 80337b66 | bellard | return;
|
311 | 14da5616 | Lars Munch | case 12: case 13: /* Reserved */ |
312 | 14da5616 | Lars Munch | return;
|
313 | 80337b66 | bellard | } |
314 | 80337b66 | bellard | break;
|
315 | 80337b66 | bellard | |
316 | 80337b66 | bellard | case 1: |
317 | 80337b66 | bellard | switch (offset) {
|
318 | 80337b66 | bellard | case 0: /* CONFIG */ |
319 | 80337b66 | bellard | SET_LOW(cr, value); |
320 | 80337b66 | bellard | return;
|
321 | 80337b66 | bellard | case 1: |
322 | 80337b66 | bellard | SET_HIGH(cr,value); |
323 | 80337b66 | bellard | return;
|
324 | 80337b66 | bellard | case 2: case 3: /* BASE */ |
325 | 80337b66 | bellard | case 4: case 5: case 6: case 7: case 8: case 9: /* IA */ |
326 | 80337b66 | bellard | /* Not implemented. */
|
327 | 80337b66 | bellard | return;
|
328 | 80337b66 | bellard | case 10: /* Genral Purpose */ |
329 | 80337b66 | bellard | SET_LOW(gpr, value); |
330 | 80337b66 | bellard | return;
|
331 | 80337b66 | bellard | case 11: |
332 | 80337b66 | bellard | SET_HIGH(gpr, value); |
333 | 80337b66 | bellard | return;
|
334 | 80337b66 | bellard | case 12: /* Control */ |
335 | 80337b66 | bellard | if (value & 1) |
336 | 80337b66 | bellard | fprintf(stderr, "smc91c111:EEPROM store not implemented\n");
|
337 | 80337b66 | bellard | if (value & 2) |
338 | 80337b66 | bellard | fprintf(stderr, "smc91c111:EEPROM reload not implemented\n");
|
339 | 80337b66 | bellard | value &= ~3;
|
340 | 80337b66 | bellard | SET_LOW(ctr, value); |
341 | 80337b66 | bellard | return;
|
342 | 80337b66 | bellard | case 13: |
343 | 80337b66 | bellard | SET_HIGH(ctr, value); |
344 | 80337b66 | bellard | return;
|
345 | 80337b66 | bellard | } |
346 | 80337b66 | bellard | break;
|
347 | 80337b66 | bellard | |
348 | 80337b66 | bellard | case 2: |
349 | 80337b66 | bellard | switch (offset) {
|
350 | 80337b66 | bellard | case 0: /* MMU Command */ |
351 | 80337b66 | bellard | switch (value >> 5) { |
352 | 80337b66 | bellard | case 0: /* no-op */ |
353 | 80337b66 | bellard | break;
|
354 | 80337b66 | bellard | case 1: /* Allocate for TX. */ |
355 | 80337b66 | bellard | s->tx_alloc = 0x80;
|
356 | 80337b66 | bellard | s->int_level &= ~INT_ALLOC; |
357 | 80337b66 | bellard | smc91c111_update(s); |
358 | 80337b66 | bellard | smc91c111_tx_alloc(s); |
359 | 80337b66 | bellard | break;
|
360 | 80337b66 | bellard | case 2: /* Reset MMU. */ |
361 | 80337b66 | bellard | s->allocated = 0;
|
362 | 80337b66 | bellard | s->tx_fifo_len = 0;
|
363 | 5198cfd9 | bellard | s->tx_fifo_done_len = 0;
|
364 | 80337b66 | bellard | s->rx_fifo_len = 0;
|
365 | 80337b66 | bellard | s->tx_alloc = 0;
|
366 | 80337b66 | bellard | break;
|
367 | 80337b66 | bellard | case 3: /* Remove from RX FIFO. */ |
368 | 80337b66 | bellard | smc91c111_pop_rx_fifo(s); |
369 | 80337b66 | bellard | break;
|
370 | 80337b66 | bellard | case 4: /* Remove from RX FIFO and release. */ |
371 | 80337b66 | bellard | if (s->rx_fifo_len > 0) { |
372 | 80337b66 | bellard | smc91c111_release_packet(s, s->rx_fifo[0]);
|
373 | 80337b66 | bellard | } |
374 | 80337b66 | bellard | smc91c111_pop_rx_fifo(s); |
375 | 80337b66 | bellard | break;
|
376 | 80337b66 | bellard | case 5: /* Release. */ |
377 | 80337b66 | bellard | smc91c111_release_packet(s, s->packet_num); |
378 | 80337b66 | bellard | break;
|
379 | 80337b66 | bellard | case 6: /* Add to TX FIFO. */ |
380 | 80337b66 | bellard | smc91c111_queue_tx(s, s->packet_num); |
381 | 80337b66 | bellard | break;
|
382 | 80337b66 | bellard | case 7: /* Reset TX FIFO. */ |
383 | 80337b66 | bellard | s->tx_fifo_len = 0;
|
384 | 5198cfd9 | bellard | s->tx_fifo_done_len = 0;
|
385 | 80337b66 | bellard | break;
|
386 | 80337b66 | bellard | } |
387 | 80337b66 | bellard | return;
|
388 | 80337b66 | bellard | case 1: |
389 | 80337b66 | bellard | /* Ignore. */
|
390 | 80337b66 | bellard | return;
|
391 | 80337b66 | bellard | case 2: /* Packet Number Register */ |
392 | 80337b66 | bellard | s->packet_num = value; |
393 | 80337b66 | bellard | return;
|
394 | 80337b66 | bellard | case 3: case 4: case 5: |
395 | 80337b66 | bellard | /* Should be readonly, but linux writes to them anyway. Ignore. */
|
396 | 80337b66 | bellard | return;
|
397 | 80337b66 | bellard | case 6: /* Pointer */ |
398 | 80337b66 | bellard | SET_LOW(ptr, value); |
399 | 80337b66 | bellard | return;
|
400 | 80337b66 | bellard | case 7: |
401 | 80337b66 | bellard | SET_HIGH(ptr, value); |
402 | 80337b66 | bellard | return;
|
403 | 80337b66 | bellard | case 8: case 9: case 10: case 11: /* Data */ |
404 | 80337b66 | bellard | { |
405 | 80337b66 | bellard | int p;
|
406 | 80337b66 | bellard | int n;
|
407 | 80337b66 | bellard | |
408 | 80337b66 | bellard | if (s->ptr & 0x8000) |
409 | 80337b66 | bellard | n = s->rx_fifo[0];
|
410 | 80337b66 | bellard | else
|
411 | 80337b66 | bellard | n = s->packet_num; |
412 | 80337b66 | bellard | p = s->ptr & 0x07ff;
|
413 | 80337b66 | bellard | if (s->ptr & 0x4000) { |
414 | 80337b66 | bellard | s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x7ff); |
415 | 80337b66 | bellard | } else {
|
416 | 80337b66 | bellard | p += (offset & 3);
|
417 | 80337b66 | bellard | } |
418 | 80337b66 | bellard | s->data[n][p] = value; |
419 | 80337b66 | bellard | } |
420 | 80337b66 | bellard | return;
|
421 | 80337b66 | bellard | case 12: /* Interrupt ACK. */ |
422 | 80337b66 | bellard | s->int_level &= ~(value & 0xd6);
|
423 | 5198cfd9 | bellard | if (value & INT_TX)
|
424 | 5198cfd9 | bellard | smc91c111_pop_tx_fifo_done(s); |
425 | 80337b66 | bellard | smc91c111_update(s); |
426 | 80337b66 | bellard | return;
|
427 | 80337b66 | bellard | case 13: /* Interrupt mask. */ |
428 | 80337b66 | bellard | s->int_mask = value; |
429 | 80337b66 | bellard | smc91c111_update(s); |
430 | 80337b66 | bellard | return;
|
431 | 80337b66 | bellard | } |
432 | 80337b66 | bellard | break;;
|
433 | 80337b66 | bellard | |
434 | 80337b66 | bellard | case 3: |
435 | 80337b66 | bellard | switch (offset) {
|
436 | 80337b66 | bellard | case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: |
437 | 80337b66 | bellard | /* Multicast table. */
|
438 | 80337b66 | bellard | /* Not implemented. */
|
439 | 80337b66 | bellard | return;
|
440 | 80337b66 | bellard | case 8: case 9: /* Management Interface. */ |
441 | 80337b66 | bellard | /* Not implemented. */
|
442 | 80337b66 | bellard | return;
|
443 | 80337b66 | bellard | case 12: /* Early receive. */ |
444 | 80337b66 | bellard | s->ercv = value & 0x1f;
|
445 | 80337b66 | bellard | case 13: |
446 | 80337b66 | bellard | /* Ignore. */
|
447 | 80337b66 | bellard | return;
|
448 | 80337b66 | bellard | } |
449 | 80337b66 | bellard | break;
|
450 | 80337b66 | bellard | } |
451 | 2ac71179 | Paul Brook | hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset); |
452 | 80337b66 | bellard | } |
453 | 80337b66 | bellard | |
454 | c227f099 | Anthony Liguori | static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset) |
455 | 80337b66 | bellard | { |
456 | 80337b66 | bellard | smc91c111_state *s = (smc91c111_state *)opaque; |
457 | 80337b66 | bellard | |
458 | 3b4b86aa | Lars Munch | offset = offset & 0xf;
|
459 | 80337b66 | bellard | if (offset == 14) { |
460 | 80337b66 | bellard | return s->bank;
|
461 | 80337b66 | bellard | } |
462 | 80337b66 | bellard | if (offset == 15) |
463 | 80337b66 | bellard | return 0x33; |
464 | 80337b66 | bellard | switch (s->bank) {
|
465 | 80337b66 | bellard | case 0: |
466 | 80337b66 | bellard | switch (offset) {
|
467 | 80337b66 | bellard | case 0: /* TCR */ |
468 | 80337b66 | bellard | return s->tcr & 0xff; |
469 | 80337b66 | bellard | case 1: |
470 | 80337b66 | bellard | return s->tcr >> 8; |
471 | 80337b66 | bellard | case 2: /* EPH Status */ |
472 | 80337b66 | bellard | return 0; |
473 | 80337b66 | bellard | case 3: |
474 | 80337b66 | bellard | return 0x40; |
475 | 80337b66 | bellard | case 4: /* RCR */ |
476 | 80337b66 | bellard | return s->rcr & 0xff; |
477 | 80337b66 | bellard | case 5: |
478 | 80337b66 | bellard | return s->rcr >> 8; |
479 | 80337b66 | bellard | case 6: /* Counter */ |
480 | 80337b66 | bellard | case 7: |
481 | 80337b66 | bellard | /* Not implemented. */
|
482 | 80337b66 | bellard | return 0; |
483 | 687fa640 | ths | case 8: /* Memory size. */ |
484 | 687fa640 | ths | return NUM_PACKETS;
|
485 | 687fa640 | ths | case 9: /* Free memory available. */ |
486 | 80337b66 | bellard | { |
487 | 80337b66 | bellard | int i;
|
488 | 80337b66 | bellard | int n;
|
489 | 80337b66 | bellard | n = 0;
|
490 | 80337b66 | bellard | for (i = 0; i < NUM_PACKETS; i++) { |
491 | 80337b66 | bellard | if (s->allocated & (1 << i)) |
492 | 80337b66 | bellard | n++; |
493 | 80337b66 | bellard | } |
494 | 80337b66 | bellard | return n;
|
495 | 80337b66 | bellard | } |
496 | 80337b66 | bellard | case 10: case 11: /* RPCR */ |
497 | 80337b66 | bellard | /* Not implemented. */
|
498 | 80337b66 | bellard | return 0; |
499 | 14da5616 | Lars Munch | case 12: case 13: /* Reserved */ |
500 | 14da5616 | Lars Munch | return 0; |
501 | 80337b66 | bellard | } |
502 | 80337b66 | bellard | break;
|
503 | 80337b66 | bellard | |
504 | 80337b66 | bellard | case 1: |
505 | 80337b66 | bellard | switch (offset) {
|
506 | 80337b66 | bellard | case 0: /* CONFIG */ |
507 | 80337b66 | bellard | return s->cr & 0xff; |
508 | 80337b66 | bellard | case 1: |
509 | 80337b66 | bellard | return s->cr >> 8; |
510 | 80337b66 | bellard | case 2: case 3: /* BASE */ |
511 | 80337b66 | bellard | /* Not implemented. */
|
512 | 80337b66 | bellard | return 0; |
513 | 80337b66 | bellard | case 4: case 5: case 6: case 7: case 8: case 9: /* IA */ |
514 | 50132156 | Gerd Hoffmann | return s->conf.macaddr.a[offset - 4]; |
515 | 80337b66 | bellard | case 10: /* General Purpose */ |
516 | 80337b66 | bellard | return s->gpr & 0xff; |
517 | 80337b66 | bellard | case 11: |
518 | 80337b66 | bellard | return s->gpr >> 8; |
519 | 80337b66 | bellard | case 12: /* Control */ |
520 | 80337b66 | bellard | return s->ctr & 0xff; |
521 | 80337b66 | bellard | case 13: |
522 | 80337b66 | bellard | return s->ctr >> 8; |
523 | 80337b66 | bellard | } |
524 | 80337b66 | bellard | break;
|
525 | 80337b66 | bellard | |
526 | 80337b66 | bellard | case 2: |
527 | 80337b66 | bellard | switch (offset) {
|
528 | 80337b66 | bellard | case 0: case 1: /* MMUCR Busy bit. */ |
529 | 80337b66 | bellard | return 0; |
530 | 80337b66 | bellard | case 2: /* Packet Number. */ |
531 | 80337b66 | bellard | return s->packet_num;
|
532 | 80337b66 | bellard | case 3: /* Allocation Result. */ |
533 | 80337b66 | bellard | return s->tx_alloc;
|
534 | 80337b66 | bellard | case 4: /* TX FIFO */ |
535 | 5198cfd9 | bellard | if (s->tx_fifo_done_len == 0) |
536 | 80337b66 | bellard | return 0x80; |
537 | 80337b66 | bellard | else
|
538 | 5198cfd9 | bellard | return s->tx_fifo_done[0]; |
539 | 80337b66 | bellard | case 5: /* RX FIFO */ |
540 | 80337b66 | bellard | if (s->rx_fifo_len == 0) |
541 | 80337b66 | bellard | return 0x80; |
542 | 80337b66 | bellard | else
|
543 | 80337b66 | bellard | return s->rx_fifo[0]; |
544 | 80337b66 | bellard | case 6: /* Pointer */ |
545 | 80337b66 | bellard | return s->ptr & 0xff; |
546 | 80337b66 | bellard | case 7: |
547 | 80337b66 | bellard | return (s->ptr >> 8) & 0xf7; |
548 | 80337b66 | bellard | case 8: case 9: case 10: case 11: /* Data */ |
549 | 80337b66 | bellard | { |
550 | 80337b66 | bellard | int p;
|
551 | 80337b66 | bellard | int n;
|
552 | 80337b66 | bellard | |
553 | 80337b66 | bellard | if (s->ptr & 0x8000) |
554 | 80337b66 | bellard | n = s->rx_fifo[0];
|
555 | 80337b66 | bellard | else
|
556 | 80337b66 | bellard | n = s->packet_num; |
557 | 80337b66 | bellard | p = s->ptr & 0x07ff;
|
558 | 80337b66 | bellard | if (s->ptr & 0x4000) { |
559 | 80337b66 | bellard | s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x07ff); |
560 | 80337b66 | bellard | } else {
|
561 | 80337b66 | bellard | p += (offset & 3);
|
562 | 80337b66 | bellard | } |
563 | 80337b66 | bellard | return s->data[n][p];
|
564 | 80337b66 | bellard | } |
565 | 80337b66 | bellard | case 12: /* Interrupt status. */ |
566 | 80337b66 | bellard | return s->int_level;
|
567 | 80337b66 | bellard | case 13: /* Interrupt mask. */ |
568 | 80337b66 | bellard | return s->int_mask;
|
569 | 80337b66 | bellard | } |
570 | 80337b66 | bellard | break;
|
571 | 80337b66 | bellard | |
572 | 80337b66 | bellard | case 3: |
573 | 80337b66 | bellard | switch (offset) {
|
574 | 80337b66 | bellard | case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: |
575 | 80337b66 | bellard | /* Multicast table. */
|
576 | 80337b66 | bellard | /* Not implemented. */
|
577 | 80337b66 | bellard | return 0; |
578 | 80337b66 | bellard | case 8: /* Management Interface. */ |
579 | 80337b66 | bellard | /* Not implemented. */
|
580 | 80337b66 | bellard | return 0x30; |
581 | 80337b66 | bellard | case 9: |
582 | 80337b66 | bellard | return 0x33; |
583 | 80337b66 | bellard | case 10: /* Revision. */ |
584 | 80337b66 | bellard | return 0x91; |
585 | 80337b66 | bellard | case 11: |
586 | 80337b66 | bellard | return 0x33; |
587 | 80337b66 | bellard | case 12: |
588 | 80337b66 | bellard | return s->ercv;
|
589 | 80337b66 | bellard | case 13: |
590 | 80337b66 | bellard | return 0; |
591 | 80337b66 | bellard | } |
592 | 80337b66 | bellard | break;
|
593 | 80337b66 | bellard | } |
594 | 2ac71179 | Paul Brook | hw_error("smc91c111_read: Bad reg %d:%x\n", s->bank, (int)offset); |
595 | 80337b66 | bellard | return 0; |
596 | 80337b66 | bellard | } |
597 | 80337b66 | bellard | |
598 | c227f099 | Anthony Liguori | static void smc91c111_writew(void *opaque, target_phys_addr_t offset, |
599 | 80337b66 | bellard | uint32_t value) |
600 | 80337b66 | bellard | { |
601 | 80337b66 | bellard | smc91c111_writeb(opaque, offset, value & 0xff);
|
602 | 80337b66 | bellard | smc91c111_writeb(opaque, offset + 1, value >> 8); |
603 | 80337b66 | bellard | } |
604 | 80337b66 | bellard | |
605 | c227f099 | Anthony Liguori | static void smc91c111_writel(void *opaque, target_phys_addr_t offset, |
606 | 80337b66 | bellard | uint32_t value) |
607 | 80337b66 | bellard | { |
608 | 80337b66 | bellard | /* 32-bit writes to offset 0xc only actually write to the bank select
|
609 | 80337b66 | bellard | register (offset 0xe) */
|
610 | 8da3ff18 | pbrook | if (offset != 0xc) |
611 | 80337b66 | bellard | smc91c111_writew(opaque, offset, value & 0xffff);
|
612 | 80337b66 | bellard | smc91c111_writew(opaque, offset + 2, value >> 16); |
613 | 80337b66 | bellard | } |
614 | 80337b66 | bellard | |
615 | c227f099 | Anthony Liguori | static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset) |
616 | 80337b66 | bellard | { |
617 | 80337b66 | bellard | uint32_t val; |
618 | 80337b66 | bellard | val = smc91c111_readb(opaque, offset); |
619 | 80337b66 | bellard | val |= smc91c111_readb(opaque, offset + 1) << 8; |
620 | 80337b66 | bellard | return val;
|
621 | 80337b66 | bellard | } |
622 | 80337b66 | bellard | |
623 | c227f099 | Anthony Liguori | static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset) |
624 | 80337b66 | bellard | { |
625 | 80337b66 | bellard | uint32_t val; |
626 | 80337b66 | bellard | val = smc91c111_readw(opaque, offset); |
627 | 80337b66 | bellard | val |= smc91c111_readw(opaque, offset + 2) << 16; |
628 | 80337b66 | bellard | return val;
|
629 | 80337b66 | bellard | } |
630 | 80337b66 | bellard | |
631 | 42a4260f | Mark McLoughlin | static int smc91c111_can_receive(VLANClientState *nc) |
632 | d861b05e | pbrook | { |
633 | 42a4260f | Mark McLoughlin | smc91c111_state *s = DO_UPCAST(NICState, nc, nc)->opaque; |
634 | d861b05e | pbrook | |
635 | d861b05e | pbrook | if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) |
636 | d861b05e | pbrook | return 1; |
637 | d861b05e | pbrook | if (s->allocated == (1 << NUM_PACKETS) - 1) |
638 | d861b05e | pbrook | return 0; |
639 | d861b05e | pbrook | return 1; |
640 | d861b05e | pbrook | } |
641 | d861b05e | pbrook | |
642 | 42a4260f | Mark McLoughlin | static ssize_t smc91c111_receive(VLANClientState *nc, const uint8_t *buf, size_t size) |
643 | 80337b66 | bellard | { |
644 | 42a4260f | Mark McLoughlin | smc91c111_state *s = DO_UPCAST(NICState, nc, nc)->opaque; |
645 | 80337b66 | bellard | int status;
|
646 | 80337b66 | bellard | int packetsize;
|
647 | 80337b66 | bellard | uint32_t crc; |
648 | 80337b66 | bellard | int packetnum;
|
649 | 80337b66 | bellard | uint8_t *p; |
650 | 80337b66 | bellard | |
651 | 80337b66 | bellard | if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) |
652 | 4f1c942b | Mark McLoughlin | return -1; |
653 | 9f083493 | ths | /* Short packets are padded with zeros. Receiving a packet
|
654 | 80337b66 | bellard | < 64 bytes long is considered an error condition. */
|
655 | 80337b66 | bellard | if (size < 64) |
656 | 80337b66 | bellard | packetsize = 64;
|
657 | 80337b66 | bellard | else
|
658 | 80337b66 | bellard | packetsize = (size & ~1);
|
659 | 80337b66 | bellard | packetsize += 6;
|
660 | 80337b66 | bellard | crc = (s->rcr & RCR_STRIP_CRC) == 0;
|
661 | 80337b66 | bellard | if (crc)
|
662 | 80337b66 | bellard | packetsize += 4;
|
663 | 80337b66 | bellard | /* TODO: Flag overrun and receive errors. */
|
664 | 80337b66 | bellard | if (packetsize > 2048) |
665 | 4f1c942b | Mark McLoughlin | return -1; |
666 | 80337b66 | bellard | packetnum = smc91c111_allocate_packet(s); |
667 | 80337b66 | bellard | if (packetnum == 0x80) |
668 | 4f1c942b | Mark McLoughlin | return -1; |
669 | 80337b66 | bellard | s->rx_fifo[s->rx_fifo_len++] = packetnum; |
670 | 80337b66 | bellard | |
671 | 80337b66 | bellard | p = &s->data[packetnum][0];
|
672 | 80337b66 | bellard | /* ??? Multicast packets? */
|
673 | 80337b66 | bellard | status = 0;
|
674 | 80337b66 | bellard | if (size > 1518) |
675 | 80337b66 | bellard | status |= RS_TOOLONG; |
676 | 80337b66 | bellard | if (size & 1) |
677 | 80337b66 | bellard | status |= RS_ODDFRAME; |
678 | 80337b66 | bellard | *(p++) = status & 0xff;
|
679 | 80337b66 | bellard | *(p++) = status >> 8;
|
680 | 80337b66 | bellard | *(p++) = packetsize & 0xff;
|
681 | 80337b66 | bellard | *(p++) = packetsize >> 8;
|
682 | 80337b66 | bellard | memcpy(p, buf, size & ~1);
|
683 | 80337b66 | bellard | p += (size & ~1);
|
684 | 80337b66 | bellard | /* Pad short packets. */
|
685 | 80337b66 | bellard | if (size < 64) { |
686 | 80337b66 | bellard | int pad;
|
687 | 3b46e624 | ths | |
688 | 80337b66 | bellard | if (size & 1) |
689 | 80337b66 | bellard | *(p++) = buf[size - 1];
|
690 | 80337b66 | bellard | pad = 64 - size;
|
691 | 80337b66 | bellard | memset(p, 0, pad);
|
692 | 80337b66 | bellard | p += pad; |
693 | 80337b66 | bellard | size = 64;
|
694 | 80337b66 | bellard | } |
695 | 80337b66 | bellard | /* It's not clear if the CRC should go before or after the last byte in
|
696 | 80337b66 | bellard | odd sized packets. Linux disables the CRC, so that's no help.
|
697 | 80337b66 | bellard | The pictures in the documentation show the CRC aligned on a 16-bit
|
698 | 80337b66 | bellard | boundary before the last odd byte, so that's what we do. */
|
699 | 80337b66 | bellard | if (crc) {
|
700 | 80337b66 | bellard | crc = crc32(~0, buf, size);
|
701 | 80337b66 | bellard | *(p++) = crc & 0xff; crc >>= 8; |
702 | 80337b66 | bellard | *(p++) = crc & 0xff; crc >>= 8; |
703 | 80337b66 | bellard | *(p++) = crc & 0xff; crc >>= 8; |
704 | 22ed1d34 | Blue Swirl | *(p++) = crc & 0xff;
|
705 | 80337b66 | bellard | } |
706 | 80337b66 | bellard | if (size & 1) { |
707 | 80337b66 | bellard | *(p++) = buf[size - 1];
|
708 | 22ed1d34 | Blue Swirl | *p = 0x60;
|
709 | 80337b66 | bellard | } else {
|
710 | 80337b66 | bellard | *(p++) = 0;
|
711 | 22ed1d34 | Blue Swirl | *p = 0x40;
|
712 | 80337b66 | bellard | } |
713 | 80337b66 | bellard | /* TODO: Raise early RX interrupt? */
|
714 | 80337b66 | bellard | s->int_level |= INT_RCV; |
715 | 80337b66 | bellard | smc91c111_update(s); |
716 | 4f1c942b | Mark McLoughlin | |
717 | 4f1c942b | Mark McLoughlin | return size;
|
718 | 80337b66 | bellard | } |
719 | 80337b66 | bellard | |
720 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const smc91c111_readfn[] = { |
721 | 80337b66 | bellard | smc91c111_readb, |
722 | 80337b66 | bellard | smc91c111_readw, |
723 | 80337b66 | bellard | smc91c111_readl |
724 | 80337b66 | bellard | }; |
725 | 80337b66 | bellard | |
726 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const smc91c111_writefn[] = { |
727 | 80337b66 | bellard | smc91c111_writeb, |
728 | 80337b66 | bellard | smc91c111_writew, |
729 | 80337b66 | bellard | smc91c111_writel |
730 | 80337b66 | bellard | }; |
731 | 80337b66 | bellard | |
732 | 42a4260f | Mark McLoughlin | static void smc91c111_cleanup(VLANClientState *nc) |
733 | b946a153 | aliguori | { |
734 | 42a4260f | Mark McLoughlin | smc91c111_state *s = DO_UPCAST(NICState, nc, nc)->opaque; |
735 | b946a153 | aliguori | |
736 | 42a4260f | Mark McLoughlin | s->nic = NULL;
|
737 | b946a153 | aliguori | } |
738 | b946a153 | aliguori | |
739 | 42a4260f | Mark McLoughlin | static NetClientInfo net_smc91c111_info = {
|
740 | 42a4260f | Mark McLoughlin | .type = NET_CLIENT_TYPE_NIC, |
741 | 42a4260f | Mark McLoughlin | .size = sizeof(NICState),
|
742 | 42a4260f | Mark McLoughlin | .can_receive = smc91c111_can_receive, |
743 | 42a4260f | Mark McLoughlin | .receive = smc91c111_receive, |
744 | 42a4260f | Mark McLoughlin | .cleanup = smc91c111_cleanup, |
745 | 42a4260f | Mark McLoughlin | }; |
746 | 42a4260f | Mark McLoughlin | |
747 | 81a322d4 | Gerd Hoffmann | static int smc91c111_init1(SysBusDevice *dev) |
748 | 80337b66 | bellard | { |
749 | 418dcf5b | Paul Brook | smc91c111_state *s = FROM_SYSBUS(smc91c111_state, dev); |
750 | 0ae18cee | aliguori | |
751 | 1eed09cb | Avi Kivity | s->mmio_index = cpu_register_io_memory(smc91c111_readfn, |
752 | 2507c12a | Alexander Graf | smc91c111_writefn, s, |
753 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
754 | 418dcf5b | Paul Brook | sysbus_init_mmio(dev, 16, s->mmio_index);
|
755 | 418dcf5b | Paul Brook | sysbus_init_irq(dev, &s->irq); |
756 | 50132156 | Gerd Hoffmann | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
757 | 42a4260f | Mark McLoughlin | s->nic = qemu_new_nic(&net_smc91c111_info, &s->conf, |
758 | 42a4260f | Mark McLoughlin | dev->qdev.info->name, dev->qdev.id, s); |
759 | 42a4260f | Mark McLoughlin | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
760 | 80337b66 | bellard | /* ??? Save/restore. */
|
761 | 81a322d4 | Gerd Hoffmann | return 0; |
762 | 80337b66 | bellard | } |
763 | 418dcf5b | Paul Brook | |
764 | 50132156 | Gerd Hoffmann | static SysBusDeviceInfo smc91c111_info = {
|
765 | 50132156 | Gerd Hoffmann | .init = smc91c111_init1, |
766 | 50132156 | Gerd Hoffmann | .qdev.name = "smc91c111",
|
767 | 50132156 | Gerd Hoffmann | .qdev.size = sizeof(smc91c111_state),
|
768 | 3ac59434 | Peter Maydell | .qdev.vmsd = &vmstate_smc91c111, |
769 | 1e36f6a5 | Juha Riihimäki | .qdev.reset = smc91c111_reset, |
770 | 50132156 | Gerd Hoffmann | .qdev.props = (Property[]) { |
771 | 50132156 | Gerd Hoffmann | DEFINE_NIC_PROPERTIES(smc91c111_state, conf), |
772 | 50132156 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
773 | 50132156 | Gerd Hoffmann | } |
774 | 50132156 | Gerd Hoffmann | }; |
775 | 50132156 | Gerd Hoffmann | |
776 | 418dcf5b | Paul Brook | static void smc91c111_register_devices(void) |
777 | 418dcf5b | Paul Brook | { |
778 | 50132156 | Gerd Hoffmann | sysbus_register_withprop(&smc91c111_info); |
779 | 418dcf5b | Paul Brook | } |
780 | 418dcf5b | Paul Brook | |
781 | 418dcf5b | Paul Brook | /* Legacy helper function. Should go away when machine config files are
|
782 | 418dcf5b | Paul Brook | implemented. */
|
783 | 418dcf5b | Paul Brook | void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq)
|
784 | 418dcf5b | Paul Brook | { |
785 | 418dcf5b | Paul Brook | DeviceState *dev; |
786 | 418dcf5b | Paul Brook | SysBusDevice *s; |
787 | 418dcf5b | Paul Brook | |
788 | 418dcf5b | Paul Brook | qemu_check_nic_model(nd, "smc91c111");
|
789 | 418dcf5b | Paul Brook | dev = qdev_create(NULL, "smc91c111"); |
790 | 50132156 | Gerd Hoffmann | qdev_set_nic_properties(dev, nd); |
791 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
792 | 418dcf5b | Paul Brook | s = sysbus_from_qdev(dev); |
793 | 418dcf5b | Paul Brook | sysbus_mmio_map(s, 0, base);
|
794 | 418dcf5b | Paul Brook | sysbus_connect_irq(s, 0, irq);
|
795 | 418dcf5b | Paul Brook | } |
796 | 418dcf5b | Paul Brook | |
797 | 418dcf5b | Paul Brook | device_init(smc91c111_register_devices) |