root / hw / mips_r4k.c @ 3e35ba93
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1 | e16fe40c | ths | /*
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2 | e16fe40c | ths | * QEMU/MIPS pseudo-board
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3 | e16fe40c | ths | *
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4 | e16fe40c | ths | * emulates a simple machine with ISA-like bus.
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5 | e16fe40c | ths | * ISA IO space mapped to the 0x14000000 (PHYS) and
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6 | e16fe40c | ths | * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
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7 | e16fe40c | ths | * All peripherial devices are attached to this "bus" with
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8 | e16fe40c | ths | * the standard PC ISA addresses.
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9 | e16fe40c | ths | */
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10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "mips.h" |
12 | 87ecb68b | pbrook | #include "pc.h" |
13 | 87ecb68b | pbrook | #include "isa.h" |
14 | 87ecb68b | pbrook | #include "net.h" |
15 | 87ecb68b | pbrook | #include "sysemu.h" |
16 | 87ecb68b | pbrook | #include "boards.h" |
17 | b305b5ba | ths | #include "flash.h" |
18 | 3b3fb322 | blueswir1 | #include "qemu-log.h" |
19 | bba831e8 | Paul Brook | #include "mips-bios.h" |
20 | ec82026c | Gerd Hoffmann | #include "ide.h" |
21 | ca20cf32 | Blue Swirl | #include "loader.h" |
22 | ca20cf32 | Blue Swirl | #include "elf.h" |
23 | 44cbbf18 | ths | |
24 | c6ee607c | pbrook | #define PHYS_TO_VIRT(x) ((x) | ~(target_ulong)0x7fffffff) |
25 | 6af0bf9c | bellard | |
26 | 5dc4b744 | ths | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
27 | 66a93e0f | bellard | |
28 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
29 | e4bcb14c | ths | |
30 | 58126404 | pbrook | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
31 | 58126404 | pbrook | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
32 | 58126404 | pbrook | static const int ide_irq[2] = { 14, 15 }; |
33 | 58126404 | pbrook | |
34 | e16fe40c | ths | static PITState *pit; /* PIT i8254 */ |
35 | 697584ab | bellard | |
36 | 1b66074b | ths | /* i8254 PIT is attached to the IRQ0 at PIC i8259 */
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37 | 6af0bf9c | bellard | |
38 | 7df526e3 | ths | static struct _loaderparams { |
39 | 7df526e3 | ths | int ram_size;
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40 | 7df526e3 | ths | const char *kernel_filename; |
41 | 7df526e3 | ths | const char *kernel_cmdline; |
42 | 7df526e3 | ths | const char *initrd_filename; |
43 | 7df526e3 | ths | } loaderparams; |
44 | 7df526e3 | ths | |
45 | c227f099 | Anthony Liguori | static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, |
46 | 6ae81775 | ths | uint32_t val) |
47 | 6ae81775 | ths | { |
48 | 6ae81775 | ths | if ((addr & 0xffff) == 0 && val == 42) |
49 | 6ae81775 | ths | qemu_system_reset_request (); |
50 | 6ae81775 | ths | else if ((addr & 0xffff) == 4 && val == 42) |
51 | 6ae81775 | ths | qemu_system_shutdown_request (); |
52 | 6ae81775 | ths | } |
53 | 6ae81775 | ths | |
54 | c227f099 | Anthony Liguori | static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) |
55 | 6ae81775 | ths | { |
56 | 6ae81775 | ths | return 0; |
57 | 6ae81775 | ths | } |
58 | 6ae81775 | ths | |
59 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mips_qemu_write[] = { |
60 | 6ae81775 | ths | &mips_qemu_writel, |
61 | 6ae81775 | ths | &mips_qemu_writel, |
62 | 6ae81775 | ths | &mips_qemu_writel, |
63 | 6ae81775 | ths | }; |
64 | 6ae81775 | ths | |
65 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mips_qemu_read[] = { |
66 | 6ae81775 | ths | &mips_qemu_readl, |
67 | 6ae81775 | ths | &mips_qemu_readl, |
68 | 6ae81775 | ths | &mips_qemu_readl, |
69 | 6ae81775 | ths | }; |
70 | 6ae81775 | ths | |
71 | 6ae81775 | ths | static int mips_qemu_iomemtype = 0; |
72 | 6ae81775 | ths | |
73 | e16ad5b0 | Aurelien Jarno | typedef struct ResetData { |
74 | e16ad5b0 | Aurelien Jarno | CPUState *env; |
75 | e16ad5b0 | Aurelien Jarno | uint64_t vector; |
76 | e16ad5b0 | Aurelien Jarno | } ResetData; |
77 | e16ad5b0 | Aurelien Jarno | |
78 | e16ad5b0 | Aurelien Jarno | static int64_t load_kernel(void) |
79 | 6ae81775 | ths | { |
80 | 74287114 | ths | int64_t entry, kernel_low, kernel_high; |
81 | e90e795e | Aurelien Jarno | long kernel_size, initrd_size, params_size;
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82 | c227f099 | Anthony Liguori | ram_addr_t initrd_offset; |
83 | e90e795e | Aurelien Jarno | uint32_t *params_buf; |
84 | ca20cf32 | Blue Swirl | int big_endian;
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85 | 6ae81775 | ths | |
86 | ca20cf32 | Blue Swirl | #ifdef TARGET_WORDS_BIGENDIAN
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87 | ca20cf32 | Blue Swirl | big_endian = 1;
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88 | ca20cf32 | Blue Swirl | #else
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89 | ca20cf32 | Blue Swirl | big_endian = 0;
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90 | ca20cf32 | Blue Swirl | #endif
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91 | 7df526e3 | ths | kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND, |
92 | b55266b5 | blueswir1 | (uint64_t *)&entry, (uint64_t *)&kernel_low, |
93 | ca20cf32 | Blue Swirl | (uint64_t *)&kernel_high, big_endian, ELF_MACHINE, 1);
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94 | c570fd16 | ths | if (kernel_size >= 0) { |
95 | c570fd16 | ths | if ((entry & ~0x7fffffffULL) == 0x80000000) |
96 | 5dc4b744 | ths | entry = (int32_t)entry; |
97 | c570fd16 | ths | } else {
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98 | 9042c0e2 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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99 | 7df526e3 | ths | loaderparams.kernel_filename); |
100 | 9042c0e2 | ths | exit(1);
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101 | 6ae81775 | ths | } |
102 | 6ae81775 | ths | |
103 | 6ae81775 | ths | /* load initrd */
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104 | 6ae81775 | ths | initrd_size = 0;
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105 | 74287114 | ths | initrd_offset = 0;
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106 | 7df526e3 | ths | if (loaderparams.initrd_filename) {
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107 | 7df526e3 | ths | initrd_size = get_image_size (loaderparams.initrd_filename); |
108 | 74287114 | ths | if (initrd_size > 0) { |
109 | 74287114 | ths | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; |
110 | 74287114 | ths | if (initrd_offset + initrd_size > ram_size) {
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111 | 74287114 | ths | fprintf(stderr, |
112 | 74287114 | ths | "qemu: memory too small for initial ram disk '%s'\n",
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113 | 7df526e3 | ths | loaderparams.initrd_filename); |
114 | 74287114 | ths | exit(1);
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115 | 74287114 | ths | } |
116 | dcac9679 | pbrook | initrd_size = load_image_targphys(loaderparams.initrd_filename, |
117 | dcac9679 | pbrook | initrd_offset, |
118 | dcac9679 | pbrook | ram_size - initrd_offset); |
119 | 74287114 | ths | } |
120 | 6ae81775 | ths | if (initrd_size == (target_ulong) -1) { |
121 | 6ae81775 | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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122 | 7df526e3 | ths | loaderparams.initrd_filename); |
123 | 6ae81775 | ths | exit(1);
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124 | 6ae81775 | ths | } |
125 | 6ae81775 | ths | } |
126 | 6ae81775 | ths | |
127 | 6ae81775 | ths | /* Store command line. */
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128 | e90e795e | Aurelien Jarno | params_size = 264;
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129 | e90e795e | Aurelien Jarno | params_buf = qemu_malloc(params_size); |
130 | e90e795e | Aurelien Jarno | |
131 | e90e795e | Aurelien Jarno | params_buf[0] = tswap32(ram_size);
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132 | e90e795e | Aurelien Jarno | params_buf[1] = tswap32(0x12345678); |
133 | e90e795e | Aurelien Jarno | |
134 | 6ae81775 | ths | if (initrd_size > 0) { |
135 | e90e795e | Aurelien Jarno | snprintf((char *)params_buf + 8, 256, "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s", |
136 | e90e795e | Aurelien Jarno | PHYS_TO_VIRT((uint32_t)initrd_offset), |
137 | e90e795e | Aurelien Jarno | initrd_size, loaderparams.kernel_cmdline); |
138 | d7585251 | pbrook | } else {
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139 | e90e795e | Aurelien Jarno | snprintf((char *)params_buf + 8, 256, "%s", loaderparams.kernel_cmdline); |
140 | 6ae81775 | ths | } |
141 | 6ae81775 | ths | |
142 | e90e795e | Aurelien Jarno | rom_add_blob_fixed("params", params_buf, params_size,
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143 | e90e795e | Aurelien Jarno | (16 << 20) - 264); |
144 | e90e795e | Aurelien Jarno | |
145 | e16ad5b0 | Aurelien Jarno | return entry;
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146 | 6ae81775 | ths | } |
147 | 6ae81775 | ths | |
148 | 6ae81775 | ths | static void main_cpu_reset(void *opaque) |
149 | 6ae81775 | ths | { |
150 | e16ad5b0 | Aurelien Jarno | ResetData *s = (ResetData *)opaque; |
151 | e16ad5b0 | Aurelien Jarno | CPUState *env = s->env; |
152 | 6ae81775 | ths | |
153 | e16ad5b0 | Aurelien Jarno | cpu_reset(env); |
154 | e16ad5b0 | Aurelien Jarno | env->active_tc.PC = s->vector; |
155 | 6ae81775 | ths | } |
156 | 66a93e0f | bellard | |
157 | b305b5ba | ths | static const int sector_len = 32 * 1024; |
158 | 70705261 | ths | static
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159 | c227f099 | Anthony Liguori | void mips_r4k_init (ram_addr_t ram_size,
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160 | 3023f332 | aliguori | const char *boot_device, |
161 | 6af0bf9c | bellard | const char *kernel_filename, const char *kernel_cmdline, |
162 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
163 | 6af0bf9c | bellard | { |
164 | 5cea8590 | Paul Brook | char *filename;
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165 | c227f099 | Anthony Liguori | ram_addr_t ram_offset; |
166 | c227f099 | Anthony Liguori | ram_addr_t bios_offset; |
167 | f7bcd4e3 | ths | int bios_size;
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168 | c68ea704 | bellard | CPUState *env; |
169 | e16ad5b0 | Aurelien Jarno | ResetData *reset_info; |
170 | 153a08db | ths | RTCState *rtc_state; |
171 | 58126404 | pbrook | int i;
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172 | d537cf6c | pbrook | qemu_irq *i8259; |
173 | f455e98c | Gerd Hoffmann | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
174 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo; |
175 | c68ea704 | bellard | |
176 | 33d68b5f | ths | /* init CPUs */
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177 | 33d68b5f | ths | if (cpu_model == NULL) { |
178 | 60aa19ab | ths | #ifdef TARGET_MIPS64
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179 | 33d68b5f | ths | cpu_model = "R4000";
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180 | 33d68b5f | ths | #else
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181 | 1c32f43e | ths | cpu_model = "24Kf";
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182 | 33d68b5f | ths | #endif
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183 | 33d68b5f | ths | } |
184 | aaed909a | bellard | env = cpu_init(cpu_model); |
185 | aaed909a | bellard | if (!env) {
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186 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
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187 | aaed909a | bellard | exit(1);
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188 | aaed909a | bellard | } |
189 | e16ad5b0 | Aurelien Jarno | reset_info = qemu_mallocz(sizeof(ResetData));
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190 | e16ad5b0 | Aurelien Jarno | reset_info->env = env; |
191 | e16ad5b0 | Aurelien Jarno | reset_info->vector = env->active_tc.PC; |
192 | e16ad5b0 | Aurelien Jarno | qemu_register_reset(main_cpu_reset, reset_info); |
193 | c68ea704 | bellard | |
194 | 6af0bf9c | bellard | /* allocate RAM */
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195 | 0ccff151 | aurel32 | if (ram_size > (256 << 20)) { |
196 | 0ccff151 | aurel32 | fprintf(stderr, |
197 | 0ccff151 | aurel32 | "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n",
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198 | 0ccff151 | aurel32 | ((unsigned int)ram_size / (1 << 20))); |
199 | 0ccff151 | aurel32 | exit(1);
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200 | 0ccff151 | aurel32 | } |
201 | dcac9679 | pbrook | ram_offset = qemu_ram_alloc(ram_size); |
202 | dcac9679 | pbrook | |
203 | dcac9679 | pbrook | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
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204 | 66a93e0f | bellard | |
205 | 6ae81775 | ths | if (!mips_qemu_iomemtype) {
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206 | 1eed09cb | Avi Kivity | mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read, |
207 | 33d68b5f | ths | mips_qemu_write, NULL);
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208 | 6ae81775 | ths | } |
209 | 6ae81775 | ths | cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); |
210 | 6ae81775 | ths | |
211 | 66a93e0f | bellard | /* Try to load a BIOS image. If this fails, we continue regardless,
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212 | 66a93e0f | bellard | but initialize the hardware ourselves. When a kernel gets
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213 | 66a93e0f | bellard | preloaded we also initialize the hardware, since the BIOS wasn't
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214 | 66a93e0f | bellard | run. */
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215 | 1192dad8 | j_mayer | if (bios_name == NULL) |
216 | 1192dad8 | j_mayer | bios_name = BIOS_FILENAME; |
217 | 5cea8590 | Paul Brook | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
218 | 5cea8590 | Paul Brook | if (filename) {
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219 | 5cea8590 | Paul Brook | bios_size = get_image_size(filename); |
220 | 5cea8590 | Paul Brook | } else {
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221 | 5cea8590 | Paul Brook | bios_size = -1;
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222 | 5cea8590 | Paul Brook | } |
223 | 2909b29a | ths | if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { |
224 | dcac9679 | pbrook | bios_offset = qemu_ram_alloc(BIOS_SIZE); |
225 | dcac9679 | pbrook | cpu_register_physical_memory(0x1fc00000, BIOS_SIZE,
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226 | dcac9679 | pbrook | bios_offset | IO_MEM_ROM); |
227 | dcac9679 | pbrook | |
228 | 5cea8590 | Paul Brook | load_image_targphys(filename, 0x1fc00000, BIOS_SIZE);
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229 | 751c6a17 | Gerd Hoffmann | } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) { |
230 | b305b5ba | ths | uint32_t mips_rom = 0x00400000;
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231 | dcac9679 | pbrook | bios_offset = qemu_ram_alloc(mips_rom); |
232 | dcac9679 | pbrook | if (!pflash_cfi01_register(0x1fc00000, bios_offset, |
233 | 751c6a17 | Gerd Hoffmann | dinfo->bdrv, sector_len, mips_rom / sector_len, |
234 | b305b5ba | ths | 4, 0, 0, 0, 0)) { |
235 | b305b5ba | ths | fprintf(stderr, "qemu: Error registering flash memory.\n");
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236 | b305b5ba | ths | } |
237 | b305b5ba | ths | } |
238 | b305b5ba | ths | else {
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239 | 66a93e0f | bellard | /* not fatal */
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240 | 66a93e0f | bellard | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
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241 | 5cea8590 | Paul Brook | bios_name); |
242 | 5cea8590 | Paul Brook | } |
243 | 5cea8590 | Paul Brook | if (filename) {
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244 | 5cea8590 | Paul Brook | qemu_free(filename); |
245 | 6af0bf9c | bellard | } |
246 | 66a93e0f | bellard | |
247 | 66a93e0f | bellard | if (kernel_filename) {
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248 | 7df526e3 | ths | loaderparams.ram_size = ram_size; |
249 | 7df526e3 | ths | loaderparams.kernel_filename = kernel_filename; |
250 | 7df526e3 | ths | loaderparams.kernel_cmdline = kernel_cmdline; |
251 | 7df526e3 | ths | loaderparams.initrd_filename = initrd_filename; |
252 | e16ad5b0 | Aurelien Jarno | reset_info->vector = load_kernel(); |
253 | 6af0bf9c | bellard | } |
254 | 6af0bf9c | bellard | |
255 | e16fe40c | ths | /* Init CPU internal devices */
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256 | d537cf6c | pbrook | cpu_mips_irq_init_cpu(env); |
257 | c68ea704 | bellard | cpu_mips_clock_init(env); |
258 | 6af0bf9c | bellard | |
259 | d537cf6c | pbrook | /* The PIC is attached to the MIPS CPU INT0 pin */
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260 | d537cf6c | pbrook | i8259 = i8259_init(env->irq[2]);
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261 | 11d23c35 | Gerd Hoffmann | isa_bus_new(NULL);
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262 | 11d23c35 | Gerd Hoffmann | isa_bus_irqs(i8259); |
263 | d537cf6c | pbrook | |
264 | 32e0c826 | Gerd Hoffmann | rtc_state = rtc_init(2000);
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265 | afdfa781 | ths | |
266 | 0699b548 | bellard | /* Register 64 KB of ISA IO space at 0x14000000 */
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267 | aef445bd | pbrook | isa_mmio_init(0x14000000, 0x00010000); |
268 | 0699b548 | bellard | isa_mem_base = 0x10000000;
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269 | 0699b548 | bellard | |
270 | d537cf6c | pbrook | pit = pit_init(0x40, i8259[0]); |
271 | afdfa781 | ths | |
272 | eddbd288 | ths | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
273 | eddbd288 | ths | if (serial_hds[i]) {
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274 | ac0be998 | Gerd Hoffmann | serial_isa_init(i, serial_hds[i]); |
275 | eddbd288 | ths | } |
276 | eddbd288 | ths | } |
277 | eddbd288 | ths | |
278 | fbe1b595 | Paul Brook | isa_vga_init(); |
279 | 9827e95c | bellard | |
280 | 0ae18cee | aliguori | if (nd_table[0].vlan) |
281 | 9453c5bc | Gerd Hoffmann | isa_ne2000_init(0x300, 9, &nd_table[0]); |
282 | 58126404 | pbrook | |
283 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
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284 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
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285 | e4bcb14c | ths | exit(1);
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286 | e4bcb14c | ths | } |
287 | e4bcb14c | ths | |
288 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
289 | f455e98c | Gerd Hoffmann | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
290 | e4bcb14c | ths | } |
291 | e4bcb14c | ths | |
292 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS; i++) |
293 | dea21e97 | Gerd Hoffmann | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
294 | e4bcb14c | ths | hd[MAX_IDE_DEVS * i], |
295 | e4bcb14c | ths | hd[MAX_IDE_DEVS * i + 1]);
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296 | 70705261 | ths | |
297 | 11d23c35 | Gerd Hoffmann | isa_create_simple("i8042");
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298 | 6af0bf9c | bellard | } |
299 | 6af0bf9c | bellard | |
300 | f80f9ec9 | Anthony Liguori | static QEMUMachine mips_machine = {
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301 | eec2743e | ths | .name = "mips",
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302 | eec2743e | ths | .desc = "mips r4k platform",
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303 | eec2743e | ths | .init = mips_r4k_init, |
304 | 6af0bf9c | bellard | }; |
305 | f80f9ec9 | Anthony Liguori | |
306 | f80f9ec9 | Anthony Liguori | static void mips_machine_init(void) |
307 | f80f9ec9 | Anthony Liguori | { |
308 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mips_machine); |
309 | f80f9ec9 | Anthony Liguori | } |
310 | f80f9ec9 | Anthony Liguori | |
311 | f80f9ec9 | Anthony Liguori | machine_init(mips_machine_init); |