root / hw / mcf_uart.c @ 3e3f6754
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1 | 5fafdf24 | ths | /*
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2 | 20dcee94 | pbrook | * ColdFire UART emulation.
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3 | 20dcee94 | pbrook | *
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4 | 20dcee94 | pbrook | * Copyright (c) 2007 CodeSourcery.
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5 | 20dcee94 | pbrook | *
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6 | 20dcee94 | pbrook | * This code is licenced under the GPL
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7 | 20dcee94 | pbrook | */
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8 | 87ecb68b | pbrook | #include "hw.h" |
9 | 87ecb68b | pbrook | #include "mcf.h" |
10 | 87ecb68b | pbrook | #include "qemu-char.h" |
11 | 20dcee94 | pbrook | |
12 | 20dcee94 | pbrook | typedef struct { |
13 | 20dcee94 | pbrook | uint8_t mr[2];
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14 | 20dcee94 | pbrook | uint8_t sr; |
15 | 20dcee94 | pbrook | uint8_t isr; |
16 | 20dcee94 | pbrook | uint8_t imr; |
17 | 20dcee94 | pbrook | uint8_t bg1; |
18 | 20dcee94 | pbrook | uint8_t bg2; |
19 | 20dcee94 | pbrook | uint8_t fifo[4];
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20 | 20dcee94 | pbrook | uint8_t tb; |
21 | 20dcee94 | pbrook | int current_mr;
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22 | 20dcee94 | pbrook | int fifo_len;
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23 | 20dcee94 | pbrook | int tx_enabled;
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24 | 20dcee94 | pbrook | int rx_enabled;
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25 | 20dcee94 | pbrook | qemu_irq irq; |
26 | 20dcee94 | pbrook | CharDriverState *chr; |
27 | 20dcee94 | pbrook | } mcf_uart_state; |
28 | 20dcee94 | pbrook | |
29 | 20dcee94 | pbrook | /* UART Status Register bits. */
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30 | 20dcee94 | pbrook | #define MCF_UART_RxRDY 0x01 |
31 | 20dcee94 | pbrook | #define MCF_UART_FFULL 0x02 |
32 | 20dcee94 | pbrook | #define MCF_UART_TxRDY 0x04 |
33 | 20dcee94 | pbrook | #define MCF_UART_TxEMP 0x08 |
34 | 20dcee94 | pbrook | #define MCF_UART_OE 0x10 |
35 | 20dcee94 | pbrook | #define MCF_UART_PE 0x20 |
36 | 20dcee94 | pbrook | #define MCF_UART_FE 0x40 |
37 | 20dcee94 | pbrook | #define MCF_UART_RB 0x80 |
38 | 20dcee94 | pbrook | |
39 | 20dcee94 | pbrook | /* Interrupt flags. */
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40 | 20dcee94 | pbrook | #define MCF_UART_TxINT 0x01 |
41 | 20dcee94 | pbrook | #define MCF_UART_RxINT 0x02 |
42 | 20dcee94 | pbrook | #define MCF_UART_DBINT 0x04 |
43 | 20dcee94 | pbrook | #define MCF_UART_COSINT 0x80 |
44 | 20dcee94 | pbrook | |
45 | 20dcee94 | pbrook | /* UMR1 flags. */
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46 | 20dcee94 | pbrook | #define MCF_UART_BC0 0x01 |
47 | 20dcee94 | pbrook | #define MCF_UART_BC1 0x02 |
48 | 20dcee94 | pbrook | #define MCF_UART_PT 0x04 |
49 | 20dcee94 | pbrook | #define MCF_UART_PM0 0x08 |
50 | 20dcee94 | pbrook | #define MCF_UART_PM1 0x10 |
51 | 20dcee94 | pbrook | #define MCF_UART_ERR 0x20 |
52 | 20dcee94 | pbrook | #define MCF_UART_RxIRQ 0x40 |
53 | 20dcee94 | pbrook | #define MCF_UART_RxRTS 0x80 |
54 | 20dcee94 | pbrook | |
55 | 20dcee94 | pbrook | static void mcf_uart_update(mcf_uart_state *s) |
56 | 20dcee94 | pbrook | { |
57 | 20dcee94 | pbrook | s->isr &= ~(MCF_UART_TxINT | MCF_UART_RxINT); |
58 | 20dcee94 | pbrook | if (s->sr & MCF_UART_TxRDY)
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59 | 20dcee94 | pbrook | s->isr |= MCF_UART_TxINT; |
60 | 20dcee94 | pbrook | if ((s->sr & ((s->mr[0] & MCF_UART_RxIRQ) |
61 | 20dcee94 | pbrook | ? MCF_UART_FFULL : MCF_UART_RxRDY)) != 0)
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62 | 20dcee94 | pbrook | s->isr |= MCF_UART_RxINT; |
63 | 20dcee94 | pbrook | |
64 | 20dcee94 | pbrook | qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
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65 | 20dcee94 | pbrook | } |
66 | 20dcee94 | pbrook | |
67 | 20dcee94 | pbrook | uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr)
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68 | 20dcee94 | pbrook | { |
69 | 20dcee94 | pbrook | mcf_uart_state *s = (mcf_uart_state *)opaque; |
70 | 20dcee94 | pbrook | switch (addr & 0x3f) { |
71 | 20dcee94 | pbrook | case 0x00: |
72 | 20dcee94 | pbrook | return s->mr[s->current_mr];
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73 | 20dcee94 | pbrook | case 0x04: |
74 | 20dcee94 | pbrook | return s->sr;
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75 | 20dcee94 | pbrook | case 0x0c: |
76 | 20dcee94 | pbrook | { |
77 | 20dcee94 | pbrook | uint8_t val; |
78 | 20dcee94 | pbrook | int i;
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79 | 20dcee94 | pbrook | |
80 | 20dcee94 | pbrook | if (s->fifo_len == 0) |
81 | 20dcee94 | pbrook | return 0; |
82 | 20dcee94 | pbrook | |
83 | 20dcee94 | pbrook | val = s->fifo[0];
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84 | 20dcee94 | pbrook | s->fifo_len--; |
85 | 20dcee94 | pbrook | for (i = 0; i < s->fifo_len; i++) |
86 | 20dcee94 | pbrook | s->fifo[i] = s->fifo[i + 1];
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87 | 20dcee94 | pbrook | s->sr &= ~MCF_UART_FFULL; |
88 | 20dcee94 | pbrook | if (s->fifo_len == 0) |
89 | 20dcee94 | pbrook | s->sr &= ~MCF_UART_RxRDY; |
90 | 20dcee94 | pbrook | mcf_uart_update(s); |
91 | 20dcee94 | pbrook | return val;
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92 | 20dcee94 | pbrook | } |
93 | 20dcee94 | pbrook | case 0x10: |
94 | 20dcee94 | pbrook | /* TODO: Implement IPCR. */
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95 | 20dcee94 | pbrook | return 0; |
96 | 20dcee94 | pbrook | case 0x14: |
97 | 20dcee94 | pbrook | return s->isr;
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98 | 20dcee94 | pbrook | case 0x18: |
99 | 20dcee94 | pbrook | return s->bg1;
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100 | 20dcee94 | pbrook | case 0x1c: |
101 | 20dcee94 | pbrook | return s->bg2;
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102 | 20dcee94 | pbrook | default:
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103 | 20dcee94 | pbrook | return 0; |
104 | 20dcee94 | pbrook | } |
105 | 20dcee94 | pbrook | } |
106 | 20dcee94 | pbrook | |
107 | 20dcee94 | pbrook | /* Update TxRDY flag and set data if present and enabled. */
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108 | 20dcee94 | pbrook | static void mcf_uart_do_tx(mcf_uart_state *s) |
109 | 20dcee94 | pbrook | { |
110 | 20dcee94 | pbrook | if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) { |
111 | 20dcee94 | pbrook | if (s->chr)
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112 | 20dcee94 | pbrook | qemu_chr_write(s->chr, (unsigned char *)&s->tb, 1); |
113 | 20dcee94 | pbrook | s->sr |= MCF_UART_TxEMP; |
114 | 20dcee94 | pbrook | } |
115 | 20dcee94 | pbrook | if (s->tx_enabled) {
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116 | 20dcee94 | pbrook | s->sr |= MCF_UART_TxRDY; |
117 | 20dcee94 | pbrook | } else {
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118 | 20dcee94 | pbrook | s->sr &= ~MCF_UART_TxRDY; |
119 | 20dcee94 | pbrook | } |
120 | 20dcee94 | pbrook | } |
121 | 20dcee94 | pbrook | |
122 | 20dcee94 | pbrook | static void mcf_do_command(mcf_uart_state *s, uint8_t cmd) |
123 | 20dcee94 | pbrook | { |
124 | 20dcee94 | pbrook | /* Misc command. */
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125 | 20dcee94 | pbrook | switch ((cmd >> 4) & 3) { |
126 | 20dcee94 | pbrook | case 0: /* No-op. */ |
127 | 20dcee94 | pbrook | break;
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128 | 20dcee94 | pbrook | case 1: /* Reset mode register pointer. */ |
129 | 20dcee94 | pbrook | s->current_mr = 0;
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130 | 20dcee94 | pbrook | break;
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131 | 20dcee94 | pbrook | case 2: /* Reset receiver. */ |
132 | 20dcee94 | pbrook | s->rx_enabled = 0;
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133 | 20dcee94 | pbrook | s->fifo_len = 0;
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134 | 20dcee94 | pbrook | s->sr &= ~(MCF_UART_RxRDY | MCF_UART_FFULL); |
135 | 20dcee94 | pbrook | break;
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136 | 20dcee94 | pbrook | case 3: /* Reset transmitter. */ |
137 | 20dcee94 | pbrook | s->tx_enabled = 0;
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138 | 20dcee94 | pbrook | s->sr |= MCF_UART_TxEMP; |
139 | 20dcee94 | pbrook | s->sr &= ~MCF_UART_TxRDY; |
140 | 20dcee94 | pbrook | break;
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141 | 20dcee94 | pbrook | case 4: /* Reset error status. */ |
142 | 20dcee94 | pbrook | break;
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143 | 20dcee94 | pbrook | case 5: /* Reset break-change interrupt. */ |
144 | 20dcee94 | pbrook | s->isr &= ~MCF_UART_DBINT; |
145 | 20dcee94 | pbrook | break;
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146 | 20dcee94 | pbrook | case 6: /* Start break. */ |
147 | 20dcee94 | pbrook | case 7: /* Stop break. */ |
148 | 20dcee94 | pbrook | break;
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149 | 20dcee94 | pbrook | } |
150 | 20dcee94 | pbrook | |
151 | 20dcee94 | pbrook | /* Transmitter command. */
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152 | 20dcee94 | pbrook | switch ((cmd >> 2) & 3) { |
153 | 20dcee94 | pbrook | case 0: /* No-op. */ |
154 | 20dcee94 | pbrook | break;
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155 | 20dcee94 | pbrook | case 1: /* Enable. */ |
156 | 20dcee94 | pbrook | s->tx_enabled = 1;
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157 | 20dcee94 | pbrook | mcf_uart_do_tx(s); |
158 | 20dcee94 | pbrook | break;
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159 | 20dcee94 | pbrook | case 2: /* Disable. */ |
160 | 20dcee94 | pbrook | s->tx_enabled = 0;
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161 | 20dcee94 | pbrook | mcf_uart_do_tx(s); |
162 | 20dcee94 | pbrook | break;
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163 | 20dcee94 | pbrook | case 3: /* Reserved. */ |
164 | 20dcee94 | pbrook | fprintf(stderr, "mcf_uart: Bad TX command\n");
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165 | 20dcee94 | pbrook | break;
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166 | 20dcee94 | pbrook | } |
167 | 20dcee94 | pbrook | |
168 | 20dcee94 | pbrook | /* Receiver command. */
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169 | 20dcee94 | pbrook | switch (cmd & 3) { |
170 | 20dcee94 | pbrook | case 0: /* No-op. */ |
171 | 20dcee94 | pbrook | break;
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172 | 20dcee94 | pbrook | case 1: /* Enable. */ |
173 | 20dcee94 | pbrook | s->rx_enabled = 1;
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174 | 20dcee94 | pbrook | break;
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175 | 20dcee94 | pbrook | case 2: |
176 | 20dcee94 | pbrook | s->rx_enabled = 0;
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177 | 20dcee94 | pbrook | break;
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178 | 20dcee94 | pbrook | case 3: /* Reserved. */ |
179 | 20dcee94 | pbrook | fprintf(stderr, "mcf_uart: Bad RX command\n");
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180 | 20dcee94 | pbrook | break;
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181 | 20dcee94 | pbrook | } |
182 | 20dcee94 | pbrook | } |
183 | 20dcee94 | pbrook | |
184 | 20dcee94 | pbrook | void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val) |
185 | 20dcee94 | pbrook | { |
186 | 20dcee94 | pbrook | mcf_uart_state *s = (mcf_uart_state *)opaque; |
187 | 20dcee94 | pbrook | switch (addr & 0x3f) { |
188 | 20dcee94 | pbrook | case 0x00: |
189 | 20dcee94 | pbrook | s->mr[s->current_mr] = val; |
190 | 20dcee94 | pbrook | s->current_mr = 1;
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191 | 20dcee94 | pbrook | break;
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192 | 20dcee94 | pbrook | case 0x04: |
193 | 20dcee94 | pbrook | /* CSR is ignored. */
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194 | 20dcee94 | pbrook | break;
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195 | 20dcee94 | pbrook | case 0x08: /* Command Register. */ |
196 | 20dcee94 | pbrook | mcf_do_command(s, val); |
197 | 20dcee94 | pbrook | break;
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198 | 20dcee94 | pbrook | case 0x0c: /* Transmit Buffer. */ |
199 | 20dcee94 | pbrook | s->sr &= ~MCF_UART_TxEMP; |
200 | 20dcee94 | pbrook | s->tb = val; |
201 | 20dcee94 | pbrook | mcf_uart_do_tx(s); |
202 | 20dcee94 | pbrook | break;
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203 | 20dcee94 | pbrook | case 0x10: |
204 | 20dcee94 | pbrook | /* ACR is ignored. */
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205 | 20dcee94 | pbrook | break;
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206 | 20dcee94 | pbrook | case 0x14: |
207 | 20dcee94 | pbrook | s->imr = val; |
208 | 20dcee94 | pbrook | break;
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209 | 20dcee94 | pbrook | default:
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210 | 20dcee94 | pbrook | break;
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211 | 20dcee94 | pbrook | } |
212 | 20dcee94 | pbrook | mcf_uart_update(s); |
213 | 20dcee94 | pbrook | } |
214 | 20dcee94 | pbrook | |
215 | 20dcee94 | pbrook | static void mcf_uart_reset(mcf_uart_state *s) |
216 | 20dcee94 | pbrook | { |
217 | 20dcee94 | pbrook | s->fifo_len = 0;
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218 | 20dcee94 | pbrook | s->mr[0] = 0; |
219 | 20dcee94 | pbrook | s->mr[1] = 0; |
220 | 20dcee94 | pbrook | s->sr = MCF_UART_TxEMP; |
221 | 20dcee94 | pbrook | s->tx_enabled = 0;
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222 | 20dcee94 | pbrook | s->rx_enabled = 0;
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223 | 20dcee94 | pbrook | s->isr = 0;
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224 | 20dcee94 | pbrook | s->imr = 0;
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225 | 20dcee94 | pbrook | } |
226 | 20dcee94 | pbrook | |
227 | 20dcee94 | pbrook | static void mcf_uart_push_byte(mcf_uart_state *s, uint8_t data) |
228 | 20dcee94 | pbrook | { |
229 | 20dcee94 | pbrook | /* Break events overwrite the last byte if the fifo is full. */
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230 | 20dcee94 | pbrook | if (s->fifo_len == 4) |
231 | 20dcee94 | pbrook | s->fifo_len--; |
232 | 20dcee94 | pbrook | |
233 | 20dcee94 | pbrook | s->fifo[s->fifo_len] = data; |
234 | 20dcee94 | pbrook | s->fifo_len++; |
235 | 20dcee94 | pbrook | s->sr |= MCF_UART_RxRDY; |
236 | 20dcee94 | pbrook | if (s->fifo_len == 4) |
237 | 20dcee94 | pbrook | s->sr |= MCF_UART_FFULL; |
238 | 20dcee94 | pbrook | |
239 | 20dcee94 | pbrook | mcf_uart_update(s); |
240 | 20dcee94 | pbrook | } |
241 | 20dcee94 | pbrook | |
242 | 20dcee94 | pbrook | static void mcf_uart_event(void *opaque, int event) |
243 | 20dcee94 | pbrook | { |
244 | 20dcee94 | pbrook | mcf_uart_state *s = (mcf_uart_state *)opaque; |
245 | 20dcee94 | pbrook | |
246 | 20dcee94 | pbrook | switch (event) {
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247 | 20dcee94 | pbrook | case CHR_EVENT_BREAK:
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248 | 20dcee94 | pbrook | s->isr |= MCF_UART_DBINT; |
249 | 20dcee94 | pbrook | mcf_uart_push_byte(s, 0);
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250 | 20dcee94 | pbrook | break;
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251 | 20dcee94 | pbrook | default:
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252 | 20dcee94 | pbrook | break;
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253 | 20dcee94 | pbrook | } |
254 | 20dcee94 | pbrook | } |
255 | 20dcee94 | pbrook | |
256 | 20dcee94 | pbrook | static int mcf_uart_can_receive(void *opaque) |
257 | 20dcee94 | pbrook | { |
258 | 20dcee94 | pbrook | mcf_uart_state *s = (mcf_uart_state *)opaque; |
259 | 20dcee94 | pbrook | |
260 | 20dcee94 | pbrook | return s->rx_enabled && (s->sr & MCF_UART_FFULL) == 0; |
261 | 20dcee94 | pbrook | } |
262 | 20dcee94 | pbrook | |
263 | 20dcee94 | pbrook | static void mcf_uart_receive(void *opaque, const uint8_t *buf, int size) |
264 | 20dcee94 | pbrook | { |
265 | 20dcee94 | pbrook | mcf_uart_state *s = (mcf_uart_state *)opaque; |
266 | 20dcee94 | pbrook | |
267 | 20dcee94 | pbrook | mcf_uart_push_byte(s, buf[0]);
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268 | 20dcee94 | pbrook | } |
269 | 20dcee94 | pbrook | |
270 | 20dcee94 | pbrook | void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
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271 | 20dcee94 | pbrook | { |
272 | 20dcee94 | pbrook | mcf_uart_state *s; |
273 | 20dcee94 | pbrook | |
274 | 20dcee94 | pbrook | s = qemu_mallocz(sizeof(mcf_uart_state));
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275 | 20dcee94 | pbrook | s->chr = chr; |
276 | 20dcee94 | pbrook | s->irq = irq; |
277 | 20dcee94 | pbrook | if (chr) {
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278 | 20dcee94 | pbrook | qemu_chr_add_handlers(chr, mcf_uart_can_receive, mcf_uart_receive, |
279 | 20dcee94 | pbrook | mcf_uart_event, s); |
280 | 20dcee94 | pbrook | } |
281 | 20dcee94 | pbrook | mcf_uart_reset(s); |
282 | 20dcee94 | pbrook | return s;
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283 | 20dcee94 | pbrook | } |
284 | 20dcee94 | pbrook | |
285 | 20dcee94 | pbrook | |
286 | 20dcee94 | pbrook | static CPUReadMemoryFunc *mcf_uart_readfn[] = {
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287 | 20dcee94 | pbrook | mcf_uart_read, |
288 | 20dcee94 | pbrook | mcf_uart_read, |
289 | 20dcee94 | pbrook | mcf_uart_read |
290 | 20dcee94 | pbrook | }; |
291 | 20dcee94 | pbrook | |
292 | 20dcee94 | pbrook | static CPUWriteMemoryFunc *mcf_uart_writefn[] = {
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293 | 20dcee94 | pbrook | mcf_uart_write, |
294 | 20dcee94 | pbrook | mcf_uart_write, |
295 | 20dcee94 | pbrook | mcf_uart_write |
296 | 20dcee94 | pbrook | }; |
297 | 20dcee94 | pbrook | |
298 | 20dcee94 | pbrook | void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
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299 | 20dcee94 | pbrook | CharDriverState *chr) |
300 | 20dcee94 | pbrook | { |
301 | 20dcee94 | pbrook | mcf_uart_state *s; |
302 | 20dcee94 | pbrook | int iomemtype;
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303 | 20dcee94 | pbrook | |
304 | 20dcee94 | pbrook | s = mcf_uart_init(irq, chr); |
305 | 20dcee94 | pbrook | iomemtype = cpu_register_io_memory(0, mcf_uart_readfn,
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306 | 20dcee94 | pbrook | mcf_uart_writefn, s); |
307 | 20dcee94 | pbrook | cpu_register_physical_memory(base, 0x40, iomemtype);
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308 | 20dcee94 | pbrook | } |