Archipelago » qemu

    uint8_t lcr;

    uint8_t mcr;

    uint8_t lsr; /* read only */

    uint8_t scr;

    /* NOTE: this hidden state is necessary for tx irq generation as

       it can be reset while reading iir */

    case 5:

        break;

    case 6:

        break;

    case 7:

        s->scr = val;

    s->irq = irq;

    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;

    s->iir = UART_IIR_NO_INT;

    register_savevm("serial", base, 1, serial_save, serial_load, s);

    s->irq = irq;

    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;

    s->iir = UART_IIR_NO_INT;

    s->base = base;

    s->it_shift = it_shift;