root / hw / pl031.c @ 3efda49d
History | View | Annotate | Download (5.4 kB)
1 |
/*
|
---|---|
2 |
* ARM AMBA PrimeCell PL031 RTC
|
3 |
*
|
4 |
* Copyright (c) 2007 CodeSourcery
|
5 |
*
|
6 |
* This file is free software; you can redistribute it and/or modify
|
7 |
* it under the terms of the GNU General Public License version 2 as
|
8 |
* published by the Free Software Foundation.
|
9 |
*
|
10 |
*/
|
11 |
|
12 |
#include"vl.h" |
13 |
|
14 |
//#define DEBUG_PL031
|
15 |
|
16 |
#ifdef DEBUG_PL031
|
17 |
#define DPRINTF(fmt, args...) \
|
18 |
do { printf("pl031: " fmt , ##args); } while (0) |
19 |
#else
|
20 |
#define DPRINTF(fmt, args...) do {} while(0) |
21 |
#endif
|
22 |
|
23 |
#define RTC_DR 0x00 /* Data read register */ |
24 |
#define RTC_MR 0x04 /* Match register */ |
25 |
#define RTC_LR 0x08 /* Data load register */ |
26 |
#define RTC_CR 0x0c /* Control register */ |
27 |
#define RTC_IMSC 0x10 /* Interrupt mask and set register */ |
28 |
#define RTC_RIS 0x14 /* Raw interrupt status register */ |
29 |
#define RTC_MIS 0x18 /* Masked interrupt status register */ |
30 |
#define RTC_ICR 0x1c /* Interrupt clear register */ |
31 |
|
32 |
typedef struct { |
33 |
QEMUTimer *timer; |
34 |
qemu_irq irq; |
35 |
uint32_t base; |
36 |
|
37 |
uint64_t start_time; |
38 |
uint32_t tick_offset; |
39 |
|
40 |
uint32_t mr; |
41 |
uint32_t lr; |
42 |
uint32_t cr; |
43 |
uint32_t im; |
44 |
uint32_t is; |
45 |
} pl031_state; |
46 |
|
47 |
static const unsigned char pl031_id[] = { |
48 |
0x31, 0x10, 0x14, 0x00, /* Device ID */ |
49 |
0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */ |
50 |
}; |
51 |
|
52 |
static void pl031_update(pl031_state *s) |
53 |
{ |
54 |
qemu_set_irq(s->irq, s->is & s->im); |
55 |
} |
56 |
|
57 |
static void pl031_interrupt(void * opaque) |
58 |
{ |
59 |
pl031_state *s = (pl031_state *)opaque; |
60 |
|
61 |
s->im = 1;
|
62 |
DPRINTF("Alarm raised\n");
|
63 |
pl031_update(s); |
64 |
} |
65 |
|
66 |
static uint32_t pl031_get_count(pl031_state *s)
|
67 |
{ |
68 |
/* This assumes qemu_get_clock returns the time since the machine was
|
69 |
created. */
|
70 |
return s->tick_offset + qemu_get_clock(vm_clock) / ticks_per_sec;
|
71 |
} |
72 |
|
73 |
static void pl031_set_alarm(pl031_state *s) |
74 |
{ |
75 |
int64_t now; |
76 |
uint32_t ticks; |
77 |
|
78 |
now = qemu_get_clock(vm_clock); |
79 |
ticks = s->tick_offset + now / ticks_per_sec; |
80 |
|
81 |
/* The timer wraps around. This subtraction also wraps in the same way,
|
82 |
and gives correct results when alarm < now_ticks. */
|
83 |
ticks = s->mr - ticks; |
84 |
DPRINTF("Alarm set in %ud ticks\n", ticks);
|
85 |
if (ticks == 0) { |
86 |
qemu_del_timer(s->timer); |
87 |
pl031_interrupt(s); |
88 |
} else {
|
89 |
qemu_mod_timer(s->timer, now + (int64_t)ticks * ticks_per_sec); |
90 |
} |
91 |
} |
92 |
|
93 |
static uint32_t pl031_read(void *opaque, target_phys_addr_t offset) |
94 |
{ |
95 |
pl031_state *s = (pl031_state *)opaque; |
96 |
|
97 |
offset -= s->base; |
98 |
|
99 |
if (offset >= 0xfe0 && offset < 0x1000) |
100 |
return pl031_id[(offset - 0xfe0) >> 2]; |
101 |
|
102 |
switch (offset) {
|
103 |
case RTC_DR:
|
104 |
return pl031_get_count(s);
|
105 |
case RTC_MR:
|
106 |
return s->mr;
|
107 |
case RTC_IMSC:
|
108 |
return s->im;
|
109 |
case RTC_RIS:
|
110 |
return s->is;
|
111 |
case RTC_LR:
|
112 |
return s->lr;
|
113 |
case RTC_CR:
|
114 |
/* RTC is permanently enabled. */
|
115 |
return 1; |
116 |
case RTC_MIS:
|
117 |
return s->is & s->im;
|
118 |
case RTC_ICR:
|
119 |
fprintf(stderr, "qemu: pl031_read: Unexpected offset 0x%x\n",
|
120 |
(int)offset);
|
121 |
break;
|
122 |
default:
|
123 |
cpu_abort(cpu_single_env, "pl031_read: Bad offset 0x%x\n",
|
124 |
(int)offset);
|
125 |
break;
|
126 |
} |
127 |
|
128 |
return 0; |
129 |
} |
130 |
|
131 |
static void pl031_write(void * opaque, target_phys_addr_t offset, |
132 |
uint32_t value) |
133 |
{ |
134 |
pl031_state *s = (pl031_state *)opaque; |
135 |
|
136 |
offset -= s->base; |
137 |
|
138 |
switch (offset) {
|
139 |
case RTC_LR:
|
140 |
s->tick_offset += value - pl031_get_count(s); |
141 |
pl031_set_alarm(s); |
142 |
break;
|
143 |
case RTC_MR:
|
144 |
s->mr = value; |
145 |
pl031_set_alarm(s); |
146 |
break;
|
147 |
case RTC_IMSC:
|
148 |
s->im = value & 1;
|
149 |
DPRINTF("Interrupt mask %d\n", s->im);
|
150 |
pl031_update(s); |
151 |
break;
|
152 |
case RTC_ICR:
|
153 |
/* The PL031 documentation (DDI0224B) states that the interupt is
|
154 |
cleared when bit 0 of the written value is set. However the
|
155 |
arm926e documentation (DDI0287B) states that the interrupt is
|
156 |
cleared when any value is written. */
|
157 |
DPRINTF("Interrupt cleared");
|
158 |
s->is = 0;
|
159 |
pl031_update(s); |
160 |
break;
|
161 |
case RTC_CR:
|
162 |
/* Written value is ignored. */
|
163 |
break;
|
164 |
|
165 |
case RTC_DR:
|
166 |
case RTC_MIS:
|
167 |
case RTC_RIS:
|
168 |
fprintf(stderr, "qemu: pl031_write: Unexpected offset 0x%x\n",
|
169 |
(int)offset);
|
170 |
break;
|
171 |
|
172 |
default:
|
173 |
cpu_abort(cpu_single_env, "pl031_write: Bad offset 0x%x\n",
|
174 |
(int)offset);
|
175 |
break;
|
176 |
} |
177 |
} |
178 |
|
179 |
static CPUWriteMemoryFunc * pl031_writefn[] = {
|
180 |
pl031_write, |
181 |
pl031_write, |
182 |
pl031_write |
183 |
}; |
184 |
|
185 |
static CPUReadMemoryFunc * pl031_readfn[] = {
|
186 |
pl031_read, |
187 |
pl031_read, |
188 |
pl031_read |
189 |
}; |
190 |
|
191 |
void pl031_init(uint32_t base, qemu_irq irq)
|
192 |
{ |
193 |
int iomemtype;
|
194 |
pl031_state *s; |
195 |
time_t ti; |
196 |
struct tm *tm;
|
197 |
|
198 |
s = qemu_mallocz(sizeof(pl031_state));
|
199 |
if (!s)
|
200 |
cpu_abort(cpu_single_env, "pl031_init: Out of memory\n");
|
201 |
|
202 |
iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s);
|
203 |
if (iomemtype == -1) |
204 |
cpu_abort(cpu_single_env, "pl031_init: Can't register I/O memory\n");
|
205 |
|
206 |
cpu_register_physical_memory(base, 0x00001000, iomemtype);
|
207 |
|
208 |
s->base = base; |
209 |
s->irq = irq; |
210 |
/* ??? We assume vm_clock is zero at this point. */
|
211 |
time(&ti); |
212 |
if (rtc_utc)
|
213 |
tm = gmtime(&ti); |
214 |
else
|
215 |
tm = localtime(&ti); |
216 |
s->tick_offset = mktime(tm); |
217 |
|
218 |
s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s); |
219 |
} |