Revision 3f0436fe
| b/target-sparc/translate.c | ||
|---|---|---|
| 1918 | 1918 |
|
| 1919 | 1919 |
// loads and stores |
| 1920 | 1920 |
cpu_addr = cpu_T[0]; |
| 1921 |
cpu_val = cpu_T[1]; |
|
| 1922 | 1921 |
|
| 1923 | 1922 |
switch (opc) {
|
| 1924 | 1923 |
case 0: /* branches/sethi */ |
| ... | ... | |
| 4745 | 4744 |
cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL); |
| 4746 | 4745 |
cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32); |
| 4747 | 4746 |
cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64); |
| 4747 |
cpu_val = tcg_temp_local_new(TCG_TYPE_TL); |
|
| 4748 | 4748 |
|
| 4749 | 4749 |
do {
|
| 4750 | 4750 |
if (env->nb_breakpoints > 0) {
|
| ... | ... | |
| 4795 | 4795 |
(dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32)); |
| 4796 | 4796 |
|
| 4797 | 4797 |
exit_gen_loop: |
| 4798 |
tcg_temp_free(cpu_val); |
|
| 4798 | 4799 |
tcg_temp_free(cpu_tmp64); |
| 4799 | 4800 |
tcg_temp_free(cpu_tmp32); |
| 4800 | 4801 |
tcg_temp_free(cpu_tmp0); |
| ... | ... | |
| 4875 | 4876 |
TCG_AREG0, offsetof(CPUState, xcc), |
| 4876 | 4877 |
"xcc"); |
| 4877 | 4878 |
#endif |
| 4878 |
/* XXX: T0 and T1 should be temporaries */
|
|
| 4879 |
/* XXX: T0 should be a temporary */
|
|
| 4879 | 4880 |
cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL, |
| 4880 | 4881 |
TCG_AREG0, offsetof(CPUState, t0), "T0"); |
| 4881 |
cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4882 |
TCG_AREG0, offsetof(CPUState, t1), "T1"); |
|
| 4883 | 4882 |
cpu_cond = tcg_global_mem_new(TCG_TYPE_TL, |
| 4884 | 4883 |
TCG_AREG0, offsetof(CPUState, cond), |
| 4885 | 4884 |
"cond"); |
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