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1 | b92e5a22 | bellard | /*
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2 | b92e5a22 | bellard | * Software MMU support
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3 | b92e5a22 | bellard | *
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4 | b92e5a22 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | b92e5a22 | bellard | *
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6 | b92e5a22 | bellard | * This library is free software; you can redistribute it and/or
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7 | b92e5a22 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | b92e5a22 | bellard | * License as published by the Free Software Foundation; either
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9 | b92e5a22 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | b92e5a22 | bellard | *
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11 | b92e5a22 | bellard | * This library is distributed in the hope that it will be useful,
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12 | b92e5a22 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | b92e5a22 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | b92e5a22 | bellard | * Lesser General Public License for more details.
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15 | b92e5a22 | bellard | *
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16 | b92e5a22 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | b92e5a22 | bellard | * License along with this library; if not, write to the Free Software
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18 | b92e5a22 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | b92e5a22 | bellard | */
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20 | b92e5a22 | bellard | #define DATA_SIZE (1 << SHIFT) |
21 | b92e5a22 | bellard | |
22 | b92e5a22 | bellard | #if DATA_SIZE == 8 |
23 | b92e5a22 | bellard | #define SUFFIX q
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24 | 61382a50 | bellard | #define USUFFIX q
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25 | b92e5a22 | bellard | #define DATA_TYPE uint64_t
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26 | b92e5a22 | bellard | #elif DATA_SIZE == 4 |
27 | b92e5a22 | bellard | #define SUFFIX l
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28 | 61382a50 | bellard | #define USUFFIX l
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29 | b92e5a22 | bellard | #define DATA_TYPE uint32_t
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30 | b92e5a22 | bellard | #elif DATA_SIZE == 2 |
31 | b92e5a22 | bellard | #define SUFFIX w
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32 | 61382a50 | bellard | #define USUFFIX uw
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33 | b92e5a22 | bellard | #define DATA_TYPE uint16_t
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34 | b92e5a22 | bellard | #elif DATA_SIZE == 1 |
35 | b92e5a22 | bellard | #define SUFFIX b
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36 | 61382a50 | bellard | #define USUFFIX ub
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37 | b92e5a22 | bellard | #define DATA_TYPE uint8_t
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38 | b92e5a22 | bellard | #else
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39 | b92e5a22 | bellard | #error unsupported data size
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40 | b92e5a22 | bellard | #endif
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41 | b92e5a22 | bellard | |
42 | b769d8fe | bellard | #ifdef SOFTMMU_CODE_ACCESS
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43 | b769d8fe | bellard | #define READ_ACCESS_TYPE 2 |
44 | b769d8fe | bellard | #else
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45 | b769d8fe | bellard | #define READ_ACCESS_TYPE 0 |
46 | b769d8fe | bellard | #endif
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47 | b769d8fe | bellard | |
48 | c27004ec | bellard | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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49 | 61382a50 | bellard | int is_user,
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50 | 61382a50 | bellard | void *retaddr);
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51 | 108c49b8 | bellard | static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr, |
52 | c27004ec | bellard | target_ulong tlb_addr) |
53 | b92e5a22 | bellard | { |
54 | b92e5a22 | bellard | DATA_TYPE res; |
55 | b92e5a22 | bellard | int index;
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56 | b92e5a22 | bellard | |
57 | b92e5a22 | bellard | index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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58 | b92e5a22 | bellard | #if SHIFT <= 2 |
59 | a4193c8a | bellard | res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr); |
60 | b92e5a22 | bellard | #else
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61 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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62 | a4193c8a | bellard | res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32; |
63 | a4193c8a | bellard | res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4); |
64 | b92e5a22 | bellard | #else
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65 | a4193c8a | bellard | res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
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66 | a4193c8a | bellard | res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32; |
67 | b92e5a22 | bellard | #endif
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68 | b92e5a22 | bellard | #endif /* SHIFT > 2 */ |
69 | b92e5a22 | bellard | return res;
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70 | b92e5a22 | bellard | } |
71 | b92e5a22 | bellard | |
72 | b92e5a22 | bellard | /* handle all cases except unaligned access which span two pages */
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73 | c27004ec | bellard | DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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74 | 61382a50 | bellard | int is_user)
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75 | b92e5a22 | bellard | { |
76 | b92e5a22 | bellard | DATA_TYPE res; |
77 | 61382a50 | bellard | int index;
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78 | c27004ec | bellard | target_ulong tlb_addr; |
79 | 108c49b8 | bellard | target_phys_addr_t physaddr; |
80 | b92e5a22 | bellard | void *retaddr;
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81 | b92e5a22 | bellard | |
82 | b92e5a22 | bellard | /* test if there is match for unaligned or IO access */
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83 | b92e5a22 | bellard | /* XXX: could done more in memory macro in a non portable way */
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84 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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85 | b92e5a22 | bellard | redo:
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86 | b92e5a22 | bellard | tlb_addr = env->tlb_read[is_user][index].address; |
87 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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88 | b92e5a22 | bellard | physaddr = addr + env->tlb_read[is_user][index].addend; |
89 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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90 | b92e5a22 | bellard | /* IO access */
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91 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
92 | b92e5a22 | bellard | goto do_unaligned_access;
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93 | b92e5a22 | bellard | res = glue(io_read, SUFFIX)(physaddr, tlb_addr); |
94 | b92e5a22 | bellard | } else if (((addr & 0xfff) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
95 | b92e5a22 | bellard | /* slow unaligned access (it spans two pages or IO) */
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96 | b92e5a22 | bellard | do_unaligned_access:
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97 | 61382a50 | bellard | retaddr = GETPC(); |
98 | 61382a50 | bellard | res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr, |
99 | 61382a50 | bellard | is_user, retaddr); |
100 | b92e5a22 | bellard | } else {
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101 | b92e5a22 | bellard | /* unaligned access in the same page */
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102 | 108c49b8 | bellard | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
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103 | b92e5a22 | bellard | } |
104 | b92e5a22 | bellard | } else {
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105 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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106 | 61382a50 | bellard | retaddr = GETPC(); |
107 | b769d8fe | bellard | tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr); |
108 | b92e5a22 | bellard | goto redo;
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109 | b92e5a22 | bellard | } |
110 | b92e5a22 | bellard | return res;
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111 | b92e5a22 | bellard | } |
112 | b92e5a22 | bellard | |
113 | b92e5a22 | bellard | /* handle all unaligned cases */
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114 | c27004ec | bellard | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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115 | 61382a50 | bellard | int is_user,
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116 | 61382a50 | bellard | void *retaddr)
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117 | b92e5a22 | bellard | { |
118 | b92e5a22 | bellard | DATA_TYPE res, res1, res2; |
119 | 61382a50 | bellard | int index, shift;
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120 | 108c49b8 | bellard | target_phys_addr_t physaddr; |
121 | c27004ec | bellard | target_ulong tlb_addr, addr1, addr2; |
122 | b92e5a22 | bellard | |
123 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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124 | b92e5a22 | bellard | redo:
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125 | b92e5a22 | bellard | tlb_addr = env->tlb_read[is_user][index].address; |
126 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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127 | b92e5a22 | bellard | physaddr = addr + env->tlb_read[is_user][index].addend; |
128 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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129 | b92e5a22 | bellard | /* IO access */
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130 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
131 | b92e5a22 | bellard | goto do_unaligned_access;
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132 | b92e5a22 | bellard | res = glue(io_read, SUFFIX)(physaddr, tlb_addr); |
133 | b92e5a22 | bellard | } else if (((addr & 0xfff) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
134 | b92e5a22 | bellard | do_unaligned_access:
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135 | b92e5a22 | bellard | /* slow unaligned access (it spans two pages) */
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136 | b92e5a22 | bellard | addr1 = addr & ~(DATA_SIZE - 1);
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137 | b92e5a22 | bellard | addr2 = addr1 + DATA_SIZE; |
138 | 61382a50 | bellard | res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1, |
139 | 61382a50 | bellard | is_user, retaddr); |
140 | 61382a50 | bellard | res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2, |
141 | 61382a50 | bellard | is_user, retaddr); |
142 | b92e5a22 | bellard | shift = (addr & (DATA_SIZE - 1)) * 8; |
143 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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144 | b92e5a22 | bellard | res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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145 | b92e5a22 | bellard | #else
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146 | b92e5a22 | bellard | res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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147 | b92e5a22 | bellard | #endif
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148 | 6986f88c | bellard | res = (DATA_TYPE)res; |
149 | b92e5a22 | bellard | } else {
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150 | b92e5a22 | bellard | /* unaligned/aligned access in the same page */
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151 | 108c49b8 | bellard | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
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152 | b92e5a22 | bellard | } |
153 | b92e5a22 | bellard | } else {
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154 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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155 | b769d8fe | bellard | tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr); |
156 | b92e5a22 | bellard | goto redo;
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157 | b92e5a22 | bellard | } |
158 | b92e5a22 | bellard | return res;
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159 | b92e5a22 | bellard | } |
160 | b92e5a22 | bellard | |
161 | b769d8fe | bellard | #ifndef SOFTMMU_CODE_ACCESS
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162 | b769d8fe | bellard | |
163 | c27004ec | bellard | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, |
164 | b769d8fe | bellard | DATA_TYPE val, |
165 | b769d8fe | bellard | int is_user,
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166 | b769d8fe | bellard | void *retaddr);
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167 | b769d8fe | bellard | |
168 | 108c49b8 | bellard | static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr, |
169 | b769d8fe | bellard | DATA_TYPE val, |
170 | c27004ec | bellard | target_ulong tlb_addr, |
171 | b769d8fe | bellard | void *retaddr)
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172 | b769d8fe | bellard | { |
173 | b769d8fe | bellard | int index;
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174 | b769d8fe | bellard | |
175 | b769d8fe | bellard | index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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176 | b769d8fe | bellard | env->mem_write_vaddr = tlb_addr; |
177 | b769d8fe | bellard | env->mem_write_pc = (unsigned long)retaddr; |
178 | b769d8fe | bellard | #if SHIFT <= 2 |
179 | b769d8fe | bellard | io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val); |
180 | b769d8fe | bellard | #else
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181 | b769d8fe | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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182 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32); |
183 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val); |
184 | b769d8fe | bellard | #else
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185 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
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186 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32); |
187 | b769d8fe | bellard | #endif
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188 | b769d8fe | bellard | #endif /* SHIFT > 2 */ |
189 | b769d8fe | bellard | } |
190 | b92e5a22 | bellard | |
191 | c27004ec | bellard | void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, |
192 | 61382a50 | bellard | DATA_TYPE val, |
193 | 61382a50 | bellard | int is_user)
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194 | b92e5a22 | bellard | { |
195 | 108c49b8 | bellard | target_phys_addr_t physaddr; |
196 | c27004ec | bellard | target_ulong tlb_addr; |
197 | b92e5a22 | bellard | void *retaddr;
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198 | 61382a50 | bellard | int index;
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199 | b92e5a22 | bellard | |
200 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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201 | b92e5a22 | bellard | redo:
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202 | b92e5a22 | bellard | tlb_addr = env->tlb_write[is_user][index].address; |
203 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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204 | 4ad06a29 | bellard | physaddr = addr + env->tlb_write[is_user][index].addend; |
205 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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206 | b92e5a22 | bellard | /* IO access */
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207 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
208 | b92e5a22 | bellard | goto do_unaligned_access;
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209 | d720b93d | bellard | retaddr = GETPC(); |
210 | d720b93d | bellard | glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr); |
211 | b92e5a22 | bellard | } else if (((addr & 0xfff) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
212 | b92e5a22 | bellard | do_unaligned_access:
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213 | 61382a50 | bellard | retaddr = GETPC(); |
214 | 61382a50 | bellard | glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val, |
215 | 61382a50 | bellard | is_user, retaddr); |
216 | b92e5a22 | bellard | } else {
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217 | b92e5a22 | bellard | /* aligned/unaligned access in the same page */
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218 | 108c49b8 | bellard | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
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219 | b92e5a22 | bellard | } |
220 | b92e5a22 | bellard | } else {
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221 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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222 | 61382a50 | bellard | retaddr = GETPC(); |
223 | 61382a50 | bellard | tlb_fill(addr, 1, is_user, retaddr);
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224 | b92e5a22 | bellard | goto redo;
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225 | b92e5a22 | bellard | } |
226 | b92e5a22 | bellard | } |
227 | b92e5a22 | bellard | |
228 | b92e5a22 | bellard | /* handles all unaligned cases */
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229 | c27004ec | bellard | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, |
230 | 61382a50 | bellard | DATA_TYPE val, |
231 | 61382a50 | bellard | int is_user,
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232 | 61382a50 | bellard | void *retaddr)
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233 | b92e5a22 | bellard | { |
234 | 108c49b8 | bellard | target_phys_addr_t physaddr; |
235 | c27004ec | bellard | target_ulong tlb_addr; |
236 | 61382a50 | bellard | int index, i;
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237 | b92e5a22 | bellard | |
238 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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239 | b92e5a22 | bellard | redo:
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240 | b92e5a22 | bellard | tlb_addr = env->tlb_write[is_user][index].address; |
241 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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242 | 4ad06a29 | bellard | physaddr = addr + env->tlb_write[is_user][index].addend; |
243 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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244 | b92e5a22 | bellard | /* IO access */
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245 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
246 | b92e5a22 | bellard | goto do_unaligned_access;
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247 | d720b93d | bellard | glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr); |
248 | b92e5a22 | bellard | } else if (((addr & 0xfff) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
249 | b92e5a22 | bellard | do_unaligned_access:
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250 | b92e5a22 | bellard | /* XXX: not efficient, but simple */
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251 | b92e5a22 | bellard | for(i = 0;i < DATA_SIZE; i++) { |
252 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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253 | 61382a50 | bellard | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)), |
254 | 61382a50 | bellard | is_user, retaddr); |
255 | b92e5a22 | bellard | #else
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256 | 61382a50 | bellard | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
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257 | 61382a50 | bellard | is_user, retaddr); |
258 | b92e5a22 | bellard | #endif
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259 | b92e5a22 | bellard | } |
260 | b92e5a22 | bellard | } else {
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261 | b92e5a22 | bellard | /* aligned/unaligned access in the same page */
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262 | 108c49b8 | bellard | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
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263 | b92e5a22 | bellard | } |
264 | b92e5a22 | bellard | } else {
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265 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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266 | 61382a50 | bellard | tlb_fill(addr, 1, is_user, retaddr);
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267 | b92e5a22 | bellard | goto redo;
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268 | b92e5a22 | bellard | } |
269 | b92e5a22 | bellard | } |
270 | b92e5a22 | bellard | |
271 | b769d8fe | bellard | #endif /* !defined(SOFTMMU_CODE_ACCESS) */ |
272 | b769d8fe | bellard | |
273 | b769d8fe | bellard | #undef READ_ACCESS_TYPE
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274 | b92e5a22 | bellard | #undef SHIFT
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275 | b92e5a22 | bellard | #undef DATA_TYPE
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276 | b92e5a22 | bellard | #undef SUFFIX
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277 | 61382a50 | bellard | #undef USUFFIX
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278 | b92e5a22 | bellard | #undef DATA_SIZE |