Revision 3f2cbf0d

b/target-i386/cpu.h
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#define PG_DIRTY_MASK	 (1 << PG_DIRTY_BIT)
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#define PG_PSE_MASK	 (1 << PG_PSE_BIT)
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#define PG_GLOBAL_MASK	 (1 << PG_GLOBAL_BIT)
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#define PG_HI_USER_MASK  0x7ff0000000000000LL
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#define PG_NX_MASK	 (1LL << PG_NX_BIT)
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#define PG_ERROR_W_BIT     1
b/target-i386/helper.c
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            if (!(pml4e & PG_PRESENT_MASK))
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                return -1;
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            pdpe_addr = ((pml4e & ~0xfff) + (((addr >> 30) & 0x1ff) << 3)) &
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                env->a20_mask;
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            pdpe_addr = ((pml4e & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
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                         (((addr >> 30) & 0x1ff) << 3)) & env->a20_mask;
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            pdpe = ldq_phys(pdpe_addr);
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            if (!(pdpe & PG_PRESENT_MASK))
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                return -1;
......
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                return -1;
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        }
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        pde_addr = ((pdpe & ~0xfff) + (((addr >> 21) & 0x1ff) << 3)) &
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            env->a20_mask;
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        pde_addr = ((pdpe & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
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                    (((addr >> 21) & 0x1ff) << 3)) & env->a20_mask;
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        pde = ldq_phys(pde_addr);
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        if (!(pde & PG_PRESENT_MASK)) {
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            return -1;
......
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            pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
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        } else {
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            /* 4 KB page */
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            pte_addr = ((pde & ~0xfff) + (((addr >> 12) & 0x1ff) << 3)) &
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                env->a20_mask;
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            pte_addr = ((pde & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
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                        (((addr >> 12) & 0x1ff) << 3)) & env->a20_mask;
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            page_size = 4096;
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            pte = ldq_phys(pte_addr);
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        }
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        pte &= ~(PG_NX_MASK | PG_HI_USER_MASK);
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        if (!(pte & PG_PRESENT_MASK))
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            return -1;
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    } else {

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