Revision 3f2cbf0d
b/target-i386/cpu.h | ||
---|---|---|
241 | 241 |
#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
242 | 242 |
#define PG_PSE_MASK (1 << PG_PSE_BIT) |
243 | 243 |
#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) |
244 |
#define PG_HI_USER_MASK 0x7ff0000000000000LL |
|
244 | 245 |
#define PG_NX_MASK (1LL << PG_NX_BIT) |
245 | 246 |
|
246 | 247 |
#define PG_ERROR_W_BIT 1 |
b/target-i386/helper.c | ||
---|---|---|
885 | 885 |
if (!(pml4e & PG_PRESENT_MASK)) |
886 | 886 |
return -1; |
887 | 887 |
|
888 |
pdpe_addr = ((pml4e & ~0xfff) + (((addr >> 30) & 0x1ff) << 3)) &
|
|
889 |
env->a20_mask; |
|
888 |
pdpe_addr = ((pml4e & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
|
|
889 |
(((addr >> 30) & 0x1ff) << 3)) & env->a20_mask;
|
|
890 | 890 |
pdpe = ldq_phys(pdpe_addr); |
891 | 891 |
if (!(pdpe & PG_PRESENT_MASK)) |
892 | 892 |
return -1; |
... | ... | |
900 | 900 |
return -1; |
901 | 901 |
} |
902 | 902 |
|
903 |
pde_addr = ((pdpe & ~0xfff) + (((addr >> 21) & 0x1ff) << 3)) &
|
|
904 |
env->a20_mask; |
|
903 |
pde_addr = ((pdpe & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
|
|
904 |
(((addr >> 21) & 0x1ff) << 3)) & env->a20_mask;
|
|
905 | 905 |
pde = ldq_phys(pde_addr); |
906 | 906 |
if (!(pde & PG_PRESENT_MASK)) { |
907 | 907 |
return -1; |
... | ... | |
912 | 912 |
pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */ |
913 | 913 |
} else { |
914 | 914 |
/* 4 KB page */ |
915 |
pte_addr = ((pde & ~0xfff) + (((addr >> 12) & 0x1ff) << 3)) &
|
|
916 |
env->a20_mask; |
|
915 |
pte_addr = ((pde & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
|
|
916 |
(((addr >> 12) & 0x1ff) << 3)) & env->a20_mask;
|
|
917 | 917 |
page_size = 4096; |
918 | 918 |
pte = ldq_phys(pte_addr); |
919 | 919 |
} |
920 |
pte &= ~(PG_NX_MASK | PG_HI_USER_MASK); |
|
920 | 921 |
if (!(pte & PG_PRESENT_MASK)) |
921 | 922 |
return -1; |
922 | 923 |
} else { |
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