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1 | c3d2689d | balrog | /*
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2 | c3d2689d | balrog | * TI OMAP processors emulation.
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3 | c3d2689d | balrog | *
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4 | c3d2689d | balrog | * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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5 | c3d2689d | balrog | *
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6 | c3d2689d | balrog | * This program is free software; you can redistribute it and/or
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7 | c3d2689d | balrog | * modify it under the terms of the GNU General Public License as
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8 | c3d2689d | balrog | * published by the Free Software Foundation; either version 2 of
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9 | c3d2689d | balrog | * the License, or (at your option) any later version.
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10 | c3d2689d | balrog | *
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11 | c3d2689d | balrog | * This program is distributed in the hope that it will be useful,
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12 | c3d2689d | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | c3d2689d | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | c3d2689d | balrog | * GNU General Public License for more details.
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15 | c3d2689d | balrog | *
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16 | c3d2689d | balrog | * You should have received a copy of the GNU General Public License
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17 | c3d2689d | balrog | * along with this program; if not, write to the Free Software
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18 | c3d2689d | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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19 | c3d2689d | balrog | * MA 02111-1307 USA
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20 | c3d2689d | balrog | */
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21 | 87ecb68b | pbrook | #include "hw.h" |
22 | 87ecb68b | pbrook | #include "arm-misc.h" |
23 | 87ecb68b | pbrook | #include "omap.h" |
24 | 87ecb68b | pbrook | #include "sysemu.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | /* We use pc-style serial ports. */
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27 | 87ecb68b | pbrook | #include "pc.h" |
28 | c3d2689d | balrog | |
29 | c3d2689d | balrog | /* Should signal the TCMI */
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30 | 66450b15 | balrog | uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
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31 | 66450b15 | balrog | { |
32 | 02645926 | balrog | uint8_t ret; |
33 | 02645926 | balrog | |
34 | 66450b15 | balrog | OMAP_8B_REG(addr); |
35 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 1); |
36 | 02645926 | balrog | return ret;
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37 | 66450b15 | balrog | } |
38 | 66450b15 | balrog | |
39 | 66450b15 | balrog | void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, |
40 | 66450b15 | balrog | uint32_t value) |
41 | 66450b15 | balrog | { |
42 | b854bc19 | balrog | uint8_t val8 = value; |
43 | b854bc19 | balrog | |
44 | 66450b15 | balrog | OMAP_8B_REG(addr); |
45 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &val8, 1); |
46 | 66450b15 | balrog | } |
47 | 66450b15 | balrog | |
48 | b30bb3a2 | balrog | uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
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49 | c3d2689d | balrog | { |
50 | b854bc19 | balrog | uint16_t ret; |
51 | b854bc19 | balrog | |
52 | c3d2689d | balrog | OMAP_16B_REG(addr); |
53 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 2); |
54 | b854bc19 | balrog | return ret;
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55 | c3d2689d | balrog | } |
56 | c3d2689d | balrog | |
57 | b30bb3a2 | balrog | void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
58 | c3d2689d | balrog | uint32_t value) |
59 | c3d2689d | balrog | { |
60 | b854bc19 | balrog | uint16_t val16 = value; |
61 | b854bc19 | balrog | |
62 | c3d2689d | balrog | OMAP_16B_REG(addr); |
63 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &val16, 2); |
64 | c3d2689d | balrog | } |
65 | c3d2689d | balrog | |
66 | b30bb3a2 | balrog | uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
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67 | c3d2689d | balrog | { |
68 | b854bc19 | balrog | uint32_t ret; |
69 | b854bc19 | balrog | |
70 | c3d2689d | balrog | OMAP_32B_REG(addr); |
71 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 4); |
72 | b854bc19 | balrog | return ret;
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73 | c3d2689d | balrog | } |
74 | c3d2689d | balrog | |
75 | b30bb3a2 | balrog | void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
76 | c3d2689d | balrog | uint32_t value) |
77 | c3d2689d | balrog | { |
78 | c3d2689d | balrog | OMAP_32B_REG(addr); |
79 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &value, 4); |
80 | c3d2689d | balrog | } |
81 | c3d2689d | balrog | |
82 | c3d2689d | balrog | /* Interrupt Handlers */
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83 | c3d2689d | balrog | struct omap_intr_handler_s {
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84 | c3d2689d | balrog | qemu_irq *pins; |
85 | c3d2689d | balrog | qemu_irq *parent_pic; |
86 | c3d2689d | balrog | target_phys_addr_t base; |
87 | c3d2689d | balrog | |
88 | c3d2689d | balrog | /* state */
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89 | c3d2689d | balrog | uint32_t irqs; |
90 | c3d2689d | balrog | uint32_t mask; |
91 | c3d2689d | balrog | uint32_t sens_edge; |
92 | c3d2689d | balrog | uint32_t fiq; |
93 | c3d2689d | balrog | int priority[32]; |
94 | c3d2689d | balrog | uint32_t new_irq_agr; |
95 | c3d2689d | balrog | uint32_t new_fiq_agr; |
96 | c3d2689d | balrog | int sir_irq;
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97 | c3d2689d | balrog | int sir_fiq;
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98 | c3d2689d | balrog | int stats[32]; |
99 | c3d2689d | balrog | }; |
100 | c3d2689d | balrog | |
101 | c3d2689d | balrog | static void omap_inth_update(struct omap_intr_handler_s *s) |
102 | c3d2689d | balrog | { |
103 | cfa0b71d | balrog | uint32_t irq = s->irqs & ~s->mask & ~s->fiq; |
104 | cfa0b71d | balrog | uint32_t fiq = s->irqs & ~s->mask & s->fiq; |
105 | c3d2689d | balrog | |
106 | cfa0b71d | balrog | if (s->new_irq_agr || !irq) {
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107 | cfa0b71d | balrog | qemu_set_irq(s->parent_pic[ARM_PIC_CPU_IRQ], irq); |
108 | cfa0b71d | balrog | if (irq)
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109 | cfa0b71d | balrog | s->new_irq_agr = 0;
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110 | cfa0b71d | balrog | } |
111 | c3d2689d | balrog | |
112 | cfa0b71d | balrog | if (s->new_fiq_agr || !irq) {
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113 | cfa0b71d | balrog | qemu_set_irq(s->parent_pic[ARM_PIC_CPU_FIQ], fiq); |
114 | cfa0b71d | balrog | if (fiq)
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115 | cfa0b71d | balrog | s->new_fiq_agr = 0;
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116 | cfa0b71d | balrog | } |
117 | c3d2689d | balrog | } |
118 | c3d2689d | balrog | |
119 | c3d2689d | balrog | static void omap_inth_sir_update(struct omap_intr_handler_s *s) |
120 | c3d2689d | balrog | { |
121 | c3d2689d | balrog | int i, intr_irq, intr_fiq, p_irq, p_fiq, p, f;
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122 | c3d2689d | balrog | uint32_t level = s->irqs & ~s->mask; |
123 | c3d2689d | balrog | |
124 | c3d2689d | balrog | intr_irq = 0;
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125 | c3d2689d | balrog | intr_fiq = 0;
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126 | c3d2689d | balrog | p_irq = -1;
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127 | c3d2689d | balrog | p_fiq = -1;
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128 | c3d2689d | balrog | /* Find the interrupt line with the highest dynamic priority */
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129 | c3d2689d | balrog | for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, level >>= f) { |
130 | c3d2689d | balrog | p = s->priority[i]; |
131 | c3d2689d | balrog | if (s->fiq & (1 << i)) { |
132 | c3d2689d | balrog | if (p > p_fiq) {
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133 | c3d2689d | balrog | p_fiq = p; |
134 | c3d2689d | balrog | intr_fiq = i; |
135 | c3d2689d | balrog | } |
136 | c3d2689d | balrog | } else {
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137 | c3d2689d | balrog | if (p > p_irq) {
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138 | c3d2689d | balrog | p_irq = p; |
139 | c3d2689d | balrog | intr_irq = i; |
140 | c3d2689d | balrog | } |
141 | c3d2689d | balrog | } |
142 | c3d2689d | balrog | |
143 | c3d2689d | balrog | f = ffs(level >> 1);
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144 | c3d2689d | balrog | } |
145 | c3d2689d | balrog | |
146 | c3d2689d | balrog | s->sir_irq = intr_irq; |
147 | c3d2689d | balrog | s->sir_fiq = intr_fiq; |
148 | c3d2689d | balrog | } |
149 | c3d2689d | balrog | |
150 | c3d2689d | balrog | #define INT_FALLING_EDGE 0 |
151 | c3d2689d | balrog | #define INT_LOW_LEVEL 1 |
152 | c3d2689d | balrog | |
153 | c3d2689d | balrog | static void omap_set_intr(void *opaque, int irq, int req) |
154 | c3d2689d | balrog | { |
155 | c3d2689d | balrog | struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
156 | c3d2689d | balrog | uint32_t rise; |
157 | c3d2689d | balrog | |
158 | c3d2689d | balrog | if (req) {
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159 | c3d2689d | balrog | rise = ~ih->irqs & (1 << irq);
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160 | c3d2689d | balrog | ih->irqs |= rise; |
161 | cfa0b71d | balrog | ih->stats[irq] += !!rise; |
162 | c3d2689d | balrog | } else {
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163 | c3d2689d | balrog | rise = ih->sens_edge & ih->irqs & (1 << irq);
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164 | c3d2689d | balrog | ih->irqs &= ~rise; |
165 | c3d2689d | balrog | } |
166 | c3d2689d | balrog | |
167 | c3d2689d | balrog | if (rise & ~ih->mask) {
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168 | c3d2689d | balrog | omap_inth_sir_update(ih); |
169 | c3d2689d | balrog | |
170 | c3d2689d | balrog | omap_inth_update(ih); |
171 | c3d2689d | balrog | } |
172 | c3d2689d | balrog | } |
173 | c3d2689d | balrog | |
174 | c3d2689d | balrog | static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) |
175 | c3d2689d | balrog | { |
176 | c3d2689d | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
177 | c3d2689d | balrog | int i, offset = addr - s->base;
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178 | c3d2689d | balrog | |
179 | c3d2689d | balrog | switch (offset) {
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180 | c3d2689d | balrog | case 0x00: /* ITR */ |
181 | c3d2689d | balrog | return s->irqs;
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182 | c3d2689d | balrog | |
183 | c3d2689d | balrog | case 0x04: /* MIR */ |
184 | c3d2689d | balrog | return s->mask;
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185 | c3d2689d | balrog | |
186 | c3d2689d | balrog | case 0x10: /* SIR_IRQ_CODE */ |
187 | c3d2689d | balrog | i = s->sir_irq; |
188 | c3d2689d | balrog | if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) { |
189 | c3d2689d | balrog | s->irqs &= ~(1 << i);
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190 | c3d2689d | balrog | omap_inth_sir_update(s); |
191 | c3d2689d | balrog | omap_inth_update(s); |
192 | c3d2689d | balrog | } |
193 | c3d2689d | balrog | return i;
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194 | c3d2689d | balrog | |
195 | c3d2689d | balrog | case 0x14: /* SIR_FIQ_CODE */ |
196 | c3d2689d | balrog | i = s->sir_fiq; |
197 | c3d2689d | balrog | if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) { |
198 | c3d2689d | balrog | s->irqs &= ~(1 << i);
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199 | c3d2689d | balrog | omap_inth_sir_update(s); |
200 | c3d2689d | balrog | omap_inth_update(s); |
201 | c3d2689d | balrog | } |
202 | c3d2689d | balrog | return i;
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203 | c3d2689d | balrog | |
204 | c3d2689d | balrog | case 0x18: /* CONTROL_REG */ |
205 | c3d2689d | balrog | return 0; |
206 | c3d2689d | balrog | |
207 | c3d2689d | balrog | case 0x1c: /* ILR0 */ |
208 | c3d2689d | balrog | case 0x20: /* ILR1 */ |
209 | c3d2689d | balrog | case 0x24: /* ILR2 */ |
210 | c3d2689d | balrog | case 0x28: /* ILR3 */ |
211 | c3d2689d | balrog | case 0x2c: /* ILR4 */ |
212 | c3d2689d | balrog | case 0x30: /* ILR5 */ |
213 | c3d2689d | balrog | case 0x34: /* ILR6 */ |
214 | c3d2689d | balrog | case 0x38: /* ILR7 */ |
215 | c3d2689d | balrog | case 0x3c: /* ILR8 */ |
216 | c3d2689d | balrog | case 0x40: /* ILR9 */ |
217 | c3d2689d | balrog | case 0x44: /* ILR10 */ |
218 | c3d2689d | balrog | case 0x48: /* ILR11 */ |
219 | c3d2689d | balrog | case 0x4c: /* ILR12 */ |
220 | c3d2689d | balrog | case 0x50: /* ILR13 */ |
221 | c3d2689d | balrog | case 0x54: /* ILR14 */ |
222 | c3d2689d | balrog | case 0x58: /* ILR15 */ |
223 | c3d2689d | balrog | case 0x5c: /* ILR16 */ |
224 | c3d2689d | balrog | case 0x60: /* ILR17 */ |
225 | c3d2689d | balrog | case 0x64: /* ILR18 */ |
226 | c3d2689d | balrog | case 0x68: /* ILR19 */ |
227 | c3d2689d | balrog | case 0x6c: /* ILR20 */ |
228 | c3d2689d | balrog | case 0x70: /* ILR21 */ |
229 | c3d2689d | balrog | case 0x74: /* ILR22 */ |
230 | c3d2689d | balrog | case 0x78: /* ILR23 */ |
231 | c3d2689d | balrog | case 0x7c: /* ILR24 */ |
232 | c3d2689d | balrog | case 0x80: /* ILR25 */ |
233 | c3d2689d | balrog | case 0x84: /* ILR26 */ |
234 | c3d2689d | balrog | case 0x88: /* ILR27 */ |
235 | c3d2689d | balrog | case 0x8c: /* ILR28 */ |
236 | c3d2689d | balrog | case 0x90: /* ILR29 */ |
237 | c3d2689d | balrog | case 0x94: /* ILR30 */ |
238 | c3d2689d | balrog | case 0x98: /* ILR31 */ |
239 | c3d2689d | balrog | i = (offset - 0x1c) >> 2; |
240 | c3d2689d | balrog | return (s->priority[i] << 2) | |
241 | c3d2689d | balrog | (((s->sens_edge >> i) & 1) << 1) | |
242 | c3d2689d | balrog | ((s->fiq >> i) & 1);
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243 | c3d2689d | balrog | |
244 | c3d2689d | balrog | case 0x9c: /* ISR */ |
245 | c3d2689d | balrog | return 0x00000000; |
246 | c3d2689d | balrog | |
247 | c3d2689d | balrog | default:
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248 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
249 | c3d2689d | balrog | break;
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250 | c3d2689d | balrog | } |
251 | c3d2689d | balrog | return 0; |
252 | c3d2689d | balrog | } |
253 | c3d2689d | balrog | |
254 | c3d2689d | balrog | static void omap_inth_write(void *opaque, target_phys_addr_t addr, |
255 | c3d2689d | balrog | uint32_t value) |
256 | c3d2689d | balrog | { |
257 | c3d2689d | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
258 | c3d2689d | balrog | int i, offset = addr - s->base;
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259 | c3d2689d | balrog | |
260 | c3d2689d | balrog | switch (offset) {
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261 | c3d2689d | balrog | case 0x00: /* ITR */ |
262 | d8f699cb | balrog | s->irqs &= value | 1;
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263 | c3d2689d | balrog | omap_inth_sir_update(s); |
264 | c3d2689d | balrog | omap_inth_update(s); |
265 | c3d2689d | balrog | return;
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266 | c3d2689d | balrog | |
267 | c3d2689d | balrog | case 0x04: /* MIR */ |
268 | c3d2689d | balrog | s->mask = value; |
269 | c3d2689d | balrog | omap_inth_sir_update(s); |
270 | c3d2689d | balrog | omap_inth_update(s); |
271 | c3d2689d | balrog | return;
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272 | c3d2689d | balrog | |
273 | c3d2689d | balrog | case 0x10: /* SIR_IRQ_CODE */ |
274 | c3d2689d | balrog | case 0x14: /* SIR_FIQ_CODE */ |
275 | c3d2689d | balrog | OMAP_RO_REG(addr); |
276 | c3d2689d | balrog | break;
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277 | c3d2689d | balrog | |
278 | c3d2689d | balrog | case 0x18: /* CONTROL_REG */ |
279 | c3d2689d | balrog | if (value & 2) |
280 | c3d2689d | balrog | s->new_fiq_agr = ~0;
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281 | c3d2689d | balrog | if (value & 1) |
282 | c3d2689d | balrog | s->new_irq_agr = ~0;
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283 | c3d2689d | balrog | omap_inth_update(s); |
284 | c3d2689d | balrog | return;
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285 | c3d2689d | balrog | |
286 | c3d2689d | balrog | case 0x1c: /* ILR0 */ |
287 | c3d2689d | balrog | case 0x20: /* ILR1 */ |
288 | c3d2689d | balrog | case 0x24: /* ILR2 */ |
289 | c3d2689d | balrog | case 0x28: /* ILR3 */ |
290 | c3d2689d | balrog | case 0x2c: /* ILR4 */ |
291 | c3d2689d | balrog | case 0x30: /* ILR5 */ |
292 | c3d2689d | balrog | case 0x34: /* ILR6 */ |
293 | c3d2689d | balrog | case 0x38: /* ILR7 */ |
294 | c3d2689d | balrog | case 0x3c: /* ILR8 */ |
295 | c3d2689d | balrog | case 0x40: /* ILR9 */ |
296 | c3d2689d | balrog | case 0x44: /* ILR10 */ |
297 | c3d2689d | balrog | case 0x48: /* ILR11 */ |
298 | c3d2689d | balrog | case 0x4c: /* ILR12 */ |
299 | c3d2689d | balrog | case 0x50: /* ILR13 */ |
300 | c3d2689d | balrog | case 0x54: /* ILR14 */ |
301 | c3d2689d | balrog | case 0x58: /* ILR15 */ |
302 | c3d2689d | balrog | case 0x5c: /* ILR16 */ |
303 | c3d2689d | balrog | case 0x60: /* ILR17 */ |
304 | c3d2689d | balrog | case 0x64: /* ILR18 */ |
305 | c3d2689d | balrog | case 0x68: /* ILR19 */ |
306 | c3d2689d | balrog | case 0x6c: /* ILR20 */ |
307 | c3d2689d | balrog | case 0x70: /* ILR21 */ |
308 | c3d2689d | balrog | case 0x74: /* ILR22 */ |
309 | c3d2689d | balrog | case 0x78: /* ILR23 */ |
310 | c3d2689d | balrog | case 0x7c: /* ILR24 */ |
311 | c3d2689d | balrog | case 0x80: /* ILR25 */ |
312 | c3d2689d | balrog | case 0x84: /* ILR26 */ |
313 | c3d2689d | balrog | case 0x88: /* ILR27 */ |
314 | c3d2689d | balrog | case 0x8c: /* ILR28 */ |
315 | c3d2689d | balrog | case 0x90: /* ILR29 */ |
316 | c3d2689d | balrog | case 0x94: /* ILR30 */ |
317 | c3d2689d | balrog | case 0x98: /* ILR31 */ |
318 | c3d2689d | balrog | i = (offset - 0x1c) >> 2; |
319 | c3d2689d | balrog | s->priority[i] = (value >> 2) & 0x1f; |
320 | c3d2689d | balrog | s->sens_edge &= ~(1 << i);
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321 | c3d2689d | balrog | s->sens_edge |= ((value >> 1) & 1) << i; |
322 | c3d2689d | balrog | s->fiq &= ~(1 << i);
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323 | c3d2689d | balrog | s->fiq |= (value & 1) << i;
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324 | c3d2689d | balrog | return;
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325 | c3d2689d | balrog | |
326 | c3d2689d | balrog | case 0x9c: /* ISR */ |
327 | c3d2689d | balrog | for (i = 0; i < 32; i ++) |
328 | c3d2689d | balrog | if (value & (1 << i)) { |
329 | c3d2689d | balrog | omap_set_intr(s, i, 1);
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330 | c3d2689d | balrog | return;
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331 | c3d2689d | balrog | } |
332 | c3d2689d | balrog | return;
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333 | c3d2689d | balrog | |
334 | c3d2689d | balrog | default:
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335 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
336 | c3d2689d | balrog | } |
337 | c3d2689d | balrog | } |
338 | c3d2689d | balrog | |
339 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_inth_readfn[] = {
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340 | c3d2689d | balrog | omap_badwidth_read32, |
341 | c3d2689d | balrog | omap_badwidth_read32, |
342 | c3d2689d | balrog | omap_inth_read, |
343 | c3d2689d | balrog | }; |
344 | c3d2689d | balrog | |
345 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_inth_writefn[] = {
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346 | c3d2689d | balrog | omap_inth_write, |
347 | c3d2689d | balrog | omap_inth_write, |
348 | c3d2689d | balrog | omap_inth_write, |
349 | c3d2689d | balrog | }; |
350 | c3d2689d | balrog | |
351 | c3d2689d | balrog | static void omap_inth_reset(struct omap_intr_handler_s *s) |
352 | c3d2689d | balrog | { |
353 | c3d2689d | balrog | s->irqs = 0x00000000;
|
354 | c3d2689d | balrog | s->mask = 0xffffffff;
|
355 | c3d2689d | balrog | s->sens_edge = 0x00000000;
|
356 | c3d2689d | balrog | s->fiq = 0x00000000;
|
357 | c3d2689d | balrog | memset(s->priority, 0, sizeof(s->priority)); |
358 | c3d2689d | balrog | s->new_irq_agr = ~0;
|
359 | c3d2689d | balrog | s->new_fiq_agr = ~0;
|
360 | c3d2689d | balrog | s->sir_irq = 0;
|
361 | c3d2689d | balrog | s->sir_fiq = 0;
|
362 | c3d2689d | balrog | |
363 | c3d2689d | balrog | omap_inth_update(s); |
364 | c3d2689d | balrog | } |
365 | c3d2689d | balrog | |
366 | c3d2689d | balrog | struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
|
367 | c3d2689d | balrog | unsigned long size, qemu_irq parent[2], omap_clk clk) |
368 | c3d2689d | balrog | { |
369 | c3d2689d | balrog | int iomemtype;
|
370 | c3d2689d | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
371 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_intr_handler_s)); |
372 | c3d2689d | balrog | |
373 | c3d2689d | balrog | s->parent_pic = parent; |
374 | c3d2689d | balrog | s->base = base; |
375 | c3d2689d | balrog | s->pins = qemu_allocate_irqs(omap_set_intr, s, 32);
|
376 | c3d2689d | balrog | omap_inth_reset(s); |
377 | c3d2689d | balrog | |
378 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
|
379 | c3d2689d | balrog | omap_inth_writefn, s); |
380 | c3d2689d | balrog | cpu_register_physical_memory(s->base, size, iomemtype); |
381 | c3d2689d | balrog | |
382 | c3d2689d | balrog | return s;
|
383 | c3d2689d | balrog | } |
384 | c3d2689d | balrog | |
385 | c3d2689d | balrog | /* OMAP1 DMA module */
|
386 | c3d2689d | balrog | typedef enum { |
387 | c3d2689d | balrog | constant = 0,
|
388 | c3d2689d | balrog | post_incremented, |
389 | c3d2689d | balrog | single_index, |
390 | c3d2689d | balrog | double_index, |
391 | c3d2689d | balrog | } omap_dma_addressing_t; |
392 | c3d2689d | balrog | |
393 | c3d2689d | balrog | struct omap_dma_channel_s {
|
394 | c3d2689d | balrog | int burst[2]; |
395 | c3d2689d | balrog | int pack[2]; |
396 | c3d2689d | balrog | enum omap_dma_port port[2]; |
397 | c3d2689d | balrog | target_phys_addr_t addr[2];
|
398 | c3d2689d | balrog | omap_dma_addressing_t mode[2];
|
399 | c3d2689d | balrog | int data_type;
|
400 | c3d2689d | balrog | int end_prog;
|
401 | c3d2689d | balrog | int repeat;
|
402 | c3d2689d | balrog | int auto_init;
|
403 | c3d2689d | balrog | int priority;
|
404 | c3d2689d | balrog | int fs;
|
405 | c3d2689d | balrog | int sync;
|
406 | c3d2689d | balrog | int running;
|
407 | c3d2689d | balrog | int interrupts;
|
408 | c3d2689d | balrog | int status;
|
409 | c3d2689d | balrog | int signalled;
|
410 | c3d2689d | balrog | int post_sync;
|
411 | c3d2689d | balrog | int transfer;
|
412 | c3d2689d | balrog | uint16_t elements; |
413 | c3d2689d | balrog | uint16_t frames; |
414 | c3d2689d | balrog | uint16_t frame_index; |
415 | c3d2689d | balrog | uint16_t element_index; |
416 | c3d2689d | balrog | uint16_t cpc; |
417 | c3d2689d | balrog | |
418 | c3d2689d | balrog | struct omap_dma_reg_set_s {
|
419 | c3d2689d | balrog | target_phys_addr_t src, dest; |
420 | c3d2689d | balrog | int frame;
|
421 | c3d2689d | balrog | int element;
|
422 | c3d2689d | balrog | int frame_delta[2]; |
423 | c3d2689d | balrog | int elem_delta[2]; |
424 | c3d2689d | balrog | int frames;
|
425 | c3d2689d | balrog | int elements;
|
426 | c3d2689d | balrog | } active_set; |
427 | c3d2689d | balrog | }; |
428 | c3d2689d | balrog | |
429 | c3d2689d | balrog | struct omap_dma_s {
|
430 | c3d2689d | balrog | qemu_irq *ih; |
431 | c3d2689d | balrog | QEMUTimer *tm; |
432 | c3d2689d | balrog | struct omap_mpu_state_s *mpu;
|
433 | c3d2689d | balrog | target_phys_addr_t base; |
434 | c3d2689d | balrog | omap_clk clk; |
435 | c3d2689d | balrog | int64_t delay; |
436 | 1af2b62d | balrog | uint32_t drq; |
437 | c3d2689d | balrog | |
438 | c3d2689d | balrog | uint16_t gcr; |
439 | c3d2689d | balrog | int run_count;
|
440 | c3d2689d | balrog | |
441 | c3d2689d | balrog | int chans;
|
442 | c3d2689d | balrog | struct omap_dma_channel_s ch[16]; |
443 | c3d2689d | balrog | struct omap_dma_lcd_channel_s lcd_ch;
|
444 | c3d2689d | balrog | }; |
445 | c3d2689d | balrog | |
446 | c3d2689d | balrog | static void omap_dma_interrupts_update(struct omap_dma_s *s) |
447 | c3d2689d | balrog | { |
448 | c3d2689d | balrog | /* First three interrupts are shared between two channels each. */
|
449 | c3d2689d | balrog | qemu_set_irq(s->ih[OMAP_INT_DMA_CH0_6], |
450 | c3d2689d | balrog | (s->ch[0].status | s->ch[6].status) & 0x3f); |
451 | c3d2689d | balrog | qemu_set_irq(s->ih[OMAP_INT_DMA_CH1_7], |
452 | c3d2689d | balrog | (s->ch[1].status | s->ch[7].status) & 0x3f); |
453 | c3d2689d | balrog | qemu_set_irq(s->ih[OMAP_INT_DMA_CH2_8], |
454 | c3d2689d | balrog | (s->ch[2].status | s->ch[8].status) & 0x3f); |
455 | c3d2689d | balrog | qemu_set_irq(s->ih[OMAP_INT_DMA_CH3], |
456 | c3d2689d | balrog | (s->ch[3].status) & 0x3f); |
457 | c3d2689d | balrog | qemu_set_irq(s->ih[OMAP_INT_DMA_CH4], |
458 | c3d2689d | balrog | (s->ch[4].status) & 0x3f); |
459 | c3d2689d | balrog | qemu_set_irq(s->ih[OMAP_INT_DMA_CH5], |
460 | c3d2689d | balrog | (s->ch[5].status) & 0x3f); |
461 | c3d2689d | balrog | } |
462 | c3d2689d | balrog | |
463 | c3d2689d | balrog | static void omap_dma_channel_load(struct omap_dma_s *s, int ch) |
464 | c3d2689d | balrog | { |
465 | c3d2689d | balrog | struct omap_dma_reg_set_s *a = &s->ch[ch].active_set;
|
466 | c3d2689d | balrog | int i;
|
467 | c3d2689d | balrog | |
468 | c3d2689d | balrog | /*
|
469 | c3d2689d | balrog | * TODO: verify address ranges and alignment
|
470 | c3d2689d | balrog | * TODO: port endianness
|
471 | c3d2689d | balrog | */
|
472 | c3d2689d | balrog | |
473 | c3d2689d | balrog | a->src = s->ch[ch].addr[0];
|
474 | c3d2689d | balrog | a->dest = s->ch[ch].addr[1];
|
475 | c3d2689d | balrog | a->frames = s->ch[ch].frames; |
476 | c3d2689d | balrog | a->elements = s->ch[ch].elements; |
477 | c3d2689d | balrog | a->frame = 0;
|
478 | c3d2689d | balrog | a->element = 0;
|
479 | c3d2689d | balrog | |
480 | c3d2689d | balrog | if (unlikely(!s->ch[ch].elements || !s->ch[ch].frames)) {
|
481 | c3d2689d | balrog | printf("%s: bad DMA request\n", __FUNCTION__);
|
482 | c3d2689d | balrog | return;
|
483 | c3d2689d | balrog | } |
484 | c3d2689d | balrog | |
485 | c3d2689d | balrog | for (i = 0; i < 2; i ++) |
486 | c3d2689d | balrog | switch (s->ch[ch].mode[i]) {
|
487 | c3d2689d | balrog | case constant:
|
488 | c3d2689d | balrog | a->elem_delta[i] = 0;
|
489 | c3d2689d | balrog | a->frame_delta[i] = 0;
|
490 | c3d2689d | balrog | break;
|
491 | c3d2689d | balrog | case post_incremented:
|
492 | c3d2689d | balrog | a->elem_delta[i] = s->ch[ch].data_type; |
493 | c3d2689d | balrog | a->frame_delta[i] = 0;
|
494 | c3d2689d | balrog | break;
|
495 | c3d2689d | balrog | case single_index:
|
496 | c3d2689d | balrog | a->elem_delta[i] = s->ch[ch].data_type + |
497 | c3d2689d | balrog | s->ch[ch].element_index - 1;
|
498 | c3d2689d | balrog | if (s->ch[ch].element_index > 0x7fff) |
499 | c3d2689d | balrog | a->elem_delta[i] -= 0x10000;
|
500 | c3d2689d | balrog | a->frame_delta[i] = 0;
|
501 | c3d2689d | balrog | break;
|
502 | c3d2689d | balrog | case double_index:
|
503 | c3d2689d | balrog | a->elem_delta[i] = s->ch[ch].data_type + |
504 | c3d2689d | balrog | s->ch[ch].element_index - 1;
|
505 | c3d2689d | balrog | if (s->ch[ch].element_index > 0x7fff) |
506 | c3d2689d | balrog | a->elem_delta[i] -= 0x10000;
|
507 | c3d2689d | balrog | a->frame_delta[i] = s->ch[ch].frame_index - |
508 | c3d2689d | balrog | s->ch[ch].element_index; |
509 | c3d2689d | balrog | if (s->ch[ch].frame_index > 0x7fff) |
510 | c3d2689d | balrog | a->frame_delta[i] -= 0x10000;
|
511 | c3d2689d | balrog | break;
|
512 | c3d2689d | balrog | default:
|
513 | c3d2689d | balrog | break;
|
514 | c3d2689d | balrog | } |
515 | c3d2689d | balrog | } |
516 | c3d2689d | balrog | |
517 | c3d2689d | balrog | static inline void omap_dma_request_run(struct omap_dma_s *s, |
518 | c3d2689d | balrog | int channel, int request) |
519 | c3d2689d | balrog | { |
520 | c3d2689d | balrog | next_channel:
|
521 | c3d2689d | balrog | if (request > 0) |
522 | c3d2689d | balrog | for (; channel < 9; channel ++) |
523 | c3d2689d | balrog | if (s->ch[channel].sync == request && s->ch[channel].running)
|
524 | c3d2689d | balrog | break;
|
525 | c3d2689d | balrog | if (channel >= 9) |
526 | c3d2689d | balrog | return;
|
527 | c3d2689d | balrog | |
528 | c3d2689d | balrog | if (s->ch[channel].transfer) {
|
529 | c3d2689d | balrog | if (request > 0) { |
530 | c3d2689d | balrog | s->ch[channel ++].post_sync = request; |
531 | c3d2689d | balrog | goto next_channel;
|
532 | c3d2689d | balrog | } |
533 | c3d2689d | balrog | s->ch[channel].status |= 0x02; /* Synchronisation drop */ |
534 | c3d2689d | balrog | omap_dma_interrupts_update(s); |
535 | c3d2689d | balrog | return;
|
536 | c3d2689d | balrog | } |
537 | c3d2689d | balrog | |
538 | c3d2689d | balrog | if (!s->ch[channel].signalled)
|
539 | c3d2689d | balrog | s->run_count ++; |
540 | c3d2689d | balrog | s->ch[channel].signalled = 1;
|
541 | c3d2689d | balrog | |
542 | c3d2689d | balrog | if (request > 0) |
543 | c3d2689d | balrog | s->ch[channel].status |= 0x40; /* External request */ |
544 | c3d2689d | balrog | |
545 | 1af2b62d | balrog | if (s->delay && !qemu_timer_pending(s->tm))
|
546 | c3d2689d | balrog | qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
547 | c3d2689d | balrog | |
548 | c3d2689d | balrog | if (request > 0) { |
549 | c3d2689d | balrog | channel ++; |
550 | c3d2689d | balrog | goto next_channel;
|
551 | c3d2689d | balrog | } |
552 | c3d2689d | balrog | } |
553 | c3d2689d | balrog | |
554 | c3d2689d | balrog | static inline void omap_dma_request_stop(struct omap_dma_s *s, int channel) |
555 | c3d2689d | balrog | { |
556 | c3d2689d | balrog | if (s->ch[channel].signalled)
|
557 | c3d2689d | balrog | s->run_count --; |
558 | c3d2689d | balrog | s->ch[channel].signalled = 0;
|
559 | c3d2689d | balrog | |
560 | c3d2689d | balrog | if (!s->run_count)
|
561 | c3d2689d | balrog | qemu_del_timer(s->tm); |
562 | c3d2689d | balrog | } |
563 | c3d2689d | balrog | |
564 | c3d2689d | balrog | static void omap_dma_channel_run(struct omap_dma_s *s) |
565 | c3d2689d | balrog | { |
566 | c3d2689d | balrog | int ch;
|
567 | c3d2689d | balrog | uint16_t status; |
568 | c3d2689d | balrog | uint8_t value[4];
|
569 | c3d2689d | balrog | struct omap_dma_port_if_s *src_p, *dest_p;
|
570 | c3d2689d | balrog | struct omap_dma_reg_set_s *a;
|
571 | c3d2689d | balrog | |
572 | c3d2689d | balrog | for (ch = 0; ch < 9; ch ++) { |
573 | c3d2689d | balrog | a = &s->ch[ch].active_set; |
574 | c3d2689d | balrog | |
575 | c3d2689d | balrog | src_p = &s->mpu->port[s->ch[ch].port[0]];
|
576 | c3d2689d | balrog | dest_p = &s->mpu->port[s->ch[ch].port[1]];
|
577 | c3d2689d | balrog | if (s->ch[ch].signalled && (!src_p->addr_valid(s->mpu, a->src) ||
|
578 | c3d2689d | balrog | !dest_p->addr_valid(s->mpu, a->dest))) { |
579 | c3d2689d | balrog | #if 0
|
580 | c3d2689d | balrog | /* Bus time-out */
|
581 | c3d2689d | balrog | if (s->ch[ch].interrupts & 0x01)
|
582 | c3d2689d | balrog | s->ch[ch].status |= 0x01;
|
583 | c3d2689d | balrog | omap_dma_request_stop(s, ch);
|
584 | c3d2689d | balrog | continue;
|
585 | c3d2689d | balrog | #endif
|
586 | c3d2689d | balrog | printf("%s: Bus time-out in DMA%i operation\n", __FUNCTION__, ch);
|
587 | c3d2689d | balrog | } |
588 | c3d2689d | balrog | |
589 | c3d2689d | balrog | status = s->ch[ch].status; |
590 | c3d2689d | balrog | while (status == s->ch[ch].status && s->ch[ch].signalled) {
|
591 | c3d2689d | balrog | /* Transfer a single element */
|
592 | c3d2689d | balrog | s->ch[ch].transfer = 1;
|
593 | c3d2689d | balrog | cpu_physical_memory_read(a->src, value, s->ch[ch].data_type); |
594 | c3d2689d | balrog | cpu_physical_memory_write(a->dest, value, s->ch[ch].data_type); |
595 | c3d2689d | balrog | s->ch[ch].transfer = 0;
|
596 | c3d2689d | balrog | |
597 | c3d2689d | balrog | a->src += a->elem_delta[0];
|
598 | c3d2689d | balrog | a->dest += a->elem_delta[1];
|
599 | c3d2689d | balrog | a->element ++; |
600 | c3d2689d | balrog | |
601 | c3d2689d | balrog | /* Check interrupt conditions */
|
602 | c3d2689d | balrog | if (a->element == a->elements) {
|
603 | c3d2689d | balrog | a->element = 0;
|
604 | c3d2689d | balrog | a->src += a->frame_delta[0];
|
605 | c3d2689d | balrog | a->dest += a->frame_delta[1];
|
606 | c3d2689d | balrog | a->frame ++; |
607 | c3d2689d | balrog | |
608 | c3d2689d | balrog | if (a->frame == a->frames) {
|
609 | c3d2689d | balrog | if (!s->ch[ch].repeat || !s->ch[ch].auto_init)
|
610 | c3d2689d | balrog | s->ch[ch].running = 0;
|
611 | c3d2689d | balrog | |
612 | c3d2689d | balrog | if (s->ch[ch].auto_init &&
|
613 | c3d2689d | balrog | (s->ch[ch].repeat || |
614 | c3d2689d | balrog | s->ch[ch].end_prog)) |
615 | c3d2689d | balrog | omap_dma_channel_load(s, ch); |
616 | c3d2689d | balrog | |
617 | c3d2689d | balrog | if (s->ch[ch].interrupts & 0x20) |
618 | c3d2689d | balrog | s->ch[ch].status |= 0x20;
|
619 | c3d2689d | balrog | |
620 | c3d2689d | balrog | if (!s->ch[ch].sync)
|
621 | c3d2689d | balrog | omap_dma_request_stop(s, ch); |
622 | c3d2689d | balrog | } |
623 | c3d2689d | balrog | |
624 | c3d2689d | balrog | if (s->ch[ch].interrupts & 0x08) |
625 | c3d2689d | balrog | s->ch[ch].status |= 0x08;
|
626 | c3d2689d | balrog | |
627 | 1af2b62d | balrog | if (s->ch[ch].sync && s->ch[ch].fs &&
|
628 | 1af2b62d | balrog | !(s->drq & (1 << s->ch[ch].sync))) {
|
629 | c3d2689d | balrog | s->ch[ch].status &= ~0x40;
|
630 | c3d2689d | balrog | omap_dma_request_stop(s, ch); |
631 | c3d2689d | balrog | } |
632 | c3d2689d | balrog | } |
633 | c3d2689d | balrog | |
634 | c3d2689d | balrog | if (a->element == 1 && a->frame == a->frames - 1) |
635 | c3d2689d | balrog | if (s->ch[ch].interrupts & 0x10) |
636 | c3d2689d | balrog | s->ch[ch].status |= 0x10;
|
637 | c3d2689d | balrog | |
638 | c3d2689d | balrog | if (a->element == (a->elements >> 1)) |
639 | c3d2689d | balrog | if (s->ch[ch].interrupts & 0x04) |
640 | c3d2689d | balrog | s->ch[ch].status |= 0x04;
|
641 | c3d2689d | balrog | |
642 | 1af2b62d | balrog | if (s->ch[ch].sync && !s->ch[ch].fs &&
|
643 | 1af2b62d | balrog | !(s->drq & (1 << s->ch[ch].sync))) {
|
644 | c3d2689d | balrog | s->ch[ch].status &= ~0x40;
|
645 | c3d2689d | balrog | omap_dma_request_stop(s, ch); |
646 | c3d2689d | balrog | } |
647 | c3d2689d | balrog | |
648 | c3d2689d | balrog | /*
|
649 | c3d2689d | balrog | * Process requests made while the element was
|
650 | c3d2689d | balrog | * being transferred.
|
651 | c3d2689d | balrog | */
|
652 | c3d2689d | balrog | if (s->ch[ch].post_sync) {
|
653 | c3d2689d | balrog | omap_dma_request_run(s, 0, s->ch[ch].post_sync);
|
654 | c3d2689d | balrog | s->ch[ch].post_sync = 0;
|
655 | c3d2689d | balrog | } |
656 | c3d2689d | balrog | |
657 | c3d2689d | balrog | #if 0
|
658 | c3d2689d | balrog | break;
|
659 | c3d2689d | balrog | #endif
|
660 | c3d2689d | balrog | } |
661 | c3d2689d | balrog | |
662 | c3d2689d | balrog | s->ch[ch].cpc = a->dest & 0x0000ffff;
|
663 | c3d2689d | balrog | } |
664 | c3d2689d | balrog | |
665 | c3d2689d | balrog | omap_dma_interrupts_update(s); |
666 | c3d2689d | balrog | if (s->run_count && s->delay)
|
667 | c3d2689d | balrog | qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
668 | c3d2689d | balrog | } |
669 | c3d2689d | balrog | |
670 | c3d2689d | balrog | static int omap_dma_ch_reg_read(struct omap_dma_s *s, |
671 | c3d2689d | balrog | int ch, int reg, uint16_t *value) { |
672 | c3d2689d | balrog | switch (reg) {
|
673 | c3d2689d | balrog | case 0x00: /* SYS_DMA_CSDP_CH0 */ |
674 | c3d2689d | balrog | *value = (s->ch[ch].burst[1] << 14) | |
675 | c3d2689d | balrog | (s->ch[ch].pack[1] << 13) | |
676 | c3d2689d | balrog | (s->ch[ch].port[1] << 9) | |
677 | c3d2689d | balrog | (s->ch[ch].burst[0] << 7) | |
678 | c3d2689d | balrog | (s->ch[ch].pack[0] << 6) | |
679 | c3d2689d | balrog | (s->ch[ch].port[0] << 2) | |
680 | c3d2689d | balrog | (s->ch[ch].data_type >> 1);
|
681 | c3d2689d | balrog | break;
|
682 | c3d2689d | balrog | |
683 | c3d2689d | balrog | case 0x02: /* SYS_DMA_CCR_CH0 */ |
684 | c3d2689d | balrog | *value = (s->ch[ch].mode[1] << 14) | |
685 | c3d2689d | balrog | (s->ch[ch].mode[0] << 12) | |
686 | c3d2689d | balrog | (s->ch[ch].end_prog << 11) |
|
687 | c3d2689d | balrog | (s->ch[ch].repeat << 9) |
|
688 | c3d2689d | balrog | (s->ch[ch].auto_init << 8) |
|
689 | c3d2689d | balrog | (s->ch[ch].running << 7) |
|
690 | c3d2689d | balrog | (s->ch[ch].priority << 6) |
|
691 | c3d2689d | balrog | (s->ch[ch].fs << 5) | s->ch[ch].sync;
|
692 | c3d2689d | balrog | break;
|
693 | c3d2689d | balrog | |
694 | c3d2689d | balrog | case 0x04: /* SYS_DMA_CICR_CH0 */ |
695 | c3d2689d | balrog | *value = s->ch[ch].interrupts; |
696 | c3d2689d | balrog | break;
|
697 | c3d2689d | balrog | |
698 | c3d2689d | balrog | case 0x06: /* SYS_DMA_CSR_CH0 */ |
699 | c3d2689d | balrog | /* FIXME: shared CSR for channels sharing the interrupts */
|
700 | c3d2689d | balrog | *value = s->ch[ch].status; |
701 | c3d2689d | balrog | s->ch[ch].status &= 0x40;
|
702 | c3d2689d | balrog | omap_dma_interrupts_update(s); |
703 | c3d2689d | balrog | break;
|
704 | c3d2689d | balrog | |
705 | c3d2689d | balrog | case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
706 | c3d2689d | balrog | *value = s->ch[ch].addr[0] & 0x0000ffff; |
707 | c3d2689d | balrog | break;
|
708 | c3d2689d | balrog | |
709 | c3d2689d | balrog | case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
710 | c3d2689d | balrog | *value = s->ch[ch].addr[0] >> 16; |
711 | c3d2689d | balrog | break;
|
712 | c3d2689d | balrog | |
713 | c3d2689d | balrog | case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
714 | c3d2689d | balrog | *value = s->ch[ch].addr[1] & 0x0000ffff; |
715 | c3d2689d | balrog | break;
|
716 | c3d2689d | balrog | |
717 | c3d2689d | balrog | case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
718 | c3d2689d | balrog | *value = s->ch[ch].addr[1] >> 16; |
719 | c3d2689d | balrog | break;
|
720 | c3d2689d | balrog | |
721 | c3d2689d | balrog | case 0x10: /* SYS_DMA_CEN_CH0 */ |
722 | c3d2689d | balrog | *value = s->ch[ch].elements; |
723 | c3d2689d | balrog | break;
|
724 | c3d2689d | balrog | |
725 | c3d2689d | balrog | case 0x12: /* SYS_DMA_CFN_CH0 */ |
726 | c3d2689d | balrog | *value = s->ch[ch].frames; |
727 | c3d2689d | balrog | break;
|
728 | c3d2689d | balrog | |
729 | c3d2689d | balrog | case 0x14: /* SYS_DMA_CFI_CH0 */ |
730 | c3d2689d | balrog | *value = s->ch[ch].frame_index; |
731 | c3d2689d | balrog | break;
|
732 | c3d2689d | balrog | |
733 | c3d2689d | balrog | case 0x16: /* SYS_DMA_CEI_CH0 */ |
734 | c3d2689d | balrog | *value = s->ch[ch].element_index; |
735 | c3d2689d | balrog | break;
|
736 | c3d2689d | balrog | |
737 | c3d2689d | balrog | case 0x18: /* SYS_DMA_CPC_CH0 */ |
738 | c3d2689d | balrog | *value = s->ch[ch].cpc; |
739 | c3d2689d | balrog | break;
|
740 | c3d2689d | balrog | |
741 | c3d2689d | balrog | default:
|
742 | c3d2689d | balrog | return 1; |
743 | c3d2689d | balrog | } |
744 | c3d2689d | balrog | return 0; |
745 | c3d2689d | balrog | } |
746 | c3d2689d | balrog | |
747 | c3d2689d | balrog | static int omap_dma_ch_reg_write(struct omap_dma_s *s, |
748 | c3d2689d | balrog | int ch, int reg, uint16_t value) { |
749 | c3d2689d | balrog | switch (reg) {
|
750 | c3d2689d | balrog | case 0x00: /* SYS_DMA_CSDP_CH0 */ |
751 | c3d2689d | balrog | s->ch[ch].burst[1] = (value & 0xc000) >> 14; |
752 | c3d2689d | balrog | s->ch[ch].pack[1] = (value & 0x2000) >> 13; |
753 | c3d2689d | balrog | s->ch[ch].port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); |
754 | c3d2689d | balrog | s->ch[ch].burst[0] = (value & 0x0180) >> 7; |
755 | c3d2689d | balrog | s->ch[ch].pack[0] = (value & 0x0040) >> 6; |
756 | c3d2689d | balrog | s->ch[ch].port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); |
757 | c3d2689d | balrog | s->ch[ch].data_type = (1 << (value & 3)); |
758 | c3d2689d | balrog | if (s->ch[ch].port[0] >= omap_dma_port_last) |
759 | c3d2689d | balrog | printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
760 | c3d2689d | balrog | s->ch[ch].port[0]);
|
761 | c3d2689d | balrog | if (s->ch[ch].port[1] >= omap_dma_port_last) |
762 | c3d2689d | balrog | printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
763 | c3d2689d | balrog | s->ch[ch].port[1]);
|
764 | c3d2689d | balrog | if ((value & 3) == 3) |
765 | c3d2689d | balrog | printf("%s: bad data_type for DMA channel %i\n", __FUNCTION__, ch);
|
766 | c3d2689d | balrog | break;
|
767 | c3d2689d | balrog | |
768 | c3d2689d | balrog | case 0x02: /* SYS_DMA_CCR_CH0 */ |
769 | c3d2689d | balrog | s->ch[ch].mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); |
770 | c3d2689d | balrog | s->ch[ch].mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); |
771 | c3d2689d | balrog | s->ch[ch].end_prog = (value & 0x0800) >> 11; |
772 | c3d2689d | balrog | s->ch[ch].repeat = (value & 0x0200) >> 9; |
773 | c3d2689d | balrog | s->ch[ch].auto_init = (value & 0x0100) >> 8; |
774 | c3d2689d | balrog | s->ch[ch].priority = (value & 0x0040) >> 6; |
775 | c3d2689d | balrog | s->ch[ch].fs = (value & 0x0020) >> 5; |
776 | c3d2689d | balrog | s->ch[ch].sync = value & 0x001f;
|
777 | c3d2689d | balrog | if (value & 0x0080) { |
778 | c3d2689d | balrog | if (s->ch[ch].running) {
|
779 | c3d2689d | balrog | if (!s->ch[ch].signalled &&
|
780 | c3d2689d | balrog | s->ch[ch].auto_init && s->ch[ch].end_prog) |
781 | c3d2689d | balrog | omap_dma_channel_load(s, ch); |
782 | c3d2689d | balrog | } else {
|
783 | c3d2689d | balrog | s->ch[ch].running = 1;
|
784 | c3d2689d | balrog | omap_dma_channel_load(s, ch); |
785 | c3d2689d | balrog | } |
786 | 1af2b62d | balrog | if (!s->ch[ch].sync || (s->drq & (1 << s->ch[ch].sync))) |
787 | c3d2689d | balrog | omap_dma_request_run(s, ch, 0);
|
788 | c3d2689d | balrog | } else {
|
789 | c3d2689d | balrog | s->ch[ch].running = 0;
|
790 | c3d2689d | balrog | omap_dma_request_stop(s, ch); |
791 | c3d2689d | balrog | } |
792 | c3d2689d | balrog | break;
|
793 | c3d2689d | balrog | |
794 | c3d2689d | balrog | case 0x04: /* SYS_DMA_CICR_CH0 */ |
795 | c3d2689d | balrog | s->ch[ch].interrupts = value & 0x003f;
|
796 | c3d2689d | balrog | break;
|
797 | c3d2689d | balrog | |
798 | c3d2689d | balrog | case 0x06: /* SYS_DMA_CSR_CH0 */ |
799 | c3d2689d | balrog | return 1; |
800 | c3d2689d | balrog | |
801 | c3d2689d | balrog | case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
802 | c3d2689d | balrog | s->ch[ch].addr[0] &= 0xffff0000; |
803 | c3d2689d | balrog | s->ch[ch].addr[0] |= value;
|
804 | c3d2689d | balrog | break;
|
805 | c3d2689d | balrog | |
806 | c3d2689d | balrog | case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
807 | c3d2689d | balrog | s->ch[ch].addr[0] &= 0x0000ffff; |
808 | b854bc19 | balrog | s->ch[ch].addr[0] |= (uint32_t) value << 16; |
809 | c3d2689d | balrog | break;
|
810 | c3d2689d | balrog | |
811 | c3d2689d | balrog | case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
812 | c3d2689d | balrog | s->ch[ch].addr[1] &= 0xffff0000; |
813 | c3d2689d | balrog | s->ch[ch].addr[1] |= value;
|
814 | c3d2689d | balrog | break;
|
815 | c3d2689d | balrog | |
816 | c3d2689d | balrog | case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
817 | c3d2689d | balrog | s->ch[ch].addr[1] &= 0x0000ffff; |
818 | b854bc19 | balrog | s->ch[ch].addr[1] |= (uint32_t) value << 16; |
819 | c3d2689d | balrog | break;
|
820 | c3d2689d | balrog | |
821 | c3d2689d | balrog | case 0x10: /* SYS_DMA_CEN_CH0 */ |
822 | c3d2689d | balrog | s->ch[ch].elements = value & 0xffff;
|
823 | c3d2689d | balrog | break;
|
824 | c3d2689d | balrog | |
825 | c3d2689d | balrog | case 0x12: /* SYS_DMA_CFN_CH0 */ |
826 | c3d2689d | balrog | s->ch[ch].frames = value & 0xffff;
|
827 | c3d2689d | balrog | break;
|
828 | c3d2689d | balrog | |
829 | c3d2689d | balrog | case 0x14: /* SYS_DMA_CFI_CH0 */ |
830 | c3d2689d | balrog | s->ch[ch].frame_index = value & 0xffff;
|
831 | c3d2689d | balrog | break;
|
832 | c3d2689d | balrog | |
833 | c3d2689d | balrog | case 0x16: /* SYS_DMA_CEI_CH0 */ |
834 | c3d2689d | balrog | s->ch[ch].element_index = value & 0xffff;
|
835 | c3d2689d | balrog | break;
|
836 | c3d2689d | balrog | |
837 | c3d2689d | balrog | case 0x18: /* SYS_DMA_CPC_CH0 */ |
838 | c3d2689d | balrog | return 1; |
839 | c3d2689d | balrog | |
840 | c3d2689d | balrog | default:
|
841 | 8731ac03 | bellard | OMAP_BAD_REG((target_phys_addr_t) reg); |
842 | c3d2689d | balrog | } |
843 | c3d2689d | balrog | return 0; |
844 | c3d2689d | balrog | } |
845 | c3d2689d | balrog | |
846 | c3d2689d | balrog | static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) |
847 | c3d2689d | balrog | { |
848 | c3d2689d | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
849 | c3d2689d | balrog | int i, reg, ch, offset = addr - s->base;
|
850 | c3d2689d | balrog | uint16_t ret; |
851 | c3d2689d | balrog | |
852 | c3d2689d | balrog | switch (offset) {
|
853 | c3d2689d | balrog | case 0x000 ... 0x2fe: |
854 | c3d2689d | balrog | reg = offset & 0x3f;
|
855 | c3d2689d | balrog | ch = (offset >> 6) & 0x0f; |
856 | c3d2689d | balrog | if (omap_dma_ch_reg_read(s, ch, reg, &ret))
|
857 | c3d2689d | balrog | break;
|
858 | c3d2689d | balrog | return ret;
|
859 | c3d2689d | balrog | |
860 | c3d2689d | balrog | case 0x300: /* SYS_DMA_LCD_CTRL */ |
861 | c3d2689d | balrog | i = s->lcd_ch.condition; |
862 | c3d2689d | balrog | s->lcd_ch.condition = 0;
|
863 | c3d2689d | balrog | qemu_irq_lower(s->lcd_ch.irq); |
864 | c3d2689d | balrog | return ((s->lcd_ch.src == imif) << 6) | (i << 3) | |
865 | c3d2689d | balrog | (s->lcd_ch.interrupts << 1) | s->lcd_ch.dual;
|
866 | c3d2689d | balrog | |
867 | c3d2689d | balrog | case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
868 | c3d2689d | balrog | return s->lcd_ch.src_f1_top & 0xffff; |
869 | c3d2689d | balrog | |
870 | c3d2689d | balrog | case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
871 | c3d2689d | balrog | return s->lcd_ch.src_f1_top >> 16; |
872 | c3d2689d | balrog | |
873 | c3d2689d | balrog | case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
874 | c3d2689d | balrog | return s->lcd_ch.src_f1_bottom & 0xffff; |
875 | c3d2689d | balrog | |
876 | c3d2689d | balrog | case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
877 | c3d2689d | balrog | return s->lcd_ch.src_f1_bottom >> 16; |
878 | c3d2689d | balrog | |
879 | c3d2689d | balrog | case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
880 | c3d2689d | balrog | return s->lcd_ch.src_f2_top & 0xffff; |
881 | c3d2689d | balrog | |
882 | c3d2689d | balrog | case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
883 | c3d2689d | balrog | return s->lcd_ch.src_f2_top >> 16; |
884 | c3d2689d | balrog | |
885 | c3d2689d | balrog | case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
886 | c3d2689d | balrog | return s->lcd_ch.src_f2_bottom & 0xffff; |
887 | c3d2689d | balrog | |
888 | c3d2689d | balrog | case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
889 | c3d2689d | balrog | return s->lcd_ch.src_f2_bottom >> 16; |
890 | c3d2689d | balrog | |
891 | c3d2689d | balrog | case 0x400: /* SYS_DMA_GCR */ |
892 | c3d2689d | balrog | return s->gcr;
|
893 | c3d2689d | balrog | } |
894 | c3d2689d | balrog | |
895 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
896 | c3d2689d | balrog | return 0; |
897 | c3d2689d | balrog | } |
898 | c3d2689d | balrog | |
899 | c3d2689d | balrog | static void omap_dma_write(void *opaque, target_phys_addr_t addr, |
900 | c3d2689d | balrog | uint32_t value) |
901 | c3d2689d | balrog | { |
902 | c3d2689d | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
903 | c3d2689d | balrog | int reg, ch, offset = addr - s->base;
|
904 | c3d2689d | balrog | |
905 | c3d2689d | balrog | switch (offset) {
|
906 | c3d2689d | balrog | case 0x000 ... 0x2fe: |
907 | c3d2689d | balrog | reg = offset & 0x3f;
|
908 | c3d2689d | balrog | ch = (offset >> 6) & 0x0f; |
909 | c3d2689d | balrog | if (omap_dma_ch_reg_write(s, ch, reg, value))
|
910 | c3d2689d | balrog | OMAP_RO_REG(addr); |
911 | c3d2689d | balrog | break;
|
912 | c3d2689d | balrog | |
913 | c3d2689d | balrog | case 0x300: /* SYS_DMA_LCD_CTRL */ |
914 | c3d2689d | balrog | s->lcd_ch.src = (value & 0x40) ? imif : emiff;
|
915 | c3d2689d | balrog | s->lcd_ch.condition = 0;
|
916 | c3d2689d | balrog | /* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
917 | c3d2689d | balrog | s->lcd_ch.interrupts = (value >> 1) & 1; |
918 | c3d2689d | balrog | s->lcd_ch.dual = value & 1;
|
919 | c3d2689d | balrog | break;
|
920 | c3d2689d | balrog | |
921 | c3d2689d | balrog | case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
922 | c3d2689d | balrog | s->lcd_ch.src_f1_top &= 0xffff0000;
|
923 | c3d2689d | balrog | s->lcd_ch.src_f1_top |= 0x0000ffff & value;
|
924 | c3d2689d | balrog | break;
|
925 | c3d2689d | balrog | |
926 | c3d2689d | balrog | case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
927 | c3d2689d | balrog | s->lcd_ch.src_f1_top &= 0x0000ffff;
|
928 | c3d2689d | balrog | s->lcd_ch.src_f1_top |= value << 16;
|
929 | c3d2689d | balrog | break;
|
930 | c3d2689d | balrog | |
931 | c3d2689d | balrog | case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
932 | c3d2689d | balrog | s->lcd_ch.src_f1_bottom &= 0xffff0000;
|
933 | c3d2689d | balrog | s->lcd_ch.src_f1_bottom |= 0x0000ffff & value;
|
934 | c3d2689d | balrog | break;
|
935 | c3d2689d | balrog | |
936 | c3d2689d | balrog | case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
937 | c3d2689d | balrog | s->lcd_ch.src_f1_bottom &= 0x0000ffff;
|
938 | c3d2689d | balrog | s->lcd_ch.src_f1_bottom |= value << 16;
|
939 | c3d2689d | balrog | break;
|
940 | c3d2689d | balrog | |
941 | c3d2689d | balrog | case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
942 | c3d2689d | balrog | s->lcd_ch.src_f2_top &= 0xffff0000;
|
943 | c3d2689d | balrog | s->lcd_ch.src_f2_top |= 0x0000ffff & value;
|
944 | c3d2689d | balrog | break;
|
945 | c3d2689d | balrog | |
946 | c3d2689d | balrog | case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
947 | c3d2689d | balrog | s->lcd_ch.src_f2_top &= 0x0000ffff;
|
948 | c3d2689d | balrog | s->lcd_ch.src_f2_top |= value << 16;
|
949 | c3d2689d | balrog | break;
|
950 | c3d2689d | balrog | |
951 | c3d2689d | balrog | case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
952 | c3d2689d | balrog | s->lcd_ch.src_f2_bottom &= 0xffff0000;
|
953 | c3d2689d | balrog | s->lcd_ch.src_f2_bottom |= 0x0000ffff & value;
|
954 | c3d2689d | balrog | break;
|
955 | c3d2689d | balrog | |
956 | c3d2689d | balrog | case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
957 | c3d2689d | balrog | s->lcd_ch.src_f2_bottom &= 0x0000ffff;
|
958 | c3d2689d | balrog | s->lcd_ch.src_f2_bottom |= value << 16;
|
959 | c3d2689d | balrog | break;
|
960 | c3d2689d | balrog | |
961 | c3d2689d | balrog | case 0x400: /* SYS_DMA_GCR */ |
962 | c3d2689d | balrog | s->gcr = value & 0x000c;
|
963 | c3d2689d | balrog | break;
|
964 | c3d2689d | balrog | |
965 | c3d2689d | balrog | default:
|
966 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
967 | c3d2689d | balrog | } |
968 | c3d2689d | balrog | } |
969 | c3d2689d | balrog | |
970 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_dma_readfn[] = {
|
971 | c3d2689d | balrog | omap_badwidth_read16, |
972 | c3d2689d | balrog | omap_dma_read, |
973 | c3d2689d | balrog | omap_badwidth_read16, |
974 | c3d2689d | balrog | }; |
975 | c3d2689d | balrog | |
976 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_dma_writefn[] = {
|
977 | c3d2689d | balrog | omap_badwidth_write16, |
978 | c3d2689d | balrog | omap_dma_write, |
979 | c3d2689d | balrog | omap_badwidth_write16, |
980 | c3d2689d | balrog | }; |
981 | c3d2689d | balrog | |
982 | c3d2689d | balrog | static void omap_dma_request(void *opaque, int drq, int req) |
983 | c3d2689d | balrog | { |
984 | c3d2689d | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
985 | 1af2b62d | balrog | /* The request pins are level triggered. */
|
986 | 1af2b62d | balrog | if (req) {
|
987 | 1af2b62d | balrog | if (~s->drq & (1 << drq)) { |
988 | 1af2b62d | balrog | s->drq |= 1 << drq;
|
989 | 1af2b62d | balrog | omap_dma_request_run(s, 0, drq);
|
990 | 1af2b62d | balrog | } |
991 | 1af2b62d | balrog | } else
|
992 | 1af2b62d | balrog | s->drq &= ~(1 << drq);
|
993 | c3d2689d | balrog | } |
994 | c3d2689d | balrog | |
995 | c3d2689d | balrog | static void omap_dma_clk_update(void *opaque, int line, int on) |
996 | c3d2689d | balrog | { |
997 | c3d2689d | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
998 | c3d2689d | balrog | |
999 | c3d2689d | balrog | if (on) {
|
1000 | d8f699cb | balrog | s->delay = ticks_per_sec >> 7;
|
1001 | c3d2689d | balrog | if (s->run_count)
|
1002 | c3d2689d | balrog | qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
1003 | c3d2689d | balrog | } else {
|
1004 | c3d2689d | balrog | s->delay = 0;
|
1005 | c3d2689d | balrog | qemu_del_timer(s->tm); |
1006 | c3d2689d | balrog | } |
1007 | c3d2689d | balrog | } |
1008 | c3d2689d | balrog | |
1009 | c3d2689d | balrog | static void omap_dma_reset(struct omap_dma_s *s) |
1010 | c3d2689d | balrog | { |
1011 | c3d2689d | balrog | int i;
|
1012 | c3d2689d | balrog | |
1013 | c3d2689d | balrog | qemu_del_timer(s->tm); |
1014 | c3d2689d | balrog | s->gcr = 0x0004;
|
1015 | 1af2b62d | balrog | s->drq = 0x00000000;
|
1016 | c3d2689d | balrog | s->run_count = 0;
|
1017 | c3d2689d | balrog | s->lcd_ch.src = emiff; |
1018 | c3d2689d | balrog | s->lcd_ch.condition = 0;
|
1019 | c3d2689d | balrog | s->lcd_ch.interrupts = 0;
|
1020 | c3d2689d | balrog | s->lcd_ch.dual = 0;
|
1021 | c3d2689d | balrog | memset(s->ch, 0, sizeof(s->ch)); |
1022 | c3d2689d | balrog | for (i = 0; i < s->chans; i ++) |
1023 | c3d2689d | balrog | s->ch[i].interrupts = 0x0003;
|
1024 | c3d2689d | balrog | } |
1025 | c3d2689d | balrog | |
1026 | c3d2689d | balrog | struct omap_dma_s *omap_dma_init(target_phys_addr_t base,
|
1027 | c3d2689d | balrog | qemu_irq pic[], struct omap_mpu_state_s *mpu, omap_clk clk)
|
1028 | c3d2689d | balrog | { |
1029 | c3d2689d | balrog | int iomemtype;
|
1030 | c3d2689d | balrog | struct omap_dma_s *s = (struct omap_dma_s *) |
1031 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_dma_s)); |
1032 | c3d2689d | balrog | |
1033 | c3d2689d | balrog | s->ih = pic; |
1034 | c3d2689d | balrog | s->base = base; |
1035 | c3d2689d | balrog | s->chans = 9;
|
1036 | c3d2689d | balrog | s->mpu = mpu; |
1037 | c3d2689d | balrog | s->clk = clk; |
1038 | c3d2689d | balrog | s->lcd_ch.irq = pic[OMAP_INT_DMA_LCD]; |
1039 | c3d2689d | balrog | s->lcd_ch.mpu = mpu; |
1040 | c3d2689d | balrog | s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s); |
1041 | c3d2689d | balrog | omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
1042 | c3d2689d | balrog | mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
|
1043 | c3d2689d | balrog | omap_dma_reset(s); |
1044 | 1af2b62d | balrog | omap_dma_clk_update(s, 0, 1); |
1045 | c3d2689d | balrog | |
1046 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
|
1047 | c3d2689d | balrog | omap_dma_writefn, s); |
1048 | c3d2689d | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
1049 | c3d2689d | balrog | |
1050 | c3d2689d | balrog | return s;
|
1051 | c3d2689d | balrog | } |
1052 | c3d2689d | balrog | |
1053 | c3d2689d | balrog | /* DMA ports */
|
1054 | b854bc19 | balrog | static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, |
1055 | c3d2689d | balrog | target_phys_addr_t addr) |
1056 | c3d2689d | balrog | { |
1057 | c3d2689d | balrog | return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
|
1058 | c3d2689d | balrog | } |
1059 | c3d2689d | balrog | |
1060 | b854bc19 | balrog | static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, |
1061 | c3d2689d | balrog | target_phys_addr_t addr) |
1062 | c3d2689d | balrog | { |
1063 | c3d2689d | balrog | return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
|
1064 | c3d2689d | balrog | } |
1065 | c3d2689d | balrog | |
1066 | b854bc19 | balrog | static int omap_validate_imif_addr(struct omap_mpu_state_s *s, |
1067 | c3d2689d | balrog | target_phys_addr_t addr) |
1068 | c3d2689d | balrog | { |
1069 | c3d2689d | balrog | return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
|
1070 | c3d2689d | balrog | } |
1071 | c3d2689d | balrog | |
1072 | b854bc19 | balrog | static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, |
1073 | c3d2689d | balrog | target_phys_addr_t addr) |
1074 | c3d2689d | balrog | { |
1075 | c3d2689d | balrog | return addr >= 0xfffb0000 && addr < 0xffff0000; |
1076 | c3d2689d | balrog | } |
1077 | c3d2689d | balrog | |
1078 | b854bc19 | balrog | static int omap_validate_local_addr(struct omap_mpu_state_s *s, |
1079 | c3d2689d | balrog | target_phys_addr_t addr) |
1080 | c3d2689d | balrog | { |
1081 | c3d2689d | balrog | return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000; |
1082 | c3d2689d | balrog | } |
1083 | c3d2689d | balrog | |
1084 | b854bc19 | balrog | static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, |
1085 | c3d2689d | balrog | target_phys_addr_t addr) |
1086 | c3d2689d | balrog | { |
1087 | c3d2689d | balrog | return addr >= 0xe1010000 && addr < 0xe1020004; |
1088 | c3d2689d | balrog | } |
1089 | c3d2689d | balrog | |
1090 | c3d2689d | balrog | /* MPU OS timers */
|
1091 | c3d2689d | balrog | struct omap_mpu_timer_s {
|
1092 | c3d2689d | balrog | qemu_irq irq; |
1093 | c3d2689d | balrog | omap_clk clk; |
1094 | c3d2689d | balrog | target_phys_addr_t base; |
1095 | c3d2689d | balrog | uint32_t val; |
1096 | c3d2689d | balrog | int64_t time; |
1097 | c3d2689d | balrog | QEMUTimer *timer; |
1098 | c3d2689d | balrog | int64_t rate; |
1099 | c3d2689d | balrog | int it_ena;
|
1100 | c3d2689d | balrog | |
1101 | c3d2689d | balrog | int enable;
|
1102 | c3d2689d | balrog | int ptv;
|
1103 | c3d2689d | balrog | int ar;
|
1104 | c3d2689d | balrog | int st;
|
1105 | c3d2689d | balrog | uint32_t reset_val; |
1106 | c3d2689d | balrog | }; |
1107 | c3d2689d | balrog | |
1108 | c3d2689d | balrog | static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) |
1109 | c3d2689d | balrog | { |
1110 | c3d2689d | balrog | uint64_t distance = qemu_get_clock(vm_clock) - timer->time; |
1111 | c3d2689d | balrog | |
1112 | c3d2689d | balrog | if (timer->st && timer->enable && timer->rate)
|
1113 | c3d2689d | balrog | return timer->val - muldiv64(distance >> (timer->ptv + 1), |
1114 | c3d2689d | balrog | timer->rate, ticks_per_sec); |
1115 | c3d2689d | balrog | else
|
1116 | c3d2689d | balrog | return timer->val;
|
1117 | c3d2689d | balrog | } |
1118 | c3d2689d | balrog | |
1119 | c3d2689d | balrog | static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) |
1120 | c3d2689d | balrog | { |
1121 | c3d2689d | balrog | timer->val = omap_timer_read(timer); |
1122 | c3d2689d | balrog | timer->time = qemu_get_clock(vm_clock); |
1123 | c3d2689d | balrog | } |
1124 | c3d2689d | balrog | |
1125 | c3d2689d | balrog | static inline void omap_timer_update(struct omap_mpu_timer_s *timer) |
1126 | c3d2689d | balrog | { |
1127 | c3d2689d | balrog | int64_t expires; |
1128 | c3d2689d | balrog | |
1129 | c3d2689d | balrog | if (timer->enable && timer->st && timer->rate) {
|
1130 | c3d2689d | balrog | timer->val = timer->reset_val; /* Should skip this on clk enable */
|
1131 | b854bc19 | balrog | expires = muldiv64(timer->val << (timer->ptv + 1),
|
1132 | c3d2689d | balrog | ticks_per_sec, timer->rate); |
1133 | b854bc19 | balrog | |
1134 | b854bc19 | balrog | /* If timer expiry would be sooner than in about 1 ms and
|
1135 | b854bc19 | balrog | * auto-reload isn't set, then fire immediately. This is a hack
|
1136 | b854bc19 | balrog | * to make systems like PalmOS run in acceptable time. PalmOS
|
1137 | b854bc19 | balrog | * sets the interval to a very low value and polls the status bit
|
1138 | b854bc19 | balrog | * in a busy loop when it wants to sleep just a couple of CPU
|
1139 | b854bc19 | balrog | * ticks. */
|
1140 | b854bc19 | balrog | if (expires > (ticks_per_sec >> 10) || timer->ar) |
1141 | b854bc19 | balrog | qemu_mod_timer(timer->timer, timer->time + expires); |
1142 | b854bc19 | balrog | else {
|
1143 | b854bc19 | balrog | timer->val = 0;
|
1144 | b854bc19 | balrog | timer->st = 0;
|
1145 | b854bc19 | balrog | if (timer->it_ena)
|
1146 | b854bc19 | balrog | qemu_irq_raise(timer->irq); |
1147 | b854bc19 | balrog | } |
1148 | c3d2689d | balrog | } else
|
1149 | c3d2689d | balrog | qemu_del_timer(timer->timer); |
1150 | c3d2689d | balrog | } |
1151 | c3d2689d | balrog | |
1152 | c3d2689d | balrog | static void omap_timer_tick(void *opaque) |
1153 | c3d2689d | balrog | { |
1154 | c3d2689d | balrog | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
1155 | c3d2689d | balrog | omap_timer_sync(timer); |
1156 | c3d2689d | balrog | |
1157 | c3d2689d | balrog | if (!timer->ar) {
|
1158 | c3d2689d | balrog | timer->val = 0;
|
1159 | c3d2689d | balrog | timer->st = 0;
|
1160 | c3d2689d | balrog | } |
1161 | c3d2689d | balrog | |
1162 | c3d2689d | balrog | if (timer->it_ena)
|
1163 | c3d2689d | balrog | qemu_irq_raise(timer->irq); |
1164 | c3d2689d | balrog | omap_timer_update(timer); |
1165 | c3d2689d | balrog | } |
1166 | c3d2689d | balrog | |
1167 | c3d2689d | balrog | static void omap_timer_clk_update(void *opaque, int line, int on) |
1168 | c3d2689d | balrog | { |
1169 | c3d2689d | balrog | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
1170 | c3d2689d | balrog | |
1171 | c3d2689d | balrog | omap_timer_sync(timer); |
1172 | c3d2689d | balrog | timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
|
1173 | c3d2689d | balrog | omap_timer_update(timer); |
1174 | c3d2689d | balrog | } |
1175 | c3d2689d | balrog | |
1176 | c3d2689d | balrog | static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) |
1177 | c3d2689d | balrog | { |
1178 | c3d2689d | balrog | omap_clk_adduser(timer->clk, |
1179 | c3d2689d | balrog | qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]); |
1180 | c3d2689d | balrog | timer->rate = omap_clk_getrate(timer->clk); |
1181 | c3d2689d | balrog | } |
1182 | c3d2689d | balrog | |
1183 | c3d2689d | balrog | static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr) |
1184 | c3d2689d | balrog | { |
1185 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
1186 | c3d2689d | balrog | int offset = addr - s->base;
|
1187 | c3d2689d | balrog | |
1188 | c3d2689d | balrog | switch (offset) {
|
1189 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
1190 | c3d2689d | balrog | return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; |
1191 | c3d2689d | balrog | |
1192 | c3d2689d | balrog | case 0x04: /* LOAD_TIM */ |
1193 | c3d2689d | balrog | break;
|
1194 | c3d2689d | balrog | |
1195 | c3d2689d | balrog | case 0x08: /* READ_TIM */ |
1196 | c3d2689d | balrog | return omap_timer_read(s);
|
1197 | c3d2689d | balrog | } |
1198 | c3d2689d | balrog | |
1199 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1200 | c3d2689d | balrog | return 0; |
1201 | c3d2689d | balrog | } |
1202 | c3d2689d | balrog | |
1203 | c3d2689d | balrog | static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr, |
1204 | c3d2689d | balrog | uint32_t value) |
1205 | c3d2689d | balrog | { |
1206 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
1207 | c3d2689d | balrog | int offset = addr - s->base;
|
1208 | c3d2689d | balrog | |
1209 | c3d2689d | balrog | switch (offset) {
|
1210 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
1211 | c3d2689d | balrog | omap_timer_sync(s); |
1212 | c3d2689d | balrog | s->enable = (value >> 5) & 1; |
1213 | c3d2689d | balrog | s->ptv = (value >> 2) & 7; |
1214 | c3d2689d | balrog | s->ar = (value >> 1) & 1; |
1215 | c3d2689d | balrog | s->st = value & 1;
|
1216 | c3d2689d | balrog | omap_timer_update(s); |
1217 | c3d2689d | balrog | return;
|
1218 | c3d2689d | balrog | |
1219 | c3d2689d | balrog | case 0x04: /* LOAD_TIM */ |
1220 | c3d2689d | balrog | s->reset_val = value; |
1221 | c3d2689d | balrog | return;
|
1222 | c3d2689d | balrog | |
1223 | c3d2689d | balrog | case 0x08: /* READ_TIM */ |
1224 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1225 | c3d2689d | balrog | break;
|
1226 | c3d2689d | balrog | |
1227 | c3d2689d | balrog | default:
|
1228 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1229 | c3d2689d | balrog | } |
1230 | c3d2689d | balrog | } |
1231 | c3d2689d | balrog | |
1232 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
|
1233 | c3d2689d | balrog | omap_badwidth_read32, |
1234 | c3d2689d | balrog | omap_badwidth_read32, |
1235 | c3d2689d | balrog | omap_mpu_timer_read, |
1236 | c3d2689d | balrog | }; |
1237 | c3d2689d | balrog | |
1238 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
|
1239 | c3d2689d | balrog | omap_badwidth_write32, |
1240 | c3d2689d | balrog | omap_badwidth_write32, |
1241 | c3d2689d | balrog | omap_mpu_timer_write, |
1242 | c3d2689d | balrog | }; |
1243 | c3d2689d | balrog | |
1244 | c3d2689d | balrog | static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) |
1245 | c3d2689d | balrog | { |
1246 | c3d2689d | balrog | qemu_del_timer(s->timer); |
1247 | c3d2689d | balrog | s->enable = 0;
|
1248 | c3d2689d | balrog | s->reset_val = 31337;
|
1249 | c3d2689d | balrog | s->val = 0;
|
1250 | c3d2689d | balrog | s->ptv = 0;
|
1251 | c3d2689d | balrog | s->ar = 0;
|
1252 | c3d2689d | balrog | s->st = 0;
|
1253 | c3d2689d | balrog | s->it_ena = 1;
|
1254 | c3d2689d | balrog | } |
1255 | c3d2689d | balrog | |
1256 | c3d2689d | balrog | struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
|
1257 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
1258 | c3d2689d | balrog | { |
1259 | c3d2689d | balrog | int iomemtype;
|
1260 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) |
1261 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_mpu_timer_s)); |
1262 | c3d2689d | balrog | |
1263 | c3d2689d | balrog | s->irq = irq; |
1264 | c3d2689d | balrog | s->clk = clk; |
1265 | c3d2689d | balrog | s->base = base; |
1266 | c3d2689d | balrog | s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s); |
1267 | c3d2689d | balrog | omap_mpu_timer_reset(s); |
1268 | c3d2689d | balrog | omap_timer_clk_setup(s); |
1269 | c3d2689d | balrog | |
1270 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
|
1271 | c3d2689d | balrog | omap_mpu_timer_writefn, s); |
1272 | c3d2689d | balrog | cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
1273 | c3d2689d | balrog | |
1274 | c3d2689d | balrog | return s;
|
1275 | c3d2689d | balrog | } |
1276 | c3d2689d | balrog | |
1277 | c3d2689d | balrog | /* Watchdog timer */
|
1278 | c3d2689d | balrog | struct omap_watchdog_timer_s {
|
1279 | c3d2689d | balrog | struct omap_mpu_timer_s timer;
|
1280 | c3d2689d | balrog | uint8_t last_wr; |
1281 | c3d2689d | balrog | int mode;
|
1282 | c3d2689d | balrog | int free;
|
1283 | c3d2689d | balrog | int reset;
|
1284 | c3d2689d | balrog | }; |
1285 | c3d2689d | balrog | |
1286 | c3d2689d | balrog | static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr) |
1287 | c3d2689d | balrog | { |
1288 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
1289 | c3d2689d | balrog | int offset = addr - s->timer.base;
|
1290 | c3d2689d | balrog | |
1291 | c3d2689d | balrog | switch (offset) {
|
1292 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
1293 | c3d2689d | balrog | return (s->timer.ptv << 9) | (s->timer.ar << 8) | |
1294 | c3d2689d | balrog | (s->timer.st << 7) | (s->free << 1); |
1295 | c3d2689d | balrog | |
1296 | c3d2689d | balrog | case 0x04: /* READ_TIMER */ |
1297 | c3d2689d | balrog | return omap_timer_read(&s->timer);
|
1298 | c3d2689d | balrog | |
1299 | c3d2689d | balrog | case 0x08: /* TIMER_MODE */ |
1300 | c3d2689d | balrog | return s->mode << 15; |
1301 | c3d2689d | balrog | } |
1302 | c3d2689d | balrog | |
1303 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1304 | c3d2689d | balrog | return 0; |
1305 | c3d2689d | balrog | } |
1306 | c3d2689d | balrog | |
1307 | c3d2689d | balrog | static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr, |
1308 | c3d2689d | balrog | uint32_t value) |
1309 | c3d2689d | balrog | { |
1310 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
1311 | c3d2689d | balrog | int offset = addr - s->timer.base;
|
1312 | c3d2689d | balrog | |
1313 | c3d2689d | balrog | switch (offset) {
|
1314 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
1315 | c3d2689d | balrog | omap_timer_sync(&s->timer); |
1316 | c3d2689d | balrog | s->timer.ptv = (value >> 9) & 7; |
1317 | c3d2689d | balrog | s->timer.ar = (value >> 8) & 1; |
1318 | c3d2689d | balrog | s->timer.st = (value >> 7) & 1; |
1319 | c3d2689d | balrog | s->free = (value >> 1) & 1; |
1320 | c3d2689d | balrog | omap_timer_update(&s->timer); |
1321 | c3d2689d | balrog | break;
|
1322 | c3d2689d | balrog | |
1323 | c3d2689d | balrog | case 0x04: /* LOAD_TIMER */ |
1324 | c3d2689d | balrog | s->timer.reset_val = value & 0xffff;
|
1325 | c3d2689d | balrog | break;
|
1326 | c3d2689d | balrog | |
1327 | c3d2689d | balrog | case 0x08: /* TIMER_MODE */ |
1328 | c3d2689d | balrog | if (!s->mode && ((value >> 15) & 1)) |
1329 | c3d2689d | balrog | omap_clk_get(s->timer.clk); |
1330 | c3d2689d | balrog | s->mode |= (value >> 15) & 1; |
1331 | c3d2689d | balrog | if (s->last_wr == 0xf5) { |
1332 | c3d2689d | balrog | if ((value & 0xff) == 0xa0) { |
1333 | d8f699cb | balrog | if (s->mode) {
|
1334 | d8f699cb | balrog | s->mode = 0;
|
1335 | d8f699cb | balrog | omap_clk_put(s->timer.clk); |
1336 | d8f699cb | balrog | } |
1337 | c3d2689d | balrog | } else {
|
1338 | c3d2689d | balrog | /* XXX: on T|E hardware somehow this has no effect,
|
1339 | c3d2689d | balrog | * on Zire 71 it works as specified. */
|
1340 | c3d2689d | balrog | s->reset = 1;
|
1341 | c3d2689d | balrog | qemu_system_reset_request(); |
1342 | c3d2689d | balrog | } |
1343 | c3d2689d | balrog | } |
1344 | c3d2689d | balrog | s->last_wr = value & 0xff;
|
1345 | c3d2689d | balrog | break;
|
1346 | c3d2689d | balrog | |
1347 | c3d2689d | balrog | default:
|
1348 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1349 | c3d2689d | balrog | } |
1350 | c3d2689d | balrog | } |
1351 | c3d2689d | balrog | |
1352 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
|
1353 | c3d2689d | balrog | omap_badwidth_read16, |
1354 | c3d2689d | balrog | omap_wd_timer_read, |
1355 | c3d2689d | balrog | omap_badwidth_read16, |
1356 | c3d2689d | balrog | }; |
1357 | c3d2689d | balrog | |
1358 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
|
1359 | c3d2689d | balrog | omap_badwidth_write16, |
1360 | c3d2689d | balrog | omap_wd_timer_write, |
1361 | c3d2689d | balrog | omap_badwidth_write16, |
1362 | c3d2689d | balrog | }; |
1363 | c3d2689d | balrog | |
1364 | c3d2689d | balrog | static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) |
1365 | c3d2689d | balrog | { |
1366 | c3d2689d | balrog | qemu_del_timer(s->timer.timer); |
1367 | c3d2689d | balrog | if (!s->mode)
|
1368 | c3d2689d | balrog | omap_clk_get(s->timer.clk); |
1369 | c3d2689d | balrog | s->mode = 1;
|
1370 | c3d2689d | balrog | s->free = 1;
|
1371 | c3d2689d | balrog | s->reset = 0;
|
1372 | c3d2689d | balrog | s->timer.enable = 1;
|
1373 | c3d2689d | balrog | s->timer.it_ena = 1;
|
1374 | c3d2689d | balrog | s->timer.reset_val = 0xffff;
|
1375 | c3d2689d | balrog | s->timer.val = 0;
|
1376 | c3d2689d | balrog | s->timer.st = 0;
|
1377 | c3d2689d | balrog | s->timer.ptv = 0;
|
1378 | c3d2689d | balrog | s->timer.ar = 0;
|
1379 | c3d2689d | balrog | omap_timer_update(&s->timer); |
1380 | c3d2689d | balrog | } |
1381 | c3d2689d | balrog | |
1382 | c3d2689d | balrog | struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
|
1383 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
1384 | c3d2689d | balrog | { |
1385 | c3d2689d | balrog | int iomemtype;
|
1386 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) |
1387 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_watchdog_timer_s)); |
1388 | c3d2689d | balrog | |
1389 | c3d2689d | balrog | s->timer.irq = irq; |
1390 | c3d2689d | balrog | s->timer.clk = clk; |
1391 | c3d2689d | balrog | s->timer.base = base; |
1392 | c3d2689d | balrog | s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
1393 | c3d2689d | balrog | omap_wd_timer_reset(s); |
1394 | c3d2689d | balrog | omap_timer_clk_setup(&s->timer); |
1395 | c3d2689d | balrog | |
1396 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
|
1397 | c3d2689d | balrog | omap_wd_timer_writefn, s); |
1398 | c3d2689d | balrog | cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
|
1399 | c3d2689d | balrog | |
1400 | c3d2689d | balrog | return s;
|
1401 | c3d2689d | balrog | } |
1402 | c3d2689d | balrog | |
1403 | c3d2689d | balrog | /* 32-kHz timer */
|
1404 | c3d2689d | balrog | struct omap_32khz_timer_s {
|
1405 | c3d2689d | balrog | struct omap_mpu_timer_s timer;
|
1406 | c3d2689d | balrog | }; |
1407 | c3d2689d | balrog | |
1408 | c3d2689d | balrog | static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr) |
1409 | c3d2689d | balrog | { |
1410 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
1411 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
1412 | c3d2689d | balrog | |
1413 | c3d2689d | balrog | switch (offset) {
|
1414 | c3d2689d | balrog | case 0x00: /* TVR */ |
1415 | c3d2689d | balrog | return s->timer.reset_val;
|
1416 | c3d2689d | balrog | |
1417 | c3d2689d | balrog | case 0x04: /* TCR */ |
1418 | c3d2689d | balrog | return omap_timer_read(&s->timer);
|
1419 | c3d2689d | balrog | |
1420 | c3d2689d | balrog | case 0x08: /* CR */ |
1421 | c3d2689d | balrog | return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; |
1422 | c3d2689d | balrog | |
1423 | c3d2689d | balrog | default:
|
1424 | c3d2689d | balrog | break;
|
1425 | c3d2689d | balrog | } |
1426 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1427 | c3d2689d | balrog | return 0; |
1428 | c3d2689d | balrog | } |
1429 | c3d2689d | balrog | |
1430 | c3d2689d | balrog | static void omap_os_timer_write(void *opaque, target_phys_addr_t addr, |
1431 | c3d2689d | balrog | uint32_t value) |
1432 | c3d2689d | balrog | { |
1433 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
1434 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
1435 | c3d2689d | balrog | |
1436 | c3d2689d | balrog | switch (offset) {
|
1437 | c3d2689d | balrog | case 0x00: /* TVR */ |
1438 | c3d2689d | balrog | s->timer.reset_val = value & 0x00ffffff;
|
1439 | c3d2689d | balrog | break;
|
1440 | c3d2689d | balrog | |
1441 | c3d2689d | balrog | case 0x04: /* TCR */ |
1442 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1443 | c3d2689d | balrog | break;
|
1444 | c3d2689d | balrog | |
1445 | c3d2689d | balrog | case 0x08: /* CR */ |
1446 | c3d2689d | balrog | s->timer.ar = (value >> 3) & 1; |
1447 | c3d2689d | balrog | s->timer.it_ena = (value >> 2) & 1; |
1448 | c3d2689d | balrog | if (s->timer.st != (value & 1) || (value & 2)) { |
1449 | c3d2689d | balrog | omap_timer_sync(&s->timer); |
1450 | c3d2689d | balrog | s->timer.enable = value & 1;
|
1451 | c3d2689d | balrog | s->timer.st = value & 1;
|
1452 | c3d2689d | balrog | omap_timer_update(&s->timer); |
1453 | c3d2689d | balrog | } |
1454 | c3d2689d | balrog | break;
|
1455 | c3d2689d | balrog | |
1456 | c3d2689d | balrog | default:
|
1457 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1458 | c3d2689d | balrog | } |
1459 | c3d2689d | balrog | } |
1460 | c3d2689d | balrog | |
1461 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
|
1462 | c3d2689d | balrog | omap_badwidth_read32, |
1463 | c3d2689d | balrog | omap_badwidth_read32, |
1464 | c3d2689d | balrog | omap_os_timer_read, |
1465 | c3d2689d | balrog | }; |
1466 | c3d2689d | balrog | |
1467 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
|
1468 | c3d2689d | balrog | omap_badwidth_write32, |
1469 | c3d2689d | balrog | omap_badwidth_write32, |
1470 | c3d2689d | balrog | omap_os_timer_write, |
1471 | c3d2689d | balrog | }; |
1472 | c3d2689d | balrog | |
1473 | c3d2689d | balrog | static void omap_os_timer_reset(struct omap_32khz_timer_s *s) |
1474 | c3d2689d | balrog | { |
1475 | c3d2689d | balrog | qemu_del_timer(s->timer.timer); |
1476 | c3d2689d | balrog | s->timer.enable = 0;
|
1477 | c3d2689d | balrog | s->timer.it_ena = 0;
|
1478 | c3d2689d | balrog | s->timer.reset_val = 0x00ffffff;
|
1479 | c3d2689d | balrog | s->timer.val = 0;
|
1480 | c3d2689d | balrog | s->timer.st = 0;
|
1481 | c3d2689d | balrog | s->timer.ptv = 0;
|
1482 | c3d2689d | balrog | s->timer.ar = 1;
|
1483 | c3d2689d | balrog | } |
1484 | c3d2689d | balrog | |
1485 | c3d2689d | balrog | struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
|
1486 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
1487 | c3d2689d | balrog | { |
1488 | c3d2689d | balrog | int iomemtype;
|
1489 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) |
1490 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_32khz_timer_s)); |
1491 | c3d2689d | balrog | |
1492 | c3d2689d | balrog | s->timer.irq = irq; |
1493 | c3d2689d | balrog | s->timer.clk = clk; |
1494 | c3d2689d | balrog | s->timer.base = base; |
1495 | c3d2689d | balrog | s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
1496 | c3d2689d | balrog | omap_os_timer_reset(s); |
1497 | c3d2689d | balrog | omap_timer_clk_setup(&s->timer); |
1498 | c3d2689d | balrog | |
1499 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
|
1500 | c3d2689d | balrog | omap_os_timer_writefn, s); |
1501 | c3d2689d | balrog | cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
|
1502 | c3d2689d | balrog | |
1503 | c3d2689d | balrog | return s;
|
1504 | c3d2689d | balrog | } |
1505 | c3d2689d | balrog | |
1506 | c3d2689d | balrog | /* Ultra Low-Power Device Module */
|
1507 | c3d2689d | balrog | static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr) |
1508 | c3d2689d | balrog | { |
1509 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1510 | c3d2689d | balrog | int offset = addr - s->ulpd_pm_base;
|
1511 | c3d2689d | balrog | uint16_t ret; |
1512 | c3d2689d | balrog | |
1513 | c3d2689d | balrog | switch (offset) {
|
1514 | c3d2689d | balrog | case 0x14: /* IT_STATUS */ |
1515 | c3d2689d | balrog | ret = s->ulpd_pm_regs[offset >> 2];
|
1516 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = 0; |
1517 | c3d2689d | balrog | qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
|
1518 | c3d2689d | balrog | return ret;
|
1519 | c3d2689d | balrog | |
1520 | c3d2689d | balrog | case 0x18: /* Reserved */ |
1521 | c3d2689d | balrog | case 0x1c: /* Reserved */ |
1522 | c3d2689d | balrog | case 0x20: /* Reserved */ |
1523 | c3d2689d | balrog | case 0x28: /* Reserved */ |
1524 | c3d2689d | balrog | case 0x2c: /* Reserved */ |
1525 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1526 | c3d2689d | balrog | case 0x00: /* COUNTER_32_LSB */ |
1527 | c3d2689d | balrog | case 0x04: /* COUNTER_32_MSB */ |
1528 | c3d2689d | balrog | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
1529 | c3d2689d | balrog | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
1530 | c3d2689d | balrog | case 0x10: /* GAUGING_CTRL */ |
1531 | c3d2689d | balrog | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
1532 | c3d2689d | balrog | case 0x30: /* CLOCK_CTRL */ |
1533 | c3d2689d | balrog | case 0x34: /* SOFT_REQ */ |
1534 | c3d2689d | balrog | case 0x38: /* COUNTER_32_FIQ */ |
1535 | c3d2689d | balrog | case 0x3c: /* DPLL_CTRL */ |
1536 | c3d2689d | balrog | case 0x40: /* STATUS_REQ */ |
1537 | c3d2689d | balrog | /* XXX: check clk::usecount state for every clock */
|
1538 | c3d2689d | balrog | case 0x48: /* LOCL_TIME */ |
1539 | c3d2689d | balrog | case 0x4c: /* APLL_CTRL */ |
1540 | c3d2689d | balrog | case 0x50: /* POWER_CTRL */ |
1541 | c3d2689d | balrog | return s->ulpd_pm_regs[offset >> 2]; |
1542 | c3d2689d | balrog | } |
1543 | c3d2689d | balrog | |
1544 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1545 | c3d2689d | balrog | return 0; |
1546 | c3d2689d | balrog | } |
1547 | c3d2689d | balrog | |
1548 | c3d2689d | balrog | static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, |
1549 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1550 | c3d2689d | balrog | { |
1551 | c3d2689d | balrog | if (diff & (1 << 4)) /* USB_MCLK_EN */ |
1552 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); |
1553 | c3d2689d | balrog | if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ |
1554 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); |
1555 | c3d2689d | balrog | } |
1556 | c3d2689d | balrog | |
1557 | c3d2689d | balrog | static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, |
1558 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1559 | c3d2689d | balrog | { |
1560 | c3d2689d | balrog | if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ |
1561 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); |
1562 | c3d2689d | balrog | if (diff & (1 << 1)) /* SOFT_COM_REQ */ |
1563 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); |
1564 | c3d2689d | balrog | if (diff & (1 << 2)) /* SOFT_SDW_REQ */ |
1565 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); |
1566 | c3d2689d | balrog | if (diff & (1 << 3)) /* SOFT_USB_REQ */ |
1567 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); |
1568 | c3d2689d | balrog | } |
1569 | c3d2689d | balrog | |
1570 | c3d2689d | balrog | static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr, |
1571 | c3d2689d | balrog | uint32_t value) |
1572 | c3d2689d | balrog | { |
1573 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1574 | c3d2689d | balrog | int offset = addr - s->ulpd_pm_base;
|
1575 | c3d2689d | balrog | int64_t now, ticks; |
1576 | c3d2689d | balrog | int div, mult;
|
1577 | c3d2689d | balrog | static const int bypass_div[4] = { 1, 2, 4, 4 }; |
1578 | c3d2689d | balrog | uint16_t diff; |
1579 | c3d2689d | balrog | |
1580 | c3d2689d | balrog | switch (offset) {
|
1581 | c3d2689d | balrog | case 0x00: /* COUNTER_32_LSB */ |
1582 | c3d2689d | balrog | case 0x04: /* COUNTER_32_MSB */ |
1583 | c3d2689d | balrog | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
1584 | c3d2689d | balrog | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
1585 | c3d2689d | balrog | case 0x14: /* IT_STATUS */ |
1586 | c3d2689d | balrog | case 0x40: /* STATUS_REQ */ |
1587 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1588 | c3d2689d | balrog | break;
|
1589 | c3d2689d | balrog | |
1590 | c3d2689d | balrog | case 0x10: /* GAUGING_CTRL */ |
1591 | c3d2689d | balrog | /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
|
1592 | c3d2689d | balrog | if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) { |
1593 | c3d2689d | balrog | now = qemu_get_clock(vm_clock); |
1594 | c3d2689d | balrog | |
1595 | c3d2689d | balrog | if (value & 1) |
1596 | c3d2689d | balrog | s->ulpd_gauge_start = now; |
1597 | c3d2689d | balrog | else {
|
1598 | c3d2689d | balrog | now -= s->ulpd_gauge_start; |
1599 | c3d2689d | balrog | |
1600 | c3d2689d | balrog | /* 32-kHz ticks */
|
1601 | c3d2689d | balrog | ticks = muldiv64(now, 32768, ticks_per_sec);
|
1602 | c3d2689d | balrog | s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; |
1603 | c3d2689d | balrog | s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; |
1604 | c3d2689d | balrog | if (ticks >> 32) /* OVERFLOW_32K */ |
1605 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; |
1606 | c3d2689d | balrog | |
1607 | c3d2689d | balrog | /* High frequency ticks */
|
1608 | c3d2689d | balrog | ticks = muldiv64(now, 12000000, ticks_per_sec);
|
1609 | c3d2689d | balrog | s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; |
1610 | c3d2689d | balrog | s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; |
1611 | c3d2689d | balrog | if (ticks >> 32) /* OVERFLOW_HI_FREQ */ |
1612 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; |
1613 | c3d2689d | balrog | |
1614 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ |
1615 | c3d2689d | balrog | qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
|
1616 | c3d2689d | balrog | } |
1617 | c3d2689d | balrog | } |
1618 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value;
|
1619 | c3d2689d | balrog | break;
|
1620 | c3d2689d | balrog | |
1621 | c3d2689d | balrog | case 0x18: /* Reserved */ |
1622 | c3d2689d | balrog | case 0x1c: /* Reserved */ |
1623 | c3d2689d | balrog | case 0x20: /* Reserved */ |
1624 | c3d2689d | balrog | case 0x28: /* Reserved */ |
1625 | c3d2689d | balrog | case 0x2c: /* Reserved */ |
1626 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1627 | c3d2689d | balrog | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
1628 | c3d2689d | balrog | case 0x38: /* COUNTER_32_FIQ */ |
1629 | c3d2689d | balrog | case 0x48: /* LOCL_TIME */ |
1630 | c3d2689d | balrog | case 0x50: /* POWER_CTRL */ |
1631 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value;
|
1632 | c3d2689d | balrog | break;
|
1633 | c3d2689d | balrog | |
1634 | c3d2689d | balrog | case 0x30: /* CLOCK_CTRL */ |
1635 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] ^ value;
|
1636 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0x3f; |
1637 | c3d2689d | balrog | omap_ulpd_clk_update(s, diff, value); |
1638 | c3d2689d | balrog | break;
|
1639 | c3d2689d | balrog | |
1640 | c3d2689d | balrog | case 0x34: /* SOFT_REQ */ |
1641 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] ^ value;
|
1642 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0x1f; |
1643 | c3d2689d | balrog | omap_ulpd_req_update(s, diff, value); |
1644 | c3d2689d | balrog | break;
|
1645 | c3d2689d | balrog | |
1646 | c3d2689d | balrog | case 0x3c: /* DPLL_CTRL */ |
1647 | c3d2689d | balrog | /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
|
1648 | c3d2689d | balrog | * omitted altogether, probably a typo. */
|
1649 | c3d2689d | balrog | /* This register has identical semantics with DPLL(1:3) control
|
1650 | c3d2689d | balrog | * registers, see omap_dpll_write() */
|
1651 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] & value;
|
1652 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0x2fff; |
1653 | c3d2689d | balrog | if (diff & (0x3ff << 2)) { |
1654 | c3d2689d | balrog | if (value & (1 << 4)) { /* PLL_ENABLE */ |
1655 | c3d2689d | balrog | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
1656 | c3d2689d | balrog | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
1657 | c3d2689d | balrog | } else {
|
1658 | c3d2689d | balrog | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
1659 | c3d2689d | balrog | mult = 1;
|
1660 | c3d2689d | balrog | } |
1661 | c3d2689d | balrog | omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
|
1662 | c3d2689d | balrog | } |
1663 | c3d2689d | balrog | |
1664 | c3d2689d | balrog | /* Enter the desired mode. */
|
1665 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] =
|
1666 | c3d2689d | balrog | (s->ulpd_pm_regs[offset >> 2] & 0xfffe) | |
1667 | c3d2689d | balrog | ((s->ulpd_pm_regs[offset >> 2] >> 4) & 1); |
1668 | c3d2689d | balrog | |
1669 | c3d2689d | balrog | /* Act as if the lock is restored. */
|
1670 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] |= 2; |
1671 | c3d2689d | balrog | break;
|
1672 | c3d2689d | balrog | |
1673 | c3d2689d | balrog | case 0x4c: /* APLL_CTRL */ |
1674 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] & value;
|
1675 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0xf; |
1676 | c3d2689d | balrog | if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ |
1677 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
|
1678 | c3d2689d | balrog | (value & (1 << 0)) ? "apll" : "dpll4")); |
1679 | c3d2689d | balrog | break;
|
1680 | c3d2689d | balrog | |
1681 | c3d2689d | balrog | default:
|
1682 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1683 | c3d2689d | balrog | } |
1684 | c3d2689d | balrog | } |
1685 | c3d2689d | balrog | |
1686 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
|
1687 | c3d2689d | balrog | omap_badwidth_read16, |
1688 | c3d2689d | balrog | omap_ulpd_pm_read, |
1689 | c3d2689d | balrog | omap_badwidth_read16, |
1690 | c3d2689d | balrog | }; |
1691 | c3d2689d | balrog | |
1692 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
|
1693 | c3d2689d | balrog | omap_badwidth_write16, |
1694 | c3d2689d | balrog | omap_ulpd_pm_write, |
1695 | c3d2689d | balrog | omap_badwidth_write16, |
1696 | c3d2689d | balrog | }; |
1697 | c3d2689d | balrog | |
1698 | c3d2689d | balrog | static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) |
1699 | c3d2689d | balrog | { |
1700 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; |
1701 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; |
1702 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; |
1703 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; |
1704 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; |
1705 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; |
1706 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; |
1707 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; |
1708 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; |
1709 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; |
1710 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; |
1711 | c3d2689d | balrog | omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); |
1712 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; |
1713 | c3d2689d | balrog | omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); |
1714 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; |
1715 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; |
1716 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; |
1717 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ |
1718 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; |
1719 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; |
1720 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; |
1721 | c3d2689d | balrog | omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); |
1722 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); |
1723 | c3d2689d | balrog | } |
1724 | c3d2689d | balrog | |
1725 | c3d2689d | balrog | static void omap_ulpd_pm_init(target_phys_addr_t base, |
1726 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1727 | c3d2689d | balrog | { |
1728 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn, |
1729 | c3d2689d | balrog | omap_ulpd_pm_writefn, mpu); |
1730 | c3d2689d | balrog | |
1731 | c3d2689d | balrog | mpu->ulpd_pm_base = base; |
1732 | c3d2689d | balrog | cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
|
1733 | c3d2689d | balrog | omap_ulpd_pm_reset(mpu); |
1734 | c3d2689d | balrog | } |
1735 | c3d2689d | balrog | |
1736 | c3d2689d | balrog | /* OMAP Pin Configuration */
|
1737 | c3d2689d | balrog | static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr) |
1738 | c3d2689d | balrog | { |
1739 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1740 | c3d2689d | balrog | int offset = addr - s->pin_cfg_base;
|
1741 | c3d2689d | balrog | |
1742 | c3d2689d | balrog | switch (offset) {
|
1743 | c3d2689d | balrog | case 0x00: /* FUNC_MUX_CTRL_0 */ |
1744 | c3d2689d | balrog | case 0x04: /* FUNC_MUX_CTRL_1 */ |
1745 | c3d2689d | balrog | case 0x08: /* FUNC_MUX_CTRL_2 */ |
1746 | c3d2689d | balrog | return s->func_mux_ctrl[offset >> 2]; |
1747 | c3d2689d | balrog | |
1748 | c3d2689d | balrog | case 0x0c: /* COMP_MODE_CTRL_0 */ |
1749 | c3d2689d | balrog | return s->comp_mode_ctrl[0]; |
1750 | c3d2689d | balrog | |
1751 | c3d2689d | balrog | case 0x10: /* FUNC_MUX_CTRL_3 */ |
1752 | c3d2689d | balrog | case 0x14: /* FUNC_MUX_CTRL_4 */ |
1753 | c3d2689d | balrog | case 0x18: /* FUNC_MUX_CTRL_5 */ |
1754 | c3d2689d | balrog | case 0x1c: /* FUNC_MUX_CTRL_6 */ |
1755 | c3d2689d | balrog | case 0x20: /* FUNC_MUX_CTRL_7 */ |
1756 | c3d2689d | balrog | case 0x24: /* FUNC_MUX_CTRL_8 */ |
1757 | c3d2689d | balrog | case 0x28: /* FUNC_MUX_CTRL_9 */ |
1758 | c3d2689d | balrog | case 0x2c: /* FUNC_MUX_CTRL_A */ |
1759 | c3d2689d | balrog | case 0x30: /* FUNC_MUX_CTRL_B */ |
1760 | c3d2689d | balrog | case 0x34: /* FUNC_MUX_CTRL_C */ |
1761 | c3d2689d | balrog | case 0x38: /* FUNC_MUX_CTRL_D */ |
1762 | c3d2689d | balrog | return s->func_mux_ctrl[(offset >> 2) - 1]; |
1763 | c3d2689d | balrog | |
1764 | c3d2689d | balrog | case 0x40: /* PULL_DWN_CTRL_0 */ |
1765 | c3d2689d | balrog | case 0x44: /* PULL_DWN_CTRL_1 */ |
1766 | c3d2689d | balrog | case 0x48: /* PULL_DWN_CTRL_2 */ |
1767 | c3d2689d | balrog | case 0x4c: /* PULL_DWN_CTRL_3 */ |
1768 | c3d2689d | balrog | return s->pull_dwn_ctrl[(offset & 0xf) >> 2]; |
1769 | c3d2689d | balrog | |
1770 | c3d2689d | balrog | case 0x50: /* GATE_INH_CTRL_0 */ |
1771 | c3d2689d | balrog | return s->gate_inh_ctrl[0]; |
1772 | c3d2689d | balrog | |
1773 | c3d2689d | balrog | case 0x60: /* VOLTAGE_CTRL_0 */ |
1774 | c3d2689d | balrog | return s->voltage_ctrl[0]; |
1775 | c3d2689d | balrog | |
1776 | c3d2689d | balrog | case 0x70: /* TEST_DBG_CTRL_0 */ |
1777 | c3d2689d | balrog | return s->test_dbg_ctrl[0]; |
1778 | c3d2689d | balrog | |
1779 | c3d2689d | balrog | case 0x80: /* MOD_CONF_CTRL_0 */ |
1780 | c3d2689d | balrog | return s->mod_conf_ctrl[0]; |
1781 | c3d2689d | balrog | } |
1782 | c3d2689d | balrog | |
1783 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1784 | c3d2689d | balrog | return 0; |
1785 | c3d2689d | balrog | } |
1786 | c3d2689d | balrog | |
1787 | c3d2689d | balrog | static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, |
1788 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
1789 | c3d2689d | balrog | { |
1790 | c3d2689d | balrog | if (s->compat1509) {
|
1791 | c3d2689d | balrog | if (diff & (1 << 9)) /* BLUETOOTH */ |
1792 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
|
1793 | c3d2689d | balrog | (~value >> 9) & 1); |
1794 | c3d2689d | balrog | if (diff & (1 << 7)) /* USB.CLKO */ |
1795 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb.clko"),
|
1796 | c3d2689d | balrog | (value >> 7) & 1); |
1797 | c3d2689d | balrog | } |
1798 | c3d2689d | balrog | } |
1799 | c3d2689d | balrog | |
1800 | c3d2689d | balrog | static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, |
1801 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
1802 | c3d2689d | balrog | { |
1803 | c3d2689d | balrog | if (s->compat1509) {
|
1804 | c3d2689d | balrog | if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */ |
1805 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
|
1806 | c3d2689d | balrog | (value >> 31) & 1); |
1807 | c3d2689d | balrog | if (diff & (1 << 1)) /* CLK32K */ |
1808 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "clk32k_out"),
|
1809 | c3d2689d | balrog | (~value >> 1) & 1); |
1810 | c3d2689d | balrog | } |
1811 | c3d2689d | balrog | } |
1812 | c3d2689d | balrog | |
1813 | c3d2689d | balrog | static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, |
1814 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
1815 | c3d2689d | balrog | { |
1816 | c3d2689d | balrog | if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */ |
1817 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart3_ck"),
|
1818 | c3d2689d | balrog | omap_findclk(s, ((value >> 31) & 1) ? |
1819 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1820 | c3d2689d | balrog | if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ |
1821 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart2_ck"),
|
1822 | c3d2689d | balrog | omap_findclk(s, ((value >> 30) & 1) ? |
1823 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1824 | c3d2689d | balrog | if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ |
1825 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart1_ck"),
|
1826 | c3d2689d | balrog | omap_findclk(s, ((value >> 29) & 1) ? |
1827 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1828 | c3d2689d | balrog | if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ |
1829 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "mmc_ck"),
|
1830 | c3d2689d | balrog | omap_findclk(s, ((value >> 23) & 1) ? |
1831 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1832 | c3d2689d | balrog | if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ |
1833 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
|
1834 | c3d2689d | balrog | omap_findclk(s, ((value >> 12) & 1) ? |
1835 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1836 | c3d2689d | balrog | if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ |
1837 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); |
1838 | c3d2689d | balrog | } |
1839 | c3d2689d | balrog | |
1840 | c3d2689d | balrog | static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr, |
1841 | c3d2689d | balrog | uint32_t value) |
1842 | c3d2689d | balrog | { |
1843 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1844 | c3d2689d | balrog | int offset = addr - s->pin_cfg_base;
|
1845 | c3d2689d | balrog | uint32_t diff; |
1846 | c3d2689d | balrog | |
1847 | c3d2689d | balrog | switch (offset) {
|
1848 | c3d2689d | balrog | case 0x00: /* FUNC_MUX_CTRL_0 */ |
1849 | c3d2689d | balrog | diff = s->func_mux_ctrl[offset >> 2] ^ value;
|
1850 | c3d2689d | balrog | s->func_mux_ctrl[offset >> 2] = value;
|
1851 | c3d2689d | balrog | omap_pin_funcmux0_update(s, diff, value); |
1852 | c3d2689d | balrog | return;
|
1853 | c3d2689d | balrog | |
1854 | c3d2689d | balrog | case 0x04: /* FUNC_MUX_CTRL_1 */ |
1855 | c3d2689d | balrog | diff = s->func_mux_ctrl[offset >> 2] ^ value;
|
1856 | c3d2689d | balrog | s->func_mux_ctrl[offset >> 2] = value;
|
1857 | c3d2689d | balrog | omap_pin_funcmux1_update(s, diff, value); |
1858 | c3d2689d | balrog | return;
|
1859 | c3d2689d | balrog | |
1860 | c3d2689d | balrog | case 0x08: /* FUNC_MUX_CTRL_2 */ |
1861 | c3d2689d | balrog | s->func_mux_ctrl[offset >> 2] = value;
|
1862 | c3d2689d | balrog | return;
|
1863 | c3d2689d | balrog | |
1864 | c3d2689d | balrog | case 0x0c: /* COMP_MODE_CTRL_0 */ |
1865 | c3d2689d | balrog | s->comp_mode_ctrl[0] = value;
|
1866 | c3d2689d | balrog | s->compat1509 = (value != 0x0000eaef);
|
1867 | c3d2689d | balrog | omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); |
1868 | c3d2689d | balrog | omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); |
1869 | c3d2689d | balrog | return;
|
1870 | c3d2689d | balrog | |
1871 | c3d2689d | balrog | case 0x10: /* FUNC_MUX_CTRL_3 */ |
1872 | c3d2689d | balrog | case 0x14: /* FUNC_MUX_CTRL_4 */ |
1873 | c3d2689d | balrog | case 0x18: /* FUNC_MUX_CTRL_5 */ |
1874 | c3d2689d | balrog | case 0x1c: /* FUNC_MUX_CTRL_6 */ |
1875 | c3d2689d | balrog | case 0x20: /* FUNC_MUX_CTRL_7 */ |
1876 | c3d2689d | balrog | case 0x24: /* FUNC_MUX_CTRL_8 */ |
1877 | c3d2689d | balrog | case 0x28: /* FUNC_MUX_CTRL_9 */ |
1878 | c3d2689d | balrog | case 0x2c: /* FUNC_MUX_CTRL_A */ |
1879 | c3d2689d | balrog | case 0x30: /* FUNC_MUX_CTRL_B */ |
1880 | c3d2689d | balrog | case 0x34: /* FUNC_MUX_CTRL_C */ |
1881 | c3d2689d | balrog | case 0x38: /* FUNC_MUX_CTRL_D */ |
1882 | c3d2689d | balrog | s->func_mux_ctrl[(offset >> 2) - 1] = value; |
1883 | c3d2689d | balrog | return;
|
1884 | c3d2689d | balrog | |
1885 | c3d2689d | balrog | case 0x40: /* PULL_DWN_CTRL_0 */ |
1886 | c3d2689d | balrog | case 0x44: /* PULL_DWN_CTRL_1 */ |
1887 | c3d2689d | balrog | case 0x48: /* PULL_DWN_CTRL_2 */ |
1888 | c3d2689d | balrog | case 0x4c: /* PULL_DWN_CTRL_3 */ |
1889 | c3d2689d | balrog | s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value; |
1890 | c3d2689d | balrog | return;
|
1891 | c3d2689d | balrog | |
1892 | c3d2689d | balrog | case 0x50: /* GATE_INH_CTRL_0 */ |
1893 | c3d2689d | balrog | s->gate_inh_ctrl[0] = value;
|
1894 | c3d2689d | balrog | return;
|
1895 | c3d2689d | balrog | |
1896 | c3d2689d | balrog | case 0x60: /* VOLTAGE_CTRL_0 */ |
1897 | c3d2689d | balrog | s->voltage_ctrl[0] = value;
|
1898 | c3d2689d | balrog | return;
|
1899 | c3d2689d | balrog | |
1900 | c3d2689d | balrog | case 0x70: /* TEST_DBG_CTRL_0 */ |
1901 | c3d2689d | balrog | s->test_dbg_ctrl[0] = value;
|
1902 | c3d2689d | balrog | return;
|
1903 | c3d2689d | balrog | |
1904 | c3d2689d | balrog | case 0x80: /* MOD_CONF_CTRL_0 */ |
1905 | c3d2689d | balrog | diff = s->mod_conf_ctrl[0] ^ value;
|
1906 | c3d2689d | balrog | s->mod_conf_ctrl[0] = value;
|
1907 | c3d2689d | balrog | omap_pin_modconf1_update(s, diff, value); |
1908 | c3d2689d | balrog | return;
|
1909 | c3d2689d | balrog | |
1910 | c3d2689d | balrog | default:
|
1911 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1912 | c3d2689d | balrog | } |
1913 | c3d2689d | balrog | } |
1914 | c3d2689d | balrog | |
1915 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
|
1916 | c3d2689d | balrog | omap_badwidth_read32, |
1917 | c3d2689d | balrog | omap_badwidth_read32, |
1918 | c3d2689d | balrog | omap_pin_cfg_read, |
1919 | c3d2689d | balrog | }; |
1920 | c3d2689d | balrog | |
1921 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
|
1922 | c3d2689d | balrog | omap_badwidth_write32, |
1923 | c3d2689d | balrog | omap_badwidth_write32, |
1924 | c3d2689d | balrog | omap_pin_cfg_write, |
1925 | c3d2689d | balrog | }; |
1926 | c3d2689d | balrog | |
1927 | c3d2689d | balrog | static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) |
1928 | c3d2689d | balrog | { |
1929 | c3d2689d | balrog | /* Start in Compatibility Mode. */
|
1930 | c3d2689d | balrog | mpu->compat1509 = 1;
|
1931 | c3d2689d | balrog | omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); |
1932 | c3d2689d | balrog | omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); |
1933 | c3d2689d | balrog | omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); |
1934 | c3d2689d | balrog | memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); |
1935 | c3d2689d | balrog | memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); |
1936 | c3d2689d | balrog | memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); |
1937 | c3d2689d | balrog | memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); |
1938 | c3d2689d | balrog | memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); |
1939 | c3d2689d | balrog | memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); |
1940 | c3d2689d | balrog | memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); |
1941 | c3d2689d | balrog | } |
1942 | c3d2689d | balrog | |
1943 | c3d2689d | balrog | static void omap_pin_cfg_init(target_phys_addr_t base, |
1944 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1945 | c3d2689d | balrog | { |
1946 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn, |
1947 | c3d2689d | balrog | omap_pin_cfg_writefn, mpu); |
1948 | c3d2689d | balrog | |
1949 | c3d2689d | balrog | mpu->pin_cfg_base = base; |
1950 | c3d2689d | balrog | cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
|
1951 | c3d2689d | balrog | omap_pin_cfg_reset(mpu); |
1952 | c3d2689d | balrog | } |
1953 | c3d2689d | balrog | |
1954 | c3d2689d | balrog | /* Device Identification, Die Identification */
|
1955 | c3d2689d | balrog | static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr) |
1956 | c3d2689d | balrog | { |
1957 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1958 | c3d2689d | balrog | |
1959 | c3d2689d | balrog | switch (addr) {
|
1960 | c3d2689d | balrog | case 0xfffe1800: /* DIE_ID_LSB */ |
1961 | c3d2689d | balrog | return 0xc9581f0e; |
1962 | c3d2689d | balrog | case 0xfffe1804: /* DIE_ID_MSB */ |
1963 | c3d2689d | balrog | return 0xa8858bfa; |
1964 | c3d2689d | balrog | |
1965 | c3d2689d | balrog | case 0xfffe2000: /* PRODUCT_ID_LSB */ |
1966 | c3d2689d | balrog | return 0x00aaaafc; |
1967 | c3d2689d | balrog | case 0xfffe2004: /* PRODUCT_ID_MSB */ |
1968 | c3d2689d | balrog | return 0xcafeb574; |
1969 | c3d2689d | balrog | |
1970 | c3d2689d | balrog | case 0xfffed400: /* JTAG_ID_LSB */ |
1971 | c3d2689d | balrog | switch (s->mpu_model) {
|
1972 | c3d2689d | balrog | case omap310:
|
1973 | c3d2689d | balrog | return 0x03310315; |
1974 | c3d2689d | balrog | case omap1510:
|
1975 | c3d2689d | balrog | return 0x03310115; |
1976 | c3d2689d | balrog | } |
1977 | c3d2689d | balrog | break;
|
1978 | c3d2689d | balrog | |
1979 | c3d2689d | balrog | case 0xfffed404: /* JTAG_ID_MSB */ |
1980 | c3d2689d | balrog | switch (s->mpu_model) {
|
1981 | c3d2689d | balrog | case omap310:
|
1982 | c3d2689d | balrog | return 0xfb57402f; |
1983 | c3d2689d | balrog | case omap1510:
|
1984 | c3d2689d | balrog | return 0xfb47002f; |
1985 | c3d2689d | balrog | } |
1986 | c3d2689d | balrog | break;
|
1987 | c3d2689d | balrog | } |
1988 | c3d2689d | balrog | |
1989 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1990 | c3d2689d | balrog | return 0; |
1991 | c3d2689d | balrog | } |
1992 | c3d2689d | balrog | |
1993 | c3d2689d | balrog | static void omap_id_write(void *opaque, target_phys_addr_t addr, |
1994 | c3d2689d | balrog | uint32_t value) |
1995 | c3d2689d | balrog | { |
1996 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1997 | c3d2689d | balrog | } |
1998 | c3d2689d | balrog | |
1999 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_id_readfn[] = {
|
2000 | c3d2689d | balrog | omap_badwidth_read32, |
2001 | c3d2689d | balrog | omap_badwidth_read32, |
2002 | c3d2689d | balrog | omap_id_read, |
2003 | c3d2689d | balrog | }; |
2004 | c3d2689d | balrog | |
2005 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_id_writefn[] = {
|
2006 | c3d2689d | balrog | omap_badwidth_write32, |
2007 | c3d2689d | balrog | omap_badwidth_write32, |
2008 | c3d2689d | balrog | omap_id_write, |
2009 | c3d2689d | balrog | }; |
2010 | c3d2689d | balrog | |
2011 | c3d2689d | balrog | static void omap_id_init(struct omap_mpu_state_s *mpu) |
2012 | c3d2689d | balrog | { |
2013 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_id_readfn, |
2014 | c3d2689d | balrog | omap_id_writefn, mpu); |
2015 | c3d2689d | balrog | cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype); |
2016 | c3d2689d | balrog | cpu_register_physical_memory(0xfffed400, 0x100, iomemtype); |
2017 | c3d2689d | balrog | if (!cpu_is_omap15xx(mpu))
|
2018 | c3d2689d | balrog | cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype); |
2019 | c3d2689d | balrog | } |
2020 | c3d2689d | balrog | |
2021 | c3d2689d | balrog | /* MPUI Control (Dummy) */
|
2022 | c3d2689d | balrog | static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr) |
2023 | c3d2689d | balrog | { |
2024 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2025 | c3d2689d | balrog | int offset = addr - s->mpui_base;
|
2026 | c3d2689d | balrog | |
2027 | c3d2689d | balrog | switch (offset) {
|
2028 | c3d2689d | balrog | case 0x00: /* CTRL */ |
2029 | c3d2689d | balrog | return s->mpui_ctrl;
|
2030 | c3d2689d | balrog | case 0x04: /* DEBUG_ADDR */ |
2031 | c3d2689d | balrog | return 0x01ffffff; |
2032 | c3d2689d | balrog | case 0x08: /* DEBUG_DATA */ |
2033 | c3d2689d | balrog | return 0xffffffff; |
2034 | c3d2689d | balrog | case 0x0c: /* DEBUG_FLAG */ |
2035 | c3d2689d | balrog | return 0x00000800; |
2036 | c3d2689d | balrog | case 0x10: /* STATUS */ |
2037 | c3d2689d | balrog | return 0x00000000; |
2038 | c3d2689d | balrog | |
2039 | c3d2689d | balrog | /* Not in OMAP310 */
|
2040 | c3d2689d | balrog | case 0x14: /* DSP_STATUS */ |
2041 | c3d2689d | balrog | case 0x18: /* DSP_BOOT_CONFIG */ |
2042 | c3d2689d | balrog | return 0x00000000; |
2043 | c3d2689d | balrog | case 0x1c: /* DSP_MPUI_CONFIG */ |
2044 | c3d2689d | balrog | return 0x0000ffff; |
2045 | c3d2689d | balrog | } |
2046 | c3d2689d | balrog | |
2047 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2048 | c3d2689d | balrog | return 0; |
2049 | c3d2689d | balrog | } |
2050 | c3d2689d | balrog | |
2051 | c3d2689d | balrog | static void omap_mpui_write(void *opaque, target_phys_addr_t addr, |
2052 | c3d2689d | balrog | uint32_t value) |
2053 | c3d2689d | balrog | { |
2054 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2055 | c3d2689d | balrog | int offset = addr - s->mpui_base;
|
2056 | c3d2689d | balrog | |
2057 | c3d2689d | balrog | switch (offset) {
|
2058 | c3d2689d | balrog | case 0x00: /* CTRL */ |
2059 | c3d2689d | balrog | s->mpui_ctrl = value & 0x007fffff;
|
2060 | c3d2689d | balrog | break;
|
2061 | c3d2689d | balrog | |
2062 | c3d2689d | balrog | case 0x04: /* DEBUG_ADDR */ |
2063 | c3d2689d | balrog | case 0x08: /* DEBUG_DATA */ |
2064 | c3d2689d | balrog | case 0x0c: /* DEBUG_FLAG */ |
2065 | c3d2689d | balrog | case 0x10: /* STATUS */ |
2066 | c3d2689d | balrog | /* Not in OMAP310 */
|
2067 | c3d2689d | balrog | case 0x14: /* DSP_STATUS */ |
2068 | c3d2689d | balrog | OMAP_RO_REG(addr); |
2069 | c3d2689d | balrog | case 0x18: /* DSP_BOOT_CONFIG */ |
2070 | c3d2689d | balrog | case 0x1c: /* DSP_MPUI_CONFIG */ |
2071 | c3d2689d | balrog | break;
|
2072 | c3d2689d | balrog | |
2073 | c3d2689d | balrog | default:
|
2074 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2075 | c3d2689d | balrog | } |
2076 | c3d2689d | balrog | } |
2077 | c3d2689d | balrog | |
2078 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_mpui_readfn[] = {
|
2079 | c3d2689d | balrog | omap_badwidth_read32, |
2080 | c3d2689d | balrog | omap_badwidth_read32, |
2081 | c3d2689d | balrog | omap_mpui_read, |
2082 | c3d2689d | balrog | }; |
2083 | c3d2689d | balrog | |
2084 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
|
2085 | c3d2689d | balrog | omap_badwidth_write32, |
2086 | c3d2689d | balrog | omap_badwidth_write32, |
2087 | c3d2689d | balrog | omap_mpui_write, |
2088 | c3d2689d | balrog | }; |
2089 | c3d2689d | balrog | |
2090 | c3d2689d | balrog | static void omap_mpui_reset(struct omap_mpu_state_s *s) |
2091 | c3d2689d | balrog | { |
2092 | c3d2689d | balrog | s->mpui_ctrl = 0x0003ff1b;
|
2093 | c3d2689d | balrog | } |
2094 | c3d2689d | balrog | |
2095 | c3d2689d | balrog | static void omap_mpui_init(target_phys_addr_t base, |
2096 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
2097 | c3d2689d | balrog | { |
2098 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn, |
2099 | c3d2689d | balrog | omap_mpui_writefn, mpu); |
2100 | c3d2689d | balrog | |
2101 | c3d2689d | balrog | mpu->mpui_base = base; |
2102 | c3d2689d | balrog | cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
|
2103 | c3d2689d | balrog | |
2104 | c3d2689d | balrog | omap_mpui_reset(mpu); |
2105 | c3d2689d | balrog | } |
2106 | c3d2689d | balrog | |
2107 | c3d2689d | balrog | /* TIPB Bridges */
|
2108 | c3d2689d | balrog | struct omap_tipb_bridge_s {
|
2109 | c3d2689d | balrog | target_phys_addr_t base; |
2110 | c3d2689d | balrog | qemu_irq abort; |
2111 | c3d2689d | balrog | |
2112 | c3d2689d | balrog | int width_intr;
|
2113 | c3d2689d | balrog | uint16_t control; |
2114 | c3d2689d | balrog | uint16_t alloc; |
2115 | c3d2689d | balrog | uint16_t buffer; |
2116 | c3d2689d | balrog | uint16_t enh_control; |
2117 | c3d2689d | balrog | }; |
2118 | c3d2689d | balrog | |
2119 | c3d2689d | balrog | static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr) |
2120 | c3d2689d | balrog | { |
2121 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
2122 | c3d2689d | balrog | int offset = addr - s->base;
|
2123 | c3d2689d | balrog | |
2124 | c3d2689d | balrog | switch (offset) {
|
2125 | c3d2689d | balrog | case 0x00: /* TIPB_CNTL */ |
2126 | c3d2689d | balrog | return s->control;
|
2127 | c3d2689d | balrog | case 0x04: /* TIPB_BUS_ALLOC */ |
2128 | c3d2689d | balrog | return s->alloc;
|
2129 | c3d2689d | balrog | case 0x08: /* MPU_TIPB_CNTL */ |
2130 | c3d2689d | balrog | return s->buffer;
|
2131 | c3d2689d | balrog | case 0x0c: /* ENHANCED_TIPB_CNTL */ |
2132 | c3d2689d | balrog | return s->enh_control;
|
2133 | c3d2689d | balrog | case 0x10: /* ADDRESS_DBG */ |
2134 | c3d2689d | balrog | case 0x14: /* DATA_DEBUG_LOW */ |
2135 | c3d2689d | balrog | case 0x18: /* DATA_DEBUG_HIGH */ |
2136 | c3d2689d | balrog | return 0xffff; |
2137 | c3d2689d | balrog | case 0x1c: /* DEBUG_CNTR_SIG */ |
2138 | c3d2689d | balrog | return 0x00f8; |
2139 | c3d2689d | balrog | } |
2140 | c3d2689d | balrog | |
2141 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2142 | c3d2689d | balrog | return 0; |
2143 | c3d2689d | balrog | } |
2144 | c3d2689d | balrog | |
2145 | c3d2689d | balrog | static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr, |
2146 | c3d2689d | balrog | uint32_t value) |
2147 | c3d2689d | balrog | { |
2148 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
2149 | c3d2689d | balrog | int offset = addr - s->base;
|
2150 | c3d2689d | balrog | |
2151 | c3d2689d | balrog | switch (offset) {
|
2152 | c3d2689d | balrog | case 0x00: /* TIPB_CNTL */ |
2153 | c3d2689d | balrog | s->control = value & 0xffff;
|
2154 | c3d2689d | balrog | break;
|
2155 | c3d2689d | balrog | |
2156 | c3d2689d | balrog | case 0x04: /* TIPB_BUS_ALLOC */ |
2157 | c3d2689d | balrog | s->alloc = value & 0x003f;
|
2158 | c3d2689d | balrog | break;
|
2159 | c3d2689d | balrog | |
2160 | c3d2689d | balrog | case 0x08: /* MPU_TIPB_CNTL */ |
2161 | c3d2689d | balrog | s->buffer = value & 0x0003;
|
2162 | c3d2689d | balrog | break;
|
2163 | c3d2689d | balrog | |
2164 | c3d2689d | balrog | case 0x0c: /* ENHANCED_TIPB_CNTL */ |
2165 | c3d2689d | balrog | s->width_intr = !(value & 2);
|
2166 | c3d2689d | balrog | s->enh_control = value & 0x000f;
|
2167 | c3d2689d | balrog | break;
|
2168 | c3d2689d | balrog | |
2169 | c3d2689d | balrog | case 0x10: /* ADDRESS_DBG */ |
2170 | c3d2689d | balrog | case 0x14: /* DATA_DEBUG_LOW */ |
2171 | c3d2689d | balrog | case 0x18: /* DATA_DEBUG_HIGH */ |
2172 | c3d2689d | balrog | case 0x1c: /* DEBUG_CNTR_SIG */ |
2173 | c3d2689d | balrog | OMAP_RO_REG(addr); |
2174 | c3d2689d | balrog | break;
|
2175 | c3d2689d | balrog | |
2176 | c3d2689d | balrog | default:
|
2177 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2178 | c3d2689d | balrog | } |
2179 | c3d2689d | balrog | } |
2180 | c3d2689d | balrog | |
2181 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
|
2182 | c3d2689d | balrog | omap_badwidth_read16, |
2183 | c3d2689d | balrog | omap_tipb_bridge_read, |
2184 | c3d2689d | balrog | omap_tipb_bridge_read, |
2185 | c3d2689d | balrog | }; |
2186 | c3d2689d | balrog | |
2187 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
|
2188 | c3d2689d | balrog | omap_badwidth_write16, |
2189 | c3d2689d | balrog | omap_tipb_bridge_write, |
2190 | c3d2689d | balrog | omap_tipb_bridge_write, |
2191 | c3d2689d | balrog | }; |
2192 | c3d2689d | balrog | |
2193 | c3d2689d | balrog | static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) |
2194 | c3d2689d | balrog | { |
2195 | c3d2689d | balrog | s->control = 0xffff;
|
2196 | c3d2689d | balrog | s->alloc = 0x0009;
|
2197 | c3d2689d | balrog | s->buffer = 0x0000;
|
2198 | c3d2689d | balrog | s->enh_control = 0x000f;
|
2199 | c3d2689d | balrog | } |
2200 | c3d2689d | balrog | |
2201 | c3d2689d | balrog | struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
|
2202 | c3d2689d | balrog | qemu_irq abort_irq, omap_clk clk) |
2203 | c3d2689d | balrog | { |
2204 | c3d2689d | balrog | int iomemtype;
|
2205 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) |
2206 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_tipb_bridge_s)); |
2207 | c3d2689d | balrog | |
2208 | c3d2689d | balrog | s->abort = abort_irq; |
2209 | c3d2689d | balrog | s->base = base; |
2210 | c3d2689d | balrog | omap_tipb_bridge_reset(s); |
2211 | c3d2689d | balrog | |
2212 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
|
2213 | c3d2689d | balrog | omap_tipb_bridge_writefn, s); |
2214 | c3d2689d | balrog | cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
2215 | c3d2689d | balrog | |
2216 | c3d2689d | balrog | return s;
|
2217 | c3d2689d | balrog | } |
2218 | c3d2689d | balrog | |
2219 | c3d2689d | balrog | /* Dummy Traffic Controller's Memory Interface */
|
2220 | c3d2689d | balrog | static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr) |
2221 | c3d2689d | balrog | { |
2222 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2223 | c3d2689d | balrog | int offset = addr - s->tcmi_base;
|
2224 | c3d2689d | balrog | uint32_t ret; |
2225 | c3d2689d | balrog | |
2226 | c3d2689d | balrog | switch (offset) {
|
2227 | d8f699cb | balrog | case 0x00: /* IMIF_PRIO */ |
2228 | d8f699cb | balrog | case 0x04: /* EMIFS_PRIO */ |
2229 | d8f699cb | balrog | case 0x08: /* EMIFF_PRIO */ |
2230 | d8f699cb | balrog | case 0x0c: /* EMIFS_CONFIG */ |
2231 | d8f699cb | balrog | case 0x10: /* EMIFS_CS0_CONFIG */ |
2232 | d8f699cb | balrog | case 0x14: /* EMIFS_CS1_CONFIG */ |
2233 | d8f699cb | balrog | case 0x18: /* EMIFS_CS2_CONFIG */ |
2234 | d8f699cb | balrog | case 0x1c: /* EMIFS_CS3_CONFIG */ |
2235 | d8f699cb | balrog | case 0x24: /* EMIFF_MRS */ |
2236 | d8f699cb | balrog | case 0x28: /* TIMEOUT1 */ |
2237 | d8f699cb | balrog | case 0x2c: /* TIMEOUT2 */ |
2238 | d8f699cb | balrog | case 0x30: /* TIMEOUT3 */ |
2239 | d8f699cb | balrog | case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ |
2240 | d8f699cb | balrog | case 0x40: /* EMIFS_CFG_DYN_WAIT */ |
2241 | c3d2689d | balrog | return s->tcmi_regs[offset >> 2]; |
2242 | c3d2689d | balrog | |
2243 | d8f699cb | balrog | case 0x20: /* EMIFF_SDRAM_CONFIG */ |
2244 | c3d2689d | balrog | ret = s->tcmi_regs[offset >> 2];
|
2245 | c3d2689d | balrog | s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ |
2246 | c3d2689d | balrog | /* XXX: We can try using the VGA_DIRTY flag for this */
|
2247 | c3d2689d | balrog | return ret;
|
2248 | c3d2689d | balrog | } |
2249 | c3d2689d | balrog | |
2250 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2251 | c3d2689d | balrog | return 0; |
2252 | c3d2689d | balrog | } |
2253 | c3d2689d | balrog | |
2254 | c3d2689d | balrog | static void omap_tcmi_write(void *opaque, target_phys_addr_t addr, |
2255 | c3d2689d | balrog | uint32_t value) |
2256 | c3d2689d | balrog | { |
2257 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2258 | c3d2689d | balrog | int offset = addr - s->tcmi_base;
|
2259 | c3d2689d | balrog | |
2260 | c3d2689d | balrog | switch (offset) {
|
2261 | d8f699cb | balrog | case 0x00: /* IMIF_PRIO */ |
2262 | d8f699cb | balrog | case 0x04: /* EMIFS_PRIO */ |
2263 | d8f699cb | balrog | case 0x08: /* EMIFF_PRIO */ |
2264 | d8f699cb | balrog | case 0x10: /* EMIFS_CS0_CONFIG */ |
2265 | d8f699cb | balrog | case 0x14: /* EMIFS_CS1_CONFIG */ |
2266 | d8f699cb | balrog | case 0x18: /* EMIFS_CS2_CONFIG */ |
2267 | d8f699cb | balrog | case 0x1c: /* EMIFS_CS3_CONFIG */ |
2268 | d8f699cb | balrog | case 0x20: /* EMIFF_SDRAM_CONFIG */ |
2269 | d8f699cb | balrog | case 0x24: /* EMIFF_MRS */ |
2270 | d8f699cb | balrog | case 0x28: /* TIMEOUT1 */ |
2271 | d8f699cb | balrog | case 0x2c: /* TIMEOUT2 */ |
2272 | d8f699cb | balrog | case 0x30: /* TIMEOUT3 */ |
2273 | d8f699cb | balrog | case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ |
2274 | d8f699cb | balrog | case 0x40: /* EMIFS_CFG_DYN_WAIT */ |
2275 | c3d2689d | balrog | s->tcmi_regs[offset >> 2] = value;
|
2276 | c3d2689d | balrog | break;
|
2277 | d8f699cb | balrog | case 0x0c: /* EMIFS_CONFIG */ |
2278 | c3d2689d | balrog | s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4); |
2279 | c3d2689d | balrog | break;
|
2280 | c3d2689d | balrog | |
2281 | c3d2689d | balrog | default:
|
2282 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2283 | c3d2689d | balrog | } |
2284 | c3d2689d | balrog | } |
2285 | c3d2689d | balrog | |
2286 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
|
2287 | c3d2689d | balrog | omap_badwidth_read32, |
2288 | c3d2689d | balrog | omap_badwidth_read32, |
2289 | c3d2689d | balrog | omap_tcmi_read, |
2290 | c3d2689d | balrog | }; |
2291 | c3d2689d | balrog | |
2292 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
|
2293 | c3d2689d | balrog | omap_badwidth_write32, |
2294 | c3d2689d | balrog | omap_badwidth_write32, |
2295 | c3d2689d | balrog | omap_tcmi_write, |
2296 | c3d2689d | balrog | }; |
2297 | c3d2689d | balrog | |
2298 | c3d2689d | balrog | static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) |
2299 | c3d2689d | balrog | { |
2300 | c3d2689d | balrog | mpu->tcmi_regs[0x00 >> 2] = 0x00000000; |
2301 | c3d2689d | balrog | mpu->tcmi_regs[0x04 >> 2] = 0x00000000; |
2302 | c3d2689d | balrog | mpu->tcmi_regs[0x08 >> 2] = 0x00000000; |
2303 | c3d2689d | balrog | mpu->tcmi_regs[0x0c >> 2] = 0x00000010; |
2304 | c3d2689d | balrog | mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; |
2305 | c3d2689d | balrog | mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; |
2306 | c3d2689d | balrog | mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; |
2307 | c3d2689d | balrog | mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; |
2308 | c3d2689d | balrog | mpu->tcmi_regs[0x20 >> 2] = 0x00618800; |
2309 | c3d2689d | balrog | mpu->tcmi_regs[0x24 >> 2] = 0x00000037; |
2310 | c3d2689d | balrog | mpu->tcmi_regs[0x28 >> 2] = 0x00000000; |
2311 | c3d2689d | balrog | mpu->tcmi_regs[0x2c >> 2] = 0x00000000; |
2312 | c3d2689d | balrog | mpu->tcmi_regs[0x30 >> 2] = 0x00000000; |
2313 | c3d2689d | balrog | mpu->tcmi_regs[0x3c >> 2] = 0x00000003; |
2314 | c3d2689d | balrog | mpu->tcmi_regs[0x40 >> 2] = 0x00000000; |
2315 | c3d2689d | balrog | } |
2316 | c3d2689d | balrog | |
2317 | c3d2689d | balrog | static void omap_tcmi_init(target_phys_addr_t base, |
2318 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
2319 | c3d2689d | balrog | { |
2320 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn, |
2321 | c3d2689d | balrog | omap_tcmi_writefn, mpu); |
2322 | c3d2689d | balrog | |
2323 | c3d2689d | balrog | mpu->tcmi_base = base; |
2324 | c3d2689d | balrog | cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
|
2325 | c3d2689d | balrog | omap_tcmi_reset(mpu); |
2326 | c3d2689d | balrog | } |
2327 | c3d2689d | balrog | |
2328 | c3d2689d | balrog | /* Digital phase-locked loops control */
|
2329 | c3d2689d | balrog | static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr) |
2330 | c3d2689d | balrog | { |
2331 | c3d2689d | balrog | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
2332 | c3d2689d | balrog | int offset = addr - s->base;
|
2333 | c3d2689d | balrog | |
2334 | c3d2689d | balrog | if (offset == 0x00) /* CTL_REG */ |
2335 | c3d2689d | balrog | return s->mode;
|
2336 | c3d2689d | balrog | |
2337 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2338 | c3d2689d | balrog | return 0; |
2339 | c3d2689d | balrog | } |
2340 | c3d2689d | balrog | |
2341 | c3d2689d | balrog | static void omap_dpll_write(void *opaque, target_phys_addr_t addr, |
2342 | c3d2689d | balrog | uint32_t value) |
2343 | c3d2689d | balrog | { |
2344 | c3d2689d | balrog | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
2345 | c3d2689d | balrog | uint16_t diff; |
2346 | c3d2689d | balrog | int offset = addr - s->base;
|
2347 | c3d2689d | balrog | static const int bypass_div[4] = { 1, 2, 4, 4 }; |
2348 | c3d2689d | balrog | int div, mult;
|
2349 | c3d2689d | balrog | |
2350 | c3d2689d | balrog | if (offset == 0x00) { /* CTL_REG */ |
2351 | c3d2689d | balrog | /* See omap_ulpd_pm_write() too */
|
2352 | c3d2689d | balrog | diff = s->mode & value; |
2353 | c3d2689d | balrog | s->mode = value & 0x2fff;
|
2354 | c3d2689d | balrog | if (diff & (0x3ff << 2)) { |
2355 | c3d2689d | balrog | if (value & (1 << 4)) { /* PLL_ENABLE */ |
2356 | c3d2689d | balrog | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
2357 | c3d2689d | balrog | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
2358 | c3d2689d | balrog | } else {
|
2359 | c3d2689d | balrog | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
2360 | c3d2689d | balrog | mult = 1;
|
2361 | c3d2689d | balrog | } |
2362 | c3d2689d | balrog | omap_clk_setrate(s->dpll, div, mult); |
2363 | c3d2689d | balrog | } |
2364 | c3d2689d | balrog | |
2365 | c3d2689d | balrog | /* Enter the desired mode. */
|
2366 | c3d2689d | balrog | s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); |
2367 | c3d2689d | balrog | |
2368 | c3d2689d | balrog | /* Act as if the lock is restored. */
|
2369 | c3d2689d | balrog | s->mode |= 2;
|
2370 | c3d2689d | balrog | } else {
|
2371 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2372 | c3d2689d | balrog | } |
2373 | c3d2689d | balrog | } |
2374 | c3d2689d | balrog | |
2375 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_dpll_readfn[] = {
|
2376 | c3d2689d | balrog | omap_badwidth_read16, |
2377 | c3d2689d | balrog | omap_dpll_read, |
2378 | c3d2689d | balrog | omap_badwidth_read16, |
2379 | c3d2689d | balrog | }; |
2380 | c3d2689d | balrog | |
2381 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
|
2382 | c3d2689d | balrog | omap_badwidth_write16, |
2383 | c3d2689d | balrog | omap_dpll_write, |
2384 | c3d2689d | balrog | omap_badwidth_write16, |
2385 | c3d2689d | balrog | }; |
2386 | c3d2689d | balrog | |
2387 | c3d2689d | balrog | static void omap_dpll_reset(struct dpll_ctl_s *s) |
2388 | c3d2689d | balrog | { |
2389 | c3d2689d | balrog | s->mode = 0x2002;
|
2390 | c3d2689d | balrog | omap_clk_setrate(s->dpll, 1, 1); |
2391 | c3d2689d | balrog | } |
2392 | c3d2689d | balrog | |
2393 | c3d2689d | balrog | static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base, |
2394 | c3d2689d | balrog | omap_clk clk) |
2395 | c3d2689d | balrog | { |
2396 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn, |
2397 | c3d2689d | balrog | omap_dpll_writefn, s); |
2398 | c3d2689d | balrog | |
2399 | c3d2689d | balrog | s->base = base; |
2400 | c3d2689d | balrog | s->dpll = clk; |
2401 | c3d2689d | balrog | omap_dpll_reset(s); |
2402 | c3d2689d | balrog | |
2403 | c3d2689d | balrog | cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
2404 | c3d2689d | balrog | } |
2405 | c3d2689d | balrog | |
2406 | c3d2689d | balrog | /* UARTs */
|
2407 | c3d2689d | balrog | struct omap_uart_s {
|
2408 | c3d2689d | balrog | SerialState *serial; /* TODO */
|
2409 | c3d2689d | balrog | }; |
2410 | c3d2689d | balrog | |
2411 | c3d2689d | balrog | static void omap_uart_reset(struct omap_uart_s *s) |
2412 | c3d2689d | balrog | { |
2413 | c3d2689d | balrog | } |
2414 | c3d2689d | balrog | |
2415 | c3d2689d | balrog | struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
|
2416 | c3d2689d | balrog | qemu_irq irq, omap_clk clk, CharDriverState *chr) |
2417 | c3d2689d | balrog | { |
2418 | c3d2689d | balrog | struct omap_uart_s *s = (struct omap_uart_s *) |
2419 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_uart_s)); |
2420 | c3d2689d | balrog | if (chr)
|
2421 | c3d2689d | balrog | s->serial = serial_mm_init(base, 2, irq, chr, 1); |
2422 | c3d2689d | balrog | return s;
|
2423 | c3d2689d | balrog | } |
2424 | c3d2689d | balrog | |
2425 | c3d2689d | balrog | /* MPU Clock/Reset/Power Mode Control */
|
2426 | c3d2689d | balrog | static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr) |
2427 | c3d2689d | balrog | { |
2428 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2429 | c3d2689d | balrog | int offset = addr - s->clkm.mpu_base;
|
2430 | c3d2689d | balrog | |
2431 | c3d2689d | balrog | switch (offset) {
|
2432 | c3d2689d | balrog | case 0x00: /* ARM_CKCTL */ |
2433 | c3d2689d | balrog | return s->clkm.arm_ckctl;
|
2434 | c3d2689d | balrog | |
2435 | c3d2689d | balrog | case 0x04: /* ARM_IDLECT1 */ |
2436 | c3d2689d | balrog | return s->clkm.arm_idlect1;
|
2437 | c3d2689d | balrog | |
2438 | c3d2689d | balrog | case 0x08: /* ARM_IDLECT2 */ |
2439 | c3d2689d | balrog | return s->clkm.arm_idlect2;
|
2440 | c3d2689d | balrog | |
2441 | c3d2689d | balrog | case 0x0c: /* ARM_EWUPCT */ |
2442 | c3d2689d | balrog | return s->clkm.arm_ewupct;
|
2443 | c3d2689d | balrog | |
2444 | c3d2689d | balrog | case 0x10: /* ARM_RSTCT1 */ |
2445 | c3d2689d | balrog | return s->clkm.arm_rstct1;
|
2446 | c3d2689d | balrog | |
2447 | c3d2689d | balrog | case 0x14: /* ARM_RSTCT2 */ |
2448 | c3d2689d | balrog | return s->clkm.arm_rstct2;
|
2449 | c3d2689d | balrog | |
2450 | c3d2689d | balrog | case 0x18: /* ARM_SYSST */ |
2451 | d8f699cb | balrog | return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; |
2452 | c3d2689d | balrog | |
2453 | c3d2689d | balrog | case 0x1c: /* ARM_CKOUT1 */ |
2454 | c3d2689d | balrog | return s->clkm.arm_ckout1;
|
2455 | c3d2689d | balrog | |
2456 | c3d2689d | balrog | case 0x20: /* ARM_CKOUT2 */ |
2457 | c3d2689d | balrog | break;
|
2458 | c3d2689d | balrog | } |
2459 | c3d2689d | balrog | |
2460 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2461 | c3d2689d | balrog | return 0; |
2462 | c3d2689d | balrog | } |
2463 | c3d2689d | balrog | |
2464 | c3d2689d | balrog | static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, |
2465 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2466 | c3d2689d | balrog | { |
2467 | c3d2689d | balrog | omap_clk clk; |
2468 | c3d2689d | balrog | |
2469 | c3d2689d | balrog | if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ |
2470 | c3d2689d | balrog | if (value & (1 << 14)) |
2471 | c3d2689d | balrog | /* Reserved */;
|
2472 | c3d2689d | balrog | else {
|
2473 | c3d2689d | balrog | clk = omap_findclk(s, "arminth_ck");
|
2474 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
2475 | c3d2689d | balrog | } |
2476 | c3d2689d | balrog | } |
2477 | c3d2689d | balrog | if (diff & (1 << 12)) { /* ARM_TIMXO */ |
2478 | c3d2689d | balrog | clk = omap_findclk(s, "armtim_ck");
|
2479 | c3d2689d | balrog | if (value & (1 << 12)) |
2480 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "clkin"));
|
2481 | c3d2689d | balrog | else
|
2482 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
2483 | c3d2689d | balrog | } |
2484 | c3d2689d | balrog | /* XXX: en_dspck */
|
2485 | c3d2689d | balrog | if (diff & (3 << 10)) { /* DSPMMUDIV */ |
2486 | c3d2689d | balrog | clk = omap_findclk(s, "dspmmu_ck");
|
2487 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); |
2488 | c3d2689d | balrog | } |
2489 | c3d2689d | balrog | if (diff & (3 << 8)) { /* TCDIV */ |
2490 | c3d2689d | balrog | clk = omap_findclk(s, "tc_ck");
|
2491 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); |
2492 | c3d2689d | balrog | } |
2493 | c3d2689d | balrog | if (diff & (3 << 6)) { /* DSPDIV */ |
2494 | c3d2689d | balrog | clk = omap_findclk(s, "dsp_ck");
|
2495 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); |
2496 | c3d2689d | balrog | } |
2497 | c3d2689d | balrog | if (diff & (3 << 4)) { /* ARMDIV */ |
2498 | c3d2689d | balrog | clk = omap_findclk(s, "arm_ck");
|
2499 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); |
2500 | c3d2689d | balrog | } |
2501 | c3d2689d | balrog | if (diff & (3 << 2)) { /* LCDDIV */ |
2502 | c3d2689d | balrog | clk = omap_findclk(s, "lcd_ck");
|
2503 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); |
2504 | c3d2689d | balrog | } |
2505 | c3d2689d | balrog | if (diff & (3 << 0)) { /* PERDIV */ |
2506 | c3d2689d | balrog | clk = omap_findclk(s, "armper_ck");
|
2507 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); |
2508 | c3d2689d | balrog | } |
2509 | c3d2689d | balrog | } |
2510 | c3d2689d | balrog | |
2511 | c3d2689d | balrog | static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, |
2512 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2513 | c3d2689d | balrog | { |
2514 | c3d2689d | balrog | omap_clk clk; |
2515 | c3d2689d | balrog | |
2516 | c3d2689d | balrog | if (value & (1 << 11)) /* SETARM_IDLE */ |
2517 | c3d2689d | balrog | cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
2518 | c3d2689d | balrog | if (!(value & (1 << 10))) /* WKUP_MODE */ |
2519 | c3d2689d | balrog | qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
|
2520 | c3d2689d | balrog | |
2521 | c3d2689d | balrog | #define SET_CANIDLE(clock, bit) \
|
2522 | c3d2689d | balrog | if (diff & (1 << bit)) { \ |
2523 | c3d2689d | balrog | clk = omap_findclk(s, clock); \ |
2524 | c3d2689d | balrog | omap_clk_canidle(clk, (value >> bit) & 1); \
|
2525 | c3d2689d | balrog | } |
2526 | c3d2689d | balrog | SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ |
2527 | c3d2689d | balrog | SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ |
2528 | c3d2689d | balrog | SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ |
2529 | c3d2689d | balrog | SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ |
2530 | c3d2689d | balrog | SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ |
2531 | c3d2689d | balrog | SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ |
2532 | c3d2689d | balrog | SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ |
2533 | c3d2689d | balrog | SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ |
2534 | c3d2689d | balrog | SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ |
2535 | c3d2689d | balrog | SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ |
2536 | c3d2689d | balrog | SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ |
2537 | c3d2689d | balrog | SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ |
2538 | c3d2689d | balrog | SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ |
2539 | c3d2689d | balrog | SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ |
2540 | c3d2689d | balrog | } |
2541 | c3d2689d | balrog | |
2542 | c3d2689d | balrog | static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, |
2543 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2544 | c3d2689d | balrog | { |
2545 | c3d2689d | balrog | omap_clk clk; |
2546 | c3d2689d | balrog | |
2547 | c3d2689d | balrog | #define SET_ONOFF(clock, bit) \
|
2548 | c3d2689d | balrog | if (diff & (1 << bit)) { \ |
2549 | c3d2689d | balrog | clk = omap_findclk(s, clock); \ |
2550 | c3d2689d | balrog | omap_clk_onoff(clk, (value >> bit) & 1); \
|
2551 | c3d2689d | balrog | } |
2552 | c3d2689d | balrog | SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ |
2553 | c3d2689d | balrog | SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ |
2554 | c3d2689d | balrog | SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ |
2555 | c3d2689d | balrog | SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ |
2556 | c3d2689d | balrog | SET_ONOFF("lb_ck", 4) /* EN_LBCK */ |
2557 | c3d2689d | balrog | SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ |
2558 | c3d2689d | balrog | SET_ONOFF("mpui_ck", 6) /* EN_APICK */ |
2559 | c3d2689d | balrog | SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ |
2560 | c3d2689d | balrog | SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ |
2561 | c3d2689d | balrog | SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ |
2562 | c3d2689d | balrog | SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ |
2563 | c3d2689d | balrog | } |
2564 | c3d2689d | balrog | |
2565 | c3d2689d | balrog | static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, |
2566 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2567 | c3d2689d | balrog | { |
2568 | c3d2689d | balrog | omap_clk clk; |
2569 | c3d2689d | balrog | |
2570 | c3d2689d | balrog | if (diff & (3 << 4)) { /* TCLKOUT */ |
2571 | c3d2689d | balrog | clk = omap_findclk(s, "tclk_out");
|
2572 | c3d2689d | balrog | switch ((value >> 4) & 3) { |
2573 | c3d2689d | balrog | case 1: |
2574 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
|
2575 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2576 | c3d2689d | balrog | break;
|
2577 | c3d2689d | balrog | case 2: |
2578 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
2579 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2580 | c3d2689d | balrog | break;
|
2581 | c3d2689d | balrog | default:
|
2582 | c3d2689d | balrog | omap_clk_onoff(clk, 0);
|
2583 | c3d2689d | balrog | } |
2584 | c3d2689d | balrog | } |
2585 | c3d2689d | balrog | if (diff & (3 << 2)) { /* DCLKOUT */ |
2586 | c3d2689d | balrog | clk = omap_findclk(s, "dclk_out");
|
2587 | c3d2689d | balrog | switch ((value >> 2) & 3) { |
2588 | c3d2689d | balrog | case 0: |
2589 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
|
2590 | c3d2689d | balrog | break;
|
2591 | c3d2689d | balrog | case 1: |
2592 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
|
2593 | c3d2689d | balrog | break;
|
2594 | c3d2689d | balrog | case 2: |
2595 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
|
2596 | c3d2689d | balrog | break;
|
2597 | c3d2689d | balrog | case 3: |
2598 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
2599 | c3d2689d | balrog | break;
|
2600 | c3d2689d | balrog | } |
2601 | c3d2689d | balrog | } |
2602 | c3d2689d | balrog | if (diff & (3 << 0)) { /* ACLKOUT */ |
2603 | c3d2689d | balrog | clk = omap_findclk(s, "aclk_out");
|
2604 | c3d2689d | balrog | switch ((value >> 0) & 3) { |
2605 | c3d2689d | balrog | case 1: |
2606 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
2607 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2608 | c3d2689d | balrog | break;
|
2609 | c3d2689d | balrog | case 2: |
2610 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
|
2611 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2612 | c3d2689d | balrog | break;
|
2613 | c3d2689d | balrog | case 3: |
2614 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
2615 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2616 | c3d2689d | balrog | break;
|
2617 | c3d2689d | balrog | default:
|
2618 | c3d2689d | balrog | omap_clk_onoff(clk, 0);
|
2619 | c3d2689d | balrog | } |
2620 | c3d2689d | balrog | } |
2621 | c3d2689d | balrog | } |
2622 | c3d2689d | balrog | |
2623 | c3d2689d | balrog | static void omap_clkm_write(void *opaque, target_phys_addr_t addr, |
2624 | c3d2689d | balrog | uint32_t value) |
2625 | c3d2689d | balrog | { |
2626 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2627 | c3d2689d | balrog | int offset = addr - s->clkm.mpu_base;
|
2628 | c3d2689d | balrog | uint16_t diff; |
2629 | c3d2689d | balrog | omap_clk clk; |
2630 | c3d2689d | balrog | static const char *clkschemename[8] = { |
2631 | c3d2689d | balrog | "fully synchronous", "fully asynchronous", "synchronous scalable", |
2632 | c3d2689d | balrog | "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", |
2633 | c3d2689d | balrog | }; |
2634 | c3d2689d | balrog | |
2635 | c3d2689d | balrog | switch (offset) {
|
2636 | c3d2689d | balrog | case 0x00: /* ARM_CKCTL */ |
2637 | c3d2689d | balrog | diff = s->clkm.arm_ckctl ^ value; |
2638 | c3d2689d | balrog | s->clkm.arm_ckctl = value & 0x7fff;
|
2639 | c3d2689d | balrog | omap_clkm_ckctl_update(s, diff, value); |
2640 | c3d2689d | balrog | return;
|
2641 | c3d2689d | balrog | |
2642 | c3d2689d | balrog | case 0x04: /* ARM_IDLECT1 */ |
2643 | c3d2689d | balrog | diff = s->clkm.arm_idlect1 ^ value; |
2644 | c3d2689d | balrog | s->clkm.arm_idlect1 = value & 0x0fff;
|
2645 | c3d2689d | balrog | omap_clkm_idlect1_update(s, diff, value); |
2646 | c3d2689d | balrog | return;
|
2647 | c3d2689d | balrog | |
2648 | c3d2689d | balrog | case 0x08: /* ARM_IDLECT2 */ |
2649 | c3d2689d | balrog | diff = s->clkm.arm_idlect2 ^ value; |
2650 | c3d2689d | balrog | s->clkm.arm_idlect2 = value & 0x07ff;
|
2651 | c3d2689d | balrog | omap_clkm_idlect2_update(s, diff, value); |
2652 | c3d2689d | balrog | return;
|
2653 | c3d2689d | balrog | |
2654 | c3d2689d | balrog | case 0x0c: /* ARM_EWUPCT */ |
2655 | c3d2689d | balrog | diff = s->clkm.arm_ewupct ^ value; |
2656 | c3d2689d | balrog | s->clkm.arm_ewupct = value & 0x003f;
|
2657 | c3d2689d | balrog | return;
|
2658 | c3d2689d | balrog | |
2659 | c3d2689d | balrog | case 0x10: /* ARM_RSTCT1 */ |
2660 | c3d2689d | balrog | diff = s->clkm.arm_rstct1 ^ value; |
2661 | c3d2689d | balrog | s->clkm.arm_rstct1 = value & 0x0007;
|
2662 | c3d2689d | balrog | if (value & 9) { |
2663 | c3d2689d | balrog | qemu_system_reset_request(); |
2664 | c3d2689d | balrog | s->clkm.cold_start = 0xa;
|
2665 | c3d2689d | balrog | } |
2666 | c3d2689d | balrog | if (diff & ~value & 4) { /* DSP_RST */ |
2667 | c3d2689d | balrog | omap_mpui_reset(s); |
2668 | c3d2689d | balrog | omap_tipb_bridge_reset(s->private_tipb); |
2669 | c3d2689d | balrog | omap_tipb_bridge_reset(s->public_tipb); |
2670 | c3d2689d | balrog | } |
2671 | c3d2689d | balrog | if (diff & 2) { /* DSP_EN */ |
2672 | c3d2689d | balrog | clk = omap_findclk(s, "dsp_ck");
|
2673 | c3d2689d | balrog | omap_clk_canidle(clk, (~value >> 1) & 1); |
2674 | c3d2689d | balrog | } |
2675 | c3d2689d | balrog | return;
|
2676 | c3d2689d | balrog | |
2677 | c3d2689d | balrog | case 0x14: /* ARM_RSTCT2 */ |
2678 | c3d2689d | balrog | s->clkm.arm_rstct2 = value & 0x0001;
|
2679 | c3d2689d | balrog | return;
|
2680 | c3d2689d | balrog | |
2681 | c3d2689d | balrog | case 0x18: /* ARM_SYSST */ |
2682 | c3d2689d | balrog | if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { |
2683 | c3d2689d | balrog | s->clkm.clocking_scheme = (value >> 11) & 7; |
2684 | c3d2689d | balrog | printf("%s: clocking scheme set to %s\n", __FUNCTION__,
|
2685 | c3d2689d | balrog | clkschemename[s->clkm.clocking_scheme]); |
2686 | c3d2689d | balrog | } |
2687 | c3d2689d | balrog | s->clkm.cold_start &= value & 0x3f;
|
2688 | c3d2689d | balrog | return;
|
2689 | c3d2689d | balrog | |
2690 | c3d2689d | balrog | case 0x1c: /* ARM_CKOUT1 */ |
2691 | c3d2689d | balrog | diff = s->clkm.arm_ckout1 ^ value; |
2692 | c3d2689d | balrog | s->clkm.arm_ckout1 = value & 0x003f;
|
2693 | c3d2689d | balrog | omap_clkm_ckout1_update(s, diff, value); |
2694 | c3d2689d | balrog | return;
|
2695 | c3d2689d | balrog | |
2696 | c3d2689d | balrog | case 0x20: /* ARM_CKOUT2 */ |
2697 | c3d2689d | balrog | default:
|
2698 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2699 | c3d2689d | balrog | } |
2700 | c3d2689d | balrog | } |
2701 | c3d2689d | balrog | |
2702 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_clkm_readfn[] = {
|
2703 | c3d2689d | balrog | omap_badwidth_read16, |
2704 | c3d2689d | balrog | omap_clkm_read, |
2705 | c3d2689d | balrog | omap_badwidth_read16, |
2706 | c3d2689d | balrog | }; |
2707 | c3d2689d | balrog | |
2708 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
|
2709 | c3d2689d | balrog | omap_badwidth_write16, |
2710 | c3d2689d | balrog | omap_clkm_write, |
2711 | c3d2689d | balrog | omap_badwidth_write16, |
2712 | c3d2689d | balrog | }; |
2713 | c3d2689d | balrog | |
2714 | c3d2689d | balrog | static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr) |
2715 | c3d2689d | balrog | { |
2716 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2717 | c3d2689d | balrog | int offset = addr - s->clkm.dsp_base;
|
2718 | c3d2689d | balrog | |
2719 | c3d2689d | balrog | switch (offset) {
|
2720 | c3d2689d | balrog | case 0x04: /* DSP_IDLECT1 */ |
2721 | c3d2689d | balrog | return s->clkm.dsp_idlect1;
|
2722 | c3d2689d | balrog | |
2723 | c3d2689d | balrog | case 0x08: /* DSP_IDLECT2 */ |
2724 | c3d2689d | balrog | return s->clkm.dsp_idlect2;
|
2725 | c3d2689d | balrog | |
2726 | c3d2689d | balrog | case 0x14: /* DSP_RSTCT2 */ |
2727 | c3d2689d | balrog | return s->clkm.dsp_rstct2;
|
2728 | c3d2689d | balrog | |
2729 | c3d2689d | balrog | case 0x18: /* DSP_SYSST */ |
2730 | d8f699cb | balrog | return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | |
2731 | c3d2689d | balrog | (s->env->halted << 6); /* Quite useless... */ |
2732 | c3d2689d | balrog | } |
2733 | c3d2689d | balrog | |
2734 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2735 | c3d2689d | balrog | return 0; |
2736 | c3d2689d | balrog | } |
2737 | c3d2689d | balrog | |
2738 | c3d2689d | balrog | static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, |
2739 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2740 | c3d2689d | balrog | { |
2741 | c3d2689d | balrog | omap_clk clk; |
2742 | c3d2689d | balrog | |
2743 | c3d2689d | balrog | SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ |
2744 | c3d2689d | balrog | } |
2745 | c3d2689d | balrog | |
2746 | c3d2689d | balrog | static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, |
2747 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2748 | c3d2689d | balrog | { |
2749 | c3d2689d | balrog | omap_clk clk; |
2750 | c3d2689d | balrog | |
2751 | c3d2689d | balrog | SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ |
2752 | c3d2689d | balrog | } |
2753 | c3d2689d | balrog | |
2754 | c3d2689d | balrog | static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr, |
2755 | c3d2689d | balrog | uint32_t value) |
2756 | c3d2689d | balrog | { |
2757 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2758 | c3d2689d | balrog | int offset = addr - s->clkm.dsp_base;
|
2759 | c3d2689d | balrog | uint16_t diff; |
2760 | c3d2689d | balrog | |
2761 | c3d2689d | balrog | switch (offset) {
|
2762 | c3d2689d | balrog | case 0x04: /* DSP_IDLECT1 */ |
2763 | c3d2689d | balrog | diff = s->clkm.dsp_idlect1 ^ value; |
2764 | c3d2689d | balrog | s->clkm.dsp_idlect1 = value & 0x01f7;
|
2765 | c3d2689d | balrog | omap_clkdsp_idlect1_update(s, diff, value); |
2766 | c3d2689d | balrog | break;
|
2767 | c3d2689d | balrog | |
2768 | c3d2689d | balrog | case 0x08: /* DSP_IDLECT2 */ |
2769 | c3d2689d | balrog | s->clkm.dsp_idlect2 = value & 0x0037;
|
2770 | c3d2689d | balrog | diff = s->clkm.dsp_idlect1 ^ value; |
2771 | c3d2689d | balrog | omap_clkdsp_idlect2_update(s, diff, value); |
2772 | c3d2689d | balrog | break;
|
2773 | c3d2689d | balrog | |
2774 | c3d2689d | balrog | case 0x14: /* DSP_RSTCT2 */ |
2775 | c3d2689d | balrog | s->clkm.dsp_rstct2 = value & 0x0001;
|
2776 | c3d2689d | balrog | break;
|
2777 | c3d2689d | balrog | |
2778 | c3d2689d | balrog | case 0x18: /* DSP_SYSST */ |
2779 | c3d2689d | balrog | s->clkm.cold_start &= value & 0x3f;
|
2780 | c3d2689d | balrog | break;
|
2781 | c3d2689d | balrog | |
2782 | c3d2689d | balrog | default:
|
2783 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2784 | c3d2689d | balrog | } |
2785 | c3d2689d | balrog | } |
2786 | c3d2689d | balrog | |
2787 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
|
2788 | c3d2689d | balrog | omap_badwidth_read16, |
2789 | c3d2689d | balrog | omap_clkdsp_read, |
2790 | c3d2689d | balrog | omap_badwidth_read16, |
2791 | c3d2689d | balrog | }; |
2792 | c3d2689d | balrog | |
2793 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
|
2794 | c3d2689d | balrog | omap_badwidth_write16, |
2795 | c3d2689d | balrog | omap_clkdsp_write, |
2796 | c3d2689d | balrog | omap_badwidth_write16, |
2797 | c3d2689d | balrog | }; |
2798 | c3d2689d | balrog | |
2799 | c3d2689d | balrog | static void omap_clkm_reset(struct omap_mpu_state_s *s) |
2800 | c3d2689d | balrog | { |
2801 | c3d2689d | balrog | if (s->wdt && s->wdt->reset)
|
2802 | c3d2689d | balrog | s->clkm.cold_start = 0x6;
|
2803 | c3d2689d | balrog | s->clkm.clocking_scheme = 0;
|
2804 | c3d2689d | balrog | omap_clkm_ckctl_update(s, ~0, 0x3000); |
2805 | c3d2689d | balrog | s->clkm.arm_ckctl = 0x3000;
|
2806 | d8f699cb | balrog | omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); |
2807 | c3d2689d | balrog | s->clkm.arm_idlect1 = 0x0400;
|
2808 | d8f699cb | balrog | omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); |
2809 | c3d2689d | balrog | s->clkm.arm_idlect2 = 0x0100;
|
2810 | c3d2689d | balrog | s->clkm.arm_ewupct = 0x003f;
|
2811 | c3d2689d | balrog | s->clkm.arm_rstct1 = 0x0000;
|
2812 | c3d2689d | balrog | s->clkm.arm_rstct2 = 0x0000;
|
2813 | c3d2689d | balrog | s->clkm.arm_ckout1 = 0x0015;
|
2814 | c3d2689d | balrog | s->clkm.dpll1_mode = 0x2002;
|
2815 | c3d2689d | balrog | omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); |
2816 | c3d2689d | balrog | s->clkm.dsp_idlect1 = 0x0040;
|
2817 | c3d2689d | balrog | omap_clkdsp_idlect2_update(s, ~0, 0x0000); |
2818 | c3d2689d | balrog | s->clkm.dsp_idlect2 = 0x0000;
|
2819 | c3d2689d | balrog | s->clkm.dsp_rstct2 = 0x0000;
|
2820 | c3d2689d | balrog | } |
2821 | c3d2689d | balrog | |
2822 | c3d2689d | balrog | static void omap_clkm_init(target_phys_addr_t mpu_base, |
2823 | c3d2689d | balrog | target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
|
2824 | c3d2689d | balrog | { |
2825 | c3d2689d | balrog | int iomemtype[2] = { |
2826 | c3d2689d | balrog | cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
|
2827 | c3d2689d | balrog | cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
|
2828 | c3d2689d | balrog | }; |
2829 | c3d2689d | balrog | |
2830 | c3d2689d | balrog | s->clkm.mpu_base = mpu_base; |
2831 | c3d2689d | balrog | s->clkm.dsp_base = dsp_base; |
2832 | d8f699cb | balrog | s->clkm.arm_idlect1 = 0x03ff;
|
2833 | d8f699cb | balrog | s->clkm.arm_idlect2 = 0x0100;
|
2834 | d8f699cb | balrog | s->clkm.dsp_idlect1 = 0x0002;
|
2835 | c3d2689d | balrog | omap_clkm_reset(s); |
2836 | d8f699cb | balrog | s->clkm.cold_start = 0x3a;
|
2837 | c3d2689d | balrog | |
2838 | c3d2689d | balrog | cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]); |
2839 | c3d2689d | balrog | cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]); |
2840 | c3d2689d | balrog | } |
2841 | c3d2689d | balrog | |
2842 | fe71e81a | balrog | /* MPU I/O */
|
2843 | fe71e81a | balrog | struct omap_mpuio_s {
|
2844 | fe71e81a | balrog | target_phys_addr_t base; |
2845 | fe71e81a | balrog | qemu_irq irq; |
2846 | fe71e81a | balrog | qemu_irq kbd_irq; |
2847 | fe71e81a | balrog | qemu_irq *in; |
2848 | fe71e81a | balrog | qemu_irq handler[16];
|
2849 | fe71e81a | balrog | qemu_irq wakeup; |
2850 | fe71e81a | balrog | |
2851 | fe71e81a | balrog | uint16_t inputs; |
2852 | fe71e81a | balrog | uint16_t outputs; |
2853 | fe71e81a | balrog | uint16_t dir; |
2854 | fe71e81a | balrog | uint16_t edge; |
2855 | fe71e81a | balrog | uint16_t mask; |
2856 | fe71e81a | balrog | uint16_t ints; |
2857 | fe71e81a | balrog | |
2858 | fe71e81a | balrog | uint16_t debounce; |
2859 | fe71e81a | balrog | uint16_t latch; |
2860 | fe71e81a | balrog | uint8_t event; |
2861 | fe71e81a | balrog | |
2862 | fe71e81a | balrog | uint8_t buttons[5];
|
2863 | fe71e81a | balrog | uint8_t row_latch; |
2864 | fe71e81a | balrog | uint8_t cols; |
2865 | fe71e81a | balrog | int kbd_mask;
|
2866 | fe71e81a | balrog | int clk;
|
2867 | fe71e81a | balrog | }; |
2868 | fe71e81a | balrog | |
2869 | fe71e81a | balrog | static void omap_mpuio_set(void *opaque, int line, int level) |
2870 | fe71e81a | balrog | { |
2871 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2872 | fe71e81a | balrog | uint16_t prev = s->inputs; |
2873 | fe71e81a | balrog | |
2874 | fe71e81a | balrog | if (level)
|
2875 | fe71e81a | balrog | s->inputs |= 1 << line;
|
2876 | fe71e81a | balrog | else
|
2877 | fe71e81a | balrog | s->inputs &= ~(1 << line);
|
2878 | fe71e81a | balrog | |
2879 | fe71e81a | balrog | if (((1 << line) & s->dir & ~s->mask) && s->clk) { |
2880 | fe71e81a | balrog | if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
|
2881 | fe71e81a | balrog | s->ints |= 1 << line;
|
2882 | fe71e81a | balrog | qemu_irq_raise(s->irq); |
2883 | fe71e81a | balrog | /* TODO: wakeup */
|
2884 | fe71e81a | balrog | } |
2885 | fe71e81a | balrog | if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ |
2886 | fe71e81a | balrog | (s->event >> 1) == line) /* PIN_SELECT */ |
2887 | fe71e81a | balrog | s->latch = s->inputs; |
2888 | fe71e81a | balrog | } |
2889 | fe71e81a | balrog | } |
2890 | fe71e81a | balrog | |
2891 | fe71e81a | balrog | static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) |
2892 | fe71e81a | balrog | { |
2893 | fe71e81a | balrog | int i;
|
2894 | fe71e81a | balrog | uint8_t *row, rows = 0, cols = ~s->cols;
|
2895 | fe71e81a | balrog | |
2896 | 38a34e1d | balrog | for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) |
2897 | fe71e81a | balrog | if (*row & cols)
|
2898 | 38a34e1d | balrog | rows |= i; |
2899 | fe71e81a | balrog | |
2900 | 38a34e1d | balrog | qemu_set_irq(s->kbd_irq, rows && ~s->kbd_mask && s->clk); |
2901 | fe71e81a | balrog | s->row_latch = rows ^ 0x1f;
|
2902 | fe71e81a | balrog | } |
2903 | fe71e81a | balrog | |
2904 | fe71e81a | balrog | static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr) |
2905 | fe71e81a | balrog | { |
2906 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2907 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2908 | fe71e81a | balrog | uint16_t ret; |
2909 | fe71e81a | balrog | |
2910 | fe71e81a | balrog | switch (offset) {
|
2911 | fe71e81a | balrog | case 0x00: /* INPUT_LATCH */ |
2912 | fe71e81a | balrog | return s->inputs;
|
2913 | fe71e81a | balrog | |
2914 | fe71e81a | balrog | case 0x04: /* OUTPUT_REG */ |
2915 | fe71e81a | balrog | return s->outputs;
|
2916 | fe71e81a | balrog | |
2917 | fe71e81a | balrog | case 0x08: /* IO_CNTL */ |
2918 | fe71e81a | balrog | return s->dir;
|
2919 | fe71e81a | balrog | |
2920 | fe71e81a | balrog | case 0x10: /* KBR_LATCH */ |
2921 | fe71e81a | balrog | return s->row_latch;
|
2922 | fe71e81a | balrog | |
2923 | fe71e81a | balrog | case 0x14: /* KBC_REG */ |
2924 | fe71e81a | balrog | return s->cols;
|
2925 | fe71e81a | balrog | |
2926 | fe71e81a | balrog | case 0x18: /* GPIO_EVENT_MODE_REG */ |
2927 | fe71e81a | balrog | return s->event;
|
2928 | fe71e81a | balrog | |
2929 | fe71e81a | balrog | case 0x1c: /* GPIO_INT_EDGE_REG */ |
2930 | fe71e81a | balrog | return s->edge;
|
2931 | fe71e81a | balrog | |
2932 | fe71e81a | balrog | case 0x20: /* KBD_INT */ |
2933 | fe71e81a | balrog | return (s->row_latch != 0x1f) && !s->kbd_mask; |
2934 | fe71e81a | balrog | |
2935 | fe71e81a | balrog | case 0x24: /* GPIO_INT */ |
2936 | fe71e81a | balrog | ret = s->ints; |
2937 | 8e129e07 | balrog | s->ints &= s->mask; |
2938 | 8e129e07 | balrog | if (ret)
|
2939 | 8e129e07 | balrog | qemu_irq_lower(s->irq); |
2940 | fe71e81a | balrog | return ret;
|
2941 | fe71e81a | balrog | |
2942 | fe71e81a | balrog | case 0x28: /* KBD_MASKIT */ |
2943 | fe71e81a | balrog | return s->kbd_mask;
|
2944 | fe71e81a | balrog | |
2945 | fe71e81a | balrog | case 0x2c: /* GPIO_MASKIT */ |
2946 | fe71e81a | balrog | return s->mask;
|
2947 | fe71e81a | balrog | |
2948 | fe71e81a | balrog | case 0x30: /* GPIO_DEBOUNCING_REG */ |
2949 | fe71e81a | balrog | return s->debounce;
|
2950 | fe71e81a | balrog | |
2951 | fe71e81a | balrog | case 0x34: /* GPIO_LATCH_REG */ |
2952 | fe71e81a | balrog | return s->latch;
|
2953 | fe71e81a | balrog | } |
2954 | fe71e81a | balrog | |
2955 | fe71e81a | balrog | OMAP_BAD_REG(addr); |
2956 | fe71e81a | balrog | return 0; |
2957 | fe71e81a | balrog | } |
2958 | fe71e81a | balrog | |
2959 | fe71e81a | balrog | static void omap_mpuio_write(void *opaque, target_phys_addr_t addr, |
2960 | fe71e81a | balrog | uint32_t value) |
2961 | fe71e81a | balrog | { |
2962 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2963 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2964 | fe71e81a | balrog | uint16_t diff; |
2965 | fe71e81a | balrog | int ln;
|
2966 | fe71e81a | balrog | |
2967 | fe71e81a | balrog | switch (offset) {
|
2968 | fe71e81a | balrog | case 0x04: /* OUTPUT_REG */ |
2969 | d8f699cb | balrog | diff = (s->outputs ^ value) & ~s->dir; |
2970 | fe71e81a | balrog | s->outputs = value; |
2971 | fe71e81a | balrog | while ((ln = ffs(diff))) {
|
2972 | fe71e81a | balrog | ln --; |
2973 | fe71e81a | balrog | if (s->handler[ln])
|
2974 | fe71e81a | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
2975 | fe71e81a | balrog | diff &= ~(1 << ln);
|
2976 | fe71e81a | balrog | } |
2977 | fe71e81a | balrog | break;
|
2978 | fe71e81a | balrog | |
2979 | fe71e81a | balrog | case 0x08: /* IO_CNTL */ |
2980 | fe71e81a | balrog | diff = s->outputs & (s->dir ^ value); |
2981 | fe71e81a | balrog | s->dir = value; |
2982 | fe71e81a | balrog | |
2983 | fe71e81a | balrog | value = s->outputs & ~s->dir; |
2984 | fe71e81a | balrog | while ((ln = ffs(diff))) {
|
2985 | fe71e81a | balrog | ln --; |
2986 | fe71e81a | balrog | if (s->handler[ln])
|
2987 | fe71e81a | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
2988 | fe71e81a | balrog | diff &= ~(1 << ln);
|
2989 | fe71e81a | balrog | } |
2990 | fe71e81a | balrog | break;
|
2991 | fe71e81a | balrog | |
2992 | fe71e81a | balrog | case 0x14: /* KBC_REG */ |
2993 | fe71e81a | balrog | s->cols = value; |
2994 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2995 | fe71e81a | balrog | break;
|
2996 | fe71e81a | balrog | |
2997 | fe71e81a | balrog | case 0x18: /* GPIO_EVENT_MODE_REG */ |
2998 | fe71e81a | balrog | s->event = value & 0x1f;
|
2999 | fe71e81a | balrog | break;
|
3000 | fe71e81a | balrog | |
3001 | fe71e81a | balrog | case 0x1c: /* GPIO_INT_EDGE_REG */ |
3002 | fe71e81a | balrog | s->edge = value; |
3003 | fe71e81a | balrog | break;
|
3004 | fe71e81a | balrog | |
3005 | fe71e81a | balrog | case 0x28: /* KBD_MASKIT */ |
3006 | fe71e81a | balrog | s->kbd_mask = value & 1;
|
3007 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
3008 | fe71e81a | balrog | break;
|
3009 | fe71e81a | balrog | |
3010 | fe71e81a | balrog | case 0x2c: /* GPIO_MASKIT */ |
3011 | fe71e81a | balrog | s->mask = value; |
3012 | fe71e81a | balrog | break;
|
3013 | fe71e81a | balrog | |
3014 | fe71e81a | balrog | case 0x30: /* GPIO_DEBOUNCING_REG */ |
3015 | fe71e81a | balrog | s->debounce = value & 0x1ff;
|
3016 | fe71e81a | balrog | break;
|
3017 | fe71e81a | balrog | |
3018 | fe71e81a | balrog | case 0x00: /* INPUT_LATCH */ |
3019 | fe71e81a | balrog | case 0x10: /* KBR_LATCH */ |
3020 | fe71e81a | balrog | case 0x20: /* KBD_INT */ |
3021 | fe71e81a | balrog | case 0x24: /* GPIO_INT */ |
3022 | fe71e81a | balrog | case 0x34: /* GPIO_LATCH_REG */ |
3023 | fe71e81a | balrog | OMAP_RO_REG(addr); |
3024 | fe71e81a | balrog | return;
|
3025 | fe71e81a | balrog | |
3026 | fe71e81a | balrog | default:
|
3027 | fe71e81a | balrog | OMAP_BAD_REG(addr); |
3028 | fe71e81a | balrog | return;
|
3029 | fe71e81a | balrog | } |
3030 | fe71e81a | balrog | } |
3031 | fe71e81a | balrog | |
3032 | fe71e81a | balrog | static CPUReadMemoryFunc *omap_mpuio_readfn[] = {
|
3033 | fe71e81a | balrog | omap_badwidth_read16, |
3034 | fe71e81a | balrog | omap_mpuio_read, |
3035 | fe71e81a | balrog | omap_badwidth_read16, |
3036 | fe71e81a | balrog | }; |
3037 | fe71e81a | balrog | |
3038 | fe71e81a | balrog | static CPUWriteMemoryFunc *omap_mpuio_writefn[] = {
|
3039 | fe71e81a | balrog | omap_badwidth_write16, |
3040 | fe71e81a | balrog | omap_mpuio_write, |
3041 | fe71e81a | balrog | omap_badwidth_write16, |
3042 | fe71e81a | balrog | }; |
3043 | fe71e81a | balrog | |
3044 | 9596ebb7 | pbrook | static void omap_mpuio_reset(struct omap_mpuio_s *s) |
3045 | fe71e81a | balrog | { |
3046 | fe71e81a | balrog | s->inputs = 0;
|
3047 | fe71e81a | balrog | s->outputs = 0;
|
3048 | fe71e81a | balrog | s->dir = ~0;
|
3049 | fe71e81a | balrog | s->event = 0;
|
3050 | fe71e81a | balrog | s->edge = 0;
|
3051 | fe71e81a | balrog | s->kbd_mask = 0;
|
3052 | fe71e81a | balrog | s->mask = 0;
|
3053 | fe71e81a | balrog | s->debounce = 0;
|
3054 | fe71e81a | balrog | s->latch = 0;
|
3055 | fe71e81a | balrog | s->ints = 0;
|
3056 | fe71e81a | balrog | s->row_latch = 0x1f;
|
3057 | 38a34e1d | balrog | s->clk = 1;
|
3058 | fe71e81a | balrog | } |
3059 | fe71e81a | balrog | |
3060 | fe71e81a | balrog | static void omap_mpuio_onoff(void *opaque, int line, int on) |
3061 | fe71e81a | balrog | { |
3062 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
3063 | fe71e81a | balrog | |
3064 | fe71e81a | balrog | s->clk = on; |
3065 | fe71e81a | balrog | if (on)
|
3066 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
3067 | fe71e81a | balrog | } |
3068 | fe71e81a | balrog | |
3069 | fe71e81a | balrog | struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
|
3070 | fe71e81a | balrog | qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
3071 | fe71e81a | balrog | omap_clk clk) |
3072 | fe71e81a | balrog | { |
3073 | fe71e81a | balrog | int iomemtype;
|
3074 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) |
3075 | fe71e81a | balrog | qemu_mallocz(sizeof(struct omap_mpuio_s)); |
3076 | fe71e81a | balrog | |
3077 | fe71e81a | balrog | s->base = base; |
3078 | fe71e81a | balrog | s->irq = gpio_int; |
3079 | fe71e81a | balrog | s->kbd_irq = kbd_int; |
3080 | fe71e81a | balrog | s->wakeup = wakeup; |
3081 | fe71e81a | balrog | s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
|
3082 | fe71e81a | balrog | omap_mpuio_reset(s); |
3083 | fe71e81a | balrog | |
3084 | fe71e81a | balrog | iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn,
|
3085 | fe71e81a | balrog | omap_mpuio_writefn, s); |
3086 | fe71e81a | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
3087 | fe71e81a | balrog | |
3088 | fe71e81a | balrog | omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]); |
3089 | fe71e81a | balrog | |
3090 | fe71e81a | balrog | return s;
|
3091 | fe71e81a | balrog | } |
3092 | fe71e81a | balrog | |
3093 | fe71e81a | balrog | qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
|
3094 | fe71e81a | balrog | { |
3095 | fe71e81a | balrog | return s->in;
|
3096 | fe71e81a | balrog | } |
3097 | fe71e81a | balrog | |
3098 | fe71e81a | balrog | void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) |
3099 | fe71e81a | balrog | { |
3100 | fe71e81a | balrog | if (line >= 16 || line < 0) |
3101 | fe71e81a | balrog | cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
|
3102 | fe71e81a | balrog | s->handler[line] = handler; |
3103 | fe71e81a | balrog | } |
3104 | fe71e81a | balrog | |
3105 | fe71e81a | balrog | void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) |
3106 | fe71e81a | balrog | { |
3107 | fe71e81a | balrog | if (row >= 5 || row < 0) |
3108 | fe71e81a | balrog | cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
|
3109 | fe71e81a | balrog | __FUNCTION__, col, row); |
3110 | fe71e81a | balrog | |
3111 | fe71e81a | balrog | if (down)
|
3112 | 38a34e1d | balrog | s->buttons[row] |= 1 << col;
|
3113 | fe71e81a | balrog | else
|
3114 | 38a34e1d | balrog | s->buttons[row] &= ~(1 << col);
|
3115 | fe71e81a | balrog | |
3116 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
3117 | fe71e81a | balrog | } |
3118 | fe71e81a | balrog | |
3119 | 64330148 | balrog | /* General-Purpose I/O */
|
3120 | 64330148 | balrog | struct omap_gpio_s {
|
3121 | 64330148 | balrog | target_phys_addr_t base; |
3122 | 64330148 | balrog | qemu_irq irq; |
3123 | 64330148 | balrog | qemu_irq *in; |
3124 | 64330148 | balrog | qemu_irq handler[16];
|
3125 | 64330148 | balrog | |
3126 | 64330148 | balrog | uint16_t inputs; |
3127 | 64330148 | balrog | uint16_t outputs; |
3128 | 64330148 | balrog | uint16_t dir; |
3129 | 64330148 | balrog | uint16_t edge; |
3130 | 64330148 | balrog | uint16_t mask; |
3131 | 64330148 | balrog | uint16_t ints; |
3132 | d8f699cb | balrog | uint16_t pins; |
3133 | 64330148 | balrog | }; |
3134 | 64330148 | balrog | |
3135 | 64330148 | balrog | static void omap_gpio_set(void *opaque, int line, int level) |
3136 | 64330148 | balrog | { |
3137 | 64330148 | balrog | struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
3138 | 64330148 | balrog | uint16_t prev = s->inputs; |
3139 | 64330148 | balrog | |
3140 | 64330148 | balrog | if (level)
|
3141 | 64330148 | balrog | s->inputs |= 1 << line;
|
3142 | 64330148 | balrog | else
|
3143 | 64330148 | balrog | s->inputs &= ~(1 << line);
|
3144 | 64330148 | balrog | |
3145 | 64330148 | balrog | if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
|
3146 | 64330148 | balrog | (1 << line) & s->dir & ~s->mask) {
|
3147 | 64330148 | balrog | s->ints |= 1 << line;
|
3148 | 64330148 | balrog | qemu_irq_raise(s->irq); |
3149 | 64330148 | balrog | } |
3150 | 64330148 | balrog | } |
3151 | 64330148 | balrog | |
3152 | 64330148 | balrog | static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr) |
3153 | 64330148 | balrog | { |
3154 | 64330148 | balrog | struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
3155 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3156 | 64330148 | balrog | |
3157 | 64330148 | balrog | switch (offset) {
|
3158 | 64330148 | balrog | case 0x00: /* DATA_INPUT */ |
3159 | d8f699cb | balrog | return s->inputs & s->pins;
|
3160 | 64330148 | balrog | |
3161 | 64330148 | balrog | case 0x04: /* DATA_OUTPUT */ |
3162 | 64330148 | balrog | return s->outputs;
|
3163 | 64330148 | balrog | |
3164 | 64330148 | balrog | case 0x08: /* DIRECTION_CONTROL */ |
3165 | 64330148 | balrog | return s->dir;
|
3166 | 64330148 | balrog | |
3167 | 64330148 | balrog | case 0x0c: /* INTERRUPT_CONTROL */ |
3168 | 64330148 | balrog | return s->edge;
|
3169 | 64330148 | balrog | |
3170 | 64330148 | balrog | case 0x10: /* INTERRUPT_MASK */ |
3171 | 64330148 | balrog | return s->mask;
|
3172 | 64330148 | balrog | |
3173 | 64330148 | balrog | case 0x14: /* INTERRUPT_STATUS */ |
3174 | 64330148 | balrog | return s->ints;
|
3175 | d8f699cb | balrog | |
3176 | d8f699cb | balrog | case 0x18: /* PIN_CONTROL (not in OMAP310) */ |
3177 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
3178 | d8f699cb | balrog | return s->pins;
|
3179 | 64330148 | balrog | } |
3180 | 64330148 | balrog | |
3181 | 64330148 | balrog | OMAP_BAD_REG(addr); |
3182 | 64330148 | balrog | return 0; |
3183 | 64330148 | balrog | } |
3184 | 64330148 | balrog | |
3185 | 64330148 | balrog | static void omap_gpio_write(void *opaque, target_phys_addr_t addr, |
3186 | 64330148 | balrog | uint32_t value) |
3187 | 64330148 | balrog | { |
3188 | 64330148 | balrog | struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
3189 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3190 | 64330148 | balrog | uint16_t diff; |
3191 | 64330148 | balrog | int ln;
|
3192 | 64330148 | balrog | |
3193 | 64330148 | balrog | switch (offset) {
|
3194 | 64330148 | balrog | case 0x00: /* DATA_INPUT */ |
3195 | 64330148 | balrog | OMAP_RO_REG(addr); |
3196 | 64330148 | balrog | return;
|
3197 | 64330148 | balrog | |
3198 | 64330148 | balrog | case 0x04: /* DATA_OUTPUT */ |
3199 | 66450b15 | balrog | diff = (s->outputs ^ value) & ~s->dir; |
3200 | 64330148 | balrog | s->outputs = value; |
3201 | 64330148 | balrog | while ((ln = ffs(diff))) {
|
3202 | 64330148 | balrog | ln --; |
3203 | 64330148 | balrog | if (s->handler[ln])
|
3204 | 64330148 | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
3205 | 64330148 | balrog | diff &= ~(1 << ln);
|
3206 | 64330148 | balrog | } |
3207 | 64330148 | balrog | break;
|
3208 | 64330148 | balrog | |
3209 | 64330148 | balrog | case 0x08: /* DIRECTION_CONTROL */ |
3210 | 64330148 | balrog | diff = s->outputs & (s->dir ^ value); |
3211 | 64330148 | balrog | s->dir = value; |
3212 | 64330148 | balrog | |
3213 | 64330148 | balrog | value = s->outputs & ~s->dir; |
3214 | 64330148 | balrog | while ((ln = ffs(diff))) {
|
3215 | 64330148 | balrog | ln --; |
3216 | 64330148 | balrog | if (s->handler[ln])
|
3217 | 64330148 | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
3218 | 64330148 | balrog | diff &= ~(1 << ln);
|
3219 | 64330148 | balrog | } |
3220 | 64330148 | balrog | break;
|
3221 | 64330148 | balrog | |
3222 | 64330148 | balrog | case 0x0c: /* INTERRUPT_CONTROL */ |
3223 | 64330148 | balrog | s->edge = value; |
3224 | 64330148 | balrog | break;
|
3225 | 64330148 | balrog | |
3226 | 64330148 | balrog | case 0x10: /* INTERRUPT_MASK */ |
3227 | 64330148 | balrog | s->mask = value; |
3228 | 64330148 | balrog | break;
|
3229 | 64330148 | balrog | |
3230 | 64330148 | balrog | case 0x14: /* INTERRUPT_STATUS */ |
3231 | 64330148 | balrog | s->ints &= ~value; |
3232 | 64330148 | balrog | if (!s->ints)
|
3233 | 64330148 | balrog | qemu_irq_lower(s->irq); |
3234 | 64330148 | balrog | break;
|
3235 | 64330148 | balrog | |
3236 | d8f699cb | balrog | case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ |
3237 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
3238 | d8f699cb | balrog | s->pins = value; |
3239 | d8f699cb | balrog | break;
|
3240 | d8f699cb | balrog | |
3241 | 64330148 | balrog | default:
|
3242 | 64330148 | balrog | OMAP_BAD_REG(addr); |
3243 | 64330148 | balrog | return;
|
3244 | 64330148 | balrog | } |
3245 | 64330148 | balrog | } |
3246 | 64330148 | balrog | |
3247 | 3efda49d | balrog | /* *Some* sources say the memory region is 32-bit. */
|
3248 | 64330148 | balrog | static CPUReadMemoryFunc *omap_gpio_readfn[] = {
|
3249 | 3efda49d | balrog | omap_badwidth_read16, |
3250 | 64330148 | balrog | omap_gpio_read, |
3251 | 3efda49d | balrog | omap_badwidth_read16, |
3252 | 64330148 | balrog | }; |
3253 | 64330148 | balrog | |
3254 | 64330148 | balrog | static CPUWriteMemoryFunc *omap_gpio_writefn[] = {
|
3255 | 3efda49d | balrog | omap_badwidth_write16, |
3256 | 64330148 | balrog | omap_gpio_write, |
3257 | 3efda49d | balrog | omap_badwidth_write16, |
3258 | 64330148 | balrog | }; |
3259 | 64330148 | balrog | |
3260 | 9596ebb7 | pbrook | static void omap_gpio_reset(struct omap_gpio_s *s) |
3261 | 64330148 | balrog | { |
3262 | 64330148 | balrog | s->inputs = 0;
|
3263 | 64330148 | balrog | s->outputs = ~0;
|
3264 | 64330148 | balrog | s->dir = ~0;
|
3265 | 64330148 | balrog | s->edge = ~0;
|
3266 | 64330148 | balrog | s->mask = ~0;
|
3267 | 64330148 | balrog | s->ints = 0;
|
3268 | d8f699cb | balrog | s->pins = ~0;
|
3269 | 64330148 | balrog | } |
3270 | 64330148 | balrog | |
3271 | 64330148 | balrog | struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
|
3272 | 64330148 | balrog | qemu_irq irq, omap_clk clk) |
3273 | 64330148 | balrog | { |
3274 | 64330148 | balrog | int iomemtype;
|
3275 | 64330148 | balrog | struct omap_gpio_s *s = (struct omap_gpio_s *) |
3276 | 64330148 | balrog | qemu_mallocz(sizeof(struct omap_gpio_s)); |
3277 | 64330148 | balrog | |
3278 | 64330148 | balrog | s->base = base; |
3279 | 64330148 | balrog | s->irq = irq; |
3280 | 64330148 | balrog | s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
|
3281 | 64330148 | balrog | omap_gpio_reset(s); |
3282 | 64330148 | balrog | |
3283 | 64330148 | balrog | iomemtype = cpu_register_io_memory(0, omap_gpio_readfn,
|
3284 | 64330148 | balrog | omap_gpio_writefn, s); |
3285 | 64330148 | balrog | cpu_register_physical_memory(s->base, 0x1000, iomemtype);
|
3286 | 64330148 | balrog | |
3287 | 64330148 | balrog | return s;
|
3288 | 64330148 | balrog | } |
3289 | 64330148 | balrog | |
3290 | 64330148 | balrog | qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
|
3291 | 64330148 | balrog | { |
3292 | 64330148 | balrog | return s->in;
|
3293 | 64330148 | balrog | } |
3294 | 64330148 | balrog | |
3295 | 64330148 | balrog | void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler) |
3296 | 64330148 | balrog | { |
3297 | 64330148 | balrog | if (line >= 16 || line < 0) |
3298 | 64330148 | balrog | cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
|
3299 | 64330148 | balrog | s->handler[line] = handler; |
3300 | 64330148 | balrog | } |
3301 | 64330148 | balrog | |
3302 | d951f6ff | balrog | /* MicroWire Interface */
|
3303 | d951f6ff | balrog | struct omap_uwire_s {
|
3304 | d951f6ff | balrog | target_phys_addr_t base; |
3305 | d951f6ff | balrog | qemu_irq txirq; |
3306 | d951f6ff | balrog | qemu_irq rxirq; |
3307 | d951f6ff | balrog | qemu_irq txdrq; |
3308 | d951f6ff | balrog | |
3309 | d951f6ff | balrog | uint16_t txbuf; |
3310 | d951f6ff | balrog | uint16_t rxbuf; |
3311 | d951f6ff | balrog | uint16_t control; |
3312 | d951f6ff | balrog | uint16_t setup[5];
|
3313 | d951f6ff | balrog | |
3314 | d951f6ff | balrog | struct uwire_slave_s *chip[4]; |
3315 | d951f6ff | balrog | }; |
3316 | d951f6ff | balrog | |
3317 | d951f6ff | balrog | static void omap_uwire_transfer_start(struct omap_uwire_s *s) |
3318 | d951f6ff | balrog | { |
3319 | d951f6ff | balrog | int chipselect = (s->control >> 10) & 3; /* INDEX */ |
3320 | d951f6ff | balrog | struct uwire_slave_s *slave = s->chip[chipselect];
|
3321 | d951f6ff | balrog | |
3322 | d951f6ff | balrog | if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ |
3323 | d951f6ff | balrog | if (s->control & (1 << 12)) /* CS_CMD */ |
3324 | d951f6ff | balrog | if (slave && slave->send)
|
3325 | d951f6ff | balrog | slave->send(slave->opaque, |
3326 | d951f6ff | balrog | s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); |
3327 | d951f6ff | balrog | s->control &= ~(1 << 14); /* CSRB */ |
3328 | d951f6ff | balrog | /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
|
3329 | d951f6ff | balrog | * a DRQ. When is the level IRQ supposed to be reset? */
|
3330 | d951f6ff | balrog | } |
3331 | d951f6ff | balrog | |
3332 | d951f6ff | balrog | if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ |
3333 | d951f6ff | balrog | if (s->control & (1 << 12)) /* CS_CMD */ |
3334 | d951f6ff | balrog | if (slave && slave->receive)
|
3335 | d951f6ff | balrog | s->rxbuf = slave->receive(slave->opaque); |
3336 | d951f6ff | balrog | s->control |= 1 << 15; /* RDRB */ |
3337 | d951f6ff | balrog | /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
|
3338 | d951f6ff | balrog | * a DRQ. When is the level IRQ supposed to be reset? */
|
3339 | d951f6ff | balrog | } |
3340 | d951f6ff | balrog | } |
3341 | d951f6ff | balrog | |
3342 | d951f6ff | balrog | static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr) |
3343 | d951f6ff | balrog | { |
3344 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; |
3345 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3346 | d951f6ff | balrog | |
3347 | d951f6ff | balrog | switch (offset) {
|
3348 | d951f6ff | balrog | case 0x00: /* RDR */ |
3349 | d951f6ff | balrog | s->control &= ~(1 << 15); /* RDRB */ |
3350 | d951f6ff | balrog | return s->rxbuf;
|
3351 | d951f6ff | balrog | |
3352 | d951f6ff | balrog | case 0x04: /* CSR */ |
3353 | d951f6ff | balrog | return s->control;
|
3354 | d951f6ff | balrog | |
3355 | d951f6ff | balrog | case 0x08: /* SR1 */ |
3356 | d951f6ff | balrog | return s->setup[0]; |
3357 | d951f6ff | balrog | case 0x0c: /* SR2 */ |
3358 | d951f6ff | balrog | return s->setup[1]; |
3359 | d951f6ff | balrog | case 0x10: /* SR3 */ |
3360 | d951f6ff | balrog | return s->setup[2]; |
3361 | d951f6ff | balrog | case 0x14: /* SR4 */ |
3362 | d951f6ff | balrog | return s->setup[3]; |
3363 | d951f6ff | balrog | case 0x18: /* SR5 */ |
3364 | d951f6ff | balrog | return s->setup[4]; |
3365 | d951f6ff | balrog | } |
3366 | d951f6ff | balrog | |
3367 | d951f6ff | balrog | OMAP_BAD_REG(addr); |
3368 | d951f6ff | balrog | return 0; |
3369 | d951f6ff | balrog | } |
3370 | d951f6ff | balrog | |
3371 | d951f6ff | balrog | static void omap_uwire_write(void *opaque, target_phys_addr_t addr, |
3372 | d951f6ff | balrog | uint32_t value) |
3373 | d951f6ff | balrog | { |
3374 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; |
3375 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3376 | d951f6ff | balrog | |
3377 | d951f6ff | balrog | switch (offset) {
|
3378 | d951f6ff | balrog | case 0x00: /* TDR */ |
3379 | d951f6ff | balrog | s->txbuf = value; /* TD */
|
3380 | d951f6ff | balrog | if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ |
3381 | d951f6ff | balrog | ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ |
3382 | cf965d24 | balrog | (s->control & (1 << 12)))) { /* CS_CMD */ |
3383 | cf965d24 | balrog | s->control |= 1 << 14; /* CSRB */ |
3384 | d951f6ff | balrog | omap_uwire_transfer_start(s); |
3385 | cf965d24 | balrog | } |
3386 | d951f6ff | balrog | break;
|
3387 | d951f6ff | balrog | |
3388 | d951f6ff | balrog | case 0x04: /* CSR */ |
3389 | d951f6ff | balrog | s->control = value & 0x1fff;
|
3390 | d951f6ff | balrog | if (value & (1 << 13)) /* START */ |
3391 | d951f6ff | balrog | omap_uwire_transfer_start(s); |
3392 | d951f6ff | balrog | break;
|
3393 | d951f6ff | balrog | |
3394 | d951f6ff | balrog | case 0x08: /* SR1 */ |
3395 | d951f6ff | balrog | s->setup[0] = value & 0x003f; |
3396 | d951f6ff | balrog | break;
|
3397 | d951f6ff | balrog | |
3398 | d951f6ff | balrog | case 0x0c: /* SR2 */ |
3399 | d951f6ff | balrog | s->setup[1] = value & 0x0fc0; |
3400 | d951f6ff | balrog | break;
|
3401 | d951f6ff | balrog | |
3402 | d951f6ff | balrog | case 0x10: /* SR3 */ |
3403 | d951f6ff | balrog | s->setup[2] = value & 0x0003; |
3404 | d951f6ff | balrog | break;
|
3405 | d951f6ff | balrog | |
3406 | d951f6ff | balrog | case 0x14: /* SR4 */ |
3407 | d951f6ff | balrog | s->setup[3] = value & 0x0001; |
3408 | d951f6ff | balrog | break;
|
3409 | d951f6ff | balrog | |
3410 | d951f6ff | balrog | case 0x18: /* SR5 */ |
3411 | d951f6ff | balrog | s->setup[4] = value & 0x000f; |
3412 | d951f6ff | balrog | break;
|
3413 | d951f6ff | balrog | |
3414 | d951f6ff | balrog | default:
|
3415 | d951f6ff | balrog | OMAP_BAD_REG(addr); |
3416 | d951f6ff | balrog | return;
|
3417 | d951f6ff | balrog | } |
3418 | d951f6ff | balrog | } |
3419 | d951f6ff | balrog | |
3420 | d951f6ff | balrog | static CPUReadMemoryFunc *omap_uwire_readfn[] = {
|
3421 | d951f6ff | balrog | omap_badwidth_read16, |
3422 | d951f6ff | balrog | omap_uwire_read, |
3423 | d951f6ff | balrog | omap_badwidth_read16, |
3424 | d951f6ff | balrog | }; |
3425 | d951f6ff | balrog | |
3426 | d951f6ff | balrog | static CPUWriteMemoryFunc *omap_uwire_writefn[] = {
|
3427 | d951f6ff | balrog | omap_badwidth_write16, |
3428 | d951f6ff | balrog | omap_uwire_write, |
3429 | d951f6ff | balrog | omap_badwidth_write16, |
3430 | d951f6ff | balrog | }; |
3431 | d951f6ff | balrog | |
3432 | 9596ebb7 | pbrook | static void omap_uwire_reset(struct omap_uwire_s *s) |
3433 | d951f6ff | balrog | { |
3434 | 66450b15 | balrog | s->control = 0;
|
3435 | d951f6ff | balrog | s->setup[0] = 0; |
3436 | d951f6ff | balrog | s->setup[1] = 0; |
3437 | d951f6ff | balrog | s->setup[2] = 0; |
3438 | d951f6ff | balrog | s->setup[3] = 0; |
3439 | d951f6ff | balrog | s->setup[4] = 0; |
3440 | d951f6ff | balrog | } |
3441 | d951f6ff | balrog | |
3442 | d951f6ff | balrog | struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
|
3443 | d951f6ff | balrog | qemu_irq *irq, qemu_irq dma, omap_clk clk) |
3444 | d951f6ff | balrog | { |
3445 | d951f6ff | balrog | int iomemtype;
|
3446 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) |
3447 | d951f6ff | balrog | qemu_mallocz(sizeof(struct omap_uwire_s)); |
3448 | d951f6ff | balrog | |
3449 | d951f6ff | balrog | s->base = base; |
3450 | d951f6ff | balrog | s->txirq = irq[0];
|
3451 | d951f6ff | balrog | s->rxirq = irq[1];
|
3452 | d951f6ff | balrog | s->txdrq = dma; |
3453 | d951f6ff | balrog | omap_uwire_reset(s); |
3454 | d951f6ff | balrog | |
3455 | d951f6ff | balrog | iomemtype = cpu_register_io_memory(0, omap_uwire_readfn,
|
3456 | d951f6ff | balrog | omap_uwire_writefn, s); |
3457 | d951f6ff | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
3458 | d951f6ff | balrog | |
3459 | d951f6ff | balrog | return s;
|
3460 | d951f6ff | balrog | } |
3461 | d951f6ff | balrog | |
3462 | d951f6ff | balrog | void omap_uwire_attach(struct omap_uwire_s *s, |
3463 | d951f6ff | balrog | struct uwire_slave_s *slave, int chipselect) |
3464 | d951f6ff | balrog | { |
3465 | d951f6ff | balrog | if (chipselect < 0 || chipselect > 3) |
3466 | d951f6ff | balrog | cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n", __FUNCTION__,
|
3467 | d951f6ff | balrog | chipselect); |
3468 | d951f6ff | balrog | |
3469 | d951f6ff | balrog | s->chip[chipselect] = slave; |
3470 | d951f6ff | balrog | } |
3471 | d951f6ff | balrog | |
3472 | 66450b15 | balrog | /* Pseudonoise Pulse-Width Light Modulator */
|
3473 | 9596ebb7 | pbrook | static void omap_pwl_update(struct omap_mpu_state_s *s) |
3474 | 66450b15 | balrog | { |
3475 | 66450b15 | balrog | int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0; |
3476 | 66450b15 | balrog | |
3477 | 66450b15 | balrog | if (output != s->pwl.output) {
|
3478 | 66450b15 | balrog | s->pwl.output = output; |
3479 | 66450b15 | balrog | printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
|
3480 | 66450b15 | balrog | } |
3481 | 66450b15 | balrog | } |
3482 | 66450b15 | balrog | |
3483 | 66450b15 | balrog | static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr) |
3484 | 66450b15 | balrog | { |
3485 | 66450b15 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3486 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3487 | 66450b15 | balrog | |
3488 | 66450b15 | balrog | switch (offset) {
|
3489 | 66450b15 | balrog | case 0x00: /* PWL_LEVEL */ |
3490 | 66450b15 | balrog | return s->pwl.level;
|
3491 | 66450b15 | balrog | case 0x04: /* PWL_CTRL */ |
3492 | 66450b15 | balrog | return s->pwl.enable;
|
3493 | 66450b15 | balrog | } |
3494 | 66450b15 | balrog | OMAP_BAD_REG(addr); |
3495 | 66450b15 | balrog | return 0; |
3496 | 66450b15 | balrog | } |
3497 | 66450b15 | balrog | |
3498 | 66450b15 | balrog | static void omap_pwl_write(void *opaque, target_phys_addr_t addr, |
3499 | 66450b15 | balrog | uint32_t value) |
3500 | 66450b15 | balrog | { |
3501 | 66450b15 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3502 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3503 | 66450b15 | balrog | |
3504 | 66450b15 | balrog | switch (offset) {
|
3505 | 66450b15 | balrog | case 0x00: /* PWL_LEVEL */ |
3506 | 66450b15 | balrog | s->pwl.level = value; |
3507 | 66450b15 | balrog | omap_pwl_update(s); |
3508 | 66450b15 | balrog | break;
|
3509 | 66450b15 | balrog | case 0x04: /* PWL_CTRL */ |
3510 | 66450b15 | balrog | s->pwl.enable = value & 1;
|
3511 | 66450b15 | balrog | omap_pwl_update(s); |
3512 | 66450b15 | balrog | break;
|
3513 | 66450b15 | balrog | default:
|
3514 | 66450b15 | balrog | OMAP_BAD_REG(addr); |
3515 | 66450b15 | balrog | return;
|
3516 | 66450b15 | balrog | } |
3517 | 66450b15 | balrog | } |
3518 | 66450b15 | balrog | |
3519 | 66450b15 | balrog | static CPUReadMemoryFunc *omap_pwl_readfn[] = {
|
3520 | 02645926 | balrog | omap_pwl_read, |
3521 | 66450b15 | balrog | omap_badwidth_read8, |
3522 | 66450b15 | balrog | omap_badwidth_read8, |
3523 | 66450b15 | balrog | }; |
3524 | 66450b15 | balrog | |
3525 | 66450b15 | balrog | static CPUWriteMemoryFunc *omap_pwl_writefn[] = {
|
3526 | 02645926 | balrog | omap_pwl_write, |
3527 | 66450b15 | balrog | omap_badwidth_write8, |
3528 | 66450b15 | balrog | omap_badwidth_write8, |
3529 | 66450b15 | balrog | }; |
3530 | 66450b15 | balrog | |
3531 | 9596ebb7 | pbrook | static void omap_pwl_reset(struct omap_mpu_state_s *s) |
3532 | 66450b15 | balrog | { |
3533 | 66450b15 | balrog | s->pwl.output = 0;
|
3534 | 66450b15 | balrog | s->pwl.level = 0;
|
3535 | 66450b15 | balrog | s->pwl.enable = 0;
|
3536 | 66450b15 | balrog | s->pwl.clk = 1;
|
3537 | 66450b15 | balrog | omap_pwl_update(s); |
3538 | 66450b15 | balrog | } |
3539 | 66450b15 | balrog | |
3540 | 66450b15 | balrog | static void omap_pwl_clk_update(void *opaque, int line, int on) |
3541 | 66450b15 | balrog | { |
3542 | 66450b15 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3543 | 66450b15 | balrog | |
3544 | 66450b15 | balrog | s->pwl.clk = on; |
3545 | 66450b15 | balrog | omap_pwl_update(s); |
3546 | 66450b15 | balrog | } |
3547 | 66450b15 | balrog | |
3548 | 66450b15 | balrog | static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s, |
3549 | 66450b15 | balrog | omap_clk clk) |
3550 | 66450b15 | balrog | { |
3551 | 66450b15 | balrog | int iomemtype;
|
3552 | 66450b15 | balrog | |
3553 | 66450b15 | balrog | omap_pwl_reset(s); |
3554 | 66450b15 | balrog | |
3555 | 66450b15 | balrog | iomemtype = cpu_register_io_memory(0, omap_pwl_readfn,
|
3556 | 66450b15 | balrog | omap_pwl_writefn, s); |
3557 | b854bc19 | balrog | cpu_register_physical_memory(base, 0x800, iomemtype);
|
3558 | 66450b15 | balrog | |
3559 | 66450b15 | balrog | omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]); |
3560 | 66450b15 | balrog | } |
3561 | 66450b15 | balrog | |
3562 | f34c417b | balrog | /* Pulse-Width Tone module */
|
3563 | f34c417b | balrog | static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr) |
3564 | f34c417b | balrog | { |
3565 | f34c417b | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3566 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3567 | f34c417b | balrog | |
3568 | f34c417b | balrog | switch (offset) {
|
3569 | f34c417b | balrog | case 0x00: /* FRC */ |
3570 | f34c417b | balrog | return s->pwt.frc;
|
3571 | f34c417b | balrog | case 0x04: /* VCR */ |
3572 | f34c417b | balrog | return s->pwt.vrc;
|
3573 | f34c417b | balrog | case 0x08: /* GCR */ |
3574 | f34c417b | balrog | return s->pwt.gcr;
|
3575 | f34c417b | balrog | } |
3576 | f34c417b | balrog | OMAP_BAD_REG(addr); |
3577 | f34c417b | balrog | return 0; |
3578 | f34c417b | balrog | } |
3579 | f34c417b | balrog | |
3580 | f34c417b | balrog | static void omap_pwt_write(void *opaque, target_phys_addr_t addr, |
3581 | f34c417b | balrog | uint32_t value) |
3582 | f34c417b | balrog | { |
3583 | f34c417b | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3584 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3585 | f34c417b | balrog | |
3586 | f34c417b | balrog | switch (offset) {
|
3587 | f34c417b | balrog | case 0x00: /* FRC */ |
3588 | f34c417b | balrog | s->pwt.frc = value & 0x3f;
|
3589 | f34c417b | balrog | break;
|
3590 | f34c417b | balrog | case 0x04: /* VRC */ |
3591 | f34c417b | balrog | if ((value ^ s->pwt.vrc) & 1) { |
3592 | f34c417b | balrog | if (value & 1) |
3593 | f34c417b | balrog | printf("%s: %iHz buzz on\n", __FUNCTION__, (int) |
3594 | f34c417b | balrog | /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
|
3595 | f34c417b | balrog | ((omap_clk_getrate(s->pwt.clk) >> 3) /
|
3596 | f34c417b | balrog | /* Pre-multiplexer divider */
|
3597 | f34c417b | balrog | ((s->pwt.gcr & 2) ? 1 : 154) / |
3598 | f34c417b | balrog | /* Octave multiplexer */
|
3599 | f34c417b | balrog | (2 << (value & 3)) * |
3600 | f34c417b | balrog | /* 101/107 divider */
|
3601 | f34c417b | balrog | ((value & (1 << 2)) ? 101 : 107) * |
3602 | f34c417b | balrog | /* 49/55 divider */
|
3603 | f34c417b | balrog | ((value & (1 << 3)) ? 49 : 55) * |
3604 | f34c417b | balrog | /* 50/63 divider */
|
3605 | f34c417b | balrog | ((value & (1 << 4)) ? 50 : 63) * |
3606 | f34c417b | balrog | /* 80/127 divider */
|
3607 | f34c417b | balrog | ((value & (1 << 5)) ? 80 : 127) / |
3608 | f34c417b | balrog | (107 * 55 * 63 * 127))); |
3609 | f34c417b | balrog | else
|
3610 | f34c417b | balrog | printf("%s: silence!\n", __FUNCTION__);
|
3611 | f34c417b | balrog | } |
3612 | f34c417b | balrog | s->pwt.vrc = value & 0x7f;
|
3613 | f34c417b | balrog | break;
|
3614 | f34c417b | balrog | case 0x08: /* GCR */ |
3615 | f34c417b | balrog | s->pwt.gcr = value & 3;
|
3616 | f34c417b | balrog | break;
|
3617 | f34c417b | balrog | default:
|
3618 | f34c417b | balrog | OMAP_BAD_REG(addr); |
3619 | f34c417b | balrog | return;
|
3620 | f34c417b | balrog | } |
3621 | f34c417b | balrog | } |
3622 | f34c417b | balrog | |
3623 | f34c417b | balrog | static CPUReadMemoryFunc *omap_pwt_readfn[] = {
|
3624 | 02645926 | balrog | omap_pwt_read, |
3625 | f34c417b | balrog | omap_badwidth_read8, |
3626 | f34c417b | balrog | omap_badwidth_read8, |
3627 | f34c417b | balrog | }; |
3628 | f34c417b | balrog | |
3629 | f34c417b | balrog | static CPUWriteMemoryFunc *omap_pwt_writefn[] = {
|
3630 | 02645926 | balrog | omap_pwt_write, |
3631 | f34c417b | balrog | omap_badwidth_write8, |
3632 | f34c417b | balrog | omap_badwidth_write8, |
3633 | f34c417b | balrog | }; |
3634 | f34c417b | balrog | |
3635 | 9596ebb7 | pbrook | static void omap_pwt_reset(struct omap_mpu_state_s *s) |
3636 | f34c417b | balrog | { |
3637 | f34c417b | balrog | s->pwt.frc = 0;
|
3638 | f34c417b | balrog | s->pwt.vrc = 0;
|
3639 | f34c417b | balrog | s->pwt.gcr = 0;
|
3640 | f34c417b | balrog | } |
3641 | f34c417b | balrog | |
3642 | f34c417b | balrog | static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s, |
3643 | f34c417b | balrog | omap_clk clk) |
3644 | f34c417b | balrog | { |
3645 | f34c417b | balrog | int iomemtype;
|
3646 | f34c417b | balrog | |
3647 | f34c417b | balrog | s->pwt.clk = clk; |
3648 | f34c417b | balrog | omap_pwt_reset(s); |
3649 | f34c417b | balrog | |
3650 | f34c417b | balrog | iomemtype = cpu_register_io_memory(0, omap_pwt_readfn,
|
3651 | f34c417b | balrog | omap_pwt_writefn, s); |
3652 | b854bc19 | balrog | cpu_register_physical_memory(base, 0x800, iomemtype);
|
3653 | f34c417b | balrog | } |
3654 | f34c417b | balrog | |
3655 | 5c1c390f | balrog | /* Real-time Clock module */
|
3656 | 5c1c390f | balrog | struct omap_rtc_s {
|
3657 | 5c1c390f | balrog | target_phys_addr_t base; |
3658 | 5c1c390f | balrog | qemu_irq irq; |
3659 | 5c1c390f | balrog | qemu_irq alarm; |
3660 | 5c1c390f | balrog | QEMUTimer *clk; |
3661 | 5c1c390f | balrog | |
3662 | 5c1c390f | balrog | uint8_t interrupts; |
3663 | 5c1c390f | balrog | uint8_t status; |
3664 | 5c1c390f | balrog | int16_t comp_reg; |
3665 | 5c1c390f | balrog | int running;
|
3666 | 5c1c390f | balrog | int pm_am;
|
3667 | 5c1c390f | balrog | int auto_comp;
|
3668 | 5c1c390f | balrog | int round;
|
3669 | 5c1c390f | balrog | struct tm *(*convert)(const time_t *timep, struct tm *result); |
3670 | 5c1c390f | balrog | struct tm alarm_tm;
|
3671 | 5c1c390f | balrog | time_t alarm_ti; |
3672 | 5c1c390f | balrog | |
3673 | 5c1c390f | balrog | struct tm current_tm;
|
3674 | 5c1c390f | balrog | time_t ti; |
3675 | 5c1c390f | balrog | uint64_t tick; |
3676 | 5c1c390f | balrog | }; |
3677 | 5c1c390f | balrog | |
3678 | 5c1c390f | balrog | static void omap_rtc_interrupts_update(struct omap_rtc_s *s) |
3679 | 5c1c390f | balrog | { |
3680 | 5c1c390f | balrog | qemu_set_irq(s->alarm, (s->status >> 6) & 1); |
3681 | 5c1c390f | balrog | } |
3682 | 5c1c390f | balrog | |
3683 | 5c1c390f | balrog | static void omap_rtc_alarm_update(struct omap_rtc_s *s) |
3684 | 5c1c390f | balrog | { |
3685 | 5c1c390f | balrog | s->alarm_ti = mktime(&s->alarm_tm); |
3686 | 5c1c390f | balrog | if (s->alarm_ti == -1) |
3687 | 5c1c390f | balrog | printf("%s: conversion failed\n", __FUNCTION__);
|
3688 | 5c1c390f | balrog | } |
3689 | 5c1c390f | balrog | |
3690 | 5c1c390f | balrog | static inline uint8_t omap_rtc_bcd(int num) |
3691 | 5c1c390f | balrog | { |
3692 | 5c1c390f | balrog | return ((num / 10) << 4) | (num % 10); |
3693 | 5c1c390f | balrog | } |
3694 | 5c1c390f | balrog | |
3695 | 5c1c390f | balrog | static inline int omap_rtc_bin(uint8_t num) |
3696 | 5c1c390f | balrog | { |
3697 | 5c1c390f | balrog | return (num & 15) + 10 * (num >> 4); |
3698 | 5c1c390f | balrog | } |
3699 | 5c1c390f | balrog | |
3700 | 5c1c390f | balrog | static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr) |
3701 | 5c1c390f | balrog | { |
3702 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; |
3703 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3704 | 5c1c390f | balrog | uint8_t i; |
3705 | 5c1c390f | balrog | |
3706 | 5c1c390f | balrog | switch (offset) {
|
3707 | 5c1c390f | balrog | case 0x00: /* SECONDS_REG */ |
3708 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_sec);
|
3709 | 5c1c390f | balrog | |
3710 | 5c1c390f | balrog | case 0x04: /* MINUTES_REG */ |
3711 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_min);
|
3712 | 5c1c390f | balrog | |
3713 | 5c1c390f | balrog | case 0x08: /* HOURS_REG */ |
3714 | 5c1c390f | balrog | if (s->pm_am)
|
3715 | 5c1c390f | balrog | return ((s->current_tm.tm_hour > 11) << 7) | |
3716 | 5c1c390f | balrog | omap_rtc_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); |
3717 | 5c1c390f | balrog | else
|
3718 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_hour);
|
3719 | 5c1c390f | balrog | |
3720 | 5c1c390f | balrog | case 0x0c: /* DAYS_REG */ |
3721 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_mday);
|
3722 | 5c1c390f | balrog | |
3723 | 5c1c390f | balrog | case 0x10: /* MONTHS_REG */ |
3724 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_mon + 1); |
3725 | 5c1c390f | balrog | |
3726 | 5c1c390f | balrog | case 0x14: /* YEARS_REG */ |
3727 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_year % 100); |
3728 | 5c1c390f | balrog | |
3729 | 5c1c390f | balrog | case 0x18: /* WEEK_REG */ |
3730 | 5c1c390f | balrog | return s->current_tm.tm_wday;
|
3731 | 5c1c390f | balrog | |
3732 | 5c1c390f | balrog | case 0x20: /* ALARM_SECONDS_REG */ |
3733 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_sec);
|
3734 | 5c1c390f | balrog | |
3735 | 5c1c390f | balrog | case 0x24: /* ALARM_MINUTES_REG */ |
3736 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_min);
|
3737 | 5c1c390f | balrog | |
3738 | 5c1c390f | balrog | case 0x28: /* ALARM_HOURS_REG */ |
3739 | 5c1c390f | balrog | if (s->pm_am)
|
3740 | 5c1c390f | balrog | return ((s->alarm_tm.tm_hour > 11) << 7) | |
3741 | 5c1c390f | balrog | omap_rtc_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); |
3742 | 5c1c390f | balrog | else
|
3743 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_hour);
|
3744 | 5c1c390f | balrog | |
3745 | 5c1c390f | balrog | case 0x2c: /* ALARM_DAYS_REG */ |
3746 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_mday);
|
3747 | 5c1c390f | balrog | |
3748 | 5c1c390f | balrog | case 0x30: /* ALARM_MONTHS_REG */ |
3749 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_mon + 1); |
3750 | 5c1c390f | balrog | |
3751 | 5c1c390f | balrog | case 0x34: /* ALARM_YEARS_REG */ |
3752 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_year % 100); |
3753 | 5c1c390f | balrog | |
3754 | 5c1c390f | balrog | case 0x40: /* RTC_CTRL_REG */ |
3755 | 5c1c390f | balrog | return (s->pm_am << 3) | (s->auto_comp << 2) | |
3756 | 5c1c390f | balrog | (s->round << 1) | s->running;
|
3757 | 5c1c390f | balrog | |
3758 | 5c1c390f | balrog | case 0x44: /* RTC_STATUS_REG */ |
3759 | 5c1c390f | balrog | i = s->status; |
3760 | 5c1c390f | balrog | s->status &= ~0x3d;
|
3761 | 5c1c390f | balrog | return i;
|
3762 | 5c1c390f | balrog | |
3763 | 5c1c390f | balrog | case 0x48: /* RTC_INTERRUPTS_REG */ |
3764 | 5c1c390f | balrog | return s->interrupts;
|
3765 | 5c1c390f | balrog | |
3766 | 5c1c390f | balrog | case 0x4c: /* RTC_COMP_LSB_REG */ |
3767 | 5c1c390f | balrog | return ((uint16_t) s->comp_reg) & 0xff; |
3768 | 5c1c390f | balrog | |
3769 | 5c1c390f | balrog | case 0x50: /* RTC_COMP_MSB_REG */ |
3770 | 5c1c390f | balrog | return ((uint16_t) s->comp_reg) >> 8; |
3771 | 5c1c390f | balrog | } |
3772 | 5c1c390f | balrog | |
3773 | 5c1c390f | balrog | OMAP_BAD_REG(addr); |
3774 | 5c1c390f | balrog | return 0; |
3775 | 5c1c390f | balrog | } |
3776 | 5c1c390f | balrog | |
3777 | 5c1c390f | balrog | static void omap_rtc_write(void *opaque, target_phys_addr_t addr, |
3778 | 5c1c390f | balrog | uint32_t value) |
3779 | 5c1c390f | balrog | { |
3780 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; |
3781 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3782 | 5c1c390f | balrog | struct tm new_tm;
|
3783 | 5c1c390f | balrog | time_t ti[2];
|
3784 | 5c1c390f | balrog | |
3785 | 5c1c390f | balrog | switch (offset) {
|
3786 | 5c1c390f | balrog | case 0x00: /* SECONDS_REG */ |
3787 | 5c1c390f | balrog | #if ALMDEBUG
|
3788 | 5c1c390f | balrog | printf("RTC SEC_REG <-- %02x\n", value);
|
3789 | 5c1c390f | balrog | #endif
|
3790 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_sec; |
3791 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value); |
3792 | 5c1c390f | balrog | return;
|
3793 | 5c1c390f | balrog | |
3794 | 5c1c390f | balrog | case 0x04: /* MINUTES_REG */ |
3795 | 5c1c390f | balrog | #if ALMDEBUG
|
3796 | 5c1c390f | balrog | printf("RTC MIN_REG <-- %02x\n", value);
|
3797 | 5c1c390f | balrog | #endif
|
3798 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_min * 60;
|
3799 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value) * 60;
|
3800 | 5c1c390f | balrog | return;
|
3801 | 5c1c390f | balrog | |
3802 | 5c1c390f | balrog | case 0x08: /* HOURS_REG */ |
3803 | 5c1c390f | balrog | #if ALMDEBUG
|
3804 | 5c1c390f | balrog | printf("RTC HRS_REG <-- %02x\n", value);
|
3805 | 5c1c390f | balrog | #endif
|
3806 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_hour * 3600;
|
3807 | 5c1c390f | balrog | if (s->pm_am) {
|
3808 | 5c1c390f | balrog | s->ti += (omap_rtc_bin(value & 0x3f) & 12) * 3600; |
3809 | 5c1c390f | balrog | s->ti += ((value >> 7) & 1) * 43200; |
3810 | 5c1c390f | balrog | } else
|
3811 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value & 0x3f) * 3600; |
3812 | 5c1c390f | balrog | return;
|
3813 | 5c1c390f | balrog | |
3814 | 5c1c390f | balrog | case 0x0c: /* DAYS_REG */ |
3815 | 5c1c390f | balrog | #if ALMDEBUG
|
3816 | 5c1c390f | balrog | printf("RTC DAY_REG <-- %02x\n", value);
|
3817 | 5c1c390f | balrog | #endif
|
3818 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_mday * 86400;
|
3819 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value) * 86400;
|
3820 | 5c1c390f | balrog | return;
|
3821 | 5c1c390f | balrog | |
3822 | 5c1c390f | balrog | case 0x10: /* MONTHS_REG */ |
3823 | 5c1c390f | balrog | #if ALMDEBUG
|
3824 | 5c1c390f | balrog | printf("RTC MTH_REG <-- %02x\n", value);
|
3825 | 5c1c390f | balrog | #endif
|
3826 | 5c1c390f | balrog | memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
|
3827 | 5c1c390f | balrog | new_tm.tm_mon = omap_rtc_bin(value); |
3828 | 5c1c390f | balrog | ti[0] = mktime(&s->current_tm);
|
3829 | 5c1c390f | balrog | ti[1] = mktime(&new_tm);
|
3830 | 5c1c390f | balrog | |
3831 | 5c1c390f | balrog | if (ti[0] != -1 && ti[1] != -1) { |
3832 | 5c1c390f | balrog | s->ti -= ti[0];
|
3833 | 5c1c390f | balrog | s->ti += ti[1];
|
3834 | 5c1c390f | balrog | } else {
|
3835 | 5c1c390f | balrog | /* A less accurate version */
|
3836 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_mon * 2592000;
|
3837 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value) * 2592000;
|
3838 | 5c1c390f | balrog | } |
3839 | 5c1c390f | balrog | return;
|
3840 | 5c1c390f | balrog | |
3841 | 5c1c390f | balrog | case 0x14: /* YEARS_REG */ |
3842 | 5c1c390f | balrog | #if ALMDEBUG
|
3843 | 5c1c390f | balrog | printf("RTC YRS_REG <-- %02x\n", value);
|
3844 | 5c1c390f | balrog | #endif
|
3845 | 5c1c390f | balrog | memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
|
3846 | 5c1c390f | balrog | new_tm.tm_year += omap_rtc_bin(value) - (new_tm.tm_year % 100);
|
3847 | 5c1c390f | balrog | ti[0] = mktime(&s->current_tm);
|
3848 | 5c1c390f | balrog | ti[1] = mktime(&new_tm);
|
3849 | 5c1c390f | balrog | |
3850 | 5c1c390f | balrog | if (ti[0] != -1 && ti[1] != -1) { |
3851 | 5c1c390f | balrog | s->ti -= ti[0];
|
3852 | 5c1c390f | balrog | s->ti += ti[1];
|
3853 | 5c1c390f | balrog | } else {
|
3854 | 5c1c390f | balrog | /* A less accurate version */
|
3855 | 5c1c390f | balrog | s->ti -= (s->current_tm.tm_year % 100) * 31536000; |
3856 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value) * 31536000;
|
3857 | 5c1c390f | balrog | } |
3858 | 5c1c390f | balrog | return;
|
3859 | 5c1c390f | balrog | |
3860 | 5c1c390f | balrog | case 0x18: /* WEEK_REG */ |
3861 | 5c1c390f | balrog | return; /* Ignored */ |
3862 | 5c1c390f | balrog | |
3863 | 5c1c390f | balrog | case 0x20: /* ALARM_SECONDS_REG */ |
3864 | 5c1c390f | balrog | #if ALMDEBUG
|
3865 | 5c1c390f | balrog | printf("ALM SEC_REG <-- %02x\n", value);
|
3866 | 5c1c390f | balrog | #endif
|
3867 | 5c1c390f | balrog | s->alarm_tm.tm_sec = omap_rtc_bin(value); |
3868 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3869 | 5c1c390f | balrog | return;
|
3870 | 5c1c390f | balrog | |
3871 | 5c1c390f | balrog | case 0x24: /* ALARM_MINUTES_REG */ |
3872 | 5c1c390f | balrog | #if ALMDEBUG
|
3873 | 5c1c390f | balrog | printf("ALM MIN_REG <-- %02x\n", value);
|
3874 | 5c1c390f | balrog | #endif
|
3875 | 5c1c390f | balrog | s->alarm_tm.tm_min = omap_rtc_bin(value); |
3876 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3877 | 5c1c390f | balrog | return;
|
3878 | 5c1c390f | balrog | |
3879 | 5c1c390f | balrog | case 0x28: /* ALARM_HOURS_REG */ |
3880 | 5c1c390f | balrog | #if ALMDEBUG
|
3881 | 5c1c390f | balrog | printf("ALM HRS_REG <-- %02x\n", value);
|
3882 | 5c1c390f | balrog | #endif
|
3883 | 5c1c390f | balrog | if (s->pm_am)
|
3884 | 5c1c390f | balrog | s->alarm_tm.tm_hour = |
3885 | 5c1c390f | balrog | ((omap_rtc_bin(value & 0x3f)) % 12) + |
3886 | 5c1c390f | balrog | ((value >> 7) & 1) * 12; |
3887 | 5c1c390f | balrog | else
|
3888 | 5c1c390f | balrog | s->alarm_tm.tm_hour = omap_rtc_bin(value); |
3889 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3890 | 5c1c390f | balrog | return;
|
3891 | 5c1c390f | balrog | |
3892 | 5c1c390f | balrog | case 0x2c: /* ALARM_DAYS_REG */ |
3893 | 5c1c390f | balrog | #if ALMDEBUG
|
3894 | 5c1c390f | balrog | printf("ALM DAY_REG <-- %02x\n", value);
|
3895 | 5c1c390f | balrog | #endif
|
3896 | 5c1c390f | balrog | s->alarm_tm.tm_mday = omap_rtc_bin(value); |
3897 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3898 | 5c1c390f | balrog | return;
|
3899 | 5c1c390f | balrog | |
3900 | 5c1c390f | balrog | case 0x30: /* ALARM_MONTHS_REG */ |
3901 | 5c1c390f | balrog | #if ALMDEBUG
|
3902 | 5c1c390f | balrog | printf("ALM MON_REG <-- %02x\n", value);
|
3903 | 5c1c390f | balrog | #endif
|
3904 | 5c1c390f | balrog | s->alarm_tm.tm_mon = omap_rtc_bin(value); |
3905 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3906 | 5c1c390f | balrog | return;
|
3907 | 5c1c390f | balrog | |
3908 | 5c1c390f | balrog | case 0x34: /* ALARM_YEARS_REG */ |
3909 | 5c1c390f | balrog | #if ALMDEBUG
|
3910 | 5c1c390f | balrog | printf("ALM YRS_REG <-- %02x\n", value);
|
3911 | 5c1c390f | balrog | #endif
|
3912 | 5c1c390f | balrog | s->alarm_tm.tm_year = omap_rtc_bin(value); |
3913 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3914 | 5c1c390f | balrog | return;
|
3915 | 5c1c390f | balrog | |
3916 | 5c1c390f | balrog | case 0x40: /* RTC_CTRL_REG */ |
3917 | 5c1c390f | balrog | #if ALMDEBUG
|
3918 | 5c1c390f | balrog | printf("RTC CONTROL <-- %02x\n", value);
|
3919 | 5c1c390f | balrog | #endif
|
3920 | 5c1c390f | balrog | s->pm_am = (value >> 3) & 1; |
3921 | 5c1c390f | balrog | s->auto_comp = (value >> 2) & 1; |
3922 | 5c1c390f | balrog | s->round = (value >> 1) & 1; |
3923 | 5c1c390f | balrog | s->running = value & 1;
|
3924 | 5c1c390f | balrog | s->status &= 0xfd;
|
3925 | 5c1c390f | balrog | s->status |= s->running << 1;
|
3926 | 5c1c390f | balrog | return;
|
3927 | 5c1c390f | balrog | |
3928 | 5c1c390f | balrog | case 0x44: /* RTC_STATUS_REG */ |
3929 | 5c1c390f | balrog | #if ALMDEBUG
|
3930 | 5c1c390f | balrog | printf("RTC STATUSL <-- %02x\n", value);
|
3931 | 5c1c390f | balrog | #endif
|
3932 | 5c1c390f | balrog | s->status &= ~((value & 0xc0) ^ 0x80); |
3933 | 5c1c390f | balrog | omap_rtc_interrupts_update(s); |
3934 | 5c1c390f | balrog | return;
|
3935 | 5c1c390f | balrog | |
3936 | 5c1c390f | balrog | case 0x48: /* RTC_INTERRUPTS_REG */ |
3937 | 5c1c390f | balrog | #if ALMDEBUG
|
3938 | 5c1c390f | balrog | printf("RTC INTRS <-- %02x\n", value);
|
3939 | 5c1c390f | balrog | #endif
|
3940 | 5c1c390f | balrog | s->interrupts = value; |
3941 | 5c1c390f | balrog | return;
|
3942 | 5c1c390f | balrog | |
3943 | 5c1c390f | balrog | case 0x4c: /* RTC_COMP_LSB_REG */ |
3944 | 5c1c390f | balrog | #if ALMDEBUG
|
3945 | 5c1c390f | balrog | printf("RTC COMPLSB <-- %02x\n", value);
|
3946 | 5c1c390f | balrog | #endif
|
3947 | 5c1c390f | balrog | s->comp_reg &= 0xff00;
|
3948 | 5c1c390f | balrog | s->comp_reg |= 0x00ff & value;
|
3949 | 5c1c390f | balrog | return;
|
3950 | 5c1c390f | balrog | |
3951 | 5c1c390f | balrog | case 0x50: /* RTC_COMP_MSB_REG */ |
3952 | 5c1c390f | balrog | #if ALMDEBUG
|
3953 | 5c1c390f | balrog | printf("RTC COMPMSB <-- %02x\n", value);
|
3954 | 5c1c390f | balrog | #endif
|
3955 | 5c1c390f | balrog | s->comp_reg &= 0x00ff;
|
3956 | 5c1c390f | balrog | s->comp_reg |= 0xff00 & (value << 8); |
3957 | 5c1c390f | balrog | return;
|
3958 | 5c1c390f | balrog | |
3959 | 5c1c390f | balrog | default:
|
3960 | 5c1c390f | balrog | OMAP_BAD_REG(addr); |
3961 | 5c1c390f | balrog | return;
|
3962 | 5c1c390f | balrog | } |
3963 | 5c1c390f | balrog | } |
3964 | 5c1c390f | balrog | |
3965 | 5c1c390f | balrog | static CPUReadMemoryFunc *omap_rtc_readfn[] = {
|
3966 | 5c1c390f | balrog | omap_rtc_read, |
3967 | 5c1c390f | balrog | omap_badwidth_read8, |
3968 | 5c1c390f | balrog | omap_badwidth_read8, |
3969 | 5c1c390f | balrog | }; |
3970 | 5c1c390f | balrog | |
3971 | 5c1c390f | balrog | static CPUWriteMemoryFunc *omap_rtc_writefn[] = {
|
3972 | 5c1c390f | balrog | omap_rtc_write, |
3973 | 5c1c390f | balrog | omap_badwidth_write8, |
3974 | 5c1c390f | balrog | omap_badwidth_write8, |
3975 | 5c1c390f | balrog | }; |
3976 | 5c1c390f | balrog | |
3977 | 5c1c390f | balrog | static void omap_rtc_tick(void *opaque) |
3978 | 5c1c390f | balrog | { |
3979 | 5c1c390f | balrog | struct omap_rtc_s *s = opaque;
|
3980 | 5c1c390f | balrog | |
3981 | 5c1c390f | balrog | if (s->round) {
|
3982 | 5c1c390f | balrog | /* Round to nearest full minute. */
|
3983 | 5c1c390f | balrog | if (s->current_tm.tm_sec < 30) |
3984 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_sec; |
3985 | 5c1c390f | balrog | else
|
3986 | 5c1c390f | balrog | s->ti += 60 - s->current_tm.tm_sec;
|
3987 | 5c1c390f | balrog | |
3988 | 5c1c390f | balrog | s->round = 0;
|
3989 | 5c1c390f | balrog | } |
3990 | 5c1c390f | balrog | |
3991 | 5c1c390f | balrog | localtime_r(&s->ti, &s->current_tm); |
3992 | 5c1c390f | balrog | |
3993 | 5c1c390f | balrog | if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { |
3994 | 5c1c390f | balrog | s->status |= 0x40;
|
3995 | 5c1c390f | balrog | omap_rtc_interrupts_update(s); |
3996 | 5c1c390f | balrog | } |
3997 | 5c1c390f | balrog | |
3998 | 5c1c390f | balrog | if (s->interrupts & 0x04) |
3999 | 5c1c390f | balrog | switch (s->interrupts & 3) { |
4000 | 5c1c390f | balrog | case 0: |
4001 | 5c1c390f | balrog | s->status |= 0x04;
|
4002 | 5c1c390f | balrog | qemu_irq_raise(s->irq); |
4003 | 5c1c390f | balrog | break;
|
4004 | 5c1c390f | balrog | case 1: |
4005 | 5c1c390f | balrog | if (s->current_tm.tm_sec)
|
4006 | 5c1c390f | balrog | break;
|
4007 | 5c1c390f | balrog | s->status |= 0x08;
|
4008 | 5c1c390f | balrog | qemu_irq_raise(s->irq); |
4009 | 5c1c390f | balrog | break;
|
4010 | 5c1c390f | balrog | case 2: |
4011 | 5c1c390f | balrog | if (s->current_tm.tm_sec || s->current_tm.tm_min)
|
4012 | 5c1c390f | balrog | break;
|
4013 | 5c1c390f | balrog | s->status |= 0x10;
|
4014 | 5c1c390f | balrog | qemu_irq_raise(s->irq); |
4015 | 5c1c390f | balrog | break;
|
4016 | 5c1c390f | balrog | case 3: |
4017 | 5c1c390f | balrog | if (s->current_tm.tm_sec ||
|
4018 | 5c1c390f | balrog | s->current_tm.tm_min || s->current_tm.tm_hour) |
4019 | 5c1c390f | balrog | break;
|
4020 | 5c1c390f | balrog | s->status |= 0x20;
|
4021 | 5c1c390f | balrog | qemu_irq_raise(s->irq); |
4022 | 5c1c390f | balrog | break;
|
4023 | 5c1c390f | balrog | } |
4024 | 5c1c390f | balrog | |
4025 | 5c1c390f | balrog | /* Move on */
|
4026 | 5c1c390f | balrog | if (s->running)
|
4027 | 5c1c390f | balrog | s->ti ++; |
4028 | 5c1c390f | balrog | s->tick += 1000;
|
4029 | 5c1c390f | balrog | |
4030 | 5c1c390f | balrog | /*
|
4031 | 5c1c390f | balrog | * Every full hour add a rough approximation of the compensation
|
4032 | 5c1c390f | balrog | * register to the 32kHz Timer (which drives the RTC) value.
|
4033 | 5c1c390f | balrog | */
|
4034 | 5c1c390f | balrog | if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
|
4035 | 5c1c390f | balrog | s->tick += s->comp_reg * 1000 / 32768; |
4036 | 5c1c390f | balrog | |
4037 | 5c1c390f | balrog | qemu_mod_timer(s->clk, s->tick); |
4038 | 5c1c390f | balrog | } |
4039 | 5c1c390f | balrog | |
4040 | 9596ebb7 | pbrook | static void omap_rtc_reset(struct omap_rtc_s *s) |
4041 | 5c1c390f | balrog | { |
4042 | 5c1c390f | balrog | s->interrupts = 0;
|
4043 | 5c1c390f | balrog | s->comp_reg = 0;
|
4044 | 5c1c390f | balrog | s->running = 0;
|
4045 | 5c1c390f | balrog | s->pm_am = 0;
|
4046 | 5c1c390f | balrog | s->auto_comp = 0;
|
4047 | 5c1c390f | balrog | s->round = 0;
|
4048 | 5c1c390f | balrog | s->tick = qemu_get_clock(rt_clock); |
4049 | 5c1c390f | balrog | memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); |
4050 | 5c1c390f | balrog | s->alarm_tm.tm_mday = 0x01;
|
4051 | 5c1c390f | balrog | s->status = 1 << 7; |
4052 | 5c1c390f | balrog | time(&s->ti); |
4053 | 5c1c390f | balrog | s->ti = mktime(s->convert(&s->ti, &s->current_tm)); |
4054 | 5c1c390f | balrog | |
4055 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
4056 | 5c1c390f | balrog | omap_rtc_tick(s); |
4057 | 5c1c390f | balrog | } |
4058 | 5c1c390f | balrog | |
4059 | 5c1c390f | balrog | struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
|
4060 | 5c1c390f | balrog | qemu_irq *irq, omap_clk clk) |
4061 | 5c1c390f | balrog | { |
4062 | 5c1c390f | balrog | int iomemtype;
|
4063 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) |
4064 | 5c1c390f | balrog | qemu_mallocz(sizeof(struct omap_rtc_s)); |
4065 | 5c1c390f | balrog | |
4066 | 5c1c390f | balrog | s->base = base; |
4067 | 5c1c390f | balrog | s->irq = irq[0];
|
4068 | 5c1c390f | balrog | s->alarm = irq[1];
|
4069 | 5c1c390f | balrog | s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s); |
4070 | 5c1c390f | balrog | s->convert = rtc_utc ? gmtime_r : localtime_r; |
4071 | 5c1c390f | balrog | |
4072 | 5c1c390f | balrog | omap_rtc_reset(s); |
4073 | 5c1c390f | balrog | |
4074 | 5c1c390f | balrog | iomemtype = cpu_register_io_memory(0, omap_rtc_readfn,
|
4075 | 5c1c390f | balrog | omap_rtc_writefn, s); |
4076 | 5c1c390f | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
4077 | 5c1c390f | balrog | |
4078 | 5c1c390f | balrog | return s;
|
4079 | 5c1c390f | balrog | } |
4080 | 5c1c390f | balrog | |
4081 | d8f699cb | balrog | /* Multi-channel Buffered Serial Port interfaces */
|
4082 | d8f699cb | balrog | struct omap_mcbsp_s {
|
4083 | d8f699cb | balrog | target_phys_addr_t base; |
4084 | d8f699cb | balrog | qemu_irq txirq; |
4085 | d8f699cb | balrog | qemu_irq rxirq; |
4086 | d8f699cb | balrog | qemu_irq txdrq; |
4087 | d8f699cb | balrog | qemu_irq rxdrq; |
4088 | d8f699cb | balrog | |
4089 | d8f699cb | balrog | uint16_t spcr[2];
|
4090 | d8f699cb | balrog | uint16_t rcr[2];
|
4091 | d8f699cb | balrog | uint16_t xcr[2];
|
4092 | d8f699cb | balrog | uint16_t srgr[2];
|
4093 | d8f699cb | balrog | uint16_t mcr[2];
|
4094 | d8f699cb | balrog | uint16_t pcr; |
4095 | d8f699cb | balrog | uint16_t rcer[8];
|
4096 | d8f699cb | balrog | uint16_t xcer[8];
|
4097 | d8f699cb | balrog | int tx_rate;
|
4098 | d8f699cb | balrog | int rx_rate;
|
4099 | d8f699cb | balrog | int tx_req;
|
4100 | d8f699cb | balrog | |
4101 | d8f699cb | balrog | struct i2s_codec_s *codec;
|
4102 | d8f699cb | balrog | }; |
4103 | d8f699cb | balrog | |
4104 | d8f699cb | balrog | static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) |
4105 | d8f699cb | balrog | { |
4106 | d8f699cb | balrog | int irq;
|
4107 | d8f699cb | balrog | |
4108 | d8f699cb | balrog | switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ |
4109 | d8f699cb | balrog | case 0: |
4110 | d8f699cb | balrog | irq = (s->spcr[0] >> 1) & 1; /* RRDY */ |
4111 | d8f699cb | balrog | break;
|
4112 | d8f699cb | balrog | case 3: |
4113 | d8f699cb | balrog | irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ |
4114 | d8f699cb | balrog | break;
|
4115 | d8f699cb | balrog | default:
|
4116 | d8f699cb | balrog | irq = 0;
|
4117 | d8f699cb | balrog | break;
|
4118 | d8f699cb | balrog | } |
4119 | d8f699cb | balrog | |
4120 | d8f699cb | balrog | qemu_set_irq(s->rxirq, irq); |
4121 | d8f699cb | balrog | |
4122 | d8f699cb | balrog | switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ |
4123 | d8f699cb | balrog | case 0: |
4124 | d8f699cb | balrog | irq = (s->spcr[1] >> 1) & 1; /* XRDY */ |
4125 | d8f699cb | balrog | break;
|
4126 | d8f699cb | balrog | case 3: |
4127 | d8f699cb | balrog | irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ |
4128 | d8f699cb | balrog | break;
|
4129 | d8f699cb | balrog | default:
|
4130 | d8f699cb | balrog | irq = 0;
|
4131 | d8f699cb | balrog | break;
|
4132 | d8f699cb | balrog | } |
4133 | d8f699cb | balrog | |
4134 | d8f699cb | balrog | qemu_set_irq(s->txirq, irq); |
4135 | d8f699cb | balrog | } |
4136 | d8f699cb | balrog | |
4137 | d8f699cb | balrog | static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) |
4138 | d8f699cb | balrog | { |
4139 | d8f699cb | balrog | int prev = s->tx_req;
|
4140 | d8f699cb | balrog | |
4141 | d8f699cb | balrog | s->tx_req = (s->tx_rate || |
4142 | d8f699cb | balrog | (s->spcr[0] & (1 << 12))) && /* CLKSTP */ |
4143 | d8f699cb | balrog | (s->spcr[1] & (1 << 6)) && /* GRST */ |
4144 | d8f699cb | balrog | (s->spcr[1] & (1 << 0)); /* XRST */ |
4145 | d8f699cb | balrog | |
4146 | d8f699cb | balrog | if (!s->tx_req && prev) {
|
4147 | d8f699cb | balrog | s->spcr[1] &= ~(1 << 1); /* XRDY */ |
4148 | d8f699cb | balrog | qemu_irq_lower(s->txdrq); |
4149 | d8f699cb | balrog | omap_mcbsp_intr_update(s); |
4150 | d8f699cb | balrog | |
4151 | d8f699cb | balrog | if (s->codec)
|
4152 | d8f699cb | balrog | s->codec->tx_swallow(s->codec->opaque); |
4153 | d8f699cb | balrog | } else if (s->codec && s->tx_req && !prev) { |
4154 | d8f699cb | balrog | s->spcr[1] |= 1 << 1; /* XRDY */ |
4155 | d8f699cb | balrog | qemu_irq_raise(s->txdrq); |
4156 | d8f699cb | balrog | omap_mcbsp_intr_update(s); |
4157 | d8f699cb | balrog | } |
4158 | d8f699cb | balrog | } |
4159 | d8f699cb | balrog | |
4160 | d8f699cb | balrog | static void omap_mcbsp_rate_update(struct omap_mcbsp_s *s) |
4161 | d8f699cb | balrog | { |
4162 | d8f699cb | balrog | int rx_clk = 0, tx_clk = 0; |
4163 | d8f699cb | balrog | int cpu_rate = 1500000; /* XXX */ |
4164 | d8f699cb | balrog | if (!s->codec)
|
4165 | d8f699cb | balrog | return;
|
4166 | d8f699cb | balrog | |
4167 | d8f699cb | balrog | if (s->spcr[1] & (1 << 6)) { /* GRST */ |
4168 | d8f699cb | balrog | if (s->spcr[0] & (1 << 0)) /* RRST */ |
4169 | d8f699cb | balrog | if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ |
4170 | d8f699cb | balrog | (s->pcr & (1 << 8))) /* CLKRM */ |
4171 | d8f699cb | balrog | if (~s->pcr & (1 << 7)) /* SCLKME */ |
4172 | d8f699cb | balrog | rx_clk = cpu_rate / |
4173 | d8f699cb | balrog | ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ |
4174 | d8f699cb | balrog | if (s->spcr[1] & (1 << 0)) /* XRST */ |
4175 | d8f699cb | balrog | if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ |
4176 | d8f699cb | balrog | (s->pcr & (1 << 9))) /* CLKXM */ |
4177 | d8f699cb | balrog | if (~s->pcr & (1 << 7)) /* SCLKME */ |
4178 | d8f699cb | balrog | tx_clk = cpu_rate / |
4179 | d8f699cb | balrog | ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ |
4180 | d8f699cb | balrog | } |
4181 | d8f699cb | balrog | |
4182 | d8f699cb | balrog | s->codec->set_rate(s->codec->opaque, rx_clk, tx_clk); |
4183 | d8f699cb | balrog | } |
4184 | d8f699cb | balrog | |
4185 | d8f699cb | balrog | static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) |
4186 | d8f699cb | balrog | { |
4187 | d8f699cb | balrog | if (!(s->spcr[0] & 1)) { /* RRST */ |
4188 | d8f699cb | balrog | if (s->codec)
|
4189 | d8f699cb | balrog | s->codec->in.len = 0;
|
4190 | d8f699cb | balrog | return;
|
4191 | d8f699cb | balrog | } |
4192 | d8f699cb | balrog | |
4193 | d8f699cb | balrog | if ((s->spcr[0] >> 1) & 1) /* RRDY */ |
4194 | d8f699cb | balrog | s->spcr[0] |= 1 << 2; /* RFULL */ |
4195 | d8f699cb | balrog | s->spcr[0] |= 1 << 1; /* RRDY */ |
4196 | d8f699cb | balrog | qemu_irq_raise(s->rxdrq); |
4197 | d8f699cb | balrog | omap_mcbsp_intr_update(s); |
4198 | d8f699cb | balrog | } |
4199 | d8f699cb | balrog | |
4200 | d8f699cb | balrog | static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) |
4201 | d8f699cb | balrog | { |
4202 | d8f699cb | balrog | s->spcr[0] &= ~(1 << 1); /* RRDY */ |
4203 | d8f699cb | balrog | qemu_irq_lower(s->rxdrq); |
4204 | d8f699cb | balrog | omap_mcbsp_intr_update(s); |
4205 | d8f699cb | balrog | } |
4206 | d8f699cb | balrog | |
4207 | d8f699cb | balrog | static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) |
4208 | d8f699cb | balrog | { |
4209 | d8f699cb | balrog | if (s->tx_rate)
|
4210 | d8f699cb | balrog | return;
|
4211 | d8f699cb | balrog | s->tx_rate = 1;
|
4212 | d8f699cb | balrog | omap_mcbsp_req_update(s); |
4213 | d8f699cb | balrog | } |
4214 | d8f699cb | balrog | |
4215 | d8f699cb | balrog | static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) |
4216 | d8f699cb | balrog | { |
4217 | d8f699cb | balrog | s->tx_rate = 0;
|
4218 | d8f699cb | balrog | omap_mcbsp_req_update(s); |
4219 | d8f699cb | balrog | } |
4220 | d8f699cb | balrog | |
4221 | d8f699cb | balrog | static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr) |
4222 | d8f699cb | balrog | { |
4223 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
4224 | d8f699cb | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
4225 | d8f699cb | balrog | uint16_t ret; |
4226 | d8f699cb | balrog | |
4227 | d8f699cb | balrog | switch (offset) {
|
4228 | d8f699cb | balrog | case 0x00: /* DRR2 */ |
4229 | d8f699cb | balrog | if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ |
4230 | d8f699cb | balrog | return 0x0000; |
4231 | d8f699cb | balrog | /* Fall through. */
|
4232 | d8f699cb | balrog | case 0x02: /* DRR1 */ |
4233 | d8f699cb | balrog | if (!s->codec)
|
4234 | d8f699cb | balrog | return 0x0000; |
4235 | d8f699cb | balrog | if (s->codec->in.len < 2) { |
4236 | d8f699cb | balrog | printf("%s: Rx FIFO underrun\n", __FUNCTION__);
|
4237 | d8f699cb | balrog | omap_mcbsp_rx_stop(s); |
4238 | d8f699cb | balrog | } else {
|
4239 | d8f699cb | balrog | s->codec->in.len -= 2;
|
4240 | d8f699cb | balrog | ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
|
4241 | d8f699cb | balrog | ret |= s->codec->in.fifo[s->codec->in.start ++]; |
4242 | d8f699cb | balrog | if (!s->codec->in.len)
|
4243 | d8f699cb | balrog | omap_mcbsp_rx_stop(s); |
4244 | d8f699cb | balrog | return ret;
|
4245 | d8f699cb | balrog | } |
4246 | d8f699cb | balrog | return 0x0000; |
4247 | d8f699cb | balrog | |
4248 | d8f699cb | balrog | case 0x04: /* DXR2 */ |
4249 | d8f699cb | balrog | case 0x06: /* DXR1 */ |
4250 | d8f699cb | balrog | return 0x0000; |
4251 | d8f699cb | balrog | |
4252 | d8f699cb | balrog | case 0x08: /* SPCR2 */ |
4253 | d8f699cb | balrog | return s->spcr[1]; |
4254 | d8f699cb | balrog | case 0x0a: /* SPCR1 */ |
4255 | d8f699cb | balrog | return s->spcr[0]; |
4256 | d8f699cb | balrog | case 0x0c: /* RCR2 */ |
4257 | d8f699cb | balrog | return s->rcr[1]; |
4258 | d8f699cb | balrog | case 0x0e: /* RCR1 */ |
4259 | d8f699cb | balrog | return s->rcr[0]; |
4260 | d8f699cb | balrog | case 0x10: /* XCR2 */ |
4261 | d8f699cb | balrog | return s->xcr[1]; |
4262 | d8f699cb | balrog | case 0x12: /* XCR1 */ |
4263 | d8f699cb | balrog | return s->xcr[0]; |
4264 | d8f699cb | balrog | case 0x14: /* SRGR2 */ |
4265 | d8f699cb | balrog | return s->srgr[1]; |
4266 | d8f699cb | balrog | case 0x16: /* SRGR1 */ |
4267 | d8f699cb | balrog | return s->srgr[0]; |
4268 | d8f699cb | balrog | case 0x18: /* MCR2 */ |
4269 | d8f699cb | balrog | return s->mcr[1]; |
4270 | d8f699cb | balrog | case 0x1a: /* MCR1 */ |
4271 | d8f699cb | balrog | return s->mcr[0]; |
4272 | d8f699cb | balrog | case 0x1c: /* RCERA */ |
4273 | d8f699cb | balrog | return s->rcer[0]; |
4274 | d8f699cb | balrog | case 0x1e: /* RCERB */ |
4275 | d8f699cb | balrog | return s->rcer[1]; |
4276 | d8f699cb | balrog | case 0x20: /* XCERA */ |
4277 | d8f699cb | balrog | return s->xcer[0]; |
4278 | d8f699cb | balrog | case 0x22: /* XCERB */ |
4279 | d8f699cb | balrog | return s->xcer[1]; |
4280 | d8f699cb | balrog | case 0x24: /* PCR0 */ |
4281 | d8f699cb | balrog | return s->pcr;
|
4282 | d8f699cb | balrog | case 0x26: /* RCERC */ |
4283 | d8f699cb | balrog | return s->rcer[2]; |
4284 | d8f699cb | balrog | case 0x28: /* RCERD */ |
4285 | d8f699cb | balrog | return s->rcer[3]; |
4286 | d8f699cb | balrog | case 0x2a: /* XCERC */ |
4287 | d8f699cb | balrog | return s->xcer[2]; |
4288 | d8f699cb | balrog | case 0x2c: /* XCERD */ |
4289 | d8f699cb | balrog | return s->xcer[3]; |
4290 | d8f699cb | balrog | case 0x2e: /* RCERE */ |
4291 | d8f699cb | balrog | return s->rcer[4]; |
4292 | d8f699cb | balrog | case 0x30: /* RCERF */ |
4293 | d8f699cb | balrog | return s->rcer[5]; |
4294 | d8f699cb | balrog | case 0x32: /* XCERE */ |
4295 | d8f699cb | balrog | return s->xcer[4]; |
4296 | d8f699cb | balrog | case 0x34: /* XCERF */ |
4297 | d8f699cb | balrog | return s->xcer[5]; |
4298 | d8f699cb | balrog | case 0x36: /* RCERG */ |
4299 | d8f699cb | balrog | return s->rcer[6]; |
4300 | d8f699cb | balrog | case 0x38: /* RCERH */ |
4301 | d8f699cb | balrog | return s->rcer[7]; |
4302 | d8f699cb | balrog | case 0x3a: /* XCERG */ |
4303 | d8f699cb | balrog | return s->xcer[6]; |
4304 | d8f699cb | balrog | case 0x3c: /* XCERH */ |
4305 | d8f699cb | balrog | return s->xcer[7]; |
4306 | d8f699cb | balrog | } |
4307 | d8f699cb | balrog | |
4308 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
4309 | d8f699cb | balrog | return 0; |
4310 | d8f699cb | balrog | } |
4311 | d8f699cb | balrog | |
4312 | d8f699cb | balrog | static void omap_mcbsp_write(void *opaque, target_phys_addr_t addr, |
4313 | d8f699cb | balrog | uint32_t value) |
4314 | d8f699cb | balrog | { |
4315 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
4316 | d8f699cb | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
4317 | d8f699cb | balrog | |
4318 | d8f699cb | balrog | switch (offset) {
|
4319 | d8f699cb | balrog | case 0x00: /* DRR2 */ |
4320 | d8f699cb | balrog | case 0x02: /* DRR1 */ |
4321 | d8f699cb | balrog | OMAP_RO_REG(addr); |
4322 | d8f699cb | balrog | return;
|
4323 | d8f699cb | balrog | |
4324 | d8f699cb | balrog | case 0x04: /* DXR2 */ |
4325 | d8f699cb | balrog | if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ |
4326 | d8f699cb | balrog | return;
|
4327 | d8f699cb | balrog | /* Fall through. */
|
4328 | d8f699cb | balrog | case 0x06: /* DXR1 */ |
4329 | d8f699cb | balrog | if (!s->codec)
|
4330 | d8f699cb | balrog | return;
|
4331 | d8f699cb | balrog | if (s->tx_req) {
|
4332 | d8f699cb | balrog | if (s->codec->out.len > s->codec->out.size - 2) { |
4333 | d8f699cb | balrog | printf("%s: Tx FIFO overrun\n", __FUNCTION__);
|
4334 | d8f699cb | balrog | omap_mcbsp_tx_stop(s); |
4335 | d8f699cb | balrog | } else {
|
4336 | d8f699cb | balrog | s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; |
4337 | d8f699cb | balrog | s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; |
4338 | d8f699cb | balrog | if (s->codec->out.len >= s->codec->out.size)
|
4339 | d8f699cb | balrog | omap_mcbsp_tx_stop(s); |
4340 | d8f699cb | balrog | } |
4341 | d8f699cb | balrog | } else
|
4342 | d8f699cb | balrog | printf("%s: Tx FIFO overrun\n", __FUNCTION__);
|
4343 | d8f699cb | balrog | return;
|
4344 | d8f699cb | balrog | |
4345 | d8f699cb | balrog | case 0x08: /* SPCR2 */ |
4346 | d8f699cb | balrog | s->spcr[1] &= 0x0002; |
4347 | d8f699cb | balrog | s->spcr[1] |= 0x03f9 & value; |
4348 | d8f699cb | balrog | s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ |
4349 | d8f699cb | balrog | if (~value & 1) { /* XRST */ |
4350 | d8f699cb | balrog | s->spcr[1] &= ~6; |
4351 | d8f699cb | balrog | qemu_irq_lower(s->rxdrq); |
4352 | d8f699cb | balrog | if (s->codec)
|
4353 | d8f699cb | balrog | s->codec->out.len = 0;
|
4354 | d8f699cb | balrog | } |
4355 | d8f699cb | balrog | if (s->codec)
|
4356 | d8f699cb | balrog | omap_mcbsp_rate_update(s); |
4357 | d8f699cb | balrog | omap_mcbsp_req_update(s); |
4358 | d8f699cb | balrog | return;
|
4359 | d8f699cb | balrog | case 0x0a: /* SPCR1 */ |
4360 | d8f699cb | balrog | s->spcr[0] &= 0x0006; |
4361 | d8f699cb | balrog | s->spcr[0] |= 0xf8f9 & value; |
4362 | d8f699cb | balrog | if (value & (1 << 15)) /* DLB */ |
4363 | d8f699cb | balrog | printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
|
4364 | d8f699cb | balrog | if (~value & 1) { /* RRST */ |
4365 | d8f699cb | balrog | s->spcr[0] &= ~6; |
4366 | d8f699cb | balrog | qemu_irq_lower(s->txdrq); |
4367 | d8f699cb | balrog | if (s->codec)
|
4368 | d8f699cb | balrog | s->codec->in.len = 0;
|
4369 | d8f699cb | balrog | } |
4370 | d8f699cb | balrog | if (s->codec)
|
4371 | d8f699cb | balrog | omap_mcbsp_rate_update(s); |
4372 | d8f699cb | balrog | omap_mcbsp_req_update(s); |
4373 | d8f699cb | balrog | return;
|
4374 | d8f699cb | balrog | |
4375 | d8f699cb | balrog | case 0x0c: /* RCR2 */ |
4376 | d8f699cb | balrog | s->rcr[1] = value & 0xffff; |
4377 | d8f699cb | balrog | return;
|
4378 | d8f699cb | balrog | case 0x0e: /* RCR1 */ |
4379 | d8f699cb | balrog | s->rcr[0] = value & 0x7fe0; |
4380 | d8f699cb | balrog | return;
|
4381 | d8f699cb | balrog | case 0x10: /* XCR2 */ |
4382 | d8f699cb | balrog | s->xcr[1] = value & 0xffff; |
4383 | d8f699cb | balrog | return;
|
4384 | d8f699cb | balrog | case 0x12: /* XCR1 */ |
4385 | d8f699cb | balrog | s->xcr[0] = value & 0x7fe0; |
4386 | d8f699cb | balrog | return;
|
4387 | d8f699cb | balrog | case 0x14: /* SRGR2 */ |
4388 | d8f699cb | balrog | s->srgr[1] = value & 0xffff; |
4389 | d8f699cb | balrog | omap_mcbsp_rate_update(s); |
4390 | d8f699cb | balrog | return;
|
4391 | d8f699cb | balrog | case 0x16: /* SRGR1 */ |
4392 | d8f699cb | balrog | s->srgr[0] = value & 0xffff; |
4393 | d8f699cb | balrog | omap_mcbsp_rate_update(s); |
4394 | d8f699cb | balrog | return;
|
4395 | d8f699cb | balrog | case 0x18: /* MCR2 */ |
4396 | d8f699cb | balrog | s->mcr[1] = value & 0x03e3; |
4397 | d8f699cb | balrog | if (value & 3) /* XMCM */ |
4398 | d8f699cb | balrog | printf("%s: Tx channel selection mode enable attempt\n",
|
4399 | d8f699cb | balrog | __FUNCTION__); |
4400 | d8f699cb | balrog | return;
|
4401 | d8f699cb | balrog | case 0x1a: /* MCR1 */ |
4402 | d8f699cb | balrog | s->mcr[0] = value & 0x03e1; |
4403 | d8f699cb | balrog | if (value & 1) /* RMCM */ |
4404 | d8f699cb | balrog | printf("%s: Rx channel selection mode enable attempt\n",
|
4405 | d8f699cb | balrog | __FUNCTION__); |
4406 | d8f699cb | balrog | return;
|
4407 | d8f699cb | balrog | case 0x1c: /* RCERA */ |
4408 | d8f699cb | balrog | s->rcer[0] = value & 0xffff; |
4409 | d8f699cb | balrog | return;
|
4410 | d8f699cb | balrog | case 0x1e: /* RCERB */ |
4411 | d8f699cb | balrog | s->rcer[1] = value & 0xffff; |
4412 | d8f699cb | balrog | return;
|
4413 | d8f699cb | balrog | case 0x20: /* XCERA */ |
4414 | d8f699cb | balrog | s->xcer[0] = value & 0xffff; |
4415 | d8f699cb | balrog | return;
|
4416 | d8f699cb | balrog | case 0x22: /* XCERB */ |
4417 | d8f699cb | balrog | s->xcer[1] = value & 0xffff; |
4418 | d8f699cb | balrog | return;
|
4419 | d8f699cb | balrog | case 0x24: /* PCR0 */ |
4420 | d8f699cb | balrog | s->pcr = value & 0x7faf;
|
4421 | d8f699cb | balrog | return;
|
4422 | d8f699cb | balrog | case 0x26: /* RCERC */ |
4423 | d8f699cb | balrog | s->rcer[2] = value & 0xffff; |
4424 | d8f699cb | balrog | return;
|
4425 | d8f699cb | balrog | case 0x28: /* RCERD */ |
4426 | d8f699cb | balrog | s->rcer[3] = value & 0xffff; |
4427 | d8f699cb | balrog | return;
|
4428 | d8f699cb | balrog | case 0x2a: /* XCERC */ |
4429 | d8f699cb | balrog | s->xcer[2] = value & 0xffff; |
4430 | d8f699cb | balrog | return;
|
4431 | d8f699cb | balrog | case 0x2c: /* XCERD */ |
4432 | d8f699cb | balrog | s->xcer[3] = value & 0xffff; |
4433 | d8f699cb | balrog | return;
|
4434 | d8f699cb | balrog | case 0x2e: /* RCERE */ |
4435 | d8f699cb | balrog | s->rcer[4] = value & 0xffff; |
4436 | d8f699cb | balrog | return;
|
4437 | d8f699cb | balrog | case 0x30: /* RCERF */ |
4438 | d8f699cb | balrog | s->rcer[5] = value & 0xffff; |
4439 | d8f699cb | balrog | return;
|
4440 | d8f699cb | balrog | case 0x32: /* XCERE */ |
4441 | d8f699cb | balrog | s->xcer[4] = value & 0xffff; |
4442 | d8f699cb | balrog | return;
|
4443 | d8f699cb | balrog | case 0x34: /* XCERF */ |
4444 | d8f699cb | balrog | s->xcer[5] = value & 0xffff; |
4445 | d8f699cb | balrog | return;
|
4446 | d8f699cb | balrog | case 0x36: /* RCERG */ |
4447 | d8f699cb | balrog | s->rcer[6] = value & 0xffff; |
4448 | d8f699cb | balrog | return;
|
4449 | d8f699cb | balrog | case 0x38: /* RCERH */ |
4450 | d8f699cb | balrog | s->rcer[7] = value & 0xffff; |
4451 | d8f699cb | balrog | return;
|
4452 | d8f699cb | balrog | case 0x3a: /* XCERG */ |
4453 | d8f699cb | balrog | s->xcer[6] = value & 0xffff; |
4454 | d8f699cb | balrog | return;
|
4455 | d8f699cb | balrog | case 0x3c: /* XCERH */ |
4456 | d8f699cb | balrog | s->xcer[7] = value & 0xffff; |
4457 | d8f699cb | balrog | return;
|
4458 | d8f699cb | balrog | } |
4459 | d8f699cb | balrog | |
4460 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
4461 | d8f699cb | balrog | } |
4462 | d8f699cb | balrog | |
4463 | d8f699cb | balrog | static CPUReadMemoryFunc *omap_mcbsp_readfn[] = {
|
4464 | d8f699cb | balrog | omap_badwidth_read16, |
4465 | d8f699cb | balrog | omap_mcbsp_read, |
4466 | d8f699cb | balrog | omap_badwidth_read16, |
4467 | d8f699cb | balrog | }; |
4468 | d8f699cb | balrog | |
4469 | d8f699cb | balrog | static CPUWriteMemoryFunc *omap_mcbsp_writefn[] = {
|
4470 | d8f699cb | balrog | omap_badwidth_write16, |
4471 | d8f699cb | balrog | omap_mcbsp_write, |
4472 | d8f699cb | balrog | omap_badwidth_write16, |
4473 | d8f699cb | balrog | }; |
4474 | d8f699cb | balrog | |
4475 | d8f699cb | balrog | static void omap_mcbsp_reset(struct omap_mcbsp_s *s) |
4476 | d8f699cb | balrog | { |
4477 | d8f699cb | balrog | memset(&s->spcr, 0, sizeof(s->spcr)); |
4478 | d8f699cb | balrog | memset(&s->rcr, 0, sizeof(s->rcr)); |
4479 | d8f699cb | balrog | memset(&s->xcr, 0, sizeof(s->xcr)); |
4480 | d8f699cb | balrog | s->srgr[0] = 0x0001; |
4481 | d8f699cb | balrog | s->srgr[1] = 0x2000; |
4482 | d8f699cb | balrog | memset(&s->mcr, 0, sizeof(s->mcr)); |
4483 | d8f699cb | balrog | memset(&s->pcr, 0, sizeof(s->pcr)); |
4484 | d8f699cb | balrog | memset(&s->rcer, 0, sizeof(s->rcer)); |
4485 | d8f699cb | balrog | memset(&s->xcer, 0, sizeof(s->xcer)); |
4486 | d8f699cb | balrog | s->tx_req = 0;
|
4487 | d8f699cb | balrog | s->tx_rate = 0;
|
4488 | d8f699cb | balrog | s->rx_rate = 0;
|
4489 | d8f699cb | balrog | } |
4490 | d8f699cb | balrog | |
4491 | d8f699cb | balrog | struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
|
4492 | d8f699cb | balrog | qemu_irq *irq, qemu_irq *dma, omap_clk clk) |
4493 | d8f699cb | balrog | { |
4494 | d8f699cb | balrog | int iomemtype;
|
4495 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) |
4496 | d8f699cb | balrog | qemu_mallocz(sizeof(struct omap_mcbsp_s)); |
4497 | d8f699cb | balrog | |
4498 | d8f699cb | balrog | s->base = base; |
4499 | d8f699cb | balrog | s->txirq = irq[0];
|
4500 | d8f699cb | balrog | s->rxirq = irq[1];
|
4501 | d8f699cb | balrog | s->txdrq = dma[0];
|
4502 | d8f699cb | balrog | s->rxdrq = dma[1];
|
4503 | d8f699cb | balrog | omap_mcbsp_reset(s); |
4504 | d8f699cb | balrog | |
4505 | d8f699cb | balrog | iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn,
|
4506 | d8f699cb | balrog | omap_mcbsp_writefn, s); |
4507 | d8f699cb | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
4508 | d8f699cb | balrog | |
4509 | d8f699cb | balrog | return s;
|
4510 | d8f699cb | balrog | } |
4511 | d8f699cb | balrog | |
4512 | 9596ebb7 | pbrook | static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) |
4513 | d8f699cb | balrog | { |
4514 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
4515 | d8f699cb | balrog | |
4516 | d8f699cb | balrog | omap_mcbsp_rx_start(s); |
4517 | d8f699cb | balrog | } |
4518 | d8f699cb | balrog | |
4519 | 9596ebb7 | pbrook | static void omap_mcbsp_i2s_start(void *opaque, int line, int level) |
4520 | d8f699cb | balrog | { |
4521 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
4522 | d8f699cb | balrog | |
4523 | d8f699cb | balrog | omap_mcbsp_tx_start(s); |
4524 | d8f699cb | balrog | } |
4525 | d8f699cb | balrog | |
4526 | d8f699cb | balrog | void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave) |
4527 | d8f699cb | balrog | { |
4528 | d8f699cb | balrog | s->codec = slave; |
4529 | d8f699cb | balrog | slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0]; |
4530 | d8f699cb | balrog | slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0]; |
4531 | d8f699cb | balrog | } |
4532 | d8f699cb | balrog | |
4533 | c3d2689d | balrog | /* General chip reset */
|
4534 | c3d2689d | balrog | static void omap_mpu_reset(void *opaque) |
4535 | c3d2689d | balrog | { |
4536 | c3d2689d | balrog | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
4537 | c3d2689d | balrog | |
4538 | c3d2689d | balrog | omap_clkm_reset(mpu); |
4539 | c3d2689d | balrog | omap_inth_reset(mpu->ih[0]);
|
4540 | c3d2689d | balrog | omap_inth_reset(mpu->ih[1]);
|
4541 | c3d2689d | balrog | omap_dma_reset(mpu->dma); |
4542 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[0]);
|
4543 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[1]);
|
4544 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[2]);
|
4545 | c3d2689d | balrog | omap_wd_timer_reset(mpu->wdt); |
4546 | c3d2689d | balrog | omap_os_timer_reset(mpu->os_timer); |
4547 | c3d2689d | balrog | omap_lcdc_reset(mpu->lcd); |
4548 | c3d2689d | balrog | omap_ulpd_pm_reset(mpu); |
4549 | c3d2689d | balrog | omap_pin_cfg_reset(mpu); |
4550 | c3d2689d | balrog | omap_mpui_reset(mpu); |
4551 | c3d2689d | balrog | omap_tipb_bridge_reset(mpu->private_tipb); |
4552 | c3d2689d | balrog | omap_tipb_bridge_reset(mpu->public_tipb); |
4553 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[0]);
|
4554 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[1]);
|
4555 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[2]);
|
4556 | d951f6ff | balrog | omap_uart_reset(mpu->uart[0]);
|
4557 | d951f6ff | balrog | omap_uart_reset(mpu->uart[1]);
|
4558 | d951f6ff | balrog | omap_uart_reset(mpu->uart[2]);
|
4559 | b30bb3a2 | balrog | omap_mmc_reset(mpu->mmc); |
4560 | fe71e81a | balrog | omap_mpuio_reset(mpu->mpuio); |
4561 | 64330148 | balrog | omap_gpio_reset(mpu->gpio); |
4562 | d951f6ff | balrog | omap_uwire_reset(mpu->microwire); |
4563 | 66450b15 | balrog | omap_pwl_reset(mpu); |
4564 | 4a2c8ac2 | balrog | omap_pwt_reset(mpu); |
4565 | 4a2c8ac2 | balrog | omap_i2c_reset(mpu->i2c); |
4566 | 5c1c390f | balrog | omap_rtc_reset(mpu->rtc); |
4567 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp1); |
4568 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp2); |
4569 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp3); |
4570 | c3d2689d | balrog | cpu_reset(mpu->env); |
4571 | c3d2689d | balrog | } |
4572 | c3d2689d | balrog | |
4573 | cf965d24 | balrog | static const struct omap_map_s { |
4574 | cf965d24 | balrog | target_phys_addr_t phys_dsp; |
4575 | cf965d24 | balrog | target_phys_addr_t phys_mpu; |
4576 | cf965d24 | balrog | uint32_t size; |
4577 | cf965d24 | balrog | const char *name; |
4578 | cf965d24 | balrog | } omap15xx_dsp_mm[] = { |
4579 | cf965d24 | balrog | /* Strobe 0 */
|
4580 | cf965d24 | balrog | { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ |
4581 | cf965d24 | balrog | { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ |
4582 | cf965d24 | balrog | { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ |
4583 | cf965d24 | balrog | { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ |
4584 | cf965d24 | balrog | { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ |
4585 | cf965d24 | balrog | { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ |
4586 | cf965d24 | balrog | { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ |
4587 | cf965d24 | balrog | { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ |
4588 | cf965d24 | balrog | { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ |
4589 | cf965d24 | balrog | { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ |
4590 | cf965d24 | balrog | { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ |
4591 | cf965d24 | balrog | { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ |
4592 | cf965d24 | balrog | { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ |
4593 | cf965d24 | balrog | { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ |
4594 | cf965d24 | balrog | { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ |
4595 | cf965d24 | balrog | { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ |
4596 | cf965d24 | balrog | { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ |
4597 | cf965d24 | balrog | /* Strobe 1 */
|
4598 | cf965d24 | balrog | { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ |
4599 | cf965d24 | balrog | |
4600 | cf965d24 | balrog | { 0 }
|
4601 | cf965d24 | balrog | }; |
4602 | cf965d24 | balrog | |
4603 | cf965d24 | balrog | static void omap_setup_dsp_mapping(const struct omap_map_s *map) |
4604 | cf965d24 | balrog | { |
4605 | cf965d24 | balrog | int io;
|
4606 | cf965d24 | balrog | |
4607 | cf965d24 | balrog | for (; map->phys_dsp; map ++) {
|
4608 | cf965d24 | balrog | io = cpu_get_physical_page_desc(map->phys_mpu); |
4609 | cf965d24 | balrog | |
4610 | cf965d24 | balrog | cpu_register_physical_memory(map->phys_dsp, map->size, io); |
4611 | cf965d24 | balrog | } |
4612 | cf965d24 | balrog | } |
4613 | cf965d24 | balrog | |
4614 | c3d2689d | balrog | static void omap_mpu_wakeup(void *opaque, int irq, int req) |
4615 | c3d2689d | balrog | { |
4616 | c3d2689d | balrog | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
4617 | c3d2689d | balrog | |
4618 | fe71e81a | balrog | if (mpu->env->halted)
|
4619 | fe71e81a | balrog | cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB); |
4620 | c3d2689d | balrog | } |
4621 | c3d2689d | balrog | |
4622 | c3d2689d | balrog | struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, |
4623 | c3d2689d | balrog | DisplayState *ds, const char *core) |
4624 | c3d2689d | balrog | { |
4625 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) |
4626 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_mpu_state_s)); |
4627 | c3d2689d | balrog | ram_addr_t imif_base, emiff_base; |
4628 | aaed909a | bellard | |
4629 | aaed909a | bellard | if (!core)
|
4630 | aaed909a | bellard | core = "ti925t";
|
4631 | c3d2689d | balrog | |
4632 | c3d2689d | balrog | /* Core */
|
4633 | c3d2689d | balrog | s->mpu_model = omap310; |
4634 | aaed909a | bellard | s->env = cpu_init(core); |
4635 | aaed909a | bellard | if (!s->env) {
|
4636 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
|
4637 | aaed909a | bellard | exit(1);
|
4638 | aaed909a | bellard | } |
4639 | c3d2689d | balrog | s->sdram_size = sdram_size; |
4640 | c3d2689d | balrog | s->sram_size = OMAP15XX_SRAM_SIZE; |
4641 | c3d2689d | balrog | |
4642 | fe71e81a | balrog | s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; |
4643 | fe71e81a | balrog | |
4644 | c3d2689d | balrog | /* Clocks */
|
4645 | c3d2689d | balrog | omap_clk_init(s); |
4646 | c3d2689d | balrog | |
4647 | c3d2689d | balrog | /* Memory-mapped stuff */
|
4648 | c3d2689d | balrog | cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size, |
4649 | c3d2689d | balrog | (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM); |
4650 | c3d2689d | balrog | cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size, |
4651 | c3d2689d | balrog | (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM); |
4652 | c3d2689d | balrog | |
4653 | c3d2689d | balrog | omap_clkm_init(0xfffece00, 0xe1008000, s); |
4654 | c3d2689d | balrog | |
4655 | c3d2689d | balrog | s->ih[0] = omap_inth_init(0xfffecb00, 0x100, |
4656 | c3d2689d | balrog | arm_pic_init_cpu(s->env), |
4657 | c3d2689d | balrog | omap_findclk(s, "arminth_ck"));
|
4658 | c3d2689d | balrog | s->ih[1] = omap_inth_init(0xfffe0000, 0x800, |
4659 | c3d2689d | balrog | &s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ],
|
4660 | c3d2689d | balrog | omap_findclk(s, "arminth_ck"));
|
4661 | c3d2689d | balrog | s->irq[0] = s->ih[0]->pins; |
4662 | c3d2689d | balrog | s->irq[1] = s->ih[1]->pins; |
4663 | c3d2689d | balrog | |
4664 | c3d2689d | balrog | s->dma = omap_dma_init(0xfffed800, s->irq[0], s, |
4665 | c3d2689d | balrog | omap_findclk(s, "dma_ck"));
|
4666 | c3d2689d | balrog | s->port[emiff ].addr_valid = omap_validate_emiff_addr; |
4667 | c3d2689d | balrog | s->port[emifs ].addr_valid = omap_validate_emifs_addr; |
4668 | c3d2689d | balrog | s->port[imif ].addr_valid = omap_validate_imif_addr; |
4669 | c3d2689d | balrog | s->port[tipb ].addr_valid = omap_validate_tipb_addr; |
4670 | c3d2689d | balrog | s->port[local ].addr_valid = omap_validate_local_addr; |
4671 | c3d2689d | balrog | s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; |
4672 | c3d2689d | balrog | |
4673 | c3d2689d | balrog | s->timer[0] = omap_mpu_timer_init(0xfffec500, |
4674 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER1],
|
4675 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
4676 | c3d2689d | balrog | s->timer[1] = omap_mpu_timer_init(0xfffec600, |
4677 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER2],
|
4678 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
4679 | c3d2689d | balrog | s->timer[2] = omap_mpu_timer_init(0xfffec700, |
4680 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER3],
|
4681 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
4682 | c3d2689d | balrog | |
4683 | c3d2689d | balrog | s->wdt = omap_wd_timer_init(0xfffec800,
|
4684 | c3d2689d | balrog | s->irq[0][OMAP_INT_WD_TIMER],
|
4685 | c3d2689d | balrog | omap_findclk(s, "armwdt_ck"));
|
4686 | c3d2689d | balrog | |
4687 | c3d2689d | balrog | s->os_timer = omap_os_timer_init(0xfffb9000,
|
4688 | c3d2689d | balrog | s->irq[1][OMAP_INT_OS_TIMER],
|
4689 | c3d2689d | balrog | omap_findclk(s, "clk32-kHz"));
|
4690 | c3d2689d | balrog | |
4691 | c3d2689d | balrog | s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL], |
4692 | c3d2689d | balrog | &s->dma->lcd_ch, ds, imif_base, emiff_base, |
4693 | c3d2689d | balrog | omap_findclk(s, "lcd_ck"));
|
4694 | c3d2689d | balrog | |
4695 | c3d2689d | balrog | omap_ulpd_pm_init(0xfffe0800, s);
|
4696 | c3d2689d | balrog | omap_pin_cfg_init(0xfffe1000, s);
|
4697 | c3d2689d | balrog | omap_id_init(s); |
4698 | c3d2689d | balrog | |
4699 | c3d2689d | balrog | omap_mpui_init(0xfffec900, s);
|
4700 | c3d2689d | balrog | |
4701 | c3d2689d | balrog | s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
|
4702 | c3d2689d | balrog | s->irq[0][OMAP_INT_BRIDGE_PRIV],
|
4703 | c3d2689d | balrog | omap_findclk(s, "tipb_ck"));
|
4704 | c3d2689d | balrog | s->public_tipb = omap_tipb_bridge_init(0xfffed300,
|
4705 | c3d2689d | balrog | s->irq[0][OMAP_INT_BRIDGE_PUB],
|
4706 | c3d2689d | balrog | omap_findclk(s, "tipb_ck"));
|
4707 | c3d2689d | balrog | |
4708 | c3d2689d | balrog | omap_tcmi_init(0xfffecc00, s);
|
4709 | c3d2689d | balrog | |
4710 | d951f6ff | balrog | s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1], |
4711 | c3d2689d | balrog | omap_findclk(s, "uart1_ck"),
|
4712 | c3d2689d | balrog | serial_hds[0]);
|
4713 | d951f6ff | balrog | s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2], |
4714 | c3d2689d | balrog | omap_findclk(s, "uart2_ck"),
|
4715 | c3d2689d | balrog | serial_hds[0] ? serial_hds[1] : 0); |
4716 | d951f6ff | balrog | s->uart[2] = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3], |
4717 | c3d2689d | balrog | omap_findclk(s, "uart3_ck"),
|
4718 | c3d2689d | balrog | serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0); |
4719 | c3d2689d | balrog | |
4720 | c3d2689d | balrog | omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1")); |
4721 | c3d2689d | balrog | omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2")); |
4722 | c3d2689d | balrog | omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3")); |
4723 | c3d2689d | balrog | |
4724 | 87ecb68b | pbrook | s->mmc = omap_mmc_init(0xfffb7800, sd_bdrv, s->irq[1][OMAP_INT_OQN], |
4725 | b30bb3a2 | balrog | &s->drq[OMAP_DMA_MMC_TX], omap_findclk(s, "mmc_ck"));
|
4726 | b30bb3a2 | balrog | |
4727 | fe71e81a | balrog | s->mpuio = omap_mpuio_init(0xfffb5000,
|
4728 | fe71e81a | balrog | s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO], |
4729 | fe71e81a | balrog | s->wakeup, omap_findclk(s, "clk32-kHz"));
|
4730 | fe71e81a | balrog | |
4731 | 3efda49d | balrog | s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1], |
4732 | 66450b15 | balrog | omap_findclk(s, "arm_gpio_ck"));
|
4733 | 64330148 | balrog | |
4734 | d951f6ff | balrog | s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX], |
4735 | d951f6ff | balrog | s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
|
4736 | d951f6ff | balrog | |
4737 | d8f699cb | balrog | omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck")); |
4738 | d8f699cb | balrog | omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck")); |
4739 | 66450b15 | balrog | |
4740 | 4a2c8ac2 | balrog | s->i2c = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C], |
4741 | 4a2c8ac2 | balrog | &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
|
4742 | 4a2c8ac2 | balrog | |
4743 | 5c1c390f | balrog | s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER], |
4744 | 5c1c390f | balrog | omap_findclk(s, "clk32-kHz"));
|
4745 | 02645926 | balrog | |
4746 | d8f699cb | balrog | s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX], |
4747 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
|
4748 | d8f699cb | balrog | s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX], |
4749 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
|
4750 | d8f699cb | balrog | s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX], |
4751 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
|
4752 | d8f699cb | balrog | |
4753 | 02645926 | balrog | /* Register mappings not currenlty implemented:
|
4754 | 02645926 | balrog | * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
|
4755 | 02645926 | balrog | * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
|
4756 | 02645926 | balrog | * USB W2FC fffb4000 - fffb47ff
|
4757 | 02645926 | balrog | * Camera Interface fffb6800 - fffb6fff
|
4758 | 02645926 | balrog | * USB Host fffba000 - fffba7ff
|
4759 | 02645926 | balrog | * FAC fffba800 - fffbafff
|
4760 | 02645926 | balrog | * HDQ/1-Wire fffbc000 - fffbc7ff
|
4761 | b854bc19 | balrog | * TIPB switches fffbc800 - fffbcfff
|
4762 | 02645926 | balrog | * LED1 fffbd000 - fffbd7ff
|
4763 | 02645926 | balrog | * LED2 fffbd800 - fffbdfff
|
4764 | 02645926 | balrog | * Mailbox fffcf000 - fffcf7ff
|
4765 | 02645926 | balrog | * Local bus IF fffec100 - fffec1ff
|
4766 | 02645926 | balrog | * Local bus MMU fffec200 - fffec2ff
|
4767 | 02645926 | balrog | * DSP MMU fffed200 - fffed2ff
|
4768 | 02645926 | balrog | */
|
4769 | 02645926 | balrog | |
4770 | cf965d24 | balrog | omap_setup_dsp_mapping(omap15xx_dsp_mm); |
4771 | cf965d24 | balrog | |
4772 | c3d2689d | balrog | qemu_register_reset(omap_mpu_reset, s); |
4773 | c3d2689d | balrog | |
4774 | c3d2689d | balrog | return s;
|
4775 | c3d2689d | balrog | } |