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1 | c1713132 | balrog | /*
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2 | c1713132 | balrog | * Intel XScale PXA255/270 processor support.
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3 | c1713132 | balrog | *
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4 | c1713132 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | c1713132 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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6 | c1713132 | balrog | *
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7 | c1713132 | balrog | * This code is licenced under the GPL.
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8 | c1713132 | balrog | */
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9 | c1713132 | balrog | |
10 | c1713132 | balrog | # include "vl.h" |
11 | c1713132 | balrog | |
12 | c1713132 | balrog | static struct { |
13 | c1713132 | balrog | target_phys_addr_t io_base; |
14 | c1713132 | balrog | int irqn;
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15 | c1713132 | balrog | } pxa255_serial[] = { |
16 | c1713132 | balrog | { 0x40100000, PXA2XX_PIC_FFUART },
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17 | c1713132 | balrog | { 0x40200000, PXA2XX_PIC_BTUART },
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18 | c1713132 | balrog | { 0x40700000, PXA2XX_PIC_STUART },
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19 | c1713132 | balrog | { 0x41600000, PXA25X_PIC_HWUART },
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20 | c1713132 | balrog | { 0, 0 } |
21 | c1713132 | balrog | }, pxa270_serial[] = { |
22 | c1713132 | balrog | { 0x40100000, PXA2XX_PIC_FFUART },
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23 | c1713132 | balrog | { 0x40200000, PXA2XX_PIC_BTUART },
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24 | c1713132 | balrog | { 0x40700000, PXA2XX_PIC_STUART },
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25 | c1713132 | balrog | { 0, 0 } |
26 | c1713132 | balrog | }; |
27 | c1713132 | balrog | |
28 | c1713132 | balrog | static struct { |
29 | c1713132 | balrog | target_phys_addr_t io_base; |
30 | c1713132 | balrog | int irqn;
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31 | c1713132 | balrog | } pxa250_ssp[] = { |
32 | c1713132 | balrog | { 0x41000000, PXA2XX_PIC_SSP },
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33 | c1713132 | balrog | { 0, 0 } |
34 | c1713132 | balrog | }, pxa255_ssp[] = { |
35 | c1713132 | balrog | { 0x41000000, PXA2XX_PIC_SSP },
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36 | c1713132 | balrog | { 0x41400000, PXA25X_PIC_NSSP },
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37 | c1713132 | balrog | { 0, 0 } |
38 | c1713132 | balrog | }, pxa26x_ssp[] = { |
39 | c1713132 | balrog | { 0x41000000, PXA2XX_PIC_SSP },
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40 | c1713132 | balrog | { 0x41400000, PXA25X_PIC_NSSP },
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41 | c1713132 | balrog | { 0x41500000, PXA26X_PIC_ASSP },
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42 | c1713132 | balrog | { 0, 0 } |
43 | c1713132 | balrog | }, pxa27x_ssp[] = { |
44 | c1713132 | balrog | { 0x41000000, PXA2XX_PIC_SSP },
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45 | c1713132 | balrog | { 0x41700000, PXA27X_PIC_SSP2 },
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46 | c1713132 | balrog | { 0x41900000, PXA2XX_PIC_SSP3 },
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47 | c1713132 | balrog | { 0, 0 } |
48 | c1713132 | balrog | }; |
49 | c1713132 | balrog | |
50 | c1713132 | balrog | #define PMCR 0x00 /* Power Manager Control register */ |
51 | c1713132 | balrog | #define PSSR 0x04 /* Power Manager Sleep Status register */ |
52 | c1713132 | balrog | #define PSPR 0x08 /* Power Manager Scratch-Pad register */ |
53 | c1713132 | balrog | #define PWER 0x0c /* Power Manager Wake-Up Enable register */ |
54 | c1713132 | balrog | #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ |
55 | c1713132 | balrog | #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ |
56 | c1713132 | balrog | #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ |
57 | c1713132 | balrog | #define PCFR 0x1c /* Power Manager General Configuration register */ |
58 | c1713132 | balrog | #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ |
59 | c1713132 | balrog | #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ |
60 | c1713132 | balrog | #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ |
61 | c1713132 | balrog | #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ |
62 | c1713132 | balrog | #define RCSR 0x30 /* Reset Controller Status register */ |
63 | c1713132 | balrog | #define PSLR 0x34 /* Power Manager Sleep Configuration register */ |
64 | c1713132 | balrog | #define PTSR 0x38 /* Power Manager Standby Configuration register */ |
65 | c1713132 | balrog | #define PVCR 0x40 /* Power Manager Voltage Change Control register */ |
66 | c1713132 | balrog | #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ |
67 | c1713132 | balrog | #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ |
68 | c1713132 | balrog | #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ |
69 | c1713132 | balrog | #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ |
70 | c1713132 | balrog | #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ |
71 | c1713132 | balrog | |
72 | 3f582262 | balrog | static uint32_t pxa2xx_i2c_read(void *, target_phys_addr_t); |
73 | 3f582262 | balrog | static void pxa2xx_i2c_write(void *, target_phys_addr_t, uint32_t); |
74 | 3f582262 | balrog | |
75 | c1713132 | balrog | static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr) |
76 | c1713132 | balrog | { |
77 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
78 | 3f582262 | balrog | if (addr > s->pm_base + PCMD31) {
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79 | 3f582262 | balrog | /* Special case: PWRI2C registers appear in the same range. */
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80 | 3f582262 | balrog | return pxa2xx_i2c_read(s->i2c[1], addr); |
81 | 3f582262 | balrog | } |
82 | c1713132 | balrog | addr -= s->pm_base; |
83 | c1713132 | balrog | |
84 | c1713132 | balrog | switch (addr) {
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85 | c1713132 | balrog | case PMCR ... PCMD31:
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86 | c1713132 | balrog | if (addr & 3) |
87 | c1713132 | balrog | goto fail;
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88 | c1713132 | balrog | |
89 | c1713132 | balrog | return s->pm_regs[addr >> 2]; |
90 | c1713132 | balrog | default:
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91 | c1713132 | balrog | fail:
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92 | c1713132 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
93 | c1713132 | balrog | break;
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94 | c1713132 | balrog | } |
95 | c1713132 | balrog | return 0; |
96 | c1713132 | balrog | } |
97 | c1713132 | balrog | |
98 | c1713132 | balrog | static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr, |
99 | c1713132 | balrog | uint32_t value) |
100 | c1713132 | balrog | { |
101 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
102 | 3f582262 | balrog | if (addr > s->pm_base + PCMD31) {
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103 | 3f582262 | balrog | /* Special case: PWRI2C registers appear in the same range. */
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104 | 3f582262 | balrog | pxa2xx_i2c_write(s->i2c[1], addr, value);
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105 | 3f582262 | balrog | return;
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106 | 3f582262 | balrog | } |
107 | c1713132 | balrog | addr -= s->pm_base; |
108 | c1713132 | balrog | |
109 | c1713132 | balrog | switch (addr) {
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110 | c1713132 | balrog | case PMCR:
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111 | c1713132 | balrog | s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a); |
112 | c1713132 | balrog | s->pm_regs[addr >> 2] |= value & 0x15; |
113 | c1713132 | balrog | break;
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114 | c1713132 | balrog | |
115 | c1713132 | balrog | case PSSR: /* Read-clean registers */ |
116 | c1713132 | balrog | case RCSR:
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117 | c1713132 | balrog | case PKSR:
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118 | c1713132 | balrog | s->pm_regs[addr >> 2] &= ~value;
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119 | c1713132 | balrog | break;
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120 | c1713132 | balrog | |
121 | c1713132 | balrog | default: /* Read-write registers */ |
122 | c1713132 | balrog | if (addr >= PMCR && addr <= PCMD31 && !(addr & 3)) { |
123 | c1713132 | balrog | s->pm_regs[addr >> 2] = value;
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124 | c1713132 | balrog | break;
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125 | c1713132 | balrog | } |
126 | c1713132 | balrog | |
127 | c1713132 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
128 | c1713132 | balrog | break;
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129 | c1713132 | balrog | } |
130 | c1713132 | balrog | } |
131 | c1713132 | balrog | |
132 | c1713132 | balrog | static CPUReadMemoryFunc *pxa2xx_pm_readfn[] = {
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133 | c1713132 | balrog | pxa2xx_pm_read, |
134 | c1713132 | balrog | pxa2xx_pm_read, |
135 | c1713132 | balrog | pxa2xx_pm_read, |
136 | c1713132 | balrog | }; |
137 | c1713132 | balrog | |
138 | c1713132 | balrog | static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = {
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139 | c1713132 | balrog | pxa2xx_pm_write, |
140 | c1713132 | balrog | pxa2xx_pm_write, |
141 | c1713132 | balrog | pxa2xx_pm_write, |
142 | c1713132 | balrog | }; |
143 | c1713132 | balrog | |
144 | c1713132 | balrog | #define CCCR 0x00 /* Core Clock Configuration register */ |
145 | c1713132 | balrog | #define CKEN 0x04 /* Clock Enable register */ |
146 | c1713132 | balrog | #define OSCC 0x08 /* Oscillator Configuration register */ |
147 | c1713132 | balrog | #define CCSR 0x0c /* Core Clock Status register */ |
148 | c1713132 | balrog | |
149 | c1713132 | balrog | static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr) |
150 | c1713132 | balrog | { |
151 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
152 | c1713132 | balrog | addr -= s->cm_base; |
153 | c1713132 | balrog | |
154 | c1713132 | balrog | switch (addr) {
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155 | c1713132 | balrog | case CCCR:
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156 | c1713132 | balrog | case CKEN:
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157 | c1713132 | balrog | case OSCC:
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158 | c1713132 | balrog | return s->cm_regs[addr >> 2]; |
159 | c1713132 | balrog | |
160 | c1713132 | balrog | case CCSR:
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161 | c1713132 | balrog | return s->cm_regs[CCCR >> 2] | (3 << 28); |
162 | c1713132 | balrog | |
163 | c1713132 | balrog | default:
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164 | c1713132 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
165 | c1713132 | balrog | break;
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166 | c1713132 | balrog | } |
167 | c1713132 | balrog | return 0; |
168 | c1713132 | balrog | } |
169 | c1713132 | balrog | |
170 | c1713132 | balrog | static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr, |
171 | c1713132 | balrog | uint32_t value) |
172 | c1713132 | balrog | { |
173 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
174 | c1713132 | balrog | addr -= s->cm_base; |
175 | c1713132 | balrog | |
176 | c1713132 | balrog | switch (addr) {
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177 | c1713132 | balrog | case CCCR:
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178 | c1713132 | balrog | case CKEN:
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179 | c1713132 | balrog | s->cm_regs[addr >> 2] = value;
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180 | c1713132 | balrog | break;
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181 | c1713132 | balrog | |
182 | c1713132 | balrog | case OSCC:
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183 | 565d2895 | balrog | s->cm_regs[addr >> 2] &= ~0x6c; |
184 | c1713132 | balrog | s->cm_regs[addr >> 2] |= value & 0x6e; |
185 | 565d2895 | balrog | if ((value >> 1) & 1) /* OON */ |
186 | 565d2895 | balrog | s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ |
187 | c1713132 | balrog | break;
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188 | c1713132 | balrog | |
189 | c1713132 | balrog | default:
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190 | c1713132 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
191 | c1713132 | balrog | break;
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192 | c1713132 | balrog | } |
193 | c1713132 | balrog | } |
194 | c1713132 | balrog | |
195 | c1713132 | balrog | static CPUReadMemoryFunc *pxa2xx_cm_readfn[] = {
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196 | c1713132 | balrog | pxa2xx_cm_read, |
197 | c1713132 | balrog | pxa2xx_cm_read, |
198 | c1713132 | balrog | pxa2xx_cm_read, |
199 | c1713132 | balrog | }; |
200 | c1713132 | balrog | |
201 | c1713132 | balrog | static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = {
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202 | c1713132 | balrog | pxa2xx_cm_write, |
203 | c1713132 | balrog | pxa2xx_cm_write, |
204 | c1713132 | balrog | pxa2xx_cm_write, |
205 | c1713132 | balrog | }; |
206 | c1713132 | balrog | |
207 | c1713132 | balrog | static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm) |
208 | c1713132 | balrog | { |
209 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
210 | c1713132 | balrog | |
211 | c1713132 | balrog | switch (reg) {
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212 | c1713132 | balrog | case 6: /* Clock Configuration register */ |
213 | c1713132 | balrog | return s->clkcfg;
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214 | c1713132 | balrog | |
215 | c1713132 | balrog | case 7: /* Power Mode register */ |
216 | c1713132 | balrog | return 0; |
217 | c1713132 | balrog | |
218 | c1713132 | balrog | default:
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219 | c1713132 | balrog | printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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220 | c1713132 | balrog | break;
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221 | c1713132 | balrog | } |
222 | c1713132 | balrog | return 0; |
223 | c1713132 | balrog | } |
224 | c1713132 | balrog | |
225 | c1713132 | balrog | static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm, |
226 | c1713132 | balrog | uint32_t value) |
227 | c1713132 | balrog | { |
228 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
229 | c1713132 | balrog | static const char *pwrmode[8] = { |
230 | c1713132 | balrog | "Normal", "Idle", "Deep-idle", "Standby", |
231 | c1713132 | balrog | "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", |
232 | c1713132 | balrog | }; |
233 | c1713132 | balrog | |
234 | c1713132 | balrog | switch (reg) {
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235 | c1713132 | balrog | case 6: /* Clock Configuration register */ |
236 | c1713132 | balrog | s->clkcfg = value & 0xf;
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237 | c1713132 | balrog | if (value & 2) |
238 | c1713132 | balrog | printf("%s: CPU frequency change attempt\n", __FUNCTION__);
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239 | c1713132 | balrog | break;
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240 | c1713132 | balrog | |
241 | c1713132 | balrog | case 7: /* Power Mode register */ |
242 | c1713132 | balrog | if (value & 8) |
243 | c1713132 | balrog | printf("%s: CPU voltage change attempt\n", __FUNCTION__);
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244 | c1713132 | balrog | switch (value & 7) { |
245 | c1713132 | balrog | case 0: |
246 | c1713132 | balrog | /* Do nothing */
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247 | c1713132 | balrog | break;
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248 | c1713132 | balrog | |
249 | c1713132 | balrog | case 1: |
250 | c1713132 | balrog | /* Idle */
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251 | c1713132 | balrog | if (!(s->cm_regs[CCCR] & (1 << 31))) { /* CPDIS */ |
252 | c1713132 | balrog | cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
253 | c1713132 | balrog | break;
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254 | c1713132 | balrog | } |
255 | c1713132 | balrog | /* Fall through. */
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256 | c1713132 | balrog | |
257 | c1713132 | balrog | case 2: |
258 | c1713132 | balrog | /* Deep-Idle */
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259 | c1713132 | balrog | cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
260 | c1713132 | balrog | s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ |
261 | c1713132 | balrog | goto message;
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262 | c1713132 | balrog | |
263 | c1713132 | balrog | case 3: |
264 | a90b7318 | balrog | s->env->uncached_cpsr = |
265 | a90b7318 | balrog | ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; |
266 | c1713132 | balrog | s->env->cp15.c1_sys = 0;
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267 | c1713132 | balrog | s->env->cp15.c1_coproc = 0;
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268 | ce819861 | pbrook | s->env->cp15.c2_base = 0;
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269 | c1713132 | balrog | s->env->cp15.c3 = 0;
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270 | c1713132 | balrog | s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ |
271 | c1713132 | balrog | s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ |
272 | c1713132 | balrog | |
273 | c1713132 | balrog | /*
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274 | c1713132 | balrog | * The scratch-pad register is almost universally used
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275 | c1713132 | balrog | * for storing the return address on suspend. For the
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276 | c1713132 | balrog | * lack of a resuming bootloader, perform a jump
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277 | c1713132 | balrog | * directly to that address.
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278 | c1713132 | balrog | */
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279 | c1713132 | balrog | memset(s->env->regs, 0, 4 * 15); |
280 | c1713132 | balrog | s->env->regs[15] = s->pm_regs[PSPR >> 2]; |
281 | c1713132 | balrog | |
282 | c1713132 | balrog | #if 0
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283 | c1713132 | balrog | buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
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284 | c1713132 | balrog | cpu_physical_memory_write(0, &buffer, 4);
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285 | c1713132 | balrog | buffer = s->pm_regs[PSPR >> 2];
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286 | c1713132 | balrog | cpu_physical_memory_write(8, &buffer, 4);
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287 | c1713132 | balrog | #endif
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288 | c1713132 | balrog | |
289 | c1713132 | balrog | /* Suspend */
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290 | c1713132 | balrog | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
291 | c1713132 | balrog | |
292 | c1713132 | balrog | goto message;
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293 | c1713132 | balrog | |
294 | c1713132 | balrog | default:
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295 | c1713132 | balrog | message:
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296 | c1713132 | balrog | printf("%s: machine entered %s mode\n", __FUNCTION__,
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297 | c1713132 | balrog | pwrmode[value & 7]);
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298 | c1713132 | balrog | } |
299 | c1713132 | balrog | break;
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300 | c1713132 | balrog | |
301 | c1713132 | balrog | default:
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302 | c1713132 | balrog | printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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303 | c1713132 | balrog | break;
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304 | c1713132 | balrog | } |
305 | c1713132 | balrog | } |
306 | c1713132 | balrog | |
307 | c1713132 | balrog | /* Performace Monitoring Registers */
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308 | c1713132 | balrog | #define CPPMNC 0 /* Performance Monitor Control register */ |
309 | c1713132 | balrog | #define CPCCNT 1 /* Clock Counter register */ |
310 | c1713132 | balrog | #define CPINTEN 4 /* Interrupt Enable register */ |
311 | c1713132 | balrog | #define CPFLAG 5 /* Overflow Flag register */ |
312 | c1713132 | balrog | #define CPEVTSEL 8 /* Event Selection register */ |
313 | c1713132 | balrog | |
314 | c1713132 | balrog | #define CPPMN0 0 /* Performance Count register 0 */ |
315 | c1713132 | balrog | #define CPPMN1 1 /* Performance Count register 1 */ |
316 | c1713132 | balrog | #define CPPMN2 2 /* Performance Count register 2 */ |
317 | c1713132 | balrog | #define CPPMN3 3 /* Performance Count register 3 */ |
318 | c1713132 | balrog | |
319 | c1713132 | balrog | static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm) |
320 | c1713132 | balrog | { |
321 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
322 | c1713132 | balrog | |
323 | c1713132 | balrog | switch (reg) {
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324 | c1713132 | balrog | case CPPMNC:
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325 | c1713132 | balrog | return s->pmnc;
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326 | c1713132 | balrog | case CPCCNT:
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327 | c1713132 | balrog | if (s->pmnc & 1) |
328 | c1713132 | balrog | return qemu_get_clock(vm_clock);
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329 | c1713132 | balrog | else
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330 | c1713132 | balrog | return 0; |
331 | c1713132 | balrog | case CPINTEN:
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332 | c1713132 | balrog | case CPFLAG:
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333 | c1713132 | balrog | case CPEVTSEL:
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334 | c1713132 | balrog | return 0; |
335 | c1713132 | balrog | |
336 | c1713132 | balrog | default:
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337 | c1713132 | balrog | printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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338 | c1713132 | balrog | break;
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339 | c1713132 | balrog | } |
340 | c1713132 | balrog | return 0; |
341 | c1713132 | balrog | } |
342 | c1713132 | balrog | |
343 | c1713132 | balrog | static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm, |
344 | c1713132 | balrog | uint32_t value) |
345 | c1713132 | balrog | { |
346 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
347 | c1713132 | balrog | |
348 | c1713132 | balrog | switch (reg) {
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349 | c1713132 | balrog | case CPPMNC:
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350 | c1713132 | balrog | s->pmnc = value; |
351 | c1713132 | balrog | break;
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352 | c1713132 | balrog | |
353 | c1713132 | balrog | case CPCCNT:
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354 | c1713132 | balrog | case CPINTEN:
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355 | c1713132 | balrog | case CPFLAG:
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356 | c1713132 | balrog | case CPEVTSEL:
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357 | c1713132 | balrog | break;
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358 | c1713132 | balrog | |
359 | c1713132 | balrog | default:
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360 | c1713132 | balrog | printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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361 | c1713132 | balrog | break;
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362 | c1713132 | balrog | } |
363 | c1713132 | balrog | } |
364 | c1713132 | balrog | |
365 | c1713132 | balrog | static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm) |
366 | c1713132 | balrog | { |
367 | c1713132 | balrog | switch (crm) {
|
368 | c1713132 | balrog | case 0: |
369 | c1713132 | balrog | return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
|
370 | c1713132 | balrog | case 1: |
371 | c1713132 | balrog | return pxa2xx_perf_read(opaque, op2, reg, crm);
|
372 | c1713132 | balrog | case 2: |
373 | c1713132 | balrog | switch (reg) {
|
374 | c1713132 | balrog | case CPPMN0:
|
375 | c1713132 | balrog | case CPPMN1:
|
376 | c1713132 | balrog | case CPPMN2:
|
377 | c1713132 | balrog | case CPPMN3:
|
378 | c1713132 | balrog | return 0; |
379 | c1713132 | balrog | } |
380 | c1713132 | balrog | /* Fall through */
|
381 | c1713132 | balrog | default:
|
382 | c1713132 | balrog | printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
|
383 | c1713132 | balrog | break;
|
384 | c1713132 | balrog | } |
385 | c1713132 | balrog | return 0; |
386 | c1713132 | balrog | } |
387 | c1713132 | balrog | |
388 | c1713132 | balrog | static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm, |
389 | c1713132 | balrog | uint32_t value) |
390 | c1713132 | balrog | { |
391 | c1713132 | balrog | switch (crm) {
|
392 | c1713132 | balrog | case 0: |
393 | c1713132 | balrog | pxa2xx_clkpwr_write(opaque, op2, reg, crm, value); |
394 | c1713132 | balrog | break;
|
395 | c1713132 | balrog | case 1: |
396 | c1713132 | balrog | pxa2xx_perf_write(opaque, op2, reg, crm, value); |
397 | c1713132 | balrog | break;
|
398 | c1713132 | balrog | case 2: |
399 | c1713132 | balrog | switch (reg) {
|
400 | c1713132 | balrog | case CPPMN0:
|
401 | c1713132 | balrog | case CPPMN1:
|
402 | c1713132 | balrog | case CPPMN2:
|
403 | c1713132 | balrog | case CPPMN3:
|
404 | c1713132 | balrog | return;
|
405 | c1713132 | balrog | } |
406 | c1713132 | balrog | /* Fall through */
|
407 | c1713132 | balrog | default:
|
408 | c1713132 | balrog | printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
|
409 | c1713132 | balrog | break;
|
410 | c1713132 | balrog | } |
411 | c1713132 | balrog | } |
412 | c1713132 | balrog | |
413 | c1713132 | balrog | #define MDCNFG 0x00 /* SDRAM Configuration register */ |
414 | c1713132 | balrog | #define MDREFR 0x04 /* SDRAM Refresh Control register */ |
415 | c1713132 | balrog | #define MSC0 0x08 /* Static Memory Control register 0 */ |
416 | c1713132 | balrog | #define MSC1 0x0c /* Static Memory Control register 1 */ |
417 | c1713132 | balrog | #define MSC2 0x10 /* Static Memory Control register 2 */ |
418 | c1713132 | balrog | #define MECR 0x14 /* Expansion Memory Bus Config register */ |
419 | c1713132 | balrog | #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ |
420 | c1713132 | balrog | #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ |
421 | c1713132 | balrog | #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ |
422 | c1713132 | balrog | #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ |
423 | c1713132 | balrog | #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ |
424 | c1713132 | balrog | #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ |
425 | c1713132 | balrog | #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ |
426 | c1713132 | balrog | #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ |
427 | c1713132 | balrog | #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ |
428 | c1713132 | balrog | #define ARB_CNTL 0x48 /* Arbiter Control register */ |
429 | c1713132 | balrog | #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ |
430 | c1713132 | balrog | #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ |
431 | c1713132 | balrog | #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ |
432 | c1713132 | balrog | #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ |
433 | c1713132 | balrog | #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ |
434 | c1713132 | balrog | #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ |
435 | c1713132 | balrog | #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ |
436 | c1713132 | balrog | |
437 | c1713132 | balrog | static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr) |
438 | c1713132 | balrog | { |
439 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
440 | c1713132 | balrog | addr -= s->mm_base; |
441 | c1713132 | balrog | |
442 | c1713132 | balrog | switch (addr) {
|
443 | c1713132 | balrog | case MDCNFG ... SA1110:
|
444 | c1713132 | balrog | if ((addr & 3) == 0) |
445 | c1713132 | balrog | return s->mm_regs[addr >> 2]; |
446 | c1713132 | balrog | |
447 | c1713132 | balrog | default:
|
448 | c1713132 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
449 | c1713132 | balrog | break;
|
450 | c1713132 | balrog | } |
451 | c1713132 | balrog | return 0; |
452 | c1713132 | balrog | } |
453 | c1713132 | balrog | |
454 | c1713132 | balrog | static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr, |
455 | c1713132 | balrog | uint32_t value) |
456 | c1713132 | balrog | { |
457 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
458 | c1713132 | balrog | addr -= s->mm_base; |
459 | c1713132 | balrog | |
460 | c1713132 | balrog | switch (addr) {
|
461 | c1713132 | balrog | case MDCNFG ... SA1110:
|
462 | c1713132 | balrog | if ((addr & 3) == 0) { |
463 | c1713132 | balrog | s->mm_regs[addr >> 2] = value;
|
464 | c1713132 | balrog | break;
|
465 | c1713132 | balrog | } |
466 | c1713132 | balrog | |
467 | c1713132 | balrog | default:
|
468 | c1713132 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
469 | c1713132 | balrog | break;
|
470 | c1713132 | balrog | } |
471 | c1713132 | balrog | } |
472 | c1713132 | balrog | |
473 | c1713132 | balrog | static CPUReadMemoryFunc *pxa2xx_mm_readfn[] = {
|
474 | c1713132 | balrog | pxa2xx_mm_read, |
475 | c1713132 | balrog | pxa2xx_mm_read, |
476 | c1713132 | balrog | pxa2xx_mm_read, |
477 | c1713132 | balrog | }; |
478 | c1713132 | balrog | |
479 | c1713132 | balrog | static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = {
|
480 | c1713132 | balrog | pxa2xx_mm_write, |
481 | c1713132 | balrog | pxa2xx_mm_write, |
482 | c1713132 | balrog | pxa2xx_mm_write, |
483 | c1713132 | balrog | }; |
484 | c1713132 | balrog | |
485 | c1713132 | balrog | /* Synchronous Serial Ports */
|
486 | c1713132 | balrog | struct pxa2xx_ssp_s {
|
487 | c1713132 | balrog | target_phys_addr_t base; |
488 | c1713132 | balrog | qemu_irq irq; |
489 | c1713132 | balrog | int enable;
|
490 | c1713132 | balrog | |
491 | c1713132 | balrog | uint32_t sscr[2];
|
492 | c1713132 | balrog | uint32_t sspsp; |
493 | c1713132 | balrog | uint32_t ssto; |
494 | c1713132 | balrog | uint32_t ssitr; |
495 | c1713132 | balrog | uint32_t sssr; |
496 | c1713132 | balrog | uint8_t sstsa; |
497 | c1713132 | balrog | uint8_t ssrsa; |
498 | c1713132 | balrog | uint8_t ssacd; |
499 | c1713132 | balrog | |
500 | c1713132 | balrog | uint32_t rx_fifo[16];
|
501 | c1713132 | balrog | int rx_level;
|
502 | c1713132 | balrog | int rx_start;
|
503 | c1713132 | balrog | |
504 | c1713132 | balrog | uint32_t (*readfn)(void *opaque);
|
505 | c1713132 | balrog | void (*writefn)(void *opaque, uint32_t value); |
506 | c1713132 | balrog | void *opaque;
|
507 | c1713132 | balrog | }; |
508 | c1713132 | balrog | |
509 | c1713132 | balrog | #define SSCR0 0x00 /* SSP Control register 0 */ |
510 | c1713132 | balrog | #define SSCR1 0x04 /* SSP Control register 1 */ |
511 | c1713132 | balrog | #define SSSR 0x08 /* SSP Status register */ |
512 | c1713132 | balrog | #define SSITR 0x0c /* SSP Interrupt Test register */ |
513 | c1713132 | balrog | #define SSDR 0x10 /* SSP Data register */ |
514 | c1713132 | balrog | #define SSTO 0x28 /* SSP Time-Out register */ |
515 | c1713132 | balrog | #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ |
516 | c1713132 | balrog | #define SSTSA 0x30 /* SSP TX Time Slot Active register */ |
517 | c1713132 | balrog | #define SSRSA 0x34 /* SSP RX Time Slot Active register */ |
518 | c1713132 | balrog | #define SSTSS 0x38 /* SSP Time Slot Status register */ |
519 | c1713132 | balrog | #define SSACD 0x3c /* SSP Audio Clock Divider register */ |
520 | c1713132 | balrog | |
521 | c1713132 | balrog | /* Bitfields for above registers */
|
522 | c1713132 | balrog | #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) |
523 | c1713132 | balrog | #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) |
524 | c1713132 | balrog | #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) |
525 | c1713132 | balrog | #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) |
526 | c1713132 | balrog | #define SSCR0_SSE (1 << 7) |
527 | c1713132 | balrog | #define SSCR0_RIM (1 << 22) |
528 | c1713132 | balrog | #define SSCR0_TIM (1 << 23) |
529 | c1713132 | balrog | #define SSCR0_MOD (1 << 31) |
530 | c1713132 | balrog | #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) |
531 | c1713132 | balrog | #define SSCR1_RIE (1 << 0) |
532 | c1713132 | balrog | #define SSCR1_TIE (1 << 1) |
533 | c1713132 | balrog | #define SSCR1_LBM (1 << 2) |
534 | c1713132 | balrog | #define SSCR1_MWDS (1 << 5) |
535 | c1713132 | balrog | #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) |
536 | c1713132 | balrog | #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) |
537 | c1713132 | balrog | #define SSCR1_EFWR (1 << 14) |
538 | c1713132 | balrog | #define SSCR1_PINTE (1 << 18) |
539 | c1713132 | balrog | #define SSCR1_TINTE (1 << 19) |
540 | c1713132 | balrog | #define SSCR1_RSRE (1 << 20) |
541 | c1713132 | balrog | #define SSCR1_TSRE (1 << 21) |
542 | c1713132 | balrog | #define SSCR1_EBCEI (1 << 29) |
543 | c1713132 | balrog | #define SSITR_INT (7 << 5) |
544 | c1713132 | balrog | #define SSSR_TNF (1 << 2) |
545 | c1713132 | balrog | #define SSSR_RNE (1 << 3) |
546 | c1713132 | balrog | #define SSSR_TFS (1 << 5) |
547 | c1713132 | balrog | #define SSSR_RFS (1 << 6) |
548 | c1713132 | balrog | #define SSSR_ROR (1 << 7) |
549 | c1713132 | balrog | #define SSSR_PINT (1 << 18) |
550 | c1713132 | balrog | #define SSSR_TINT (1 << 19) |
551 | c1713132 | balrog | #define SSSR_EOC (1 << 20) |
552 | c1713132 | balrog | #define SSSR_TUR (1 << 21) |
553 | c1713132 | balrog | #define SSSR_BCE (1 << 23) |
554 | c1713132 | balrog | #define SSSR_RW 0x00bc0080 |
555 | c1713132 | balrog | |
556 | c1713132 | balrog | static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s) |
557 | c1713132 | balrog | { |
558 | c1713132 | balrog | int level = 0; |
559 | c1713132 | balrog | |
560 | c1713132 | balrog | level |= s->ssitr & SSITR_INT; |
561 | c1713132 | balrog | level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
|
562 | c1713132 | balrog | level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
|
563 | c1713132 | balrog | level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); |
564 | c1713132 | balrog | level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
|
565 | c1713132 | balrog | level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
|
566 | c1713132 | balrog | level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
|
567 | c1713132 | balrog | level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
|
568 | c1713132 | balrog | level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
|
569 | c1713132 | balrog | qemu_set_irq(s->irq, !!level); |
570 | c1713132 | balrog | } |
571 | c1713132 | balrog | |
572 | c1713132 | balrog | static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s) |
573 | c1713132 | balrog | { |
574 | c1713132 | balrog | s->sssr &= ~(0xf << 12); /* Clear RFL */ |
575 | c1713132 | balrog | s->sssr &= ~(0xf << 8); /* Clear TFL */ |
576 | c1713132 | balrog | s->sssr &= ~SSSR_TNF; |
577 | c1713132 | balrog | if (s->enable) {
|
578 | c1713132 | balrog | s->sssr |= ((s->rx_level - 1) & 0xf) << 12; |
579 | c1713132 | balrog | if (s->rx_level >= SSCR1_RFT(s->sscr[1])) |
580 | c1713132 | balrog | s->sssr |= SSSR_RFS; |
581 | c1713132 | balrog | else
|
582 | c1713132 | balrog | s->sssr &= ~SSSR_RFS; |
583 | c1713132 | balrog | if (0 <= SSCR1_TFT(s->sscr[1])) |
584 | c1713132 | balrog | s->sssr |= SSSR_TFS; |
585 | c1713132 | balrog | else
|
586 | c1713132 | balrog | s->sssr &= ~SSSR_TFS; |
587 | c1713132 | balrog | if (s->rx_level)
|
588 | c1713132 | balrog | s->sssr |= SSSR_RNE; |
589 | c1713132 | balrog | else
|
590 | c1713132 | balrog | s->sssr &= ~SSSR_RNE; |
591 | c1713132 | balrog | s->sssr |= SSSR_TNF; |
592 | c1713132 | balrog | } |
593 | c1713132 | balrog | |
594 | c1713132 | balrog | pxa2xx_ssp_int_update(s); |
595 | c1713132 | balrog | } |
596 | c1713132 | balrog | |
597 | c1713132 | balrog | static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr) |
598 | c1713132 | balrog | { |
599 | c1713132 | balrog | struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque; |
600 | c1713132 | balrog | uint32_t retval; |
601 | c1713132 | balrog | addr -= s->base; |
602 | c1713132 | balrog | |
603 | c1713132 | balrog | switch (addr) {
|
604 | c1713132 | balrog | case SSCR0:
|
605 | c1713132 | balrog | return s->sscr[0]; |
606 | c1713132 | balrog | case SSCR1:
|
607 | c1713132 | balrog | return s->sscr[1]; |
608 | c1713132 | balrog | case SSPSP:
|
609 | c1713132 | balrog | return s->sspsp;
|
610 | c1713132 | balrog | case SSTO:
|
611 | c1713132 | balrog | return s->ssto;
|
612 | c1713132 | balrog | case SSITR:
|
613 | c1713132 | balrog | return s->ssitr;
|
614 | c1713132 | balrog | case SSSR:
|
615 | c1713132 | balrog | return s->sssr | s->ssitr;
|
616 | c1713132 | balrog | case SSDR:
|
617 | c1713132 | balrog | if (!s->enable)
|
618 | c1713132 | balrog | return 0xffffffff; |
619 | c1713132 | balrog | if (s->rx_level < 1) { |
620 | c1713132 | balrog | printf("%s: SSP Rx Underrun\n", __FUNCTION__);
|
621 | c1713132 | balrog | return 0xffffffff; |
622 | c1713132 | balrog | } |
623 | c1713132 | balrog | s->rx_level --; |
624 | c1713132 | balrog | retval = s->rx_fifo[s->rx_start ++]; |
625 | c1713132 | balrog | s->rx_start &= 0xf;
|
626 | c1713132 | balrog | pxa2xx_ssp_fifo_update(s); |
627 | c1713132 | balrog | return retval;
|
628 | c1713132 | balrog | case SSTSA:
|
629 | c1713132 | balrog | return s->sstsa;
|
630 | c1713132 | balrog | case SSRSA:
|
631 | c1713132 | balrog | return s->ssrsa;
|
632 | c1713132 | balrog | case SSTSS:
|
633 | c1713132 | balrog | return 0; |
634 | c1713132 | balrog | case SSACD:
|
635 | c1713132 | balrog | return s->ssacd;
|
636 | c1713132 | balrog | default:
|
637 | c1713132 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
638 | c1713132 | balrog | break;
|
639 | c1713132 | balrog | } |
640 | c1713132 | balrog | return 0; |
641 | c1713132 | balrog | } |
642 | c1713132 | balrog | |
643 | c1713132 | balrog | static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr, |
644 | c1713132 | balrog | uint32_t value) |
645 | c1713132 | balrog | { |
646 | c1713132 | balrog | struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque; |
647 | c1713132 | balrog | addr -= s->base; |
648 | c1713132 | balrog | |
649 | c1713132 | balrog | switch (addr) {
|
650 | c1713132 | balrog | case SSCR0:
|
651 | c1713132 | balrog | s->sscr[0] = value & 0xc7ffffff; |
652 | c1713132 | balrog | s->enable = value & SSCR0_SSE; |
653 | c1713132 | balrog | if (value & SSCR0_MOD)
|
654 | c1713132 | balrog | printf("%s: Attempt to use network mode\n", __FUNCTION__);
|
655 | c1713132 | balrog | if (s->enable && SSCR0_DSS(value) < 4) |
656 | c1713132 | balrog | printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
|
657 | c1713132 | balrog | SSCR0_DSS(value)); |
658 | c1713132 | balrog | if (!(value & SSCR0_SSE)) {
|
659 | c1713132 | balrog | s->sssr = 0;
|
660 | c1713132 | balrog | s->ssitr = 0;
|
661 | c1713132 | balrog | s->rx_level = 0;
|
662 | c1713132 | balrog | } |
663 | c1713132 | balrog | pxa2xx_ssp_fifo_update(s); |
664 | c1713132 | balrog | break;
|
665 | c1713132 | balrog | |
666 | c1713132 | balrog | case SSCR1:
|
667 | c1713132 | balrog | s->sscr[1] = value;
|
668 | c1713132 | balrog | if (value & (SSCR1_LBM | SSCR1_EFWR))
|
669 | c1713132 | balrog | printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
|
670 | c1713132 | balrog | pxa2xx_ssp_fifo_update(s); |
671 | c1713132 | balrog | break;
|
672 | c1713132 | balrog | |
673 | c1713132 | balrog | case SSPSP:
|
674 | c1713132 | balrog | s->sspsp = value; |
675 | c1713132 | balrog | break;
|
676 | c1713132 | balrog | |
677 | c1713132 | balrog | case SSTO:
|
678 | c1713132 | balrog | s->ssto = value; |
679 | c1713132 | balrog | break;
|
680 | c1713132 | balrog | |
681 | c1713132 | balrog | case SSITR:
|
682 | c1713132 | balrog | s->ssitr = value & SSITR_INT; |
683 | c1713132 | balrog | pxa2xx_ssp_int_update(s); |
684 | c1713132 | balrog | break;
|
685 | c1713132 | balrog | |
686 | c1713132 | balrog | case SSSR:
|
687 | c1713132 | balrog | s->sssr &= ~(value & SSSR_RW); |
688 | c1713132 | balrog | pxa2xx_ssp_int_update(s); |
689 | c1713132 | balrog | break;
|
690 | c1713132 | balrog | |
691 | c1713132 | balrog | case SSDR:
|
692 | c1713132 | balrog | if (SSCR0_UWIRE(s->sscr[0])) { |
693 | c1713132 | balrog | if (s->sscr[1] & SSCR1_MWDS) |
694 | c1713132 | balrog | value &= 0xffff;
|
695 | c1713132 | balrog | else
|
696 | c1713132 | balrog | value &= 0xff;
|
697 | c1713132 | balrog | } else
|
698 | c1713132 | balrog | /* Note how 32bits overflow does no harm here */
|
699 | c1713132 | balrog | value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; |
700 | c1713132 | balrog | |
701 | c1713132 | balrog | /* Data goes from here to the Tx FIFO and is shifted out from
|
702 | c1713132 | balrog | * there directly to the slave, no need to buffer it.
|
703 | c1713132 | balrog | */
|
704 | c1713132 | balrog | if (s->enable) {
|
705 | c1713132 | balrog | if (s->writefn)
|
706 | c1713132 | balrog | s->writefn(s->opaque, value); |
707 | c1713132 | balrog | |
708 | c1713132 | balrog | if (s->rx_level < 0x10) { |
709 | c1713132 | balrog | if (s->readfn)
|
710 | c1713132 | balrog | s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] =
|
711 | c1713132 | balrog | s->readfn(s->opaque); |
712 | c1713132 | balrog | else
|
713 | c1713132 | balrog | s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = 0x0; |
714 | c1713132 | balrog | } else
|
715 | c1713132 | balrog | s->sssr |= SSSR_ROR; |
716 | c1713132 | balrog | } |
717 | c1713132 | balrog | pxa2xx_ssp_fifo_update(s); |
718 | c1713132 | balrog | break;
|
719 | c1713132 | balrog | |
720 | c1713132 | balrog | case SSTSA:
|
721 | c1713132 | balrog | s->sstsa = value; |
722 | c1713132 | balrog | break;
|
723 | c1713132 | balrog | |
724 | c1713132 | balrog | case SSRSA:
|
725 | c1713132 | balrog | s->ssrsa = value; |
726 | c1713132 | balrog | break;
|
727 | c1713132 | balrog | |
728 | c1713132 | balrog | case SSACD:
|
729 | c1713132 | balrog | s->ssacd = value; |
730 | c1713132 | balrog | break;
|
731 | c1713132 | balrog | |
732 | c1713132 | balrog | default:
|
733 | c1713132 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
734 | c1713132 | balrog | break;
|
735 | c1713132 | balrog | } |
736 | c1713132 | balrog | } |
737 | c1713132 | balrog | |
738 | c1713132 | balrog | void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port, |
739 | c1713132 | balrog | uint32_t (*readfn)(void *opaque),
|
740 | c1713132 | balrog | void (*writefn)(void *opaque, uint32_t value), void *opaque) |
741 | c1713132 | balrog | { |
742 | c1713132 | balrog | if (!port) {
|
743 | c1713132 | balrog | printf("%s: no such SSP\n", __FUNCTION__);
|
744 | c1713132 | balrog | exit(-1);
|
745 | c1713132 | balrog | } |
746 | c1713132 | balrog | |
747 | c1713132 | balrog | port->opaque = opaque; |
748 | c1713132 | balrog | port->readfn = readfn; |
749 | c1713132 | balrog | port->writefn = writefn; |
750 | c1713132 | balrog | } |
751 | c1713132 | balrog | |
752 | c1713132 | balrog | static CPUReadMemoryFunc *pxa2xx_ssp_readfn[] = {
|
753 | c1713132 | balrog | pxa2xx_ssp_read, |
754 | c1713132 | balrog | pxa2xx_ssp_read, |
755 | c1713132 | balrog | pxa2xx_ssp_read, |
756 | c1713132 | balrog | }; |
757 | c1713132 | balrog | |
758 | c1713132 | balrog | static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = {
|
759 | c1713132 | balrog | pxa2xx_ssp_write, |
760 | c1713132 | balrog | pxa2xx_ssp_write, |
761 | c1713132 | balrog | pxa2xx_ssp_write, |
762 | c1713132 | balrog | }; |
763 | c1713132 | balrog | |
764 | c1713132 | balrog | /* Real-Time Clock */
|
765 | c1713132 | balrog | #define RCNR 0x00 /* RTC Counter register */ |
766 | c1713132 | balrog | #define RTAR 0x04 /* RTC Alarm register */ |
767 | c1713132 | balrog | #define RTSR 0x08 /* RTC Status register */ |
768 | c1713132 | balrog | #define RTTR 0x0c /* RTC Timer Trim register */ |
769 | c1713132 | balrog | #define RDCR 0x10 /* RTC Day Counter register */ |
770 | c1713132 | balrog | #define RYCR 0x14 /* RTC Year Counter register */ |
771 | c1713132 | balrog | #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ |
772 | c1713132 | balrog | #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ |
773 | c1713132 | balrog | #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ |
774 | c1713132 | balrog | #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ |
775 | c1713132 | balrog | #define SWCR 0x28 /* RTC Stopwatch Counter register */ |
776 | c1713132 | balrog | #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ |
777 | c1713132 | balrog | #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ |
778 | c1713132 | balrog | #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ |
779 | c1713132 | balrog | #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ |
780 | c1713132 | balrog | |
781 | c1713132 | balrog | static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s *s) |
782 | c1713132 | balrog | { |
783 | c1713132 | balrog | qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
|
784 | c1713132 | balrog | } |
785 | c1713132 | balrog | |
786 | c1713132 | balrog | static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s) |
787 | c1713132 | balrog | { |
788 | c1713132 | balrog | int64_t rt = qemu_get_clock(rt_clock); |
789 | c1713132 | balrog | s->last_rcnr += ((rt - s->last_hz) << 15) /
|
790 | c1713132 | balrog | (1000 * ((s->rttr & 0xffff) + 1)); |
791 | c1713132 | balrog | s->last_rdcr += ((rt - s->last_hz) << 15) /
|
792 | c1713132 | balrog | (1000 * ((s->rttr & 0xffff) + 1)); |
793 | c1713132 | balrog | s->last_hz = rt; |
794 | c1713132 | balrog | } |
795 | c1713132 | balrog | |
796 | c1713132 | balrog | static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s) |
797 | c1713132 | balrog | { |
798 | c1713132 | balrog | int64_t rt = qemu_get_clock(rt_clock); |
799 | c1713132 | balrog | if (s->rtsr & (1 << 12)) |
800 | c1713132 | balrog | s->last_swcr += (rt - s->last_sw) / 10;
|
801 | c1713132 | balrog | s->last_sw = rt; |
802 | c1713132 | balrog | } |
803 | c1713132 | balrog | |
804 | c1713132 | balrog | static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s) |
805 | c1713132 | balrog | { |
806 | c1713132 | balrog | int64_t rt = qemu_get_clock(rt_clock); |
807 | c1713132 | balrog | if (s->rtsr & (1 << 15)) |
808 | c1713132 | balrog | s->last_swcr += rt - s->last_pi; |
809 | c1713132 | balrog | s->last_pi = rt; |
810 | c1713132 | balrog | } |
811 | c1713132 | balrog | |
812 | c1713132 | balrog | static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s, |
813 | c1713132 | balrog | uint32_t rtsr) |
814 | c1713132 | balrog | { |
815 | c1713132 | balrog | if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) |
816 | c1713132 | balrog | qemu_mod_timer(s->rtc_hz, s->last_hz + |
817 | c1713132 | balrog | (((s->rtar - s->last_rcnr) * 1000 *
|
818 | c1713132 | balrog | ((s->rttr & 0xffff) + 1)) >> 15)); |
819 | c1713132 | balrog | else
|
820 | c1713132 | balrog | qemu_del_timer(s->rtc_hz); |
821 | c1713132 | balrog | |
822 | c1713132 | balrog | if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) |
823 | c1713132 | balrog | qemu_mod_timer(s->rtc_rdal1, s->last_hz + |
824 | c1713132 | balrog | (((s->rdar1 - s->last_rdcr) * 1000 *
|
825 | c1713132 | balrog | ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ |
826 | c1713132 | balrog | else
|
827 | c1713132 | balrog | qemu_del_timer(s->rtc_rdal1); |
828 | c1713132 | balrog | |
829 | c1713132 | balrog | if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) |
830 | c1713132 | balrog | qemu_mod_timer(s->rtc_rdal2, s->last_hz + |
831 | c1713132 | balrog | (((s->rdar2 - s->last_rdcr) * 1000 *
|
832 | c1713132 | balrog | ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ |
833 | c1713132 | balrog | else
|
834 | c1713132 | balrog | qemu_del_timer(s->rtc_rdal2); |
835 | c1713132 | balrog | |
836 | c1713132 | balrog | if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) |
837 | c1713132 | balrog | qemu_mod_timer(s->rtc_swal1, s->last_sw + |
838 | c1713132 | balrog | (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ |
839 | c1713132 | balrog | else
|
840 | c1713132 | balrog | qemu_del_timer(s->rtc_swal1); |
841 | c1713132 | balrog | |
842 | c1713132 | balrog | if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) |
843 | c1713132 | balrog | qemu_mod_timer(s->rtc_swal2, s->last_sw + |
844 | c1713132 | balrog | (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ |
845 | c1713132 | balrog | else
|
846 | c1713132 | balrog | qemu_del_timer(s->rtc_swal2); |
847 | c1713132 | balrog | |
848 | c1713132 | balrog | if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) |
849 | c1713132 | balrog | qemu_mod_timer(s->rtc_pi, s->last_pi + |
850 | c1713132 | balrog | (s->piar & 0xffff) - s->last_rtcpicr);
|
851 | c1713132 | balrog | else
|
852 | c1713132 | balrog | qemu_del_timer(s->rtc_pi); |
853 | c1713132 | balrog | } |
854 | c1713132 | balrog | |
855 | c1713132 | balrog | static inline void pxa2xx_rtc_hz_tick(void *opaque) |
856 | c1713132 | balrog | { |
857 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
858 | c1713132 | balrog | s->rtsr |= (1 << 0); |
859 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
860 | c1713132 | balrog | pxa2xx_rtc_int_update(s); |
861 | c1713132 | balrog | } |
862 | c1713132 | balrog | |
863 | c1713132 | balrog | static inline void pxa2xx_rtc_rdal1_tick(void *opaque) |
864 | c1713132 | balrog | { |
865 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
866 | c1713132 | balrog | s->rtsr |= (1 << 4); |
867 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
868 | c1713132 | balrog | pxa2xx_rtc_int_update(s); |
869 | c1713132 | balrog | } |
870 | c1713132 | balrog | |
871 | c1713132 | balrog | static inline void pxa2xx_rtc_rdal2_tick(void *opaque) |
872 | c1713132 | balrog | { |
873 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
874 | c1713132 | balrog | s->rtsr |= (1 << 6); |
875 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
876 | c1713132 | balrog | pxa2xx_rtc_int_update(s); |
877 | c1713132 | balrog | } |
878 | c1713132 | balrog | |
879 | c1713132 | balrog | static inline void pxa2xx_rtc_swal1_tick(void *opaque) |
880 | c1713132 | balrog | { |
881 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
882 | c1713132 | balrog | s->rtsr |= (1 << 8); |
883 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
884 | c1713132 | balrog | pxa2xx_rtc_int_update(s); |
885 | c1713132 | balrog | } |
886 | c1713132 | balrog | |
887 | c1713132 | balrog | static inline void pxa2xx_rtc_swal2_tick(void *opaque) |
888 | c1713132 | balrog | { |
889 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
890 | c1713132 | balrog | s->rtsr |= (1 << 10); |
891 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
892 | c1713132 | balrog | pxa2xx_rtc_int_update(s); |
893 | c1713132 | balrog | } |
894 | c1713132 | balrog | |
895 | c1713132 | balrog | static inline void pxa2xx_rtc_pi_tick(void *opaque) |
896 | c1713132 | balrog | { |
897 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
898 | c1713132 | balrog | s->rtsr |= (1 << 13); |
899 | c1713132 | balrog | pxa2xx_rtc_piupdate(s); |
900 | c1713132 | balrog | s->last_rtcpicr = 0;
|
901 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
902 | c1713132 | balrog | pxa2xx_rtc_int_update(s); |
903 | c1713132 | balrog | } |
904 | c1713132 | balrog | |
905 | c1713132 | balrog | static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr) |
906 | c1713132 | balrog | { |
907 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
908 | c1713132 | balrog | addr -= s->rtc_base; |
909 | c1713132 | balrog | |
910 | c1713132 | balrog | switch (addr) {
|
911 | c1713132 | balrog | case RTTR:
|
912 | c1713132 | balrog | return s->rttr;
|
913 | c1713132 | balrog | case RTSR:
|
914 | c1713132 | balrog | return s->rtsr;
|
915 | c1713132 | balrog | case RTAR:
|
916 | c1713132 | balrog | return s->rtar;
|
917 | c1713132 | balrog | case RDAR1:
|
918 | c1713132 | balrog | return s->rdar1;
|
919 | c1713132 | balrog | case RDAR2:
|
920 | c1713132 | balrog | return s->rdar2;
|
921 | c1713132 | balrog | case RYAR1:
|
922 | c1713132 | balrog | return s->ryar1;
|
923 | c1713132 | balrog | case RYAR2:
|
924 | c1713132 | balrog | return s->ryar2;
|
925 | c1713132 | balrog | case SWAR1:
|
926 | c1713132 | balrog | return s->swar1;
|
927 | c1713132 | balrog | case SWAR2:
|
928 | c1713132 | balrog | return s->swar2;
|
929 | c1713132 | balrog | case PIAR:
|
930 | c1713132 | balrog | return s->piar;
|
931 | c1713132 | balrog | case RCNR:
|
932 | c1713132 | balrog | return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) / |
933 | c1713132 | balrog | (1000 * ((s->rttr & 0xffff) + 1)); |
934 | c1713132 | balrog | case RDCR:
|
935 | c1713132 | balrog | return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) / |
936 | c1713132 | balrog | (1000 * ((s->rttr & 0xffff) + 1)); |
937 | c1713132 | balrog | case RYCR:
|
938 | c1713132 | balrog | return s->last_rycr;
|
939 | c1713132 | balrog | case SWCR:
|
940 | c1713132 | balrog | if (s->rtsr & (1 << 12)) |
941 | c1713132 | balrog | return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10; |
942 | c1713132 | balrog | else
|
943 | c1713132 | balrog | return s->last_swcr;
|
944 | c1713132 | balrog | default:
|
945 | c1713132 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
946 | c1713132 | balrog | break;
|
947 | c1713132 | balrog | } |
948 | c1713132 | balrog | return 0; |
949 | c1713132 | balrog | } |
950 | c1713132 | balrog | |
951 | c1713132 | balrog | static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr, |
952 | c1713132 | balrog | uint32_t value) |
953 | c1713132 | balrog | { |
954 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
955 | c1713132 | balrog | addr -= s->rtc_base; |
956 | c1713132 | balrog | |
957 | c1713132 | balrog | switch (addr) {
|
958 | c1713132 | balrog | case RTTR:
|
959 | c1713132 | balrog | if (!(s->rttr & (1 << 31))) { |
960 | c1713132 | balrog | pxa2xx_rtc_hzupdate(s); |
961 | c1713132 | balrog | s->rttr = value; |
962 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
963 | c1713132 | balrog | } |
964 | c1713132 | balrog | break;
|
965 | c1713132 | balrog | |
966 | c1713132 | balrog | case RTSR:
|
967 | c1713132 | balrog | if ((s->rtsr ^ value) & (1 << 15)) |
968 | c1713132 | balrog | pxa2xx_rtc_piupdate(s); |
969 | c1713132 | balrog | |
970 | c1713132 | balrog | if ((s->rtsr ^ value) & (1 << 12)) |
971 | c1713132 | balrog | pxa2xx_rtc_swupdate(s); |
972 | c1713132 | balrog | |
973 | c1713132 | balrog | if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) |
974 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, value); |
975 | c1713132 | balrog | |
976 | c1713132 | balrog | s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); |
977 | c1713132 | balrog | pxa2xx_rtc_int_update(s); |
978 | c1713132 | balrog | break;
|
979 | c1713132 | balrog | |
980 | c1713132 | balrog | case RTAR:
|
981 | c1713132 | balrog | s->rtar = value; |
982 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
983 | c1713132 | balrog | break;
|
984 | c1713132 | balrog | |
985 | c1713132 | balrog | case RDAR1:
|
986 | c1713132 | balrog | s->rdar1 = value; |
987 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
988 | c1713132 | balrog | break;
|
989 | c1713132 | balrog | |
990 | c1713132 | balrog | case RDAR2:
|
991 | c1713132 | balrog | s->rdar2 = value; |
992 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
993 | c1713132 | balrog | break;
|
994 | c1713132 | balrog | |
995 | c1713132 | balrog | case RYAR1:
|
996 | c1713132 | balrog | s->ryar1 = value; |
997 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
998 | c1713132 | balrog | break;
|
999 | c1713132 | balrog | |
1000 | c1713132 | balrog | case RYAR2:
|
1001 | c1713132 | balrog | s->ryar2 = value; |
1002 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
1003 | c1713132 | balrog | break;
|
1004 | c1713132 | balrog | |
1005 | c1713132 | balrog | case SWAR1:
|
1006 | c1713132 | balrog | pxa2xx_rtc_swupdate(s); |
1007 | c1713132 | balrog | s->swar1 = value; |
1008 | c1713132 | balrog | s->last_swcr = 0;
|
1009 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
1010 | c1713132 | balrog | break;
|
1011 | c1713132 | balrog | |
1012 | c1713132 | balrog | case SWAR2:
|
1013 | c1713132 | balrog | s->swar2 = value; |
1014 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
1015 | c1713132 | balrog | break;
|
1016 | c1713132 | balrog | |
1017 | c1713132 | balrog | case PIAR:
|
1018 | c1713132 | balrog | s->piar = value; |
1019 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
1020 | c1713132 | balrog | break;
|
1021 | c1713132 | balrog | |
1022 | c1713132 | balrog | case RCNR:
|
1023 | c1713132 | balrog | pxa2xx_rtc_hzupdate(s); |
1024 | c1713132 | balrog | s->last_rcnr = value; |
1025 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
1026 | c1713132 | balrog | break;
|
1027 | c1713132 | balrog | |
1028 | c1713132 | balrog | case RDCR:
|
1029 | c1713132 | balrog | pxa2xx_rtc_hzupdate(s); |
1030 | c1713132 | balrog | s->last_rdcr = value; |
1031 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
1032 | c1713132 | balrog | break;
|
1033 | c1713132 | balrog | |
1034 | c1713132 | balrog | case RYCR:
|
1035 | c1713132 | balrog | s->last_rycr = value; |
1036 | c1713132 | balrog | break;
|
1037 | c1713132 | balrog | |
1038 | c1713132 | balrog | case SWCR:
|
1039 | c1713132 | balrog | pxa2xx_rtc_swupdate(s); |
1040 | c1713132 | balrog | s->last_swcr = value; |
1041 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
1042 | c1713132 | balrog | break;
|
1043 | c1713132 | balrog | |
1044 | c1713132 | balrog | case RTCPICR:
|
1045 | c1713132 | balrog | pxa2xx_rtc_piupdate(s); |
1046 | c1713132 | balrog | s->last_rtcpicr = value & 0xffff;
|
1047 | c1713132 | balrog | pxa2xx_rtc_alarm_update(s, s->rtsr); |
1048 | c1713132 | balrog | break;
|
1049 | c1713132 | balrog | |
1050 | c1713132 | balrog | default:
|
1051 | c1713132 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1052 | c1713132 | balrog | } |
1053 | c1713132 | balrog | } |
1054 | c1713132 | balrog | |
1055 | c1713132 | balrog | static void pxa2xx_rtc_reset(struct pxa2xx_state_s *s) |
1056 | c1713132 | balrog | { |
1057 | c1713132 | balrog | struct tm *tm;
|
1058 | c1713132 | balrog | time_t ti; |
1059 | c1713132 | balrog | int wom;
|
1060 | c1713132 | balrog | |
1061 | c1713132 | balrog | s->rttr = 0x7fff;
|
1062 | c1713132 | balrog | s->rtsr = 0;
|
1063 | c1713132 | balrog | |
1064 | c1713132 | balrog | time(&ti); |
1065 | c1713132 | balrog | if (rtc_utc)
|
1066 | c1713132 | balrog | tm = gmtime(&ti); |
1067 | c1713132 | balrog | else
|
1068 | c1713132 | balrog | tm = localtime(&ti); |
1069 | c1713132 | balrog | wom = ((tm->tm_mday - 1) / 7) + 1; |
1070 | c1713132 | balrog | |
1071 | c1713132 | balrog | s->last_rcnr = (uint32_t) ti; |
1072 | c1713132 | balrog | s->last_rdcr = (wom << 20) | ((tm->tm_wday + 1) << 17) | |
1073 | c1713132 | balrog | (tm->tm_hour << 12) | (tm->tm_min << 6) | tm->tm_sec; |
1074 | c1713132 | balrog | s->last_rycr = ((tm->tm_year + 1900) << 9) | |
1075 | c1713132 | balrog | ((tm->tm_mon + 1) << 5) | tm->tm_mday; |
1076 | c1713132 | balrog | s->last_swcr = (tm->tm_hour << 19) |
|
1077 | c1713132 | balrog | (tm->tm_min << 13) | (tm->tm_sec << 7); |
1078 | c1713132 | balrog | s->last_rtcpicr = 0;
|
1079 | c1713132 | balrog | s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock); |
1080 | c1713132 | balrog | |
1081 | c1713132 | balrog | s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s); |
1082 | c1713132 | balrog | s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s); |
1083 | c1713132 | balrog | s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s); |
1084 | c1713132 | balrog | s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s); |
1085 | c1713132 | balrog | s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s); |
1086 | c1713132 | balrog | s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s); |
1087 | c1713132 | balrog | } |
1088 | c1713132 | balrog | |
1089 | c1713132 | balrog | static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
|
1090 | c1713132 | balrog | pxa2xx_rtc_read, |
1091 | c1713132 | balrog | pxa2xx_rtc_read, |
1092 | c1713132 | balrog | pxa2xx_rtc_read, |
1093 | c1713132 | balrog | }; |
1094 | c1713132 | balrog | |
1095 | c1713132 | balrog | static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
|
1096 | c1713132 | balrog | pxa2xx_rtc_write, |
1097 | c1713132 | balrog | pxa2xx_rtc_write, |
1098 | c1713132 | balrog | pxa2xx_rtc_write, |
1099 | c1713132 | balrog | }; |
1100 | c1713132 | balrog | |
1101 | 3f582262 | balrog | /* I2C Interface */
|
1102 | 3f582262 | balrog | struct pxa2xx_i2c_s {
|
1103 | 3f582262 | balrog | i2c_slave slave; |
1104 | 3f582262 | balrog | i2c_bus *bus; |
1105 | 3f582262 | balrog | target_phys_addr_t base; |
1106 | 3f582262 | balrog | qemu_irq irq; |
1107 | 3f582262 | balrog | |
1108 | 3f582262 | balrog | uint16_t control; |
1109 | 3f582262 | balrog | uint16_t status; |
1110 | 3f582262 | balrog | uint8_t ibmr; |
1111 | 3f582262 | balrog | uint8_t data; |
1112 | 3f582262 | balrog | }; |
1113 | 3f582262 | balrog | |
1114 | 3f582262 | balrog | #define IBMR 0x80 /* I2C Bus Monitor register */ |
1115 | 3f582262 | balrog | #define IDBR 0x88 /* I2C Data Buffer register */ |
1116 | 3f582262 | balrog | #define ICR 0x90 /* I2C Control register */ |
1117 | 3f582262 | balrog | #define ISR 0x98 /* I2C Status register */ |
1118 | 3f582262 | balrog | #define ISAR 0xa0 /* I2C Slave Address register */ |
1119 | 3f582262 | balrog | |
1120 | 3f582262 | balrog | static void pxa2xx_i2c_update(struct pxa2xx_i2c_s *s) |
1121 | 3f582262 | balrog | { |
1122 | 3f582262 | balrog | uint16_t level = 0;
|
1123 | 3f582262 | balrog | level |= s->status & s->control & (1 << 10); /* BED */ |
1124 | 3f582262 | balrog | level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ |
1125 | 3f582262 | balrog | level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ |
1126 | 3f582262 | balrog | level |= s->status & (1 << 9); /* SAD */ |
1127 | 3f582262 | balrog | qemu_set_irq(s->irq, !!level); |
1128 | 3f582262 | balrog | } |
1129 | 3f582262 | balrog | |
1130 | 3f582262 | balrog | /* These are only stubs now. */
|
1131 | 3f582262 | balrog | static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event) |
1132 | 3f582262 | balrog | { |
1133 | 3f582262 | balrog | struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c; |
1134 | 3f582262 | balrog | |
1135 | 3f582262 | balrog | switch (event) {
|
1136 | 3f582262 | balrog | case I2C_START_SEND:
|
1137 | 3f582262 | balrog | s->status |= (1 << 9); /* set SAD */ |
1138 | 3f582262 | balrog | s->status &= ~(1 << 0); /* clear RWM */ |
1139 | 3f582262 | balrog | break;
|
1140 | 3f582262 | balrog | case I2C_START_RECV:
|
1141 | 3f582262 | balrog | s->status |= (1 << 9); /* set SAD */ |
1142 | 3f582262 | balrog | s->status |= 1 << 0; /* set RWM */ |
1143 | 3f582262 | balrog | break;
|
1144 | 3f582262 | balrog | case I2C_FINISH:
|
1145 | 3f582262 | balrog | s->status |= (1 << 4); /* set SSD */ |
1146 | 3f582262 | balrog | break;
|
1147 | 3f582262 | balrog | case I2C_NACK:
|
1148 | 3f582262 | balrog | s->status |= 1 << 1; /* set ACKNAK */ |
1149 | 3f582262 | balrog | break;
|
1150 | 3f582262 | balrog | } |
1151 | 3f582262 | balrog | pxa2xx_i2c_update(s); |
1152 | 3f582262 | balrog | } |
1153 | 3f582262 | balrog | |
1154 | 3f582262 | balrog | static int pxa2xx_i2c_rx(i2c_slave *i2c) |
1155 | 3f582262 | balrog | { |
1156 | 3f582262 | balrog | struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c; |
1157 | 3f582262 | balrog | if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) |
1158 | 3f582262 | balrog | return 0; |
1159 | 3f582262 | balrog | |
1160 | 3f582262 | balrog | if (s->status & (1 << 0)) { /* RWM */ |
1161 | 3f582262 | balrog | s->status |= 1 << 6; /* set ITE */ |
1162 | 3f582262 | balrog | } |
1163 | 3f582262 | balrog | pxa2xx_i2c_update(s); |
1164 | 3f582262 | balrog | |
1165 | 3f582262 | balrog | return s->data;
|
1166 | 3f582262 | balrog | } |
1167 | 3f582262 | balrog | |
1168 | 3f582262 | balrog | static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data) |
1169 | 3f582262 | balrog | { |
1170 | 3f582262 | balrog | struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c; |
1171 | 3f582262 | balrog | if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) |
1172 | 3f582262 | balrog | return 1; |
1173 | 3f582262 | balrog | |
1174 | 3f582262 | balrog | if (!(s->status & (1 << 0))) { /* RWM */ |
1175 | 3f582262 | balrog | s->status |= 1 << 7; /* set IRF */ |
1176 | 3f582262 | balrog | s->data = data; |
1177 | 3f582262 | balrog | } |
1178 | 3f582262 | balrog | pxa2xx_i2c_update(s); |
1179 | 3f582262 | balrog | |
1180 | 3f582262 | balrog | return 1; |
1181 | 3f582262 | balrog | } |
1182 | 3f582262 | balrog | |
1183 | 3f582262 | balrog | static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr) |
1184 | 3f582262 | balrog | { |
1185 | 3f582262 | balrog | struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; |
1186 | 3f582262 | balrog | addr -= s->base; |
1187 | 3f582262 | balrog | |
1188 | 3f582262 | balrog | switch (addr) {
|
1189 | 3f582262 | balrog | case ICR:
|
1190 | 3f582262 | balrog | return s->control;
|
1191 | 3f582262 | balrog | case ISR:
|
1192 | 3f582262 | balrog | return s->status | (i2c_bus_busy(s->bus) << 2); |
1193 | 3f582262 | balrog | case ISAR:
|
1194 | 3f582262 | balrog | return s->slave.address;
|
1195 | 3f582262 | balrog | case IDBR:
|
1196 | 3f582262 | balrog | return s->data;
|
1197 | 3f582262 | balrog | case IBMR:
|
1198 | 3f582262 | balrog | if (s->status & (1 << 2)) |
1199 | 3f582262 | balrog | s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ |
1200 | 3f582262 | balrog | else
|
1201 | 3f582262 | balrog | s->ibmr = 0;
|
1202 | 3f582262 | balrog | return s->ibmr;
|
1203 | 3f582262 | balrog | default:
|
1204 | 3f582262 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1205 | 3f582262 | balrog | break;
|
1206 | 3f582262 | balrog | } |
1207 | 3f582262 | balrog | return 0; |
1208 | 3f582262 | balrog | } |
1209 | 3f582262 | balrog | |
1210 | 3f582262 | balrog | static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr, |
1211 | 3f582262 | balrog | uint32_t value) |
1212 | 3f582262 | balrog | { |
1213 | 3f582262 | balrog | struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; |
1214 | 3f582262 | balrog | int ack;
|
1215 | 3f582262 | balrog | addr -= s->base; |
1216 | 3f582262 | balrog | |
1217 | 3f582262 | balrog | switch (addr) {
|
1218 | 3f582262 | balrog | case ICR:
|
1219 | 3f582262 | balrog | s->control = value & 0xfff7;
|
1220 | 3f582262 | balrog | if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ |
1221 | 3f582262 | balrog | /* TODO: slave mode */
|
1222 | 3f582262 | balrog | if (value & (1 << 0)) { /* START condition */ |
1223 | 3f582262 | balrog | if (s->data & 1) |
1224 | 3f582262 | balrog | s->status |= 1 << 0; /* set RWM */ |
1225 | 3f582262 | balrog | else
|
1226 | 3f582262 | balrog | s->status &= ~(1 << 0); /* clear RWM */ |
1227 | 3f582262 | balrog | ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); |
1228 | 3f582262 | balrog | } else {
|
1229 | 3f582262 | balrog | if (s->status & (1 << 0)) { /* RWM */ |
1230 | 3f582262 | balrog | s->data = i2c_recv(s->bus); |
1231 | 3f582262 | balrog | if (value & (1 << 2)) /* ACKNAK */ |
1232 | 3f582262 | balrog | i2c_nack(s->bus); |
1233 | 3f582262 | balrog | ack = 1;
|
1234 | 3f582262 | balrog | } else
|
1235 | 3f582262 | balrog | ack = !i2c_send(s->bus, s->data); |
1236 | 3f582262 | balrog | } |
1237 | 3f582262 | balrog | |
1238 | 3f582262 | balrog | if (value & (1 << 1)) /* STOP condition */ |
1239 | 3f582262 | balrog | i2c_end_transfer(s->bus); |
1240 | 3f582262 | balrog | |
1241 | 3f582262 | balrog | if (ack) {
|
1242 | 3f582262 | balrog | if (value & (1 << 0)) /* START condition */ |
1243 | 3f582262 | balrog | s->status |= 1 << 6; /* set ITE */ |
1244 | 3f582262 | balrog | else
|
1245 | 3f582262 | balrog | if (s->status & (1 << 0)) /* RWM */ |
1246 | 3f582262 | balrog | s->status |= 1 << 7; /* set IRF */ |
1247 | 3f582262 | balrog | else
|
1248 | 3f582262 | balrog | s->status |= 1 << 6; /* set ITE */ |
1249 | 3f582262 | balrog | s->status &= ~(1 << 1); /* clear ACKNAK */ |
1250 | 3f582262 | balrog | } else {
|
1251 | 3f582262 | balrog | s->status |= 1 << 6; /* set ITE */ |
1252 | 3f582262 | balrog | s->status |= 1 << 10; /* set BED */ |
1253 | 3f582262 | balrog | s->status |= 1 << 1; /* set ACKNAK */ |
1254 | 3f582262 | balrog | } |
1255 | 3f582262 | balrog | } |
1256 | 3f582262 | balrog | if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ |
1257 | 3f582262 | balrog | if (value & (1 << 4)) /* MA */ |
1258 | 3f582262 | balrog | i2c_end_transfer(s->bus); |
1259 | 3f582262 | balrog | pxa2xx_i2c_update(s); |
1260 | 3f582262 | balrog | break;
|
1261 | 3f582262 | balrog | |
1262 | 3f582262 | balrog | case ISR:
|
1263 | 3f582262 | balrog | s->status &= ~(value & 0x07f0);
|
1264 | 3f582262 | balrog | pxa2xx_i2c_update(s); |
1265 | 3f582262 | balrog | break;
|
1266 | 3f582262 | balrog | |
1267 | 3f582262 | balrog | case ISAR:
|
1268 | 3f582262 | balrog | i2c_set_slave_address(&s->slave, value & 0x7f);
|
1269 | 3f582262 | balrog | break;
|
1270 | 3f582262 | balrog | |
1271 | 3f582262 | balrog | case IDBR:
|
1272 | 3f582262 | balrog | s->data = value & 0xff;
|
1273 | 3f582262 | balrog | break;
|
1274 | 3f582262 | balrog | |
1275 | 3f582262 | balrog | default:
|
1276 | 3f582262 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1277 | 3f582262 | balrog | } |
1278 | 3f582262 | balrog | } |
1279 | 3f582262 | balrog | |
1280 | 3f582262 | balrog | static CPUReadMemoryFunc *pxa2xx_i2c_readfn[] = {
|
1281 | 3f582262 | balrog | pxa2xx_i2c_read, |
1282 | 3f582262 | balrog | pxa2xx_i2c_read, |
1283 | 3f582262 | balrog | pxa2xx_i2c_read, |
1284 | 3f582262 | balrog | }; |
1285 | 3f582262 | balrog | |
1286 | 3f582262 | balrog | static CPUWriteMemoryFunc *pxa2xx_i2c_writefn[] = {
|
1287 | 3f582262 | balrog | pxa2xx_i2c_write, |
1288 | 3f582262 | balrog | pxa2xx_i2c_write, |
1289 | 3f582262 | balrog | pxa2xx_i2c_write, |
1290 | 3f582262 | balrog | }; |
1291 | 3f582262 | balrog | |
1292 | 3f582262 | balrog | struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
|
1293 | 3f582262 | balrog | qemu_irq irq, int ioregister)
|
1294 | 3f582262 | balrog | { |
1295 | 3f582262 | balrog | int iomemtype;
|
1296 | 3f582262 | balrog | struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) |
1297 | 3f582262 | balrog | qemu_mallocz(sizeof(struct pxa2xx_i2c_s)); |
1298 | 3f582262 | balrog | |
1299 | 3f582262 | balrog | s->base = base; |
1300 | 3f582262 | balrog | s->irq = irq; |
1301 | 3f582262 | balrog | s->slave.event = pxa2xx_i2c_event; |
1302 | 3f582262 | balrog | s->slave.recv = pxa2xx_i2c_rx; |
1303 | 3f582262 | balrog | s->slave.send = pxa2xx_i2c_tx; |
1304 | 3f582262 | balrog | s->bus = i2c_init_bus(); |
1305 | 3f582262 | balrog | |
1306 | 3f582262 | balrog | if (ioregister) {
|
1307 | 3f582262 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
|
1308 | 3f582262 | balrog | pxa2xx_i2c_writefn, s); |
1309 | 3f582262 | balrog | cpu_register_physical_memory(s->base & 0xfffff000, 0xfff, iomemtype); |
1310 | 3f582262 | balrog | } |
1311 | 3f582262 | balrog | |
1312 | 3f582262 | balrog | return s;
|
1313 | 3f582262 | balrog | } |
1314 | 3f582262 | balrog | |
1315 | 3f582262 | balrog | i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s)
|
1316 | 3f582262 | balrog | { |
1317 | 3f582262 | balrog | return s->bus;
|
1318 | 3f582262 | balrog | } |
1319 | 3f582262 | balrog | |
1320 | c1713132 | balrog | /* PXA Inter-IC Sound Controller */
|
1321 | c1713132 | balrog | static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s) |
1322 | c1713132 | balrog | { |
1323 | c1713132 | balrog | i2s->rx_len = 0;
|
1324 | c1713132 | balrog | i2s->tx_len = 0;
|
1325 | c1713132 | balrog | i2s->fifo_len = 0;
|
1326 | c1713132 | balrog | i2s->clk = 0x1a;
|
1327 | c1713132 | balrog | i2s->control[0] = 0x00; |
1328 | c1713132 | balrog | i2s->control[1] = 0x00; |
1329 | c1713132 | balrog | i2s->status = 0x00;
|
1330 | c1713132 | balrog | i2s->mask = 0x00;
|
1331 | c1713132 | balrog | } |
1332 | c1713132 | balrog | |
1333 | c1713132 | balrog | #define SACR_TFTH(val) ((val >> 8) & 0xf) |
1334 | c1713132 | balrog | #define SACR_RFTH(val) ((val >> 12) & 0xf) |
1335 | c1713132 | balrog | #define SACR_DREC(val) (val & (1 << 3)) |
1336 | c1713132 | balrog | #define SACR_DPRL(val) (val & (1 << 4)) |
1337 | c1713132 | balrog | |
1338 | c1713132 | balrog | static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s) |
1339 | c1713132 | balrog | { |
1340 | c1713132 | balrog | int rfs, tfs;
|
1341 | c1713132 | balrog | rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
|
1342 | c1713132 | balrog | !SACR_DREC(i2s->control[1]);
|
1343 | c1713132 | balrog | tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
|
1344 | c1713132 | balrog | i2s->enable && !SACR_DPRL(i2s->control[1]);
|
1345 | c1713132 | balrog | |
1346 | c1713132 | balrog | pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs); |
1347 | c1713132 | balrog | pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs); |
1348 | c1713132 | balrog | |
1349 | c1713132 | balrog | i2s->status &= 0xe0;
|
1350 | c1713132 | balrog | if (i2s->rx_len)
|
1351 | c1713132 | balrog | i2s->status |= 1 << 1; /* RNE */ |
1352 | c1713132 | balrog | if (i2s->enable)
|
1353 | c1713132 | balrog | i2s->status |= 1 << 2; /* BSY */ |
1354 | c1713132 | balrog | if (tfs)
|
1355 | c1713132 | balrog | i2s->status |= 1 << 3; /* TFS */ |
1356 | c1713132 | balrog | if (rfs)
|
1357 | c1713132 | balrog | i2s->status |= 1 << 4; /* RFS */ |
1358 | c1713132 | balrog | if (!(i2s->tx_len && i2s->enable))
|
1359 | c1713132 | balrog | i2s->status |= i2s->fifo_len << 8; /* TFL */ |
1360 | c1713132 | balrog | i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ |
1361 | c1713132 | balrog | |
1362 | c1713132 | balrog | qemu_set_irq(i2s->irq, i2s->status & i2s->mask); |
1363 | c1713132 | balrog | } |
1364 | c1713132 | balrog | |
1365 | c1713132 | balrog | #define SACR0 0x00 /* Serial Audio Global Control register */ |
1366 | c1713132 | balrog | #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ |
1367 | c1713132 | balrog | #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ |
1368 | c1713132 | balrog | #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ |
1369 | c1713132 | balrog | #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ |
1370 | c1713132 | balrog | #define SADIV 0x60 /* Serial Audio Clock Divider register */ |
1371 | c1713132 | balrog | #define SADR 0x80 /* Serial Audio Data register */ |
1372 | c1713132 | balrog | |
1373 | c1713132 | balrog | static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr) |
1374 | c1713132 | balrog | { |
1375 | c1713132 | balrog | struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; |
1376 | c1713132 | balrog | addr -= s->base; |
1377 | c1713132 | balrog | |
1378 | c1713132 | balrog | switch (addr) {
|
1379 | c1713132 | balrog | case SACR0:
|
1380 | c1713132 | balrog | return s->control[0]; |
1381 | c1713132 | balrog | case SACR1:
|
1382 | c1713132 | balrog | return s->control[1]; |
1383 | c1713132 | balrog | case SASR0:
|
1384 | c1713132 | balrog | return s->status;
|
1385 | c1713132 | balrog | case SAIMR:
|
1386 | c1713132 | balrog | return s->mask;
|
1387 | c1713132 | balrog | case SAICR:
|
1388 | c1713132 | balrog | return 0; |
1389 | c1713132 | balrog | case SADIV:
|
1390 | c1713132 | balrog | return s->clk;
|
1391 | c1713132 | balrog | case SADR:
|
1392 | c1713132 | balrog | if (s->rx_len > 0) { |
1393 | c1713132 | balrog | s->rx_len --; |
1394 | c1713132 | balrog | pxa2xx_i2s_update(s); |
1395 | c1713132 | balrog | return s->codec_in(s->opaque);
|
1396 | c1713132 | balrog | } |
1397 | c1713132 | balrog | return 0; |
1398 | c1713132 | balrog | default:
|
1399 | c1713132 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1400 | c1713132 | balrog | break;
|
1401 | c1713132 | balrog | } |
1402 | c1713132 | balrog | return 0; |
1403 | c1713132 | balrog | } |
1404 | c1713132 | balrog | |
1405 | c1713132 | balrog | static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr, |
1406 | c1713132 | balrog | uint32_t value) |
1407 | c1713132 | balrog | { |
1408 | c1713132 | balrog | struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; |
1409 | c1713132 | balrog | uint32_t *sample; |
1410 | c1713132 | balrog | addr -= s->base; |
1411 | c1713132 | balrog | |
1412 | c1713132 | balrog | switch (addr) {
|
1413 | c1713132 | balrog | case SACR0:
|
1414 | c1713132 | balrog | if (value & (1 << 3)) /* RST */ |
1415 | c1713132 | balrog | pxa2xx_i2s_reset(s); |
1416 | c1713132 | balrog | s->control[0] = value & 0xff3d; |
1417 | c1713132 | balrog | if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ |
1418 | c1713132 | balrog | for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) |
1419 | c1713132 | balrog | s->codec_out(s->opaque, *sample); |
1420 | c1713132 | balrog | s->status &= ~(1 << 7); /* I2SOFF */ |
1421 | c1713132 | balrog | } |
1422 | c1713132 | balrog | if (value & (1 << 4)) /* EFWR */ |
1423 | c1713132 | balrog | printf("%s: Attempt to use special function\n", __FUNCTION__);
|
1424 | c1713132 | balrog | s->enable = ((value ^ 4) & 5) == 5; /* ENB && !RST*/ |
1425 | c1713132 | balrog | pxa2xx_i2s_update(s); |
1426 | c1713132 | balrog | break;
|
1427 | c1713132 | balrog | case SACR1:
|
1428 | c1713132 | balrog | s->control[1] = value & 0x0039; |
1429 | c1713132 | balrog | if (value & (1 << 5)) /* ENLBF */ |
1430 | c1713132 | balrog | printf("%s: Attempt to use loopback function\n", __FUNCTION__);
|
1431 | c1713132 | balrog | if (value & (1 << 4)) /* DPRL */ |
1432 | c1713132 | balrog | s->fifo_len = 0;
|
1433 | c1713132 | balrog | pxa2xx_i2s_update(s); |
1434 | c1713132 | balrog | break;
|
1435 | c1713132 | balrog | case SAIMR:
|
1436 | c1713132 | balrog | s->mask = value & 0x0078;
|
1437 | c1713132 | balrog | pxa2xx_i2s_update(s); |
1438 | c1713132 | balrog | break;
|
1439 | c1713132 | balrog | case SAICR:
|
1440 | c1713132 | balrog | s->status &= ~(value & (3 << 5)); |
1441 | c1713132 | balrog | pxa2xx_i2s_update(s); |
1442 | c1713132 | balrog | break;
|
1443 | c1713132 | balrog | case SADIV:
|
1444 | c1713132 | balrog | s->clk = value & 0x007f;
|
1445 | c1713132 | balrog | break;
|
1446 | c1713132 | balrog | case SADR:
|
1447 | c1713132 | balrog | if (s->tx_len && s->enable) {
|
1448 | c1713132 | balrog | s->tx_len --; |
1449 | c1713132 | balrog | pxa2xx_i2s_update(s); |
1450 | c1713132 | balrog | s->codec_out(s->opaque, value); |
1451 | c1713132 | balrog | } else if (s->fifo_len < 16) { |
1452 | c1713132 | balrog | s->fifo[s->fifo_len ++] = value; |
1453 | c1713132 | balrog | pxa2xx_i2s_update(s); |
1454 | c1713132 | balrog | } |
1455 | c1713132 | balrog | break;
|
1456 | c1713132 | balrog | default:
|
1457 | c1713132 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1458 | c1713132 | balrog | } |
1459 | c1713132 | balrog | } |
1460 | c1713132 | balrog | |
1461 | c1713132 | balrog | static CPUReadMemoryFunc *pxa2xx_i2s_readfn[] = {
|
1462 | c1713132 | balrog | pxa2xx_i2s_read, |
1463 | c1713132 | balrog | pxa2xx_i2s_read, |
1464 | c1713132 | balrog | pxa2xx_i2s_read, |
1465 | c1713132 | balrog | }; |
1466 | c1713132 | balrog | |
1467 | c1713132 | balrog | static CPUWriteMemoryFunc *pxa2xx_i2s_writefn[] = {
|
1468 | c1713132 | balrog | pxa2xx_i2s_write, |
1469 | c1713132 | balrog | pxa2xx_i2s_write, |
1470 | c1713132 | balrog | pxa2xx_i2s_write, |
1471 | c1713132 | balrog | }; |
1472 | c1713132 | balrog | |
1473 | c1713132 | balrog | static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) |
1474 | c1713132 | balrog | { |
1475 | c1713132 | balrog | struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; |
1476 | c1713132 | balrog | uint32_t *sample; |
1477 | c1713132 | balrog | |
1478 | c1713132 | balrog | /* Signal FIFO errors */
|
1479 | c1713132 | balrog | if (s->enable && s->tx_len)
|
1480 | c1713132 | balrog | s->status |= 1 << 5; /* TUR */ |
1481 | c1713132 | balrog | if (s->enable && s->rx_len)
|
1482 | c1713132 | balrog | s->status |= 1 << 6; /* ROR */ |
1483 | c1713132 | balrog | |
1484 | c1713132 | balrog | /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
|
1485 | c1713132 | balrog | * handle the cases where it makes a difference. */
|
1486 | c1713132 | balrog | s->tx_len = tx - s->fifo_len; |
1487 | c1713132 | balrog | s->rx_len = rx; |
1488 | c1713132 | balrog | /* Note that is s->codec_out wasn't set, we wouldn't get called. */
|
1489 | c1713132 | balrog | if (s->enable)
|
1490 | c1713132 | balrog | for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
|
1491 | c1713132 | balrog | s->codec_out(s->opaque, *sample); |
1492 | c1713132 | balrog | pxa2xx_i2s_update(s); |
1493 | c1713132 | balrog | } |
1494 | c1713132 | balrog | |
1495 | c1713132 | balrog | static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base, |
1496 | c1713132 | balrog | qemu_irq irq, struct pxa2xx_dma_state_s *dma)
|
1497 | c1713132 | balrog | { |
1498 | c1713132 | balrog | int iomemtype;
|
1499 | c1713132 | balrog | struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) |
1500 | c1713132 | balrog | qemu_mallocz(sizeof(struct pxa2xx_i2s_s)); |
1501 | c1713132 | balrog | |
1502 | c1713132 | balrog | s->base = base; |
1503 | c1713132 | balrog | s->irq = irq; |
1504 | c1713132 | balrog | s->dma = dma; |
1505 | c1713132 | balrog | s->data_req = pxa2xx_i2s_data_req; |
1506 | c1713132 | balrog | |
1507 | c1713132 | balrog | pxa2xx_i2s_reset(s); |
1508 | c1713132 | balrog | |
1509 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
|
1510 | c1713132 | balrog | pxa2xx_i2s_writefn, s); |
1511 | c1713132 | balrog | cpu_register_physical_memory(s->base & 0xfff00000, 0xfffff, iomemtype); |
1512 | c1713132 | balrog | |
1513 | c1713132 | balrog | return s;
|
1514 | c1713132 | balrog | } |
1515 | c1713132 | balrog | |
1516 | c1713132 | balrog | /* PXA Fast Infra-red Communications Port */
|
1517 | c1713132 | balrog | struct pxa2xx_fir_s {
|
1518 | c1713132 | balrog | target_phys_addr_t base; |
1519 | c1713132 | balrog | qemu_irq irq; |
1520 | c1713132 | balrog | struct pxa2xx_dma_state_s *dma;
|
1521 | c1713132 | balrog | int enable;
|
1522 | c1713132 | balrog | CharDriverState *chr; |
1523 | c1713132 | balrog | |
1524 | c1713132 | balrog | uint8_t control[3];
|
1525 | c1713132 | balrog | uint8_t status[2];
|
1526 | c1713132 | balrog | |
1527 | c1713132 | balrog | int rx_len;
|
1528 | c1713132 | balrog | int rx_start;
|
1529 | c1713132 | balrog | uint8_t rx_fifo[64];
|
1530 | c1713132 | balrog | }; |
1531 | c1713132 | balrog | |
1532 | c1713132 | balrog | static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s) |
1533 | c1713132 | balrog | { |
1534 | c1713132 | balrog | s->control[0] = 0x00; |
1535 | c1713132 | balrog | s->control[1] = 0x00; |
1536 | c1713132 | balrog | s->control[2] = 0x00; |
1537 | c1713132 | balrog | s->status[0] = 0x00; |
1538 | c1713132 | balrog | s->status[1] = 0x00; |
1539 | c1713132 | balrog | s->enable = 0;
|
1540 | c1713132 | balrog | } |
1541 | c1713132 | balrog | |
1542 | c1713132 | balrog | static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s) |
1543 | c1713132 | balrog | { |
1544 | c1713132 | balrog | static const int tresh[4] = { 8, 16, 32, 0 }; |
1545 | c1713132 | balrog | int intr = 0; |
1546 | c1713132 | balrog | if ((s->control[0] & (1 << 4)) && /* RXE */ |
1547 | c1713132 | balrog | s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ |
1548 | c1713132 | balrog | s->status[0] |= 1 << 4; /* RFS */ |
1549 | c1713132 | balrog | else
|
1550 | c1713132 | balrog | s->status[0] &= ~(1 << 4); /* RFS */ |
1551 | c1713132 | balrog | if (s->control[0] & (1 << 3)) /* TXE */ |
1552 | c1713132 | balrog | s->status[0] |= 1 << 3; /* TFS */ |
1553 | c1713132 | balrog | else
|
1554 | c1713132 | balrog | s->status[0] &= ~(1 << 3); /* TFS */ |
1555 | c1713132 | balrog | if (s->rx_len)
|
1556 | c1713132 | balrog | s->status[1] |= 1 << 2; /* RNE */ |
1557 | c1713132 | balrog | else
|
1558 | c1713132 | balrog | s->status[1] &= ~(1 << 2); /* RNE */ |
1559 | c1713132 | balrog | if (s->control[0] & (1 << 4)) /* RXE */ |
1560 | c1713132 | balrog | s->status[1] |= 1 << 0; /* RSY */ |
1561 | c1713132 | balrog | else
|
1562 | c1713132 | balrog | s->status[1] &= ~(1 << 0); /* RSY */ |
1563 | c1713132 | balrog | |
1564 | c1713132 | balrog | intr |= (s->control[0] & (1 << 5)) && /* RIE */ |
1565 | c1713132 | balrog | (s->status[0] & (1 << 4)); /* RFS */ |
1566 | c1713132 | balrog | intr |= (s->control[0] & (1 << 6)) && /* TIE */ |
1567 | c1713132 | balrog | (s->status[0] & (1 << 3)); /* TFS */ |
1568 | c1713132 | balrog | intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ |
1569 | c1713132 | balrog | (s->status[0] & (1 << 6)); /* EOC */ |
1570 | c1713132 | balrog | intr |= (s->control[0] & (1 << 2)) && /* TUS */ |
1571 | c1713132 | balrog | (s->status[0] & (1 << 1)); /* TUR */ |
1572 | c1713132 | balrog | intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ |
1573 | c1713132 | balrog | |
1574 | c1713132 | balrog | pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1); |
1575 | c1713132 | balrog | pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1); |
1576 | c1713132 | balrog | |
1577 | c1713132 | balrog | qemu_set_irq(s->irq, intr && s->enable); |
1578 | c1713132 | balrog | } |
1579 | c1713132 | balrog | |
1580 | c1713132 | balrog | #define ICCR0 0x00 /* FICP Control register 0 */ |
1581 | c1713132 | balrog | #define ICCR1 0x04 /* FICP Control register 1 */ |
1582 | c1713132 | balrog | #define ICCR2 0x08 /* FICP Control register 2 */ |
1583 | c1713132 | balrog | #define ICDR 0x0c /* FICP Data register */ |
1584 | c1713132 | balrog | #define ICSR0 0x14 /* FICP Status register 0 */ |
1585 | c1713132 | balrog | #define ICSR1 0x18 /* FICP Status register 1 */ |
1586 | c1713132 | balrog | #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ |
1587 | c1713132 | balrog | |
1588 | c1713132 | balrog | static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr) |
1589 | c1713132 | balrog | { |
1590 | c1713132 | balrog | struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; |
1591 | c1713132 | balrog | uint8_t ret; |
1592 | c1713132 | balrog | addr -= s->base; |
1593 | c1713132 | balrog | |
1594 | c1713132 | balrog | switch (addr) {
|
1595 | c1713132 | balrog | case ICCR0:
|
1596 | c1713132 | balrog | return s->control[0]; |
1597 | c1713132 | balrog | case ICCR1:
|
1598 | c1713132 | balrog | return s->control[1]; |
1599 | c1713132 | balrog | case ICCR2:
|
1600 | c1713132 | balrog | return s->control[2]; |
1601 | c1713132 | balrog | case ICDR:
|
1602 | c1713132 | balrog | s->status[0] &= ~0x01; |
1603 | c1713132 | balrog | s->status[1] &= ~0x72; |
1604 | c1713132 | balrog | if (s->rx_len) {
|
1605 | c1713132 | balrog | s->rx_len --; |
1606 | c1713132 | balrog | ret = s->rx_fifo[s->rx_start ++]; |
1607 | c1713132 | balrog | s->rx_start &= 63;
|
1608 | c1713132 | balrog | pxa2xx_fir_update(s); |
1609 | c1713132 | balrog | return ret;
|
1610 | c1713132 | balrog | } |
1611 | c1713132 | balrog | printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
|
1612 | c1713132 | balrog | break;
|
1613 | c1713132 | balrog | case ICSR0:
|
1614 | c1713132 | balrog | return s->status[0]; |
1615 | c1713132 | balrog | case ICSR1:
|
1616 | c1713132 | balrog | return s->status[1] | (1 << 3); /* TNF */ |
1617 | c1713132 | balrog | case ICFOR:
|
1618 | c1713132 | balrog | return s->rx_len;
|
1619 | c1713132 | balrog | default:
|
1620 | c1713132 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1621 | c1713132 | balrog | break;
|
1622 | c1713132 | balrog | } |
1623 | c1713132 | balrog | return 0; |
1624 | c1713132 | balrog | } |
1625 | c1713132 | balrog | |
1626 | c1713132 | balrog | static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr, |
1627 | c1713132 | balrog | uint32_t value) |
1628 | c1713132 | balrog | { |
1629 | c1713132 | balrog | struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; |
1630 | c1713132 | balrog | uint8_t ch; |
1631 | c1713132 | balrog | addr -= s->base; |
1632 | c1713132 | balrog | |
1633 | c1713132 | balrog | switch (addr) {
|
1634 | c1713132 | balrog | case ICCR0:
|
1635 | c1713132 | balrog | s->control[0] = value;
|
1636 | c1713132 | balrog | if (!(value & (1 << 4))) /* RXE */ |
1637 | c1713132 | balrog | s->rx_len = s->rx_start = 0;
|
1638 | c1713132 | balrog | if (!(value & (1 << 3))) /* TXE */ |
1639 | c1713132 | balrog | /* Nop */;
|
1640 | c1713132 | balrog | s->enable = value & 1; /* ITR */ |
1641 | c1713132 | balrog | if (!s->enable)
|
1642 | c1713132 | balrog | s->status[0] = 0; |
1643 | c1713132 | balrog | pxa2xx_fir_update(s); |
1644 | c1713132 | balrog | break;
|
1645 | c1713132 | balrog | case ICCR1:
|
1646 | c1713132 | balrog | s->control[1] = value;
|
1647 | c1713132 | balrog | break;
|
1648 | c1713132 | balrog | case ICCR2:
|
1649 | c1713132 | balrog | s->control[2] = value & 0x3f; |
1650 | c1713132 | balrog | pxa2xx_fir_update(s); |
1651 | c1713132 | balrog | break;
|
1652 | c1713132 | balrog | case ICDR:
|
1653 | c1713132 | balrog | if (s->control[2] & (1 << 2)) /* TXP */ |
1654 | c1713132 | balrog | ch = value; |
1655 | c1713132 | balrog | else
|
1656 | c1713132 | balrog | ch = ~value; |
1657 | c1713132 | balrog | if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */ |
1658 | c1713132 | balrog | qemu_chr_write(s->chr, &ch, 1);
|
1659 | c1713132 | balrog | break;
|
1660 | c1713132 | balrog | case ICSR0:
|
1661 | c1713132 | balrog | s->status[0] &= ~(value & 0x66); |
1662 | c1713132 | balrog | pxa2xx_fir_update(s); |
1663 | c1713132 | balrog | break;
|
1664 | c1713132 | balrog | case ICFOR:
|
1665 | c1713132 | balrog | break;
|
1666 | c1713132 | balrog | default:
|
1667 | c1713132 | balrog | printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1668 | c1713132 | balrog | } |
1669 | c1713132 | balrog | } |
1670 | c1713132 | balrog | |
1671 | c1713132 | balrog | static CPUReadMemoryFunc *pxa2xx_fir_readfn[] = {
|
1672 | c1713132 | balrog | pxa2xx_fir_read, |
1673 | c1713132 | balrog | pxa2xx_fir_read, |
1674 | c1713132 | balrog | pxa2xx_fir_read, |
1675 | c1713132 | balrog | }; |
1676 | c1713132 | balrog | |
1677 | c1713132 | balrog | static CPUWriteMemoryFunc *pxa2xx_fir_writefn[] = {
|
1678 | c1713132 | balrog | pxa2xx_fir_write, |
1679 | c1713132 | balrog | pxa2xx_fir_write, |
1680 | c1713132 | balrog | pxa2xx_fir_write, |
1681 | c1713132 | balrog | }; |
1682 | c1713132 | balrog | |
1683 | c1713132 | balrog | static int pxa2xx_fir_is_empty(void *opaque) |
1684 | c1713132 | balrog | { |
1685 | c1713132 | balrog | struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; |
1686 | c1713132 | balrog | return (s->rx_len < 64); |
1687 | c1713132 | balrog | } |
1688 | c1713132 | balrog | |
1689 | c1713132 | balrog | static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) |
1690 | c1713132 | balrog | { |
1691 | c1713132 | balrog | struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; |
1692 | c1713132 | balrog | if (!(s->control[0] & (1 << 4))) /* RXE */ |
1693 | c1713132 | balrog | return;
|
1694 | c1713132 | balrog | |
1695 | c1713132 | balrog | while (size --) {
|
1696 | c1713132 | balrog | s->status[1] |= 1 << 4; /* EOF */ |
1697 | c1713132 | balrog | if (s->rx_len >= 64) { |
1698 | c1713132 | balrog | s->status[1] |= 1 << 6; /* ROR */ |
1699 | c1713132 | balrog | break;
|
1700 | c1713132 | balrog | } |
1701 | c1713132 | balrog | |
1702 | c1713132 | balrog | if (s->control[2] & (1 << 3)) /* RXP */ |
1703 | c1713132 | balrog | s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
|
1704 | c1713132 | balrog | else
|
1705 | c1713132 | balrog | s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
|
1706 | c1713132 | balrog | } |
1707 | c1713132 | balrog | |
1708 | c1713132 | balrog | pxa2xx_fir_update(s); |
1709 | c1713132 | balrog | } |
1710 | c1713132 | balrog | |
1711 | c1713132 | balrog | static void pxa2xx_fir_event(void *opaque, int event) |
1712 | c1713132 | balrog | { |
1713 | c1713132 | balrog | } |
1714 | c1713132 | balrog | |
1715 | c1713132 | balrog | static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base, |
1716 | c1713132 | balrog | qemu_irq irq, struct pxa2xx_dma_state_s *dma,
|
1717 | c1713132 | balrog | CharDriverState *chr) |
1718 | c1713132 | balrog | { |
1719 | c1713132 | balrog | int iomemtype;
|
1720 | c1713132 | balrog | struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) |
1721 | c1713132 | balrog | qemu_mallocz(sizeof(struct pxa2xx_fir_s)); |
1722 | c1713132 | balrog | |
1723 | c1713132 | balrog | s->base = base; |
1724 | c1713132 | balrog | s->irq = irq; |
1725 | c1713132 | balrog | s->dma = dma; |
1726 | c1713132 | balrog | s->chr = chr; |
1727 | c1713132 | balrog | |
1728 | c1713132 | balrog | pxa2xx_fir_reset(s); |
1729 | c1713132 | balrog | |
1730 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
|
1731 | c1713132 | balrog | pxa2xx_fir_writefn, s); |
1732 | c1713132 | balrog | cpu_register_physical_memory(s->base, 0xfff, iomemtype);
|
1733 | c1713132 | balrog | |
1734 | c1713132 | balrog | if (chr)
|
1735 | c1713132 | balrog | qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty, |
1736 | c1713132 | balrog | pxa2xx_fir_rx, pxa2xx_fir_event, s); |
1737 | c1713132 | balrog | |
1738 | c1713132 | balrog | return s;
|
1739 | c1713132 | balrog | } |
1740 | c1713132 | balrog | |
1741 | c1713132 | balrog | void pxa2xx_reset(int line, int level, void *opaque) |
1742 | c1713132 | balrog | { |
1743 | c1713132 | balrog | struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
1744 | c1713132 | balrog | if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ |
1745 | c1713132 | balrog | cpu_reset(s->env); |
1746 | c1713132 | balrog | /* TODO: reset peripherals */
|
1747 | c1713132 | balrog | } |
1748 | c1713132 | balrog | } |
1749 | c1713132 | balrog | |
1750 | c1713132 | balrog | /* Initialise a PXA270 integrated chip (ARM based core). */
|
1751 | d95b2f8d | balrog | struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, |
1752 | d95b2f8d | balrog | DisplayState *ds, const char *revision) |
1753 | c1713132 | balrog | { |
1754 | c1713132 | balrog | struct pxa2xx_state_s *s;
|
1755 | c1713132 | balrog | struct pxa2xx_ssp_s *ssp;
|
1756 | c1713132 | balrog | int iomemtype, i;
|
1757 | c1713132 | balrog | s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s)); |
1758 | c1713132 | balrog | |
1759 | 4207117c | balrog | if (revision && strncmp(revision, "pxa27", 5)) { |
1760 | 4207117c | balrog | fprintf(stderr, "Machine requires a PXA27x processor.\n");
|
1761 | 4207117c | balrog | exit(1);
|
1762 | 4207117c | balrog | } |
1763 | 4207117c | balrog | |
1764 | c1713132 | balrog | s->env = cpu_init(); |
1765 | 4207117c | balrog | cpu_arm_set_model(s->env, revision ?: "pxa270");
|
1766 | c1713132 | balrog | |
1767 | d95b2f8d | balrog | /* SDRAM & Internal Memory Storage */
|
1768 | d95b2f8d | balrog | cpu_register_physical_memory(PXA2XX_SDRAM_BASE, |
1769 | d95b2f8d | balrog | sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM); |
1770 | d95b2f8d | balrog | cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, |
1771 | d95b2f8d | balrog | 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM); |
1772 | d95b2f8d | balrog | |
1773 | c1713132 | balrog | s->pic = pxa2xx_pic_init(0x40d00000, s->env);
|
1774 | c1713132 | balrog | |
1775 | c1713132 | balrog | s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
|
1776 | c1713132 | balrog | |
1777 | a171fe39 | balrog | pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
|
1778 | 3f582262 | balrog | s->pic[PXA27X_PIC_OST_4_11]); |
1779 | a171fe39 | balrog | |
1780 | c1713132 | balrog | s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121); |
1781 | c1713132 | balrog | |
1782 | a171fe39 | balrog | s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
|
1783 | a171fe39 | balrog | |
1784 | c1713132 | balrog | for (i = 0; pxa270_serial[i].io_base; i ++) |
1785 | c1713132 | balrog | if (serial_hds[i])
|
1786 | c1713132 | balrog | serial_mm_init(pxa270_serial[i].io_base, 2,
|
1787 | c1713132 | balrog | s->pic[pxa270_serial[i].irqn], serial_hds[i], 1);
|
1788 | c1713132 | balrog | else
|
1789 | c1713132 | balrog | break;
|
1790 | c1713132 | balrog | if (serial_hds[i])
|
1791 | c1713132 | balrog | s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
|
1792 | c1713132 | balrog | s->dma, serial_hds[i]); |
1793 | c1713132 | balrog | |
1794 | a171fe39 | balrog | if (ds)
|
1795 | a171fe39 | balrog | s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
|
1796 | a171fe39 | balrog | |
1797 | c1713132 | balrog | s->cm_base = 0x41300000;
|
1798 | c1713132 | balrog | s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */ |
1799 | c1713132 | balrog | s->clkcfg = 0x00000009; /* Turbo mode active */ |
1800 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
|
1801 | c1713132 | balrog | pxa2xx_cm_writefn, s); |
1802 | c1713132 | balrog | cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype);
|
1803 | c1713132 | balrog | |
1804 | c1713132 | balrog | cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
|
1805 | c1713132 | balrog | |
1806 | c1713132 | balrog | s->mm_base = 0x48000000;
|
1807 | c1713132 | balrog | s->mm_regs[MDMRS >> 2] = 0x00020002; |
1808 | c1713132 | balrog | s->mm_regs[MDREFR >> 2] = 0x03ca4000; |
1809 | c1713132 | balrog | s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ |
1810 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
|
1811 | c1713132 | balrog | pxa2xx_mm_writefn, s); |
1812 | c1713132 | balrog | cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype);
|
1813 | c1713132 | balrog | |
1814 | c1713132 | balrog | for (i = 0; pxa27x_ssp[i].io_base; i ++); |
1815 | c1713132 | balrog | s->ssp = (struct pxa2xx_ssp_s **)
|
1816 | c1713132 | balrog | qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i); |
1817 | c1713132 | balrog | ssp = (struct pxa2xx_ssp_s *)
|
1818 | c1713132 | balrog | qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i); |
1819 | c1713132 | balrog | for (i = 0; pxa27x_ssp[i].io_base; i ++) { |
1820 | c1713132 | balrog | s->ssp[i] = &ssp[i]; |
1821 | c1713132 | balrog | ssp[i].base = pxa27x_ssp[i].io_base; |
1822 | c1713132 | balrog | ssp[i].irq = s->pic[pxa27x_ssp[i].irqn]; |
1823 | c1713132 | balrog | |
1824 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
|
1825 | c1713132 | balrog | pxa2xx_ssp_writefn, &ssp[i]); |
1826 | c1713132 | balrog | cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
|
1827 | c1713132 | balrog | } |
1828 | c1713132 | balrog | |
1829 | a171fe39 | balrog | if (usb_enabled) {
|
1830 | a171fe39 | balrog | usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]); |
1831 | a171fe39 | balrog | } |
1832 | a171fe39 | balrog | |
1833 | a171fe39 | balrog | s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000); |
1834 | a171fe39 | balrog | s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000); |
1835 | a171fe39 | balrog | |
1836 | c1713132 | balrog | s->rtc_base = 0x40900000;
|
1837 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
|
1838 | c1713132 | balrog | pxa2xx_rtc_writefn, s); |
1839 | c1713132 | balrog | cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
|
1840 | c1713132 | balrog | pxa2xx_rtc_reset(s); |
1841 | c1713132 | balrog | |
1842 | 3f582262 | balrog | /* Note that PM registers are in the same page with PWRI2C registers.
|
1843 | 3f582262 | balrog | * As a workaround we don't map PWRI2C into memory and we expect
|
1844 | 3f582262 | balrog | * PM handlers to call PWRI2C handlers when appropriate. */
|
1845 | 3f582262 | balrog | s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 1); |
1846 | 3f582262 | balrog | s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0); |
1847 | 3f582262 | balrog | |
1848 | c1713132 | balrog | s->pm_base = 0x40f00000;
|
1849 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
|
1850 | c1713132 | balrog | pxa2xx_pm_writefn, s); |
1851 | c1713132 | balrog | cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype);
|
1852 | c1713132 | balrog | |
1853 | c1713132 | balrog | s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
|
1854 | c1713132 | balrog | |
1855 | c1713132 | balrog | /* GPIO1 resets the processor */
|
1856 | c1713132 | balrog | /* The handler can be overriden by board-specific code */
|
1857 | c1713132 | balrog | pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
|
1858 | c1713132 | balrog | return s;
|
1859 | c1713132 | balrog | } |
1860 | c1713132 | balrog | |
1861 | c1713132 | balrog | /* Initialise a PXA255 integrated chip (ARM based core). */
|
1862 | d95b2f8d | balrog | struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, |
1863 | d95b2f8d | balrog | DisplayState *ds) |
1864 | c1713132 | balrog | { |
1865 | c1713132 | balrog | struct pxa2xx_state_s *s;
|
1866 | c1713132 | balrog | struct pxa2xx_ssp_s *ssp;
|
1867 | c1713132 | balrog | int iomemtype, i;
|
1868 | c1713132 | balrog | s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s)); |
1869 | c1713132 | balrog | |
1870 | c1713132 | balrog | s->env = cpu_init(); |
1871 | c1713132 | balrog | cpu_arm_set_model(s->env, "pxa255");
|
1872 | c1713132 | balrog | |
1873 | d95b2f8d | balrog | /* SDRAM & Internal Memory Storage */
|
1874 | a07dec22 | balrog | cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size, |
1875 | a07dec22 | balrog | qemu_ram_alloc(sdram_size) | IO_MEM_RAM); |
1876 | a07dec22 | balrog | cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE, |
1877 | a07dec22 | balrog | qemu_ram_alloc(PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM); |
1878 | d95b2f8d | balrog | |
1879 | c1713132 | balrog | s->pic = pxa2xx_pic_init(0x40d00000, s->env);
|
1880 | c1713132 | balrog | |
1881 | c1713132 | balrog | s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
|
1882 | c1713132 | balrog | |
1883 | 3f582262 | balrog | pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
|
1884 | a171fe39 | balrog | |
1885 | 3bdd58a4 | balrog | s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85); |
1886 | c1713132 | balrog | |
1887 | a171fe39 | balrog | s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
|
1888 | a171fe39 | balrog | |
1889 | c1713132 | balrog | for (i = 0; pxa255_serial[i].io_base; i ++) |
1890 | c1713132 | balrog | if (serial_hds[i])
|
1891 | c1713132 | balrog | serial_mm_init(pxa255_serial[i].io_base, 2,
|
1892 | c1713132 | balrog | s->pic[pxa255_serial[i].irqn], serial_hds[i], 1);
|
1893 | c1713132 | balrog | else
|
1894 | c1713132 | balrog | break;
|
1895 | c1713132 | balrog | if (serial_hds[i])
|
1896 | c1713132 | balrog | s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
|
1897 | c1713132 | balrog | s->dma, serial_hds[i]); |
1898 | c1713132 | balrog | |
1899 | a171fe39 | balrog | if (ds)
|
1900 | a171fe39 | balrog | s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
|
1901 | a171fe39 | balrog | |
1902 | c1713132 | balrog | s->cm_base = 0x41300000;
|
1903 | c1713132 | balrog | s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */ |
1904 | c1713132 | balrog | s->clkcfg = 0x00000009; /* Turbo mode active */ |
1905 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
|
1906 | c1713132 | balrog | pxa2xx_cm_writefn, s); |
1907 | c1713132 | balrog | cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype);
|
1908 | c1713132 | balrog | |
1909 | c1713132 | balrog | cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
|
1910 | c1713132 | balrog | |
1911 | c1713132 | balrog | s->mm_base = 0x48000000;
|
1912 | c1713132 | balrog | s->mm_regs[MDMRS >> 2] = 0x00020002; |
1913 | c1713132 | balrog | s->mm_regs[MDREFR >> 2] = 0x03ca4000; |
1914 | c1713132 | balrog | s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ |
1915 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
|
1916 | c1713132 | balrog | pxa2xx_mm_writefn, s); |
1917 | c1713132 | balrog | cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype);
|
1918 | c1713132 | balrog | |
1919 | c1713132 | balrog | for (i = 0; pxa255_ssp[i].io_base; i ++); |
1920 | c1713132 | balrog | s->ssp = (struct pxa2xx_ssp_s **)
|
1921 | c1713132 | balrog | qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i); |
1922 | c1713132 | balrog | ssp = (struct pxa2xx_ssp_s *)
|
1923 | c1713132 | balrog | qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i); |
1924 | c1713132 | balrog | for (i = 0; pxa255_ssp[i].io_base; i ++) { |
1925 | c1713132 | balrog | s->ssp[i] = &ssp[i]; |
1926 | c1713132 | balrog | ssp[i].base = pxa255_ssp[i].io_base; |
1927 | c1713132 | balrog | ssp[i].irq = s->pic[pxa255_ssp[i].irqn]; |
1928 | c1713132 | balrog | |
1929 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
|
1930 | c1713132 | balrog | pxa2xx_ssp_writefn, &ssp[i]); |
1931 | c1713132 | balrog | cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
|
1932 | c1713132 | balrog | } |
1933 | c1713132 | balrog | |
1934 | a171fe39 | balrog | if (usb_enabled) {
|
1935 | a171fe39 | balrog | usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]); |
1936 | a171fe39 | balrog | } |
1937 | a171fe39 | balrog | |
1938 | a171fe39 | balrog | s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000); |
1939 | a171fe39 | balrog | s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000); |
1940 | a171fe39 | balrog | |
1941 | c1713132 | balrog | s->rtc_base = 0x40900000;
|
1942 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
|
1943 | c1713132 | balrog | pxa2xx_rtc_writefn, s); |
1944 | c1713132 | balrog | cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
|
1945 | c1713132 | balrog | pxa2xx_rtc_reset(s); |
1946 | c1713132 | balrog | |
1947 | 3f582262 | balrog | /* Note that PM registers are in the same page with PWRI2C registers.
|
1948 | 3f582262 | balrog | * As a workaround we don't map PWRI2C into memory and we expect
|
1949 | 3f582262 | balrog | * PM handlers to call PWRI2C handlers when appropriate. */
|
1950 | 3f582262 | balrog | s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 1); |
1951 | 3f582262 | balrog | s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0); |
1952 | 3f582262 | balrog | |
1953 | c1713132 | balrog | s->pm_base = 0x40f00000;
|
1954 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
|
1955 | c1713132 | balrog | pxa2xx_pm_writefn, s); |
1956 | c1713132 | balrog | cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype);
|
1957 | c1713132 | balrog | |
1958 | c1713132 | balrog | s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
|
1959 | c1713132 | balrog | |
1960 | c1713132 | balrog | /* GPIO1 resets the processor */
|
1961 | c1713132 | balrog | /* The handler can be overriden by board-specific code */
|
1962 | c1713132 | balrog | pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
|
1963 | c1713132 | balrog | return s;
|
1964 | c1713132 | balrog | } |