root / hw / pxa2xx_timer.c @ 3f582262
History | View | Annotate | Download (11.2 kB)
1 | a171fe39 | balrog | /*
|
---|---|---|---|
2 | a171fe39 | balrog | * Intel XScale PXA255/270 OS Timers.
|
3 | a171fe39 | balrog | *
|
4 | a171fe39 | balrog | * Copyright (c) 2006 Openedhand Ltd.
|
5 | a171fe39 | balrog | * Copyright (c) 2006 Thorsten Zitterell
|
6 | a171fe39 | balrog | *
|
7 | a171fe39 | balrog | * This code is licenced under the GPL.
|
8 | a171fe39 | balrog | */
|
9 | a171fe39 | balrog | |
10 | a171fe39 | balrog | #include "vl.h" |
11 | a171fe39 | balrog | |
12 | a171fe39 | balrog | #define OSMR0 0x00 |
13 | a171fe39 | balrog | #define OSMR1 0x04 |
14 | a171fe39 | balrog | #define OSMR2 0x08 |
15 | a171fe39 | balrog | #define OSMR3 0x0c |
16 | a171fe39 | balrog | #define OSMR4 0x80 |
17 | a171fe39 | balrog | #define OSMR5 0x84 |
18 | a171fe39 | balrog | #define OSMR6 0x88 |
19 | a171fe39 | balrog | #define OSMR7 0x8c |
20 | a171fe39 | balrog | #define OSMR8 0x90 |
21 | a171fe39 | balrog | #define OSMR9 0x94 |
22 | a171fe39 | balrog | #define OSMR10 0x98 |
23 | a171fe39 | balrog | #define OSMR11 0x9c |
24 | a171fe39 | balrog | #define OSCR 0x10 /* OS Timer Count */ |
25 | a171fe39 | balrog | #define OSCR4 0x40 |
26 | a171fe39 | balrog | #define OSCR5 0x44 |
27 | a171fe39 | balrog | #define OSCR6 0x48 |
28 | a171fe39 | balrog | #define OSCR7 0x4c |
29 | a171fe39 | balrog | #define OSCR8 0x50 |
30 | a171fe39 | balrog | #define OSCR9 0x54 |
31 | a171fe39 | balrog | #define OSCR10 0x58 |
32 | a171fe39 | balrog | #define OSCR11 0x5c |
33 | a171fe39 | balrog | #define OSSR 0x14 /* Timer status register */ |
34 | a171fe39 | balrog | #define OWER 0x18 |
35 | a171fe39 | balrog | #define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */ |
36 | a171fe39 | balrog | #define OMCR4 0xc0 /* OS Match Control registers */ |
37 | a171fe39 | balrog | #define OMCR5 0xc4 |
38 | a171fe39 | balrog | #define OMCR6 0xc8 |
39 | a171fe39 | balrog | #define OMCR7 0xcc |
40 | a171fe39 | balrog | #define OMCR8 0xd0 |
41 | a171fe39 | balrog | #define OMCR9 0xd4 |
42 | a171fe39 | balrog | #define OMCR10 0xd8 |
43 | a171fe39 | balrog | #define OMCR11 0xdc |
44 | a171fe39 | balrog | #define OSNR 0x20 |
45 | a171fe39 | balrog | |
46 | a171fe39 | balrog | #define PXA25X_FREQ 3686400 /* 3.6864 MHz */ |
47 | a171fe39 | balrog | #define PXA27X_FREQ 3250000 /* 3.25 MHz */ |
48 | a171fe39 | balrog | |
49 | a171fe39 | balrog | static int pxa2xx_timer4_freq[8] = { |
50 | a171fe39 | balrog | [0] = 0, |
51 | a171fe39 | balrog | [1] = 32768, |
52 | a171fe39 | balrog | [2] = 1000, |
53 | a171fe39 | balrog | [3] = 1, |
54 | a171fe39 | balrog | [4] = 1000000, |
55 | a171fe39 | balrog | /* [5] is the "Externally supplied clock". Assign if necessary. */
|
56 | a171fe39 | balrog | [5 ... 7] = 0, |
57 | a171fe39 | balrog | }; |
58 | a171fe39 | balrog | |
59 | a171fe39 | balrog | struct pxa2xx_timer0_s {
|
60 | a171fe39 | balrog | uint32_t value; |
61 | a171fe39 | balrog | int level;
|
62 | a171fe39 | balrog | qemu_irq irq; |
63 | a171fe39 | balrog | QEMUTimer *qtimer; |
64 | a171fe39 | balrog | int num;
|
65 | a171fe39 | balrog | void *info;
|
66 | a171fe39 | balrog | }; |
67 | a171fe39 | balrog | |
68 | a171fe39 | balrog | struct pxa2xx_timer4_s {
|
69 | 3bdd58a4 | balrog | struct pxa2xx_timer0_s tm;
|
70 | a171fe39 | balrog | int32_t oldclock; |
71 | a171fe39 | balrog | int32_t clock; |
72 | a171fe39 | balrog | uint64_t lastload; |
73 | a171fe39 | balrog | uint32_t freq; |
74 | a171fe39 | balrog | uint32_t control; |
75 | a171fe39 | balrog | }; |
76 | a171fe39 | balrog | |
77 | a171fe39 | balrog | typedef struct { |
78 | 3f582262 | balrog | target_phys_addr_t base; |
79 | a171fe39 | balrog | int32_t clock; |
80 | a171fe39 | balrog | int32_t oldclock; |
81 | a171fe39 | balrog | uint64_t lastload; |
82 | a171fe39 | balrog | uint32_t freq; |
83 | a171fe39 | balrog | struct pxa2xx_timer0_s timer[4]; |
84 | a171fe39 | balrog | struct pxa2xx_timer4_s *tm4;
|
85 | a171fe39 | balrog | uint32_t events; |
86 | a171fe39 | balrog | uint32_t irq_enabled; |
87 | a171fe39 | balrog | uint32_t reset3; |
88 | a171fe39 | balrog | uint32_t snapshot; |
89 | a171fe39 | balrog | } pxa2xx_timer_info; |
90 | a171fe39 | balrog | |
91 | a171fe39 | balrog | static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu) |
92 | a171fe39 | balrog | { |
93 | a171fe39 | balrog | pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
94 | a171fe39 | balrog | int i;
|
95 | a171fe39 | balrog | uint32_t now_vm; |
96 | a171fe39 | balrog | uint64_t new_qemu; |
97 | a171fe39 | balrog | |
98 | a171fe39 | balrog | now_vm = s->clock + |
99 | a171fe39 | balrog | muldiv64(now_qemu - s->lastload, s->freq, ticks_per_sec); |
100 | a171fe39 | balrog | |
101 | a171fe39 | balrog | for (i = 0; i < 4; i ++) { |
102 | a171fe39 | balrog | new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm), |
103 | a171fe39 | balrog | ticks_per_sec, s->freq); |
104 | a171fe39 | balrog | qemu_mod_timer(s->timer[i].qtimer, new_qemu); |
105 | a171fe39 | balrog | } |
106 | a171fe39 | balrog | } |
107 | a171fe39 | balrog | |
108 | a171fe39 | balrog | static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) |
109 | a171fe39 | balrog | { |
110 | a171fe39 | balrog | pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
111 | a171fe39 | balrog | uint32_t now_vm; |
112 | a171fe39 | balrog | uint64_t new_qemu; |
113 | a171fe39 | balrog | static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 }; |
114 | a171fe39 | balrog | int counter;
|
115 | a171fe39 | balrog | |
116 | a171fe39 | balrog | if (s->tm4[n].control & (1 << 7)) |
117 | a171fe39 | balrog | counter = n; |
118 | a171fe39 | balrog | else
|
119 | a171fe39 | balrog | counter = counters[n]; |
120 | a171fe39 | balrog | |
121 | a171fe39 | balrog | if (!s->tm4[counter].freq) {
|
122 | 3f582262 | balrog | qemu_del_timer(s->tm4[n].tm.qtimer); |
123 | a171fe39 | balrog | return;
|
124 | a171fe39 | balrog | } |
125 | a171fe39 | balrog | |
126 | a171fe39 | balrog | now_vm = s->tm4[counter].clock + muldiv64(now_qemu - |
127 | a171fe39 | balrog | s->tm4[counter].lastload, |
128 | a171fe39 | balrog | s->tm4[counter].freq, ticks_per_sec); |
129 | a171fe39 | balrog | |
130 | 3bdd58a4 | balrog | new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm), |
131 | a171fe39 | balrog | ticks_per_sec, s->tm4[counter].freq); |
132 | 3f582262 | balrog | qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu); |
133 | a171fe39 | balrog | } |
134 | a171fe39 | balrog | |
135 | a171fe39 | balrog | static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset) |
136 | a171fe39 | balrog | { |
137 | a171fe39 | balrog | pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
138 | a171fe39 | balrog | int tm = 0; |
139 | a171fe39 | balrog | |
140 | a171fe39 | balrog | offset -= s->base; |
141 | a171fe39 | balrog | |
142 | a171fe39 | balrog | switch (offset) {
|
143 | a171fe39 | balrog | case OSMR3: tm ++;
|
144 | a171fe39 | balrog | case OSMR2: tm ++;
|
145 | a171fe39 | balrog | case OSMR1: tm ++;
|
146 | a171fe39 | balrog | case OSMR0:
|
147 | a171fe39 | balrog | return s->timer[tm].value;
|
148 | a171fe39 | balrog | case OSMR11: tm ++;
|
149 | a171fe39 | balrog | case OSMR10: tm ++;
|
150 | a171fe39 | balrog | case OSMR9: tm ++;
|
151 | a171fe39 | balrog | case OSMR8: tm ++;
|
152 | a171fe39 | balrog | case OSMR7: tm ++;
|
153 | a171fe39 | balrog | case OSMR6: tm ++;
|
154 | a171fe39 | balrog | case OSMR5: tm ++;
|
155 | a171fe39 | balrog | case OSMR4:
|
156 | a171fe39 | balrog | if (!s->tm4)
|
157 | a171fe39 | balrog | goto badreg;
|
158 | 3bdd58a4 | balrog | return s->tm4[tm].tm.value;
|
159 | a171fe39 | balrog | case OSCR:
|
160 | a171fe39 | balrog | return s->clock + muldiv64(qemu_get_clock(vm_clock) -
|
161 | a171fe39 | balrog | s->lastload, s->freq, ticks_per_sec); |
162 | a171fe39 | balrog | case OSCR11: tm ++;
|
163 | a171fe39 | balrog | case OSCR10: tm ++;
|
164 | a171fe39 | balrog | case OSCR9: tm ++;
|
165 | a171fe39 | balrog | case OSCR8: tm ++;
|
166 | a171fe39 | balrog | case OSCR7: tm ++;
|
167 | a171fe39 | balrog | case OSCR6: tm ++;
|
168 | a171fe39 | balrog | case OSCR5: tm ++;
|
169 | a171fe39 | balrog | case OSCR4:
|
170 | a171fe39 | balrog | if (!s->tm4)
|
171 | a171fe39 | balrog | goto badreg;
|
172 | a171fe39 | balrog | |
173 | a171fe39 | balrog | if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) { |
174 | a171fe39 | balrog | if (s->tm4[tm - 1].freq) |
175 | a171fe39 | balrog | s->snapshot = s->tm4[tm - 1].clock + muldiv64(
|
176 | a171fe39 | balrog | qemu_get_clock(vm_clock) - |
177 | a171fe39 | balrog | s->tm4[tm - 1].lastload,
|
178 | a171fe39 | balrog | s->tm4[tm - 1].freq, ticks_per_sec);
|
179 | a171fe39 | balrog | else
|
180 | a171fe39 | balrog | s->snapshot = s->tm4[tm - 1].clock;
|
181 | a171fe39 | balrog | } |
182 | a171fe39 | balrog | |
183 | a171fe39 | balrog | if (!s->tm4[tm].freq)
|
184 | a171fe39 | balrog | return s->tm4[tm].clock;
|
185 | a171fe39 | balrog | return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
|
186 | a171fe39 | balrog | s->tm4[tm].lastload, s->tm4[tm].freq, ticks_per_sec); |
187 | a171fe39 | balrog | case OIER:
|
188 | a171fe39 | balrog | return s->irq_enabled;
|
189 | a171fe39 | balrog | case OSSR: /* Status register */ |
190 | a171fe39 | balrog | return s->events;
|
191 | a171fe39 | balrog | case OWER:
|
192 | a171fe39 | balrog | return s->reset3;
|
193 | a171fe39 | balrog | case OMCR11: tm ++;
|
194 | a171fe39 | balrog | case OMCR10: tm ++;
|
195 | a171fe39 | balrog | case OMCR9: tm ++;
|
196 | a171fe39 | balrog | case OMCR8: tm ++;
|
197 | a171fe39 | balrog | case OMCR7: tm ++;
|
198 | a171fe39 | balrog | case OMCR6: tm ++;
|
199 | a171fe39 | balrog | case OMCR5: tm ++;
|
200 | a171fe39 | balrog | case OMCR4:
|
201 | a171fe39 | balrog | if (!s->tm4)
|
202 | a171fe39 | balrog | goto badreg;
|
203 | a171fe39 | balrog | return s->tm4[tm].control;
|
204 | a171fe39 | balrog | case OSNR:
|
205 | a171fe39 | balrog | return s->snapshot;
|
206 | a171fe39 | balrog | default:
|
207 | a171fe39 | balrog | badreg:
|
208 | a171fe39 | balrog | cpu_abort(cpu_single_env, "pxa2xx_timer_read: Bad offset "
|
209 | a171fe39 | balrog | REG_FMT "\n", offset);
|
210 | a171fe39 | balrog | } |
211 | a171fe39 | balrog | |
212 | a171fe39 | balrog | return 0; |
213 | a171fe39 | balrog | } |
214 | a171fe39 | balrog | |
215 | a171fe39 | balrog | static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset, |
216 | a171fe39 | balrog | uint32_t value) |
217 | a171fe39 | balrog | { |
218 | a171fe39 | balrog | int i, tm = 0; |
219 | a171fe39 | balrog | pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
220 | a171fe39 | balrog | |
221 | a171fe39 | balrog | offset -= s->base; |
222 | a171fe39 | balrog | |
223 | a171fe39 | balrog | switch (offset) {
|
224 | a171fe39 | balrog | case OSMR3: tm ++;
|
225 | a171fe39 | balrog | case OSMR2: tm ++;
|
226 | a171fe39 | balrog | case OSMR1: tm ++;
|
227 | a171fe39 | balrog | case OSMR0:
|
228 | a171fe39 | balrog | s->timer[tm].value = value; |
229 | a171fe39 | balrog | pxa2xx_timer_update(s, qemu_get_clock(vm_clock)); |
230 | a171fe39 | balrog | break;
|
231 | a171fe39 | balrog | case OSMR11: tm ++;
|
232 | a171fe39 | balrog | case OSMR10: tm ++;
|
233 | a171fe39 | balrog | case OSMR9: tm ++;
|
234 | a171fe39 | balrog | case OSMR8: tm ++;
|
235 | a171fe39 | balrog | case OSMR7: tm ++;
|
236 | a171fe39 | balrog | case OSMR6: tm ++;
|
237 | a171fe39 | balrog | case OSMR5: tm ++;
|
238 | a171fe39 | balrog | case OSMR4:
|
239 | a171fe39 | balrog | if (!s->tm4)
|
240 | a171fe39 | balrog | goto badreg;
|
241 | 3bdd58a4 | balrog | s->tm4[tm].tm.value = value; |
242 | a171fe39 | balrog | pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
243 | a171fe39 | balrog | break;
|
244 | a171fe39 | balrog | case OSCR:
|
245 | a171fe39 | balrog | s->oldclock = s->clock; |
246 | a171fe39 | balrog | s->lastload = qemu_get_clock(vm_clock); |
247 | a171fe39 | balrog | s->clock = value; |
248 | a171fe39 | balrog | pxa2xx_timer_update(s, s->lastload); |
249 | a171fe39 | balrog | break;
|
250 | a171fe39 | balrog | case OSCR11: tm ++;
|
251 | a171fe39 | balrog | case OSCR10: tm ++;
|
252 | a171fe39 | balrog | case OSCR9: tm ++;
|
253 | a171fe39 | balrog | case OSCR8: tm ++;
|
254 | a171fe39 | balrog | case OSCR7: tm ++;
|
255 | a171fe39 | balrog | case OSCR6: tm ++;
|
256 | a171fe39 | balrog | case OSCR5: tm ++;
|
257 | a171fe39 | balrog | case OSCR4:
|
258 | a171fe39 | balrog | if (!s->tm4)
|
259 | a171fe39 | balrog | goto badreg;
|
260 | a171fe39 | balrog | s->tm4[tm].oldclock = s->tm4[tm].clock; |
261 | a171fe39 | balrog | s->tm4[tm].lastload = qemu_get_clock(vm_clock); |
262 | a171fe39 | balrog | s->tm4[tm].clock = value; |
263 | a171fe39 | balrog | pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm); |
264 | a171fe39 | balrog | break;
|
265 | a171fe39 | balrog | case OIER:
|
266 | a171fe39 | balrog | s->irq_enabled = value & 0xfff;
|
267 | a171fe39 | balrog | break;
|
268 | a171fe39 | balrog | case OSSR: /* Status register */ |
269 | a171fe39 | balrog | s->events &= ~value; |
270 | a171fe39 | balrog | for (i = 0; i < 4; i ++, value >>= 1) { |
271 | a171fe39 | balrog | if (s->timer[i].level && (value & 1)) { |
272 | a171fe39 | balrog | s->timer[i].level = 0;
|
273 | a171fe39 | balrog | qemu_irq_lower(s->timer[i].irq); |
274 | a171fe39 | balrog | } |
275 | a171fe39 | balrog | } |
276 | a171fe39 | balrog | if (s->tm4) {
|
277 | a171fe39 | balrog | for (i = 0; i < 8; i ++, value >>= 1) |
278 | 3bdd58a4 | balrog | if (s->tm4[i].tm.level && (value & 1)) |
279 | 3bdd58a4 | balrog | s->tm4[i].tm.level = 0;
|
280 | a171fe39 | balrog | if (!(s->events & 0xff0)) |
281 | 3bdd58a4 | balrog | qemu_irq_lower(s->tm4->tm.irq); |
282 | a171fe39 | balrog | } |
283 | a171fe39 | balrog | break;
|
284 | a171fe39 | balrog | case OWER: /* XXX: Reset on OSMR3 match? */ |
285 | a171fe39 | balrog | s->reset3 = value; |
286 | a171fe39 | balrog | break;
|
287 | a171fe39 | balrog | case OMCR7: tm ++;
|
288 | a171fe39 | balrog | case OMCR6: tm ++;
|
289 | a171fe39 | balrog | case OMCR5: tm ++;
|
290 | a171fe39 | balrog | case OMCR4:
|
291 | a171fe39 | balrog | if (!s->tm4)
|
292 | a171fe39 | balrog | goto badreg;
|
293 | a171fe39 | balrog | s->tm4[tm].control = value & 0x0ff;
|
294 | a171fe39 | balrog | /* XXX Stop if running (shouldn't happen) */
|
295 | a171fe39 | balrog | if ((value & (1 << 7)) || tm == 0) |
296 | a171fe39 | balrog | s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
|
297 | a171fe39 | balrog | else {
|
298 | a171fe39 | balrog | s->tm4[tm].freq = 0;
|
299 | a171fe39 | balrog | pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
300 | a171fe39 | balrog | } |
301 | a171fe39 | balrog | break;
|
302 | a171fe39 | balrog | case OMCR11: tm ++;
|
303 | a171fe39 | balrog | case OMCR10: tm ++;
|
304 | a171fe39 | balrog | case OMCR9: tm ++;
|
305 | a171fe39 | balrog | case OMCR8: tm += 4; |
306 | a171fe39 | balrog | if (!s->tm4)
|
307 | a171fe39 | balrog | goto badreg;
|
308 | a171fe39 | balrog | s->tm4[tm].control = value & 0x3ff;
|
309 | a171fe39 | balrog | /* XXX Stop if running (shouldn't happen) */
|
310 | a171fe39 | balrog | if ((value & (1 << 7)) || !(tm & 1)) |
311 | a171fe39 | balrog | s->tm4[tm].freq = |
312 | a171fe39 | balrog | pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)]; |
313 | a171fe39 | balrog | else {
|
314 | a171fe39 | balrog | s->tm4[tm].freq = 0;
|
315 | a171fe39 | balrog | pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
316 | a171fe39 | balrog | } |
317 | a171fe39 | balrog | break;
|
318 | a171fe39 | balrog | default:
|
319 | a171fe39 | balrog | badreg:
|
320 | a171fe39 | balrog | cpu_abort(cpu_single_env, "pxa2xx_timer_write: Bad offset "
|
321 | a171fe39 | balrog | REG_FMT "\n", offset);
|
322 | a171fe39 | balrog | } |
323 | a171fe39 | balrog | } |
324 | a171fe39 | balrog | |
325 | a171fe39 | balrog | static CPUReadMemoryFunc *pxa2xx_timer_readfn[] = {
|
326 | a171fe39 | balrog | pxa2xx_timer_read, |
327 | a171fe39 | balrog | pxa2xx_timer_read, |
328 | a171fe39 | balrog | pxa2xx_timer_read, |
329 | a171fe39 | balrog | }; |
330 | a171fe39 | balrog | |
331 | a171fe39 | balrog | static CPUWriteMemoryFunc *pxa2xx_timer_writefn[] = {
|
332 | a171fe39 | balrog | pxa2xx_timer_write, |
333 | a171fe39 | balrog | pxa2xx_timer_write, |
334 | a171fe39 | balrog | pxa2xx_timer_write, |
335 | a171fe39 | balrog | }; |
336 | a171fe39 | balrog | |
337 | a171fe39 | balrog | static void pxa2xx_timer_tick(void *opaque) |
338 | a171fe39 | balrog | { |
339 | a171fe39 | balrog | struct pxa2xx_timer0_s *t = (struct pxa2xx_timer0_s *) opaque; |
340 | a171fe39 | balrog | pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info; |
341 | a171fe39 | balrog | |
342 | a171fe39 | balrog | if (i->irq_enabled & (1 << t->num)) { |
343 | a171fe39 | balrog | t->level = 1;
|
344 | a171fe39 | balrog | i->events |= 1 << t->num;
|
345 | a171fe39 | balrog | qemu_irq_raise(t->irq); |
346 | a171fe39 | balrog | } |
347 | a171fe39 | balrog | |
348 | a171fe39 | balrog | if (t->num == 3) |
349 | a171fe39 | balrog | if (i->reset3 & 1) { |
350 | a171fe39 | balrog | i->reset3 = 0;
|
351 | 3f582262 | balrog | qemu_system_reset_request(); |
352 | a171fe39 | balrog | } |
353 | a171fe39 | balrog | } |
354 | a171fe39 | balrog | |
355 | a171fe39 | balrog | static void pxa2xx_timer_tick4(void *opaque) |
356 | a171fe39 | balrog | { |
357 | a171fe39 | balrog | struct pxa2xx_timer4_s *t = (struct pxa2xx_timer4_s *) opaque; |
358 | 3bdd58a4 | balrog | pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->tm.info; |
359 | a171fe39 | balrog | |
360 | 3bdd58a4 | balrog | pxa2xx_timer_tick(&t->tm); |
361 | a171fe39 | balrog | if (t->control & (1 << 3)) |
362 | a171fe39 | balrog | t->clock = 0;
|
363 | a171fe39 | balrog | if (t->control & (1 << 6)) |
364 | 3bdd58a4 | balrog | pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4);
|
365 | a171fe39 | balrog | } |
366 | a171fe39 | balrog | |
367 | a171fe39 | balrog | static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
|
368 | 3f582262 | balrog | qemu_irq *irqs) |
369 | a171fe39 | balrog | { |
370 | a171fe39 | balrog | int i;
|
371 | a171fe39 | balrog | int iomemtype;
|
372 | a171fe39 | balrog | pxa2xx_timer_info *s; |
373 | a171fe39 | balrog | |
374 | a171fe39 | balrog | s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
|
375 | a171fe39 | balrog | s->base = base; |
376 | a171fe39 | balrog | s->irq_enabled = 0;
|
377 | a171fe39 | balrog | s->oldclock = 0;
|
378 | a171fe39 | balrog | s->clock = 0;
|
379 | a171fe39 | balrog | s->lastload = qemu_get_clock(vm_clock); |
380 | a171fe39 | balrog | s->reset3 = 0;
|
381 | a171fe39 | balrog | |
382 | a171fe39 | balrog | for (i = 0; i < 4; i ++) { |
383 | a171fe39 | balrog | s->timer[i].value = 0;
|
384 | a171fe39 | balrog | s->timer[i].irq = irqs[i]; |
385 | a171fe39 | balrog | s->timer[i].info = s; |
386 | a171fe39 | balrog | s->timer[i].num = i; |
387 | a171fe39 | balrog | s->timer[i].level = 0;
|
388 | a171fe39 | balrog | s->timer[i].qtimer = qemu_new_timer(vm_clock, |
389 | a171fe39 | balrog | pxa2xx_timer_tick, &s->timer[i]); |
390 | a171fe39 | balrog | } |
391 | a171fe39 | balrog | |
392 | a171fe39 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn,
|
393 | a171fe39 | balrog | pxa2xx_timer_writefn, s); |
394 | a171fe39 | balrog | cpu_register_physical_memory(base, 0x00000fff, iomemtype);
|
395 | a171fe39 | balrog | return s;
|
396 | a171fe39 | balrog | } |
397 | a171fe39 | balrog | |
398 | 3f582262 | balrog | void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs)
|
399 | a171fe39 | balrog | { |
400 | 3f582262 | balrog | pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs); |
401 | a171fe39 | balrog | s->freq = PXA25X_FREQ; |
402 | a171fe39 | balrog | s->tm4 = 0;
|
403 | a171fe39 | balrog | } |
404 | a171fe39 | balrog | |
405 | a171fe39 | balrog | void pxa27x_timer_init(target_phys_addr_t base,
|
406 | 3f582262 | balrog | qemu_irq *irqs, qemu_irq irq4) |
407 | a171fe39 | balrog | { |
408 | 3f582262 | balrog | pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs); |
409 | a171fe39 | balrog | int i;
|
410 | a171fe39 | balrog | s->freq = PXA27X_FREQ; |
411 | a171fe39 | balrog | s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 * |
412 | a171fe39 | balrog | sizeof(struct pxa2xx_timer4_s)); |
413 | a171fe39 | balrog | for (i = 0; i < 8; i ++) { |
414 | 3bdd58a4 | balrog | s->tm4[i].tm.value = 0;
|
415 | 3bdd58a4 | balrog | s->tm4[i].tm.irq = irq4; |
416 | 3bdd58a4 | balrog | s->tm4[i].tm.info = s; |
417 | 3bdd58a4 | balrog | s->tm4[i].tm.num = i + 4;
|
418 | 3bdd58a4 | balrog | s->tm4[i].tm.level = 0;
|
419 | a171fe39 | balrog | s->tm4[i].freq = 0;
|
420 | a171fe39 | balrog | s->tm4[i].control = 0x0;
|
421 | 3bdd58a4 | balrog | s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock, |
422 | a171fe39 | balrog | pxa2xx_timer_tick4, &s->tm4[i]); |
423 | a171fe39 | balrog | } |
424 | a171fe39 | balrog | } |