root / hw / arm_sysctl.c @ 3f66aa9c
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| 1 | 5fafdf24 | ths | /*
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| 2 | e69954b9 | pbrook | * Status and system control registers for ARM RealView/Versatile boards.
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| 3 | e69954b9 | pbrook | *
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| 4 | 9ee6e8bb | pbrook | * Copyright (c) 2006-2007 CodeSourcery.
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| 5 | e69954b9 | pbrook | * Written by Paul Brook
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| 6 | e69954b9 | pbrook | *
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| 7 | e69954b9 | pbrook | * This code is licenced under the GPL.
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| 8 | e69954b9 | pbrook | */
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| 9 | e69954b9 | pbrook | |
| 10 | 042eb37a | Daniel Jacobowitz | #include "hw.h" |
| 11 | 042eb37a | Daniel Jacobowitz | #include "qemu-timer.h" |
| 12 | 82634c2d | Paul Brook | #include "sysbus.h" |
| 13 | 9596ebb7 | pbrook | #include "primecell.h" |
| 14 | 87ecb68b | pbrook | #include "sysemu.h" |
| 15 | e69954b9 | pbrook | |
| 16 | e69954b9 | pbrook | #define LOCK_VALUE 0xa05f |
| 17 | e69954b9 | pbrook | |
| 18 | e69954b9 | pbrook | typedef struct { |
| 19 | 82634c2d | Paul Brook | SysBusDevice busdev; |
| 20 | e69954b9 | pbrook | uint32_t sys_id; |
| 21 | e69954b9 | pbrook | uint32_t leds; |
| 22 | e69954b9 | pbrook | uint16_t lockval; |
| 23 | e69954b9 | pbrook | uint32_t cfgdata1; |
| 24 | e69954b9 | pbrook | uint32_t cfgdata2; |
| 25 | e69954b9 | pbrook | uint32_t flags; |
| 26 | e69954b9 | pbrook | uint32_t nvflags; |
| 27 | e69954b9 | pbrook | uint32_t resetlevel; |
| 28 | e69954b9 | pbrook | } arm_sysctl_state; |
| 29 | e69954b9 | pbrook | |
| 30 | c227f099 | Anthony Liguori | static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset) |
| 31 | e69954b9 | pbrook | {
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| 32 | e69954b9 | pbrook | arm_sysctl_state *s = (arm_sysctl_state *)opaque; |
| 33 | e69954b9 | pbrook | |
| 34 | e69954b9 | pbrook | switch (offset) {
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| 35 | e69954b9 | pbrook | case 0x00: /* ID */ |
| 36 | e69954b9 | pbrook | return s->sys_id;
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| 37 | e69954b9 | pbrook | case 0x04: /* SW */ |
| 38 | e69954b9 | pbrook | /* General purpose hardware switches.
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| 39 | e69954b9 | pbrook | We don't have a useful way of exposing these to the user. */
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| 40 | e69954b9 | pbrook | return 0; |
| 41 | e69954b9 | pbrook | case 0x08: /* LED */ |
| 42 | e69954b9 | pbrook | return s->leds;
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| 43 | e69954b9 | pbrook | case 0x20: /* LOCK */ |
| 44 | e69954b9 | pbrook | return s->lockval;
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| 45 | e69954b9 | pbrook | case 0x0c: /* OSC0 */ |
| 46 | e69954b9 | pbrook | case 0x10: /* OSC1 */ |
| 47 | e69954b9 | pbrook | case 0x14: /* OSC2 */ |
| 48 | e69954b9 | pbrook | case 0x18: /* OSC3 */ |
| 49 | e69954b9 | pbrook | case 0x1c: /* OSC4 */ |
| 50 | e69954b9 | pbrook | case 0x24: /* 100HZ */ |
| 51 | e69954b9 | pbrook | /* ??? Implement these. */
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| 52 | e69954b9 | pbrook | return 0; |
| 53 | e69954b9 | pbrook | case 0x28: /* CFGDATA1 */ |
| 54 | e69954b9 | pbrook | return s->cfgdata1;
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| 55 | e69954b9 | pbrook | case 0x2c: /* CFGDATA2 */ |
| 56 | e69954b9 | pbrook | return s->cfgdata2;
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| 57 | e69954b9 | pbrook | case 0x30: /* FLAGS */ |
| 58 | e69954b9 | pbrook | return s->flags;
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| 59 | e69954b9 | pbrook | case 0x38: /* NVFLAGS */ |
| 60 | e69954b9 | pbrook | return s->nvflags;
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| 61 | e69954b9 | pbrook | case 0x40: /* RESETCTL */ |
| 62 | e69954b9 | pbrook | return s->resetlevel;
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| 63 | e69954b9 | pbrook | case 0x44: /* PCICTL */ |
| 64 | e69954b9 | pbrook | return 1; |
| 65 | e69954b9 | pbrook | case 0x48: /* MCI */ |
| 66 | e69954b9 | pbrook | return 0; |
| 67 | e69954b9 | pbrook | case 0x4c: /* FLASH */ |
| 68 | e69954b9 | pbrook | return 0; |
| 69 | e69954b9 | pbrook | case 0x50: /* CLCD */ |
| 70 | e69954b9 | pbrook | return 0x1000; |
| 71 | e69954b9 | pbrook | case 0x54: /* CLCDSER */ |
| 72 | e69954b9 | pbrook | return 0; |
| 73 | e69954b9 | pbrook | case 0x58: /* BOOTCS */ |
| 74 | e69954b9 | pbrook | return 0; |
| 75 | e69954b9 | pbrook | case 0x5c: /* 24MHz */ |
| 76 | 042eb37a | Daniel Jacobowitz | return muldiv64(qemu_get_clock(vm_clock), 24000000, get_ticks_per_sec()); |
| 77 | e69954b9 | pbrook | case 0x60: /* MISC */ |
| 78 | e69954b9 | pbrook | return 0; |
| 79 | e69954b9 | pbrook | case 0x84: /* PROCID0 */ |
| 80 | e69954b9 | pbrook | /* ??? Don't know what the proper value for the core tile ID is. */
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| 81 | e69954b9 | pbrook | return 0x02000000; |
| 82 | e69954b9 | pbrook | case 0x88: /* PROCID1 */ |
| 83 | e69954b9 | pbrook | return 0xff000000; |
| 84 | e69954b9 | pbrook | case 0x64: /* DMAPSR0 */ |
| 85 | e69954b9 | pbrook | case 0x68: /* DMAPSR1 */ |
| 86 | e69954b9 | pbrook | case 0x6c: /* DMAPSR2 */ |
| 87 | e69954b9 | pbrook | case 0x70: /* IOSEL */ |
| 88 | e69954b9 | pbrook | case 0x74: /* PLDCTL */ |
| 89 | e69954b9 | pbrook | case 0x80: /* BUSID */ |
| 90 | e69954b9 | pbrook | case 0x8c: /* OSCRESET0 */ |
| 91 | e69954b9 | pbrook | case 0x90: /* OSCRESET1 */ |
| 92 | e69954b9 | pbrook | case 0x94: /* OSCRESET2 */ |
| 93 | e69954b9 | pbrook | case 0x98: /* OSCRESET3 */ |
| 94 | e69954b9 | pbrook | case 0x9c: /* OSCRESET4 */ |
| 95 | e69954b9 | pbrook | case 0xc0: /* SYS_TEST_OSC0 */ |
| 96 | e69954b9 | pbrook | case 0xc4: /* SYS_TEST_OSC1 */ |
| 97 | e69954b9 | pbrook | case 0xc8: /* SYS_TEST_OSC2 */ |
| 98 | e69954b9 | pbrook | case 0xcc: /* SYS_TEST_OSC3 */ |
| 99 | e69954b9 | pbrook | case 0xd0: /* SYS_TEST_OSC4 */ |
| 100 | e69954b9 | pbrook | return 0; |
| 101 | e69954b9 | pbrook | default:
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| 102 | e69954b9 | pbrook | printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset); |
| 103 | e69954b9 | pbrook | return 0; |
| 104 | e69954b9 | pbrook | } |
| 105 | e69954b9 | pbrook | } |
| 106 | e69954b9 | pbrook | |
| 107 | c227f099 | Anthony Liguori | static void arm_sysctl_write(void *opaque, target_phys_addr_t offset, |
| 108 | e69954b9 | pbrook | uint32_t val) |
| 109 | e69954b9 | pbrook | {
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| 110 | e69954b9 | pbrook | arm_sysctl_state *s = (arm_sysctl_state *)opaque; |
| 111 | e69954b9 | pbrook | |
| 112 | e69954b9 | pbrook | switch (offset) {
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| 113 | e69954b9 | pbrook | case 0x08: /* LED */ |
| 114 | e69954b9 | pbrook | s->leds = val; |
| 115 | e69954b9 | pbrook | case 0x0c: /* OSC0 */ |
| 116 | e69954b9 | pbrook | case 0x10: /* OSC1 */ |
| 117 | e69954b9 | pbrook | case 0x14: /* OSC2 */ |
| 118 | e69954b9 | pbrook | case 0x18: /* OSC3 */ |
| 119 | e69954b9 | pbrook | case 0x1c: /* OSC4 */ |
| 120 | e69954b9 | pbrook | /* ??? */
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| 121 | e69954b9 | pbrook | break;
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| 122 | e69954b9 | pbrook | case 0x20: /* LOCK */ |
| 123 | e69954b9 | pbrook | if (val == LOCK_VALUE)
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| 124 | e69954b9 | pbrook | s->lockval = val; |
| 125 | e69954b9 | pbrook | else
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| 126 | e69954b9 | pbrook | s->lockval = val & 0x7fff;
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| 127 | e69954b9 | pbrook | break;
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| 128 | e69954b9 | pbrook | case 0x28: /* CFGDATA1 */ |
| 129 | e69954b9 | pbrook | /* ??? Need to implement this. */
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| 130 | e69954b9 | pbrook | s->cfgdata1 = val; |
| 131 | e69954b9 | pbrook | break;
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| 132 | e69954b9 | pbrook | case 0x2c: /* CFGDATA2 */ |
| 133 | e69954b9 | pbrook | /* ??? Need to implement this. */
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| 134 | e69954b9 | pbrook | s->cfgdata2 = val; |
| 135 | e69954b9 | pbrook | break;
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| 136 | e69954b9 | pbrook | case 0x30: /* FLAGSSET */ |
| 137 | e69954b9 | pbrook | s->flags |= val; |
| 138 | e69954b9 | pbrook | break;
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| 139 | e69954b9 | pbrook | case 0x34: /* FLAGSCLR */ |
| 140 | e69954b9 | pbrook | s->flags &= ~val; |
| 141 | e69954b9 | pbrook | break;
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| 142 | e69954b9 | pbrook | case 0x38: /* NVFLAGSSET */ |
| 143 | e69954b9 | pbrook | s->nvflags |= val; |
| 144 | e69954b9 | pbrook | break;
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| 145 | e69954b9 | pbrook | case 0x3c: /* NVFLAGSCLR */ |
| 146 | e69954b9 | pbrook | s->nvflags &= ~val; |
| 147 | e69954b9 | pbrook | break;
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| 148 | e69954b9 | pbrook | case 0x40: /* RESETCTL */ |
| 149 | e69954b9 | pbrook | if (s->lockval == LOCK_VALUE) {
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| 150 | e69954b9 | pbrook | s->resetlevel = val; |
| 151 | e69954b9 | pbrook | if (val & 0x100) |
| 152 | f3d6b95e | pbrook | qemu_system_reset_request (); |
| 153 | e69954b9 | pbrook | } |
| 154 | e69954b9 | pbrook | break;
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| 155 | e69954b9 | pbrook | case 0x44: /* PCICTL */ |
| 156 | e69954b9 | pbrook | /* nothing to do. */
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| 157 | e69954b9 | pbrook | break;
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| 158 | e69954b9 | pbrook | case 0x4c: /* FLASH */ |
| 159 | e69954b9 | pbrook | case 0x50: /* CLCD */ |
| 160 | e69954b9 | pbrook | case 0x54: /* CLCDSER */ |
| 161 | e69954b9 | pbrook | case 0x64: /* DMAPSR0 */ |
| 162 | e69954b9 | pbrook | case 0x68: /* DMAPSR1 */ |
| 163 | e69954b9 | pbrook | case 0x6c: /* DMAPSR2 */ |
| 164 | e69954b9 | pbrook | case 0x70: /* IOSEL */ |
| 165 | e69954b9 | pbrook | case 0x74: /* PLDCTL */ |
| 166 | e69954b9 | pbrook | case 0x80: /* BUSID */ |
| 167 | e69954b9 | pbrook | case 0x84: /* PROCID0 */ |
| 168 | e69954b9 | pbrook | case 0x88: /* PROCID1 */ |
| 169 | e69954b9 | pbrook | case 0x8c: /* OSCRESET0 */ |
| 170 | e69954b9 | pbrook | case 0x90: /* OSCRESET1 */ |
| 171 | e69954b9 | pbrook | case 0x94: /* OSCRESET2 */ |
| 172 | e69954b9 | pbrook | case 0x98: /* OSCRESET3 */ |
| 173 | e69954b9 | pbrook | case 0x9c: /* OSCRESET4 */ |
| 174 | e69954b9 | pbrook | break;
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| 175 | e69954b9 | pbrook | default:
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| 176 | e69954b9 | pbrook | printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset); |
| 177 | e69954b9 | pbrook | return;
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| 178 | e69954b9 | pbrook | } |
| 179 | e69954b9 | pbrook | } |
| 180 | e69954b9 | pbrook | |
| 181 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const arm_sysctl_readfn[] = { |
| 182 | e69954b9 | pbrook | arm_sysctl_read, |
| 183 | e69954b9 | pbrook | arm_sysctl_read, |
| 184 | e69954b9 | pbrook | arm_sysctl_read |
| 185 | e69954b9 | pbrook | }; |
| 186 | e69954b9 | pbrook | |
| 187 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = { |
| 188 | e69954b9 | pbrook | arm_sysctl_write, |
| 189 | e69954b9 | pbrook | arm_sysctl_write, |
| 190 | e69954b9 | pbrook | arm_sysctl_write |
| 191 | e69954b9 | pbrook | }; |
| 192 | e69954b9 | pbrook | |
| 193 | 81a322d4 | Gerd Hoffmann | static int arm_sysctl_init1(SysBusDevice *dev) |
| 194 | e69954b9 | pbrook | {
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| 195 | 82634c2d | Paul Brook | arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev); |
| 196 | e69954b9 | pbrook | int iomemtype;
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| 197 | e69954b9 | pbrook | |
| 198 | 9ee6e8bb | pbrook | /* The MPcore bootloader uses these flags to start secondary CPUs.
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| 199 | 9ee6e8bb | pbrook | We don't use a bootloader, so do this here. */
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| 200 | 9ee6e8bb | pbrook | s->flags = 3;
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| 201 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(arm_sysctl_readfn, |
| 202 | e69954b9 | pbrook | arm_sysctl_writefn, s); |
| 203 | 82634c2d | Paul Brook | sysbus_init_mmio(dev, 0x1000, iomemtype);
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| 204 | e69954b9 | pbrook | /* ??? Save/restore. */
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| 205 | 81a322d4 | Gerd Hoffmann | return 0; |
| 206 | e69954b9 | pbrook | } |
| 207 | 82634c2d | Paul Brook | |
| 208 | 82634c2d | Paul Brook | /* Legacy helper function. */
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| 209 | 82634c2d | Paul Brook | void arm_sysctl_init(uint32_t base, uint32_t sys_id)
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| 210 | 82634c2d | Paul Brook | {
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| 211 | 82634c2d | Paul Brook | DeviceState *dev; |
| 212 | 82634c2d | Paul Brook | |
| 213 | 82634c2d | Paul Brook | dev = qdev_create(NULL, "realview_sysctl"); |
| 214 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_uint32(dev, "sys_id", sys_id);
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| 215 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
| 216 | 82634c2d | Paul Brook | sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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| 217 | 82634c2d | Paul Brook | } |
| 218 | 82634c2d | Paul Brook | |
| 219 | ee6847d1 | Gerd Hoffmann | static SysBusDeviceInfo arm_sysctl_info = {
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| 220 | ee6847d1 | Gerd Hoffmann | .init = arm_sysctl_init1, |
| 221 | ee6847d1 | Gerd Hoffmann | .qdev.name = "realview_sysctl",
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| 222 | ee6847d1 | Gerd Hoffmann | .qdev.size = sizeof(arm_sysctl_state),
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| 223 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) {
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| 224 | e325775b | Gerd Hoffmann | DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0), |
| 225 | e325775b | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
| 226 | ee6847d1 | Gerd Hoffmann | } |
| 227 | ee6847d1 | Gerd Hoffmann | }; |
| 228 | ee6847d1 | Gerd Hoffmann | |
| 229 | 82634c2d | Paul Brook | static void arm_sysctl_register_devices(void) |
| 230 | 82634c2d | Paul Brook | {
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| 231 | ee6847d1 | Gerd Hoffmann | sysbus_register_withprop(&arm_sysctl_info); |
| 232 | 82634c2d | Paul Brook | } |
| 233 | 82634c2d | Paul Brook | |
| 234 | 82634c2d | Paul Brook | device_init(arm_sysctl_register_devices) |