Revision 3fbb33d0
| b/hw/cirrus_vga.c | ||
|---|---|---|
| 2004 | 2004 |
static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr) |
| 2005 | 2005 |
{
|
| 2006 | 2006 |
uint32_t v; |
| 2007 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2008 |
v = cirrus_vga_mem_readb(opaque, addr) << 8; |
|
| 2009 |
v |= cirrus_vga_mem_readb(opaque, addr + 1); |
|
| 2010 |
#else |
|
| 2007 |
|
|
| 2011 | 2008 |
v = cirrus_vga_mem_readb(opaque, addr); |
| 2012 | 2009 |
v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8; |
| 2013 |
#endif |
|
| 2014 | 2010 |
return v; |
| 2015 | 2011 |
} |
| 2016 | 2012 |
|
| 2017 | 2013 |
static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr) |
| 2018 | 2014 |
{
|
| 2019 | 2015 |
uint32_t v; |
| 2020 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2021 |
v = cirrus_vga_mem_readb(opaque, addr) << 24; |
|
| 2022 |
v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16; |
|
| 2023 |
v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8; |
|
| 2024 |
v |= cirrus_vga_mem_readb(opaque, addr + 3); |
|
| 2025 |
#else |
|
| 2016 |
|
|
| 2026 | 2017 |
v = cirrus_vga_mem_readb(opaque, addr); |
| 2027 | 2018 |
v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8; |
| 2028 | 2019 |
v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16; |
| 2029 | 2020 |
v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24; |
| 2030 |
#endif |
|
| 2031 | 2021 |
return v; |
| 2032 | 2022 |
} |
| 2033 | 2023 |
|
| ... | ... | |
| 2098 | 2088 |
|
| 2099 | 2089 |
static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 2100 | 2090 |
{
|
| 2101 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2102 |
cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff); |
|
| 2103 |
cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff); |
|
| 2104 |
#else |
|
| 2105 | 2091 |
cirrus_vga_mem_writeb(opaque, addr, val & 0xff); |
| 2106 | 2092 |
cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
| 2107 |
#endif |
|
| 2108 | 2093 |
} |
| 2109 | 2094 |
|
| 2110 | 2095 |
static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 2111 | 2096 |
{
|
| 2112 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2113 |
cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff); |
|
| 2114 |
cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
|
| 2115 |
cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
|
| 2116 |
cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff); |
|
| 2117 |
#else |
|
| 2118 | 2097 |
cirrus_vga_mem_writeb(opaque, addr, val & 0xff); |
| 2119 | 2098 |
cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
| 2120 | 2099 |
cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
| 2121 | 2100 |
cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
| 2122 |
#endif |
|
| 2123 | 2101 |
} |
| 2124 | 2102 |
|
| 2125 | 2103 |
static CPUReadMemoryFunc * const cirrus_vga_mem_read[3] = {
|
| ... | ... | |
| 2341 | 2319 |
static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr) |
| 2342 | 2320 |
{
|
| 2343 | 2321 |
uint32_t v; |
| 2344 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2345 |
v = cirrus_linear_readb(opaque, addr) << 8; |
|
| 2346 |
v |= cirrus_linear_readb(opaque, addr + 1); |
|
| 2347 |
#else |
|
| 2322 |
|
|
| 2348 | 2323 |
v = cirrus_linear_readb(opaque, addr); |
| 2349 | 2324 |
v |= cirrus_linear_readb(opaque, addr + 1) << 8; |
| 2350 |
#endif |
|
| 2351 | 2325 |
return v; |
| 2352 | 2326 |
} |
| 2353 | 2327 |
|
| 2354 | 2328 |
static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr) |
| 2355 | 2329 |
{
|
| 2356 | 2330 |
uint32_t v; |
| 2357 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2358 |
v = cirrus_linear_readb(opaque, addr) << 24; |
|
| 2359 |
v |= cirrus_linear_readb(opaque, addr + 1) << 16; |
|
| 2360 |
v |= cirrus_linear_readb(opaque, addr + 2) << 8; |
|
| 2361 |
v |= cirrus_linear_readb(opaque, addr + 3); |
|
| 2362 |
#else |
|
| 2331 |
|
|
| 2363 | 2332 |
v = cirrus_linear_readb(opaque, addr); |
| 2364 | 2333 |
v |= cirrus_linear_readb(opaque, addr + 1) << 8; |
| 2365 | 2334 |
v |= cirrus_linear_readb(opaque, addr + 2) << 16; |
| 2366 | 2335 |
v |= cirrus_linear_readb(opaque, addr + 3) << 24; |
| 2367 |
#endif |
|
| 2368 | 2336 |
return v; |
| 2369 | 2337 |
} |
| 2370 | 2338 |
|
| ... | ... | |
| 2412 | 2380 |
static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr, |
| 2413 | 2381 |
uint32_t val) |
| 2414 | 2382 |
{
|
| 2415 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2416 |
cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff); |
|
| 2417 |
cirrus_linear_writeb(opaque, addr + 1, val & 0xff); |
|
| 2418 |
#else |
|
| 2419 | 2383 |
cirrus_linear_writeb(opaque, addr, val & 0xff); |
| 2420 | 2384 |
cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
| 2421 |
#endif |
|
| 2422 | 2385 |
} |
| 2423 | 2386 |
|
| 2424 | 2387 |
static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr, |
| 2425 | 2388 |
uint32_t val) |
| 2426 | 2389 |
{
|
| 2427 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2428 |
cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff); |
|
| 2429 |
cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
|
| 2430 |
cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
|
| 2431 |
cirrus_linear_writeb(opaque, addr + 3, val & 0xff); |
|
| 2432 |
#else |
|
| 2433 | 2390 |
cirrus_linear_writeb(opaque, addr, val & 0xff); |
| 2434 | 2391 |
cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
| 2435 | 2392 |
cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
| 2436 | 2393 |
cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
| 2437 |
#endif |
|
| 2438 | 2394 |
} |
| 2439 | 2395 |
|
| 2440 | 2396 |
|
| ... | ... | |
| 2469 | 2425 |
static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr) |
| 2470 | 2426 |
{
|
| 2471 | 2427 |
uint32_t v; |
| 2472 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2473 |
v = cirrus_linear_bitblt_readb(opaque, addr) << 8; |
|
| 2474 |
v |= cirrus_linear_bitblt_readb(opaque, addr + 1); |
|
| 2475 |
#else |
|
| 2428 |
|
|
| 2476 | 2429 |
v = cirrus_linear_bitblt_readb(opaque, addr); |
| 2477 | 2430 |
v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8; |
| 2478 |
#endif |
|
| 2479 | 2431 |
return v; |
| 2480 | 2432 |
} |
| 2481 | 2433 |
|
| 2482 | 2434 |
static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr) |
| 2483 | 2435 |
{
|
| 2484 | 2436 |
uint32_t v; |
| 2485 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2486 |
v = cirrus_linear_bitblt_readb(opaque, addr) << 24; |
|
| 2487 |
v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16; |
|
| 2488 |
v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8; |
|
| 2489 |
v |= cirrus_linear_bitblt_readb(opaque, addr + 3); |
|
| 2490 |
#else |
|
| 2437 |
|
|
| 2491 | 2438 |
v = cirrus_linear_bitblt_readb(opaque, addr); |
| 2492 | 2439 |
v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8; |
| 2493 | 2440 |
v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16; |
| 2494 | 2441 |
v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24; |
| 2495 |
#endif |
|
| 2496 | 2442 |
return v; |
| 2497 | 2443 |
} |
| 2498 | 2444 |
|
| ... | ... | |
| 2513 | 2459 |
static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr, |
| 2514 | 2460 |
uint32_t val) |
| 2515 | 2461 |
{
|
| 2516 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2517 |
cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff); |
|
| 2518 |
cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff); |
|
| 2519 |
#else |
|
| 2520 | 2462 |
cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff); |
| 2521 | 2463 |
cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
| 2522 |
#endif |
|
| 2523 | 2464 |
} |
| 2524 | 2465 |
|
| 2525 | 2466 |
static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr, |
| 2526 | 2467 |
uint32_t val) |
| 2527 | 2468 |
{
|
| 2528 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2529 |
cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff); |
|
| 2530 |
cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
|
| 2531 |
cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
|
| 2532 |
cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff); |
|
| 2533 |
#else |
|
| 2534 | 2469 |
cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff); |
| 2535 | 2470 |
cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
| 2536 | 2471 |
cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
| 2537 | 2472 |
cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
| 2538 |
#endif |
|
| 2539 | 2473 |
} |
| 2540 | 2474 |
|
| 2541 | 2475 |
|
| ... | ... | |
| 2842 | 2776 |
static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr) |
| 2843 | 2777 |
{
|
| 2844 | 2778 |
uint32_t v; |
| 2845 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2846 |
v = cirrus_mmio_readb(opaque, addr) << 8; |
|
| 2847 |
v |= cirrus_mmio_readb(opaque, addr + 1); |
|
| 2848 |
#else |
|
| 2779 |
|
|
| 2849 | 2780 |
v = cirrus_mmio_readb(opaque, addr); |
| 2850 | 2781 |
v |= cirrus_mmio_readb(opaque, addr + 1) << 8; |
| 2851 |
#endif |
|
| 2852 | 2782 |
return v; |
| 2853 | 2783 |
} |
| 2854 | 2784 |
|
| 2855 | 2785 |
static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr) |
| 2856 | 2786 |
{
|
| 2857 | 2787 |
uint32_t v; |
| 2858 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2859 |
v = cirrus_mmio_readb(opaque, addr) << 24; |
|
| 2860 |
v |= cirrus_mmio_readb(opaque, addr + 1) << 16; |
|
| 2861 |
v |= cirrus_mmio_readb(opaque, addr + 2) << 8; |
|
| 2862 |
v |= cirrus_mmio_readb(opaque, addr + 3); |
|
| 2863 |
#else |
|
| 2788 |
|
|
| 2864 | 2789 |
v = cirrus_mmio_readb(opaque, addr); |
| 2865 | 2790 |
v |= cirrus_mmio_readb(opaque, addr + 1) << 8; |
| 2866 | 2791 |
v |= cirrus_mmio_readb(opaque, addr + 2) << 16; |
| 2867 | 2792 |
v |= cirrus_mmio_readb(opaque, addr + 3) << 24; |
| 2868 |
#endif |
|
| 2869 | 2793 |
return v; |
| 2870 | 2794 |
} |
| 2871 | 2795 |
|
| ... | ... | |
| 2886 | 2810 |
static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr, |
| 2887 | 2811 |
uint32_t val) |
| 2888 | 2812 |
{
|
| 2889 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2890 |
cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff); |
|
| 2891 |
cirrus_mmio_writeb(opaque, addr + 1, val & 0xff); |
|
| 2892 |
#else |
|
| 2893 | 2813 |
cirrus_mmio_writeb(opaque, addr, val & 0xff); |
| 2894 | 2814 |
cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
| 2895 |
#endif |
|
| 2896 | 2815 |
} |
| 2897 | 2816 |
|
| 2898 | 2817 |
static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr, |
| 2899 | 2818 |
uint32_t val) |
| 2900 | 2819 |
{
|
| 2901 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2902 |
cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff); |
|
| 2903 |
cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
|
| 2904 |
cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
|
| 2905 |
cirrus_mmio_writeb(opaque, addr + 3, val & 0xff); |
|
| 2906 |
#else |
|
| 2907 | 2820 |
cirrus_mmio_writeb(opaque, addr, val & 0xff); |
| 2908 | 2821 |
cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
| 2909 | 2822 |
cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
| 2910 | 2823 |
cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
| 2911 |
#endif |
|
| 2912 | 2824 |
} |
| 2913 | 2825 |
|
| 2914 | 2826 |
|
| ... | ... | |
| 3078 | 2990 |
|
| 3079 | 2991 |
s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read, |
| 3080 | 2992 |
cirrus_vga_mem_write, s, |
| 3081 |
DEVICE_NATIVE_ENDIAN);
|
|
| 2993 |
DEVICE_LITTLE_ENDIAN);
|
|
| 3082 | 2994 |
cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000, |
| 3083 | 2995 |
s->vga.vga_io_memory); |
| 3084 | 2996 |
qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000); |
| ... | ... | |
| 3086 | 2998 |
/* I/O handler for LFB */ |
| 3087 | 2999 |
s->cirrus_linear_io_addr = |
| 3088 | 3000 |
cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s, |
| 3089 |
DEVICE_NATIVE_ENDIAN);
|
|
| 3001 |
DEVICE_LITTLE_ENDIAN);
|
|
| 3090 | 3002 |
|
| 3091 | 3003 |
/* I/O handler for LFB */ |
| 3092 | 3004 |
s->cirrus_linear_bitblt_io_addr = |
| 3093 | 3005 |
cpu_register_io_memory(cirrus_linear_bitblt_read, |
| 3094 | 3006 |
cirrus_linear_bitblt_write, s, |
| 3095 |
DEVICE_NATIVE_ENDIAN);
|
|
| 3007 |
DEVICE_LITTLE_ENDIAN);
|
|
| 3096 | 3008 |
|
| 3097 | 3009 |
/* I/O handler for memory-mapped I/O */ |
| 3098 | 3010 |
s->cirrus_mmio_io_addr = |
| 3099 | 3011 |
cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s, |
| 3100 |
DEVICE_NATIVE_ENDIAN);
|
|
| 3012 |
DEVICE_LITTLE_ENDIAN);
|
|
| 3101 | 3013 |
|
| 3102 | 3014 |
s->real_vram_size = |
| 3103 | 3015 |
(s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; |
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