root / target-ppc / op_helper.c @ 3fc6c082
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1 | 9a64fbe4 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation helpers for qemu.
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3 | 9a64fbe4 | bellard | *
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4 | 3fc6c082 | bellard | * Copyright (c) 2003-2005 Jocelyn Mayer
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5 | 9a64fbe4 | bellard | *
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6 | 9a64fbe4 | bellard | * This library is free software; you can redistribute it and/or
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7 | 9a64fbe4 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 9a64fbe4 | bellard | * License as published by the Free Software Foundation; either
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9 | 9a64fbe4 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 9a64fbe4 | bellard | *
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11 | 9a64fbe4 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 9a64fbe4 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 9a64fbe4 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 9a64fbe4 | bellard | * Lesser General Public License for more details.
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15 | 9a64fbe4 | bellard | *
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16 | 9a64fbe4 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 9a64fbe4 | bellard | * License along with this library; if not, write to the Free Software
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18 | 9a64fbe4 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 9a64fbe4 | bellard | */
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20 | 9a64fbe4 | bellard | #include <math.h> |
21 | 9a64fbe4 | bellard | #include "exec.h" |
22 | 9a64fbe4 | bellard | |
23 | 9a64fbe4 | bellard | #define MEMSUFFIX _raw
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24 | 9a64fbe4 | bellard | #include "op_helper_mem.h" |
25 | a541f297 | bellard | #if !defined(CONFIG_USER_ONLY)
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26 | 9a64fbe4 | bellard | #define MEMSUFFIX _user
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27 | 9a64fbe4 | bellard | #include "op_helper_mem.h" |
28 | 9a64fbe4 | bellard | #define MEMSUFFIX _kernel
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29 | 9a64fbe4 | bellard | #include "op_helper_mem.h" |
30 | 9a64fbe4 | bellard | #endif
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31 | 9a64fbe4 | bellard | |
32 | 9a64fbe4 | bellard | /*****************************************************************************/
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33 | 9a64fbe4 | bellard | /* Exceptions processing helpers */
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34 | 9fddaa0c | bellard | void cpu_loop_exit(void) |
35 | 9a64fbe4 | bellard | { |
36 | 9fddaa0c | bellard | longjmp(env->jmp_env, 1);
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37 | 9a64fbe4 | bellard | } |
38 | 9a64fbe4 | bellard | |
39 | 9fddaa0c | bellard | void do_raise_exception_err (uint32_t exception, int error_code) |
40 | 9a64fbe4 | bellard | { |
41 | 9fddaa0c | bellard | #if 0
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42 | 9fddaa0c | bellard | printf("Raise exception %3x code : %d\n", exception, error_code);
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43 | 9fddaa0c | bellard | #endif
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44 | 9fddaa0c | bellard | switch (exception) {
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45 | 9fddaa0c | bellard | case EXCP_EXTERNAL:
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46 | 9fddaa0c | bellard | case EXCP_DECR:
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47 | 9fddaa0c | bellard | printf("DECREMENTER & EXTERNAL exceptions should be hard interrupts !\n");
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48 | 9fddaa0c | bellard | if (msr_ee == 0) |
49 | 9fddaa0c | bellard | return;
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50 | 9fddaa0c | bellard | break;
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51 | 9fddaa0c | bellard | case EXCP_PROGRAM:
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52 | 9fddaa0c | bellard | if (error_code == EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0) |
53 | 9fddaa0c | bellard | return;
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54 | 9fddaa0c | bellard | break;
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55 | 9fddaa0c | bellard | default:
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56 | 9fddaa0c | bellard | break;
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57 | 9a64fbe4 | bellard | } |
58 | 9fddaa0c | bellard | env->exception_index = exception; |
59 | 9fddaa0c | bellard | env->error_code = error_code; |
60 | 9a64fbe4 | bellard | cpu_loop_exit(); |
61 | 9a64fbe4 | bellard | } |
62 | 9fddaa0c | bellard | |
63 | 9fddaa0c | bellard | void do_raise_exception (uint32_t exception)
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64 | 9fddaa0c | bellard | { |
65 | 9fddaa0c | bellard | do_raise_exception_err(exception, 0);
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66 | 9a64fbe4 | bellard | } |
67 | 9a64fbe4 | bellard | |
68 | 9a64fbe4 | bellard | /*****************************************************************************/
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69 | 9a64fbe4 | bellard | /* Helpers for "fat" micro operations */
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70 | 9a64fbe4 | bellard | /* shift right arithmetic helper */
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71 | 9a64fbe4 | bellard | void do_sraw (void) |
72 | 9a64fbe4 | bellard | { |
73 | 9a64fbe4 | bellard | int32_t ret; |
74 | 9a64fbe4 | bellard | |
75 | 9a64fbe4 | bellard | xer_ca = 0;
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76 | 9a64fbe4 | bellard | if (T1 & 0x20) { |
77 | 9a64fbe4 | bellard | ret = (-1) * (T0 >> 31); |
78 | 4b3686fa | bellard | if (ret < 0 && (T0 & ~0x80000000) != 0) |
79 | 9a64fbe4 | bellard | xer_ca = 1;
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80 | 4b3686fa | bellard | #if 1 // TRY |
81 | 4b3686fa | bellard | } else if (T1 == 0) { |
82 | 4b3686fa | bellard | ret = T0; |
83 | 4b3686fa | bellard | #endif
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84 | 9a64fbe4 | bellard | } else {
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85 | 9a64fbe4 | bellard | ret = (int32_t)T0 >> (T1 & 0x1f);
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86 | 9a64fbe4 | bellard | if (ret < 0 && ((int32_t)T0 & ((1 << T1) - 1)) != 0) |
87 | 9a64fbe4 | bellard | xer_ca = 1;
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88 | 9a64fbe4 | bellard | } |
89 | 4b3686fa | bellard | T0 = ret; |
90 | 9a64fbe4 | bellard | } |
91 | 9a64fbe4 | bellard | |
92 | 9a64fbe4 | bellard | /* Floating point operations helpers */
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93 | 9a64fbe4 | bellard | void do_fctiw (void) |
94 | 9a64fbe4 | bellard | { |
95 | 9a64fbe4 | bellard | union {
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96 | 9a64fbe4 | bellard | double d;
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97 | 9a64fbe4 | bellard | uint64_t i; |
98 | 4ecc3190 | bellard | } p; |
99 | 9a64fbe4 | bellard | |
100 | 4ecc3190 | bellard | /* XXX: higher bits are not supposed to be significant.
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101 | 3fc6c082 | bellard | * to make tests easier, return the same as a real PowerPC 750 (aka G3)
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102 | 4ecc3190 | bellard | */
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103 | 4ecc3190 | bellard | p.i = float64_to_int32(FT0, &env->fp_status); |
104 | 4ecc3190 | bellard | p.i |= 0xFFF80000ULL << 32; |
105 | 4ecc3190 | bellard | FT0 = p.d; |
106 | 9a64fbe4 | bellard | } |
107 | 9a64fbe4 | bellard | |
108 | 9a64fbe4 | bellard | void do_fctiwz (void) |
109 | 9a64fbe4 | bellard | { |
110 | 9a64fbe4 | bellard | union {
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111 | 9a64fbe4 | bellard | double d;
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112 | 9a64fbe4 | bellard | uint64_t i; |
113 | 4ecc3190 | bellard | } p; |
114 | 4ecc3190 | bellard | |
115 | 4ecc3190 | bellard | /* XXX: higher bits are not supposed to be significant.
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116 | 3fc6c082 | bellard | * to make tests easier, return the same as a real PowerPC 750 (aka G3)
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117 | 4ecc3190 | bellard | */
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118 | 4ecc3190 | bellard | p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status); |
119 | 4ecc3190 | bellard | p.i |= 0xFFF80000ULL << 32; |
120 | 4ecc3190 | bellard | FT0 = p.d; |
121 | 9a64fbe4 | bellard | } |
122 | 9a64fbe4 | bellard | |
123 | 4b3686fa | bellard | void do_fnmadd (void) |
124 | 4b3686fa | bellard | { |
125 | 4ecc3190 | bellard | FT0 = (FT0 * FT1) + FT2; |
126 | 4ecc3190 | bellard | if (!isnan(FT0))
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127 | 4ecc3190 | bellard | FT0 = -FT0; |
128 | 4b3686fa | bellard | } |
129 | 4b3686fa | bellard | |
130 | 4b3686fa | bellard | void do_fnmsub (void) |
131 | 4b3686fa | bellard | { |
132 | 4ecc3190 | bellard | FT0 = (FT0 * FT1) - FT2; |
133 | 4ecc3190 | bellard | if (!isnan(FT0))
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134 | 4ecc3190 | bellard | FT0 = -FT0; |
135 | 4b3686fa | bellard | } |
136 | 4b3686fa | bellard | |
137 | 4ecc3190 | bellard | void do_fdiv (void) |
138 | 1ef59d0a | bellard | { |
139 | 4ecc3190 | bellard | if (FT0 == -0.0 && FT1 == -0.0) |
140 | 4ecc3190 | bellard | FT0 = 0.0 / 0.0; |
141 | 4ecc3190 | bellard | else
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142 | 4ecc3190 | bellard | FT0 /= FT1; |
143 | 1ef59d0a | bellard | } |
144 | 1ef59d0a | bellard | |
145 | 9a64fbe4 | bellard | void do_fsqrt (void) |
146 | 9a64fbe4 | bellard | { |
147 | 9a64fbe4 | bellard | FT0 = sqrt(FT0); |
148 | 9a64fbe4 | bellard | } |
149 | 9a64fbe4 | bellard | |
150 | 9a64fbe4 | bellard | void do_fres (void) |
151 | 9a64fbe4 | bellard | { |
152 | 4ecc3190 | bellard | union {
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153 | 4ecc3190 | bellard | double d;
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154 | 4ecc3190 | bellard | uint64_t i; |
155 | 4ecc3190 | bellard | } p; |
156 | 4ecc3190 | bellard | |
157 | 4ecc3190 | bellard | if (isnormal(FT0)) {
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158 | 4ecc3190 | bellard | FT0 = (float)(1.0 / FT0); |
159 | 4ecc3190 | bellard | } else {
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160 | 4ecc3190 | bellard | p.d = FT0; |
161 | 4ecc3190 | bellard | if (p.i == 0x8000000000000000ULL) { |
162 | 4ecc3190 | bellard | p.i = 0xFFF0000000000000ULL;
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163 | 4ecc3190 | bellard | } else if (p.i == 0x0000000000000000ULL) { |
164 | 4ecc3190 | bellard | p.i = 0x7FF0000000000000ULL;
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165 | 4ecc3190 | bellard | } else if (isnan(FT0)) { |
166 | 4ecc3190 | bellard | p.i = 0x7FF8000000000000ULL;
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167 | 4ecc3190 | bellard | } else if (FT0 < 0.0) { |
168 | 4ecc3190 | bellard | p.i = 0x8000000000000000ULL;
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169 | 4ecc3190 | bellard | } else {
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170 | 4ecc3190 | bellard | p.i = 0x0000000000000000ULL;
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171 | 4ecc3190 | bellard | } |
172 | 4ecc3190 | bellard | FT0 = p.d; |
173 | 4ecc3190 | bellard | } |
174 | 9a64fbe4 | bellard | } |
175 | 9a64fbe4 | bellard | |
176 | 4ecc3190 | bellard | void do_frsqrte (void) |
177 | 9a64fbe4 | bellard | { |
178 | 4ecc3190 | bellard | union {
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179 | 4ecc3190 | bellard | double d;
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180 | 4ecc3190 | bellard | uint64_t i; |
181 | 4ecc3190 | bellard | } p; |
182 | 4ecc3190 | bellard | |
183 | 4ecc3190 | bellard | if (isnormal(FT0) && FT0 > 0.0) { |
184 | 4ecc3190 | bellard | FT0 = (float)(1.0 / sqrt(FT0)); |
185 | 4ecc3190 | bellard | } else {
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186 | 4ecc3190 | bellard | p.d = FT0; |
187 | 4ecc3190 | bellard | if (p.i == 0x8000000000000000ULL) { |
188 | 4ecc3190 | bellard | p.i = 0xFFF0000000000000ULL;
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189 | 4ecc3190 | bellard | } else if (p.i == 0x0000000000000000ULL) { |
190 | 4ecc3190 | bellard | p.i = 0x7FF0000000000000ULL;
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191 | 4ecc3190 | bellard | } else if (isnan(FT0)) { |
192 | 4ecc3190 | bellard | if (!(p.i & 0x0008000000000000ULL)) |
193 | 4ecc3190 | bellard | p.i |= 0x000FFFFFFFFFFFFFULL;
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194 | 4ecc3190 | bellard | } else if (FT0 < 0) { |
195 | 4ecc3190 | bellard | p.i = 0x7FF8000000000000ULL;
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196 | 4ecc3190 | bellard | } else {
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197 | 4ecc3190 | bellard | p.i = 0x0000000000000000ULL;
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198 | 4ecc3190 | bellard | } |
199 | 4ecc3190 | bellard | FT0 = p.d; |
200 | 4ecc3190 | bellard | } |
201 | 9a64fbe4 | bellard | } |
202 | 9a64fbe4 | bellard | |
203 | 9a64fbe4 | bellard | void do_fsel (void) |
204 | 9a64fbe4 | bellard | { |
205 | 9a64fbe4 | bellard | if (FT0 >= 0) |
206 | 9a64fbe4 | bellard | FT0 = FT1; |
207 | 4ecc3190 | bellard | else
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208 | 4ecc3190 | bellard | FT0 = FT2; |
209 | 9a64fbe4 | bellard | } |
210 | 9a64fbe4 | bellard | |
211 | 9a64fbe4 | bellard | void do_fcmpu (void) |
212 | 9a64fbe4 | bellard | { |
213 | 9a64fbe4 | bellard | if (isnan(FT0) || isnan(FT1)) {
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214 | 9a64fbe4 | bellard | T0 = 0x01;
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215 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x1; |
216 | 9a64fbe4 | bellard | env->fpscr[6] |= 0x1; |
217 | 9a64fbe4 | bellard | } else if (FT0 < FT1) { |
218 | 9a64fbe4 | bellard | T0 = 0x08;
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219 | 9a64fbe4 | bellard | } else if (FT0 > FT1) { |
220 | 9a64fbe4 | bellard | T0 = 0x04;
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221 | 9a64fbe4 | bellard | } else {
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222 | 9a64fbe4 | bellard | T0 = 0x02;
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223 | 9a64fbe4 | bellard | } |
224 | 4b3686fa | bellard | env->fpscr[3] = T0;
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225 | 9a64fbe4 | bellard | } |
226 | 9a64fbe4 | bellard | |
227 | 9a64fbe4 | bellard | void do_fcmpo (void) |
228 | 9a64fbe4 | bellard | { |
229 | 9a64fbe4 | bellard | env->fpscr[4] &= ~0x1; |
230 | 9a64fbe4 | bellard | if (isnan(FT0) || isnan(FT1)) {
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231 | 9a64fbe4 | bellard | T0 = 0x01;
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232 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x1; |
233 | 9a64fbe4 | bellard | /* I don't know how to test "quiet" nan... */
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234 | 9a64fbe4 | bellard | if (0 /* || ! quiet_nan(...) */) { |
235 | 9a64fbe4 | bellard | env->fpscr[6] |= 0x1; |
236 | 9a64fbe4 | bellard | if (!(env->fpscr[1] & 0x8)) |
237 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x8; |
238 | 9a64fbe4 | bellard | } else {
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239 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x8; |
240 | 9a64fbe4 | bellard | } |
241 | 9a64fbe4 | bellard | } else if (FT0 < FT1) { |
242 | 9a64fbe4 | bellard | T0 = 0x08;
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243 | 9a64fbe4 | bellard | } else if (FT0 > FT1) { |
244 | 9a64fbe4 | bellard | T0 = 0x04;
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245 | 9a64fbe4 | bellard | } else {
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246 | 9a64fbe4 | bellard | T0 = 0x02;
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247 | 9a64fbe4 | bellard | } |
248 | 4b3686fa | bellard | env->fpscr[3] = T0;
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249 | 9a64fbe4 | bellard | } |
250 | 9a64fbe4 | bellard | |
251 | 9a64fbe4 | bellard | void do_fabs (void) |
252 | 9a64fbe4 | bellard | { |
253 | 4ecc3190 | bellard | union {
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254 | 4ecc3190 | bellard | double d;
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255 | 4ecc3190 | bellard | uint64_t i; |
256 | 4ecc3190 | bellard | } p; |
257 | 4ecc3190 | bellard | |
258 | 4ecc3190 | bellard | p.d = FT0; |
259 | 4ecc3190 | bellard | p.i &= ~0x8000000000000000ULL;
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260 | 4ecc3190 | bellard | FT0 = p.d; |
261 | 9a64fbe4 | bellard | } |
262 | 9a64fbe4 | bellard | |
263 | 9a64fbe4 | bellard | void do_fnabs (void) |
264 | 9a64fbe4 | bellard | { |
265 | 4ecc3190 | bellard | union {
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266 | 4ecc3190 | bellard | double d;
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267 | 4ecc3190 | bellard | uint64_t i; |
268 | 4ecc3190 | bellard | } p; |
269 | 4ecc3190 | bellard | |
270 | 4ecc3190 | bellard | p.d = FT0; |
271 | 4ecc3190 | bellard | p.i |= 0x8000000000000000ULL;
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272 | 4ecc3190 | bellard | FT0 = p.d; |
273 | 9a64fbe4 | bellard | } |
274 | 9a64fbe4 | bellard | |
275 | 9a64fbe4 | bellard | /* Instruction cache invalidation helper */
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276 | 985a19d6 | bellard | #define ICACHE_LINE_SIZE 32 |
277 | 985a19d6 | bellard | |
278 | 4b3686fa | bellard | void do_check_reservation (void) |
279 | 4b3686fa | bellard | { |
280 | 18fba28c | bellard | if ((env->reserve & ~0x03) == T0) |
281 | 4b3686fa | bellard | env->reserve = -1;
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282 | 4b3686fa | bellard | } |
283 | 4b3686fa | bellard | |
284 | 9a64fbe4 | bellard | void do_icbi (void) |
285 | 9a64fbe4 | bellard | { |
286 | 985a19d6 | bellard | /* Invalidate one cache line */
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287 | 985a19d6 | bellard | T0 &= ~(ICACHE_LINE_SIZE - 1);
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288 | 985a19d6 | bellard | tb_invalidate_page_range(T0, T0 + ICACHE_LINE_SIZE); |
289 | 9a64fbe4 | bellard | } |
290 | 9a64fbe4 | bellard | |
291 | 9a64fbe4 | bellard | /* TLB invalidation helpers */
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292 | 9a64fbe4 | bellard | void do_tlbia (void) |
293 | 9a64fbe4 | bellard | { |
294 | ad081323 | bellard | tlb_flush(env, 1);
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295 | 9a64fbe4 | bellard | } |
296 | 9a64fbe4 | bellard | |
297 | 9a64fbe4 | bellard | void do_tlbie (void) |
298 | 9a64fbe4 | bellard | { |
299 | 9a64fbe4 | bellard | tlb_flush_page(env, T0); |
300 | 9a64fbe4 | bellard | } |