Revision 4018bae9 target-ppc/cpu.h
| b/target-ppc/cpu.h | ||
|---|---|---|
| 441 | 441 |
#endif |
| 442 | 442 |
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enum {
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| 444 |
POWERPC_FLAG_NONE = 0x00000000, |
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| 444 |
POWERPC_FLAG_NONE = 0x00000000,
|
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/* Flag for MSR bit 25 signification (VRE/SPE) */ |
| 446 |
POWERPC_FLAG_SPE = 0x00000001, |
|
| 447 |
POWERPC_FLAG_VRE = 0x00000002, |
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| 446 |
POWERPC_FLAG_SPE = 0x00000001,
|
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| 447 |
POWERPC_FLAG_VRE = 0x00000002,
|
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| 448 | 448 |
/* Flag for MSR bit 17 signification (TGPR/CE) */ |
| 449 |
POWERPC_FLAG_TGPR = 0x00000004, |
|
| 450 |
POWERPC_FLAG_CE = 0x00000008, |
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| 449 |
POWERPC_FLAG_TGPR = 0x00000004,
|
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POWERPC_FLAG_CE = 0x00000008,
|
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| 451 | 451 |
/* Flag for MSR bit 10 signification (SE/DWE/UBLE) */ |
| 452 |
POWERPC_FLAG_SE = 0x00000010, |
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| 453 |
POWERPC_FLAG_DWE = 0x00000020, |
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| 454 |
POWERPC_FLAG_UBLE = 0x00000040, |
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| 452 |
POWERPC_FLAG_SE = 0x00000010,
|
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POWERPC_FLAG_DWE = 0x00000020,
|
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| 454 |
POWERPC_FLAG_UBLE = 0x00000040,
|
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| 455 | 455 |
/* Flag for MSR bit 9 signification (BE/DE) */ |
| 456 |
POWERPC_FLAG_BE = 0x00000080, |
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| 457 |
POWERPC_FLAG_DE = 0x00000100, |
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| 456 |
POWERPC_FLAG_BE = 0x00000080,
|
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| 457 |
POWERPC_FLAG_DE = 0x00000100,
|
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| 458 | 458 |
/* Flag for MSR bit 2 signification (PX/PMM) */ |
| 459 |
POWERPC_FLAG_PX = 0x00000200, |
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| 460 |
POWERPC_FLAG_PMM = 0x00000400, |
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POWERPC_FLAG_PX = 0x00000200, |
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| 460 |
POWERPC_FLAG_PMM = 0x00000400, |
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| 461 |
/* Flag for special features */ |
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| 462 |
/* Decrementer clock: RTC clock (POWER, 601) or bus clock */ |
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POWERPC_FLAG_RTC_CLK = 0x00010000, |
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POWERPC_FLAG_BUS_CLK = 0x00020000, |
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}; |
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/*****************************************************************************/ |
Also available in: Unified diff