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1 | d19893da | bellard | /*
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2 | d19893da | bellard | * Host code generation
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3 | d19893da | bellard | *
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4 | d19893da | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d19893da | bellard | *
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6 | d19893da | bellard | * This library is free software; you can redistribute it and/or
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7 | d19893da | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d19893da | bellard | * License as published by the Free Software Foundation; either
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9 | d19893da | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d19893da | bellard | *
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11 | d19893da | bellard | * This library is distributed in the hope that it will be useful,
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12 | d19893da | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d19893da | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d19893da | bellard | * Lesser General Public License for more details.
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15 | d19893da | bellard | *
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16 | d19893da | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | d19893da | bellard | * License along with this library; if not, write to the Free Software
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18 | d19893da | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | d19893da | bellard | */
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20 | d19893da | bellard | #include <stdarg.h> |
21 | d19893da | bellard | #include <stdlib.h> |
22 | d19893da | bellard | #include <stdio.h> |
23 | d19893da | bellard | #include <string.h> |
24 | d19893da | bellard | #include <inttypes.h> |
25 | d19893da | bellard | |
26 | d19893da | bellard | #include "config.h" |
27 | 2054396a | bellard | |
28 | d19893da | bellard | #define IN_OP_I386
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29 | 2054396a | bellard | #if defined(TARGET_I386)
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30 | 2054396a | bellard | #include "cpu-i386.h" |
31 | 2054396a | bellard | #define OPC_CPU_H "opc-i386.h" |
32 | 2054396a | bellard | #elif defined(TARGET_ARM)
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33 | 2054396a | bellard | #include "cpu-arm.h" |
34 | 2054396a | bellard | #define OPC_CPU_H "opc-arm.h" |
35 | 2054396a | bellard | #else
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36 | 2054396a | bellard | #error unsupported target CPU
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37 | 2054396a | bellard | #endif
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38 | 2054396a | bellard | |
39 | d19893da | bellard | #include "exec.h" |
40 | d19893da | bellard | #include "disas.h" |
41 | d19893da | bellard | |
42 | d19893da | bellard | enum {
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43 | d19893da | bellard | #define DEF(s, n, copy_size) INDEX_op_ ## s, |
44 | 2054396a | bellard | #include OPC_CPU_H
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45 | d19893da | bellard | #undef DEF
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46 | d19893da | bellard | NB_OPS, |
47 | d19893da | bellard | }; |
48 | d19893da | bellard | |
49 | d19893da | bellard | #include "dyngen.h" |
50 | 2054396a | bellard | #if defined(TARGET_I386)
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51 | 2054396a | bellard | #include "op-i386.h" |
52 | 2054396a | bellard | #elif defined(TARGET_ARM)
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53 | 2054396a | bellard | #include "op-arm.h" |
54 | 2054396a | bellard | #else
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55 | 2054396a | bellard | #error unsupported target CPU
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56 | 2054396a | bellard | #endif
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57 | d19893da | bellard | |
58 | d19893da | bellard | uint16_t gen_opc_buf[OPC_BUF_SIZE]; |
59 | d19893da | bellard | uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE]; |
60 | d19893da | bellard | uint32_t gen_opc_pc[OPC_BUF_SIZE]; |
61 | d19893da | bellard | uint8_t gen_opc_instr_start[OPC_BUF_SIZE]; |
62 | f76af4b3 | bellard | #if defined(TARGET_I386)
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63 | f76af4b3 | bellard | uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
64 | f76af4b3 | bellard | #endif
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65 | d19893da | bellard | |
66 | d19893da | bellard | #ifdef DEBUG_DISAS
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67 | d19893da | bellard | static const char *op_str[] = { |
68 | d19893da | bellard | #define DEF(s, n, copy_size) #s, |
69 | 2054396a | bellard | #include OPC_CPU_H
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70 | d19893da | bellard | #undef DEF
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71 | d19893da | bellard | }; |
72 | d19893da | bellard | |
73 | d19893da | bellard | static uint8_t op_nb_args[] = {
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74 | d19893da | bellard | #define DEF(s, n, copy_size) n,
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75 | 2054396a | bellard | #include OPC_CPU_H
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76 | d19893da | bellard | #undef DEF
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77 | d19893da | bellard | }; |
78 | d19893da | bellard | |
79 | d19893da | bellard | void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf) |
80 | d19893da | bellard | { |
81 | d19893da | bellard | const uint16_t *opc_ptr;
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82 | d19893da | bellard | const uint32_t *opparam_ptr;
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83 | d19893da | bellard | int c, n, i;
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84 | d19893da | bellard | |
85 | d19893da | bellard | opc_ptr = opc_buf; |
86 | d19893da | bellard | opparam_ptr = opparam_buf; |
87 | d19893da | bellard | for(;;) {
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88 | d19893da | bellard | c = *opc_ptr++; |
89 | d19893da | bellard | n = op_nb_args[c]; |
90 | d19893da | bellard | fprintf(logfile, "0x%04x: %s",
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91 | d19893da | bellard | (int)(opc_ptr - opc_buf - 1), op_str[c]); |
92 | d19893da | bellard | for(i = 0; i < n; i++) { |
93 | d19893da | bellard | fprintf(logfile, " 0x%x", opparam_ptr[i]);
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94 | d19893da | bellard | } |
95 | d19893da | bellard | fprintf(logfile, "\n");
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96 | d19893da | bellard | if (c == INDEX_op_end)
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97 | d19893da | bellard | break;
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98 | d19893da | bellard | opparam_ptr += n; |
99 | d19893da | bellard | } |
100 | d19893da | bellard | } |
101 | d19893da | bellard | |
102 | d19893da | bellard | #endif
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103 | d19893da | bellard | |
104 | d19893da | bellard | /* return non zero if the very first instruction is invalid so that
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105 | d19893da | bellard | the virtual CPU can trigger an exception.
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106 | d19893da | bellard | |
107 | d19893da | bellard | '*gen_code_size_ptr' contains the size of the generated code (host
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108 | d19893da | bellard | code).
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109 | d19893da | bellard | */
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110 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, TranslationBlock *tb,
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111 | d19893da | bellard | int max_code_size, int *gen_code_size_ptr) |
112 | d19893da | bellard | { |
113 | d19893da | bellard | uint8_t *gen_code_buf; |
114 | d19893da | bellard | int gen_code_size;
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115 | d19893da | bellard | |
116 | 4c3a88a2 | bellard | if (gen_intermediate_code(env, tb) < 0) |
117 | d19893da | bellard | return -1; |
118 | d19893da | bellard | |
119 | d19893da | bellard | /* generate machine code */
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120 | d19893da | bellard | tb->tb_next_offset[0] = 0xffff; |
121 | d19893da | bellard | tb->tb_next_offset[1] = 0xffff; |
122 | d19893da | bellard | gen_code_buf = tb->tc_ptr; |
123 | d19893da | bellard | gen_code_size = dyngen_code(gen_code_buf, tb->tb_next_offset, |
124 | d19893da | bellard | #ifdef USE_DIRECT_JUMP
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125 | d19893da | bellard | tb->tb_jmp_offset, |
126 | d19893da | bellard | #else
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127 | d19893da | bellard | NULL,
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128 | d19893da | bellard | #endif
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129 | d19893da | bellard | gen_opc_buf, gen_opparam_buf); |
130 | d19893da | bellard | *gen_code_size_ptr = gen_code_size; |
131 | d19893da | bellard | #ifdef DEBUG_DISAS
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132 | d19893da | bellard | if (loglevel) {
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133 | d19893da | bellard | fprintf(logfile, "OUT: [size=%d]\n", *gen_code_size_ptr);
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134 | d19893da | bellard | disas(logfile, gen_code_buf, *gen_code_size_ptr, 1, 0); |
135 | d19893da | bellard | fprintf(logfile, "\n");
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136 | d19893da | bellard | fflush(logfile); |
137 | d19893da | bellard | } |
138 | d19893da | bellard | #endif
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139 | d19893da | bellard | return 0; |
140 | d19893da | bellard | } |
141 | d19893da | bellard | |
142 | d19893da | bellard | static const unsigned short opc_copy_size[] = { |
143 | d19893da | bellard | #define DEF(s, n, copy_size) copy_size,
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144 | 2054396a | bellard | #include OPC_CPU_H
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145 | d19893da | bellard | #undef DEF
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146 | d19893da | bellard | }; |
147 | d19893da | bellard | |
148 | f76af4b3 | bellard | /* The cpu state corresponding to 'searched_pc' is restored.
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149 | d19893da | bellard | */
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150 | f76af4b3 | bellard | int cpu_restore_state(TranslationBlock *tb,
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151 | f76af4b3 | bellard | CPUState *env, unsigned long searched_pc) |
152 | d19893da | bellard | { |
153 | d19893da | bellard | int j, c;
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154 | d19893da | bellard | unsigned long tc_ptr; |
155 | d19893da | bellard | uint16_t *opc_ptr; |
156 | d19893da | bellard | |
157 | 4c3a88a2 | bellard | if (gen_intermediate_code_pc(env, tb) < 0) |
158 | d19893da | bellard | return -1; |
159 | d19893da | bellard | |
160 | d19893da | bellard | /* find opc index corresponding to search_pc */
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161 | d19893da | bellard | tc_ptr = (unsigned long)tb->tc_ptr; |
162 | d19893da | bellard | if (searched_pc < tc_ptr)
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163 | d19893da | bellard | return -1; |
164 | d19893da | bellard | j = 0;
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165 | d19893da | bellard | opc_ptr = gen_opc_buf; |
166 | d19893da | bellard | for(;;) {
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167 | d19893da | bellard | c = *opc_ptr; |
168 | d19893da | bellard | if (c == INDEX_op_end)
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169 | d19893da | bellard | return -1; |
170 | d19893da | bellard | tc_ptr += opc_copy_size[c]; |
171 | d19893da | bellard | if (searched_pc < tc_ptr)
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172 | d19893da | bellard | break;
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173 | d19893da | bellard | opc_ptr++; |
174 | d19893da | bellard | } |
175 | d19893da | bellard | j = opc_ptr - gen_opc_buf; |
176 | d19893da | bellard | /* now find start of instruction before */
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177 | d19893da | bellard | while (gen_opc_instr_start[j] == 0) |
178 | d19893da | bellard | j--; |
179 | f76af4b3 | bellard | #if defined(TARGET_I386)
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180 | f76af4b3 | bellard | { |
181 | f76af4b3 | bellard | int cc_op;
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182 | 3c1cf9fa | bellard | #ifdef DEBUG_DISAS
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183 | 3c1cf9fa | bellard | if (loglevel) {
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184 | 3c1cf9fa | bellard | int i;
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185 | 6e0374f6 | bellard | fprintf(logfile, "RESTORE:\n");
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186 | 3c1cf9fa | bellard | for(i=0;i<=j; i++) { |
187 | 3c1cf9fa | bellard | if (gen_opc_instr_start[i]) {
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188 | 6e0374f6 | bellard | fprintf(logfile, "0x%04x: 0x%08x\n", i, gen_opc_pc[i]);
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189 | 3c1cf9fa | bellard | } |
190 | 3c1cf9fa | bellard | } |
191 | 6e0374f6 | bellard | fprintf(logfile, "spc=0x%08lx j=0x%x eip=0x%lx cs_base=%lx\n",
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192 | 6e0374f6 | bellard | searched_pc, j, gen_opc_pc[j] - tb->cs_base, tb->cs_base); |
193 | 3c1cf9fa | bellard | } |
194 | 3c1cf9fa | bellard | #endif
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195 | f76af4b3 | bellard | env->eip = gen_opc_pc[j] - tb->cs_base; |
196 | f76af4b3 | bellard | cc_op = gen_opc_cc_op[j]; |
197 | f76af4b3 | bellard | if (cc_op != CC_OP_DYNAMIC)
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198 | f76af4b3 | bellard | env->cc_op = cc_op; |
199 | f76af4b3 | bellard | } |
200 | f76af4b3 | bellard | #elif defined(TARGET_ARM)
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201 | f76af4b3 | bellard | env->regs[15] = gen_opc_pc[j];
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202 | f76af4b3 | bellard | #endif
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203 | d19893da | bellard | return 0; |
204 | d19893da | bellard | } |
205 | d19893da | bellard |