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1 | 6f7e9aec | bellard | /*
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2 | 6f7e9aec | bellard | * QEMU ESP emulation
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3 | 6f7e9aec | bellard | *
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4 | 6f7e9aec | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 6f7e9aec | bellard | *
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6 | 6f7e9aec | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 6f7e9aec | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 6f7e9aec | bellard | * in the Software without restriction, including without limitation the rights
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9 | 6f7e9aec | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 6f7e9aec | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 6f7e9aec | bellard | * furnished to do so, subject to the following conditions:
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12 | 6f7e9aec | bellard | *
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13 | 6f7e9aec | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 6f7e9aec | bellard | * all copies or substantial portions of the Software.
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15 | 6f7e9aec | bellard | *
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16 | 6f7e9aec | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 6f7e9aec | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 6f7e9aec | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 6f7e9aec | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 6f7e9aec | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 6f7e9aec | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 6f7e9aec | bellard | * THE SOFTWARE.
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23 | 6f7e9aec | bellard | */
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24 | 6f7e9aec | bellard | #include "vl.h" |
25 | 6f7e9aec | bellard | |
26 | 6f7e9aec | bellard | /* debug ESP card */
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27 | 2f275b8f | bellard | //#define DEBUG_ESP
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28 | 6f7e9aec | bellard | |
29 | 6f7e9aec | bellard | #ifdef DEBUG_ESP
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30 | 6f7e9aec | bellard | #define DPRINTF(fmt, args...) \
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31 | 6f7e9aec | bellard | do { printf("ESP: " fmt , ##args); } while (0) |
32 | 6f7e9aec | bellard | #else
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33 | 6f7e9aec | bellard | #define DPRINTF(fmt, args...)
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34 | 6f7e9aec | bellard | #endif
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35 | 6f7e9aec | bellard | |
36 | 6f7e9aec | bellard | #define ESPDMA_REGS 4 |
37 | 6f7e9aec | bellard | #define ESPDMA_MAXADDR (ESPDMA_REGS * 4 - 1) |
38 | 6f7e9aec | bellard | #define ESP_MAXREG 0x3f |
39 | 6f7e9aec | bellard | |
40 | 6f7e9aec | bellard | typedef struct ESPState { |
41 | 6f7e9aec | bellard | BlockDriverState **bd; |
42 | 2f275b8f | bellard | uint8_t rregs[ESP_MAXREG]; |
43 | 2f275b8f | bellard | uint8_t wregs[ESP_MAXREG]; |
44 | 6f7e9aec | bellard | int irq;
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45 | 6f7e9aec | bellard | uint32_t espdmaregs[ESPDMA_REGS]; |
46 | 2f275b8f | bellard | uint32_t ti_size; |
47 | 2f275b8f | bellard | int ti_dir;
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48 | 2f275b8f | bellard | uint8_t ti_buf[65536];
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49 | 6f7e9aec | bellard | } ESPState; |
50 | 6f7e9aec | bellard | |
51 | 2f275b8f | bellard | #define STAT_DO 0x00 |
52 | 2f275b8f | bellard | #define STAT_DI 0x01 |
53 | 2f275b8f | bellard | #define STAT_CD 0x02 |
54 | 2f275b8f | bellard | #define STAT_ST 0x03 |
55 | 2f275b8f | bellard | #define STAT_MI 0x06 |
56 | 2f275b8f | bellard | #define STAT_MO 0x07 |
57 | 2f275b8f | bellard | |
58 | 2f275b8f | bellard | #define STAT_TC 0x10 |
59 | 2f275b8f | bellard | #define STAT_IN 0x80 |
60 | 2f275b8f | bellard | |
61 | 2f275b8f | bellard | #define INTR_FC 0x08 |
62 | 2f275b8f | bellard | #define INTR_BS 0x10 |
63 | 2f275b8f | bellard | #define INTR_DC 0x20 |
64 | 2f275b8f | bellard | |
65 | 2f275b8f | bellard | #define SEQ_0 0x0 |
66 | 2f275b8f | bellard | #define SEQ_CD 0x4 |
67 | 2f275b8f | bellard | |
68 | 2f275b8f | bellard | static void handle_satn(ESPState *s) |
69 | 2f275b8f | bellard | { |
70 | 2f275b8f | bellard | uint8_t buf[32];
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71 | 2f275b8f | bellard | uint32_t dmaptr, dmalen; |
72 | 2f275b8f | bellard | unsigned int i; |
73 | 2f275b8f | bellard | int64_t nb_sectors; |
74 | 2f275b8f | bellard | int target;
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75 | 2f275b8f | bellard | |
76 | 2f275b8f | bellard | dmaptr = iommu_translate(s->espdmaregs[1]);
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77 | 2f275b8f | bellard | dmalen = s->wregs[0] | (s->wregs[1] << 8); |
78 | 2f275b8f | bellard | DPRINTF("Select with ATN at %8.8x len %d\n", dmaptr, dmalen);
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79 | 2f275b8f | bellard | DPRINTF("DMA Direction: %c\n", s->espdmaregs[0] & 0x100? 'w': 'r'); |
80 | 2f275b8f | bellard | cpu_physical_memory_read(dmaptr, buf, dmalen); |
81 | 2f275b8f | bellard | for (i = 0; i < dmalen; i++) { |
82 | 2f275b8f | bellard | DPRINTF("Command %2.2x\n", buf[i]);
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83 | 2f275b8f | bellard | } |
84 | 2f275b8f | bellard | s->ti_dir = 0;
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85 | 2f275b8f | bellard | s->ti_size = 0;
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86 | 2f275b8f | bellard | target = s->wregs[4] & 7; |
87 | 2f275b8f | bellard | |
88 | 2f275b8f | bellard | if (target > 4 || !s->bd[target]) { // No such drive |
89 | 2f275b8f | bellard | s->rregs[4] = STAT_IN;
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90 | 2f275b8f | bellard | s->rregs[5] = INTR_DC;
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91 | 2f275b8f | bellard | s->rregs[6] = SEQ_0;
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92 | 2f275b8f | bellard | s->espdmaregs[0] |= 1; |
93 | 2f275b8f | bellard | pic_set_irq(s->irq, 1);
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94 | 2f275b8f | bellard | return;
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95 | 2f275b8f | bellard | } |
96 | 2f275b8f | bellard | switch (buf[1]) { |
97 | 2f275b8f | bellard | case 0x0: |
98 | 2f275b8f | bellard | DPRINTF("Test Unit Ready (len %d)\n", buf[5]); |
99 | 2f275b8f | bellard | break;
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100 | 2f275b8f | bellard | case 0x12: |
101 | 2f275b8f | bellard | DPRINTF("Inquiry (len %d)\n", buf[5]); |
102 | 2f275b8f | bellard | memset(s->ti_buf, 0, 36); |
103 | 2f275b8f | bellard | if (bdrv_get_type_hint(s->bd[target]) == BDRV_TYPE_CDROM) {
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104 | 2f275b8f | bellard | s->ti_buf[0] = 5; |
105 | 2f275b8f | bellard | memcpy(&s->ti_buf[16], "QEMU CDROM ", 16); |
106 | 2f275b8f | bellard | } else {
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107 | 2f275b8f | bellard | s->ti_buf[0] = 0; |
108 | 2f275b8f | bellard | memcpy(&s->ti_buf[16], "QEMU HARDDISK ", 16); |
109 | 2f275b8f | bellard | } |
110 | 2f275b8f | bellard | memcpy(&s->ti_buf[8], "QEMU ", 8); |
111 | 2f275b8f | bellard | s->ti_buf[2] = 1; |
112 | 2f275b8f | bellard | s->ti_buf[3] = 2; |
113 | 2f275b8f | bellard | s->ti_dir = 1;
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114 | 2f275b8f | bellard | s->ti_size = 36;
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115 | 2f275b8f | bellard | break;
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116 | 2f275b8f | bellard | case 0x1a: |
117 | 2f275b8f | bellard | DPRINTF("Mode Sense(6) (page %d, len %d)\n", buf[3], buf[5]); |
118 | 2f275b8f | bellard | break;
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119 | 2f275b8f | bellard | case 0x25: |
120 | 2f275b8f | bellard | DPRINTF("Read Capacity (len %d)\n", buf[5]); |
121 | 2f275b8f | bellard | memset(s->ti_buf, 0, 8); |
122 | 2f275b8f | bellard | bdrv_get_geometry(s->bd[target], &nb_sectors); |
123 | 2f275b8f | bellard | s->ti_buf[0] = (nb_sectors >> 24) & 0xff; |
124 | 2f275b8f | bellard | s->ti_buf[1] = (nb_sectors >> 16) & 0xff; |
125 | 2f275b8f | bellard | s->ti_buf[2] = (nb_sectors >> 8) & 0xff; |
126 | 2f275b8f | bellard | s->ti_buf[3] = nb_sectors & 0xff; |
127 | 2f275b8f | bellard | s->ti_buf[4] = 0; |
128 | 2f275b8f | bellard | s->ti_buf[5] = 0; |
129 | 2f275b8f | bellard | s->ti_buf[6] = 2; |
130 | 2f275b8f | bellard | s->ti_buf[7] = 0; |
131 | 2f275b8f | bellard | s->ti_dir = 1;
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132 | 2f275b8f | bellard | s->ti_size = 8;
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133 | 2f275b8f | bellard | break;
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134 | 2f275b8f | bellard | case 0x28: |
135 | 2f275b8f | bellard | { |
136 | 2f275b8f | bellard | int64_t offset, len; |
137 | 2f275b8f | bellard | |
138 | 2f275b8f | bellard | offset = (buf[3] << 24) | (buf[4] << 16) | (buf[5] << 8) | buf[6]; |
139 | 2f275b8f | bellard | len = (buf[8] << 8) | buf[9]; |
140 | 2f275b8f | bellard | DPRINTF("Read (10) (offset %lld len %lld)\n", offset, len);
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141 | 2f275b8f | bellard | bdrv_read(s->bd[target], offset, s->ti_buf, len); |
142 | 2f275b8f | bellard | s->ti_dir = 1;
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143 | 2f275b8f | bellard | s->ti_size = len * 512;
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144 | 2f275b8f | bellard | break;
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145 | 2f275b8f | bellard | } |
146 | 2f275b8f | bellard | case 0x2a: |
147 | 2f275b8f | bellard | { |
148 | 2f275b8f | bellard | int64_t offset, len; |
149 | 2f275b8f | bellard | |
150 | 2f275b8f | bellard | offset = (buf[3] << 24) | (buf[4] << 16) | (buf[5] << 8) | buf[6]; |
151 | 2f275b8f | bellard | len = (buf[8] << 8) | buf[9]; |
152 | 2f275b8f | bellard | DPRINTF("Write (10) (offset %lld len %lld)\n", offset, len);
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153 | 2f275b8f | bellard | bdrv_write(s->bd[target], offset, s->ti_buf, len); |
154 | 2f275b8f | bellard | s->ti_dir = 0;
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155 | 2f275b8f | bellard | s->ti_size = len * 512;
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156 | 2f275b8f | bellard | break;
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157 | 2f275b8f | bellard | } |
158 | 2f275b8f | bellard | default:
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159 | 2f275b8f | bellard | DPRINTF("Unknown command (%2.2x)\n", buf[1]); |
160 | 2f275b8f | bellard | break;
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161 | 2f275b8f | bellard | } |
162 | 2f275b8f | bellard | s->rregs[4] = STAT_IN | STAT_TC | STAT_DI;
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163 | 2f275b8f | bellard | s->rregs[5] = INTR_BS | INTR_FC;
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164 | 2f275b8f | bellard | s->rregs[6] = SEQ_CD;
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165 | 2f275b8f | bellard | s->espdmaregs[0] |= 1; |
166 | 2f275b8f | bellard | pic_set_irq(s->irq, 1);
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167 | 2f275b8f | bellard | } |
168 | 2f275b8f | bellard | |
169 | 2f275b8f | bellard | static void dma_write(ESPState *s, const uint8_t *buf, uint32_t len) |
170 | 2f275b8f | bellard | { |
171 | 2f275b8f | bellard | uint32_t dmaptr, dmalen; |
172 | 2f275b8f | bellard | |
173 | 2f275b8f | bellard | dmaptr = iommu_translate(s->espdmaregs[1]);
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174 | 2f275b8f | bellard | dmalen = s->wregs[0] | (s->wregs[1] << 8); |
175 | 2f275b8f | bellard | DPRINTF("DMA Direction: %c\n", s->espdmaregs[0] & 0x100? 'w': 'r'); |
176 | 2f275b8f | bellard | cpu_physical_memory_write(dmaptr, buf, len); |
177 | 2f275b8f | bellard | s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
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178 | 2f275b8f | bellard | s->rregs[5] = INTR_BS | INTR_FC;
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179 | 2f275b8f | bellard | s->rregs[6] = SEQ_CD;
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180 | 2f275b8f | bellard | s->espdmaregs[0] |= 1; |
181 | 2f275b8f | bellard | pic_set_irq(s->irq, 1);
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182 | 2f275b8f | bellard | |
183 | 2f275b8f | bellard | } |
184 | 2f275b8f | bellard | static const uint8_t okbuf[] = {0, 0}; |
185 | 2f275b8f | bellard | |
186 | 2f275b8f | bellard | static void handle_ti(ESPState *s) |
187 | 2f275b8f | bellard | { |
188 | 2f275b8f | bellard | uint32_t dmaptr, dmalen; |
189 | 2f275b8f | bellard | unsigned int i; |
190 | 2f275b8f | bellard | |
191 | 2f275b8f | bellard | dmaptr = iommu_translate(s->espdmaregs[1]);
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192 | 2f275b8f | bellard | dmalen = s->wregs[0] | (s->wregs[1] << 8); |
193 | 2f275b8f | bellard | DPRINTF("Transfer Information at %8.8x len %d\n", dmaptr, dmalen);
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194 | 2f275b8f | bellard | DPRINTF("DMA Direction: %c\n", s->espdmaregs[0] & 0x100? 'w': 'r'); |
195 | 2f275b8f | bellard | for (i = 0; i < s->ti_size; i++) { |
196 | 2f275b8f | bellard | dmaptr = iommu_translate(s->espdmaregs[1] + i);
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197 | 2f275b8f | bellard | if (s->ti_dir)
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198 | 2f275b8f | bellard | cpu_physical_memory_write(dmaptr, &s->ti_buf[i], 1);
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199 | 2f275b8f | bellard | else
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200 | 2f275b8f | bellard | cpu_physical_memory_read(dmaptr, &s->ti_buf[i], 1);
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201 | 2f275b8f | bellard | } |
202 | 2f275b8f | bellard | s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
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203 | 2f275b8f | bellard | s->rregs[5] = INTR_BS;
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204 | 2f275b8f | bellard | s->rregs[6] = 0; |
205 | 2f275b8f | bellard | s->espdmaregs[0] |= 1; |
206 | 2f275b8f | bellard | pic_set_irq(s->irq, 1);
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207 | 2f275b8f | bellard | } |
208 | 2f275b8f | bellard | |
209 | 6f7e9aec | bellard | static void esp_reset(void *opaque) |
210 | 6f7e9aec | bellard | { |
211 | 6f7e9aec | bellard | ESPState *s = opaque; |
212 | 2f275b8f | bellard | memset(s->rregs, 0, ESP_MAXREG);
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213 | 2f275b8f | bellard | s->rregs[0x0e] = 0x4; // Indicate fas100a |
214 | 6f7e9aec | bellard | memset(s->espdmaregs, 0, ESPDMA_REGS * 4); |
215 | 6f7e9aec | bellard | } |
216 | 6f7e9aec | bellard | |
217 | 6f7e9aec | bellard | static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
218 | 6f7e9aec | bellard | { |
219 | 6f7e9aec | bellard | ESPState *s = opaque; |
220 | 6f7e9aec | bellard | uint32_t saddr; |
221 | 6f7e9aec | bellard | |
222 | 6f7e9aec | bellard | saddr = (addr & ESP_MAXREG) >> 2;
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223 | 6f7e9aec | bellard | switch (saddr) {
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224 | 6f7e9aec | bellard | default:
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225 | 6f7e9aec | bellard | break;
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226 | 6f7e9aec | bellard | } |
227 | 2f275b8f | bellard | DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
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228 | 2f275b8f | bellard | return s->rregs[saddr];
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229 | 6f7e9aec | bellard | } |
230 | 6f7e9aec | bellard | |
231 | 6f7e9aec | bellard | static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
232 | 6f7e9aec | bellard | { |
233 | 6f7e9aec | bellard | ESPState *s = opaque; |
234 | 6f7e9aec | bellard | uint32_t saddr; |
235 | 6f7e9aec | bellard | |
236 | 6f7e9aec | bellard | saddr = (addr & ESP_MAXREG) >> 2;
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237 | 2f275b8f | bellard | DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val);
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238 | 6f7e9aec | bellard | switch (saddr) {
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239 | 6f7e9aec | bellard | case 3: |
240 | 6f7e9aec | bellard | // Command
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241 | 6f7e9aec | bellard | switch(val & 0x7f) { |
242 | 6f7e9aec | bellard | case 0: |
243 | 2f275b8f | bellard | DPRINTF("NOP (%2.2x)\n", val);
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244 | 2f275b8f | bellard | break;
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245 | 2f275b8f | bellard | case 1: |
246 | 2f275b8f | bellard | DPRINTF("Flush FIFO (%2.2x)\n", val);
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247 | 2f275b8f | bellard | s->rregs[6] = 0; |
248 | 2f275b8f | bellard | s->rregs[5] = INTR_FC;
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249 | 6f7e9aec | bellard | break;
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250 | 6f7e9aec | bellard | case 2: |
251 | 2f275b8f | bellard | DPRINTF("Chip reset (%2.2x)\n", val);
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252 | 6f7e9aec | bellard | esp_reset(s); |
253 | 6f7e9aec | bellard | break;
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254 | 6f7e9aec | bellard | case 3: |
255 | 2f275b8f | bellard | DPRINTF("Bus reset (%2.2x)\n", val);
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256 | 2f275b8f | bellard | break;
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257 | 2f275b8f | bellard | case 0x10: |
258 | 2f275b8f | bellard | handle_ti(s); |
259 | 2f275b8f | bellard | break;
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260 | 2f275b8f | bellard | case 0x11: |
261 | 2f275b8f | bellard | DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
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262 | 2f275b8f | bellard | dma_write(s, okbuf, 2);
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263 | 2f275b8f | bellard | break;
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264 | 2f275b8f | bellard | case 0x12: |
265 | 2f275b8f | bellard | DPRINTF("Message Accepted (%2.2x)\n", val);
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266 | 2f275b8f | bellard | dma_write(s, okbuf, 2);
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267 | 2f275b8f | bellard | s->rregs[5] = INTR_DC;
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268 | 2f275b8f | bellard | s->rregs[6] = 0; |
269 | 6f7e9aec | bellard | break;
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270 | 6f7e9aec | bellard | case 0x1a: |
271 | 2f275b8f | bellard | DPRINTF("Set ATN (%2.2x)\n", val);
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272 | 6f7e9aec | bellard | break;
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273 | 6f7e9aec | bellard | case 0x42: |
274 | 2f275b8f | bellard | handle_satn(s); |
275 | 2f275b8f | bellard | break;
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276 | 2f275b8f | bellard | case 0x43: |
277 | 2f275b8f | bellard | DPRINTF("Set ATN & stop (%2.2x)\n", val);
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278 | 2f275b8f | bellard | handle_satn(s); |
279 | 2f275b8f | bellard | break;
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280 | 2f275b8f | bellard | default:
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281 | 2f275b8f | bellard | DPRINTF("Unhandled command (%2.2x)\n", val);
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282 | 6f7e9aec | bellard | break;
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283 | 6f7e9aec | bellard | } |
284 | 6f7e9aec | bellard | break;
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285 | 6f7e9aec | bellard | case 4 ... 7: |
286 | 6f7e9aec | bellard | case 9 ... 0xf: |
287 | 6f7e9aec | bellard | break;
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288 | 6f7e9aec | bellard | default:
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289 | 6f7e9aec | bellard | break;
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290 | 6f7e9aec | bellard | } |
291 | 2f275b8f | bellard | s->wregs[saddr] = val; |
292 | 6f7e9aec | bellard | } |
293 | 6f7e9aec | bellard | |
294 | 6f7e9aec | bellard | static CPUReadMemoryFunc *esp_mem_read[3] = { |
295 | 6f7e9aec | bellard | esp_mem_readb, |
296 | 6f7e9aec | bellard | esp_mem_readb, |
297 | 6f7e9aec | bellard | esp_mem_readb, |
298 | 6f7e9aec | bellard | }; |
299 | 6f7e9aec | bellard | |
300 | 6f7e9aec | bellard | static CPUWriteMemoryFunc *esp_mem_write[3] = { |
301 | 6f7e9aec | bellard | esp_mem_writeb, |
302 | 6f7e9aec | bellard | esp_mem_writeb, |
303 | 6f7e9aec | bellard | esp_mem_writeb, |
304 | 6f7e9aec | bellard | }; |
305 | 6f7e9aec | bellard | |
306 | 6f7e9aec | bellard | static uint32_t espdma_mem_readl(void *opaque, target_phys_addr_t addr) |
307 | 6f7e9aec | bellard | { |
308 | 6f7e9aec | bellard | ESPState *s = opaque; |
309 | 6f7e9aec | bellard | uint32_t saddr; |
310 | 6f7e9aec | bellard | |
311 | 6f7e9aec | bellard | saddr = (addr & ESPDMA_MAXADDR) >> 2;
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312 | 2f275b8f | bellard | DPRINTF("read dmareg[%d]: 0x%2.2x\n", saddr, s->espdmaregs[saddr]);
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313 | 6f7e9aec | bellard | return s->espdmaregs[saddr];
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314 | 6f7e9aec | bellard | } |
315 | 6f7e9aec | bellard | |
316 | 6f7e9aec | bellard | static void espdma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
317 | 6f7e9aec | bellard | { |
318 | 6f7e9aec | bellard | ESPState *s = opaque; |
319 | 6f7e9aec | bellard | uint32_t saddr; |
320 | 6f7e9aec | bellard | |
321 | 6f7e9aec | bellard | saddr = (addr & ESPDMA_MAXADDR) >> 2;
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322 | 2f275b8f | bellard | DPRINTF("write dmareg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->espdmaregs[saddr], val);
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323 | 2f275b8f | bellard | switch (saddr) {
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324 | 2f275b8f | bellard | case 0: |
325 | 2f275b8f | bellard | if (!(val & 0x10)) |
326 | 2f275b8f | bellard | pic_set_irq(s->irq, 0);
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327 | 2f275b8f | bellard | break;
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328 | 2f275b8f | bellard | default:
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329 | 2f275b8f | bellard | break;
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330 | 2f275b8f | bellard | } |
331 | 6f7e9aec | bellard | s->espdmaregs[saddr] = val; |
332 | 6f7e9aec | bellard | } |
333 | 6f7e9aec | bellard | |
334 | 6f7e9aec | bellard | static CPUReadMemoryFunc *espdma_mem_read[3] = { |
335 | 6f7e9aec | bellard | espdma_mem_readl, |
336 | 6f7e9aec | bellard | espdma_mem_readl, |
337 | 6f7e9aec | bellard | espdma_mem_readl, |
338 | 6f7e9aec | bellard | }; |
339 | 6f7e9aec | bellard | |
340 | 6f7e9aec | bellard | static CPUWriteMemoryFunc *espdma_mem_write[3] = { |
341 | 6f7e9aec | bellard | espdma_mem_writel, |
342 | 6f7e9aec | bellard | espdma_mem_writel, |
343 | 6f7e9aec | bellard | espdma_mem_writel, |
344 | 6f7e9aec | bellard | }; |
345 | 6f7e9aec | bellard | |
346 | 6f7e9aec | bellard | static void esp_save(QEMUFile *f, void *opaque) |
347 | 6f7e9aec | bellard | { |
348 | 6f7e9aec | bellard | ESPState *s = opaque; |
349 | 2f275b8f | bellard | unsigned int i; |
350 | 2f275b8f | bellard | |
351 | 2f275b8f | bellard | qemu_put_buffer(f, s->rregs, ESP_MAXREG); |
352 | 2f275b8f | bellard | qemu_put_buffer(f, s->wregs, ESP_MAXREG); |
353 | 2f275b8f | bellard | qemu_put_be32s(f, &s->irq); |
354 | 2f275b8f | bellard | for (i = 0; i < ESPDMA_REGS; i++) |
355 | 2f275b8f | bellard | qemu_put_be32s(f, &s->espdmaregs[i]); |
356 | 6f7e9aec | bellard | } |
357 | 6f7e9aec | bellard | |
358 | 6f7e9aec | bellard | static int esp_load(QEMUFile *f, void *opaque, int version_id) |
359 | 6f7e9aec | bellard | { |
360 | 6f7e9aec | bellard | ESPState *s = opaque; |
361 | 2f275b8f | bellard | unsigned int i; |
362 | 6f7e9aec | bellard | |
363 | 6f7e9aec | bellard | if (version_id != 1) |
364 | 6f7e9aec | bellard | return -EINVAL;
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365 | 6f7e9aec | bellard | |
366 | 2f275b8f | bellard | qemu_get_buffer(f, s->rregs, ESP_MAXREG); |
367 | 2f275b8f | bellard | qemu_get_buffer(f, s->wregs, ESP_MAXREG); |
368 | 2f275b8f | bellard | qemu_get_be32s(f, &s->irq); |
369 | 2f275b8f | bellard | for (i = 0; i < ESPDMA_REGS; i++) |
370 | 2f275b8f | bellard | qemu_get_be32s(f, &s->espdmaregs[i]); |
371 | 2f275b8f | bellard | |
372 | 6f7e9aec | bellard | return 0; |
373 | 6f7e9aec | bellard | } |
374 | 6f7e9aec | bellard | |
375 | 6f7e9aec | bellard | void esp_init(BlockDriverState **bd, int irq, uint32_t espaddr, uint32_t espdaddr) |
376 | 6f7e9aec | bellard | { |
377 | 6f7e9aec | bellard | ESPState *s; |
378 | 6f7e9aec | bellard | int esp_io_memory, espdma_io_memory;
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379 | 6f7e9aec | bellard | |
380 | 6f7e9aec | bellard | s = qemu_mallocz(sizeof(ESPState));
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381 | 6f7e9aec | bellard | if (!s)
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382 | 6f7e9aec | bellard | return;
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383 | 6f7e9aec | bellard | |
384 | 6f7e9aec | bellard | s->bd = bd; |
385 | 6f7e9aec | bellard | s->irq = irq; |
386 | 6f7e9aec | bellard | |
387 | 6f7e9aec | bellard | esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
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388 | 6f7e9aec | bellard | cpu_register_physical_memory(espaddr, ESP_MAXREG*4, esp_io_memory);
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389 | 6f7e9aec | bellard | |
390 | 6f7e9aec | bellard | espdma_io_memory = cpu_register_io_memory(0, espdma_mem_read, espdma_mem_write, s);
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391 | 6f7e9aec | bellard | cpu_register_physical_memory(espdaddr, 16, espdma_io_memory);
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392 | 6f7e9aec | bellard | |
393 | 6f7e9aec | bellard | esp_reset(s); |
394 | 6f7e9aec | bellard | |
395 | 6f7e9aec | bellard | register_savevm("esp", espaddr, 1, esp_save, esp_load, s); |
396 | 6f7e9aec | bellard | qemu_register_reset(esp_reset, s); |
397 | 6f7e9aec | bellard | } |