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/*
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* QEMU i8255x (PRO100) emulation
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*
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* Copyright (c) 2006-2007 Stefan Weil
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*
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* Portions of the code are copies from grub / etherboot eepro100.c
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* and linux e100.c.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Tested features (i82559):
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* PXE boot (i386) no valid link
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* Linux networking (i386) ok
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*
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* Untested:
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* non-i386 platforms
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* Windows networking
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*
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* References:
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*
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* Intel 8255x 10/100 Mbps Ethernet Controller Family
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* Open Source Software Developer Manual
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*/
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#if defined(TARGET_I386)
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# warning "PXE boot still not working!" |
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#endif
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#include <stddef.h> /* offsetof */ |
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#include <stdbool.h> |
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#include "hw.h" |
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#include "loader.h" /* rom_add_option */ |
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#include "pci.h" |
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#include "net.h" |
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#include "eeprom93xx.h" |
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/* Common declarations for all PCI devices. */
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#define PCI_CONFIG_8(offset, value) \
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(pci_conf[offset] = (value)) |
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#define PCI_CONFIG_16(offset, value) \
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(*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value)) |
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#define PCI_CONFIG_32(offset, value) \
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(*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value)) |
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#define KiB 1024 |
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/* Debug EEPRO100 card. */
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//~ #define DEBUG_EEPRO100
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#ifdef DEBUG_EEPRO100
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#define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__) |
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#else
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#define logout(fmt, ...) ((void)0) |
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#endif
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/* Set flags to 0 to disable debug output. */
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#define INT 1 /* interrupt related actions */ |
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#define MDI 1 /* mdi related actions */ |
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#define OTHER 1 |
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#define RXTX 1 |
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#define EEPROM 1 /* eeprom related actions */ |
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#define TRACE(flag, command) ((flag) ? (command) : (void)0) |
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#define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n") |
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#define MAX_ETH_FRAME_SIZE 1514 |
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/* This driver supports several different devices which are declared here. */
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#define i82550 0x82550 |
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#define i82551 0x82551 |
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#define i82557A 0x82557a |
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#define i82557B 0x82557b |
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#define i82557C 0x82557c |
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#define i82558A 0x82558a |
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#define i82558B 0x82558b |
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#define i82559A 0x82559a |
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#define i82559B 0x82559b |
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#define i82559C 0x82559c |
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#define i82559ER 0x82559e |
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#define i82562 0x82562 |
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/* Use 64 word EEPROM. TODO: could be a runtime option. */
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#define EEPROM_SIZE 64 |
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#define PCI_MEM_SIZE (4 * KiB) |
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#define PCI_IO_SIZE 64 |
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#define PCI_FLASH_SIZE (128 * KiB) |
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#define BIT(n) (1 << (n)) |
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#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) |
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/* The SCB accepts the following controls for the Tx and Rx units: */
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#define CU_NOP 0x0000 /* No operation. */ |
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#define CU_START 0x0010 /* CU start. */ |
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#define CU_RESUME 0x0020 /* CU resume. */ |
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#define CU_STATSADDR 0x0040 /* Load dump counters address. */ |
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#define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ |
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#define CU_CMD_BASE 0x0060 /* Load CU base address. */ |
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#define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ |
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#define CU_SRESUME 0x00a0 /* CU static resume. */ |
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#define RU_NOP 0x0000 |
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#define RX_START 0x0001 |
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#define RX_RESUME 0x0002 |
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#define RX_ABORT 0x0004 |
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#define RX_ADDR_LOAD 0x0006 |
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#define RX_RESUMENR 0x0007 |
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#define INT_MASK 0x0100 |
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#define DRVR_INT 0x0200 /* Driver generated interrupt. */ |
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/* Offsets to the various registers.
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All accesses need not be longword aligned. */
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enum speedo_offsets {
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SCBStatus = 0,
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SCBAck = 1,
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SCBCmd = 2, /* Rx/Command Unit command and status. */ |
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SCBIntmask = 3,
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SCBPointer = 4, /* General purpose pointer. */ |
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SCBPort = 8, /* Misc. commands and operands. */ |
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SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */ |
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SCBCtrlMDI = 16, /* MDI interface control. */ |
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SCBEarlyRx = 20, /* Early receive byte count. */ |
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SCBFlow = 24,
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}; |
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/* A speedo3 transmit buffer descriptor with two buffers... */
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typedef struct { |
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uint16_t status; |
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uint16_t command; |
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uint32_t link; /* void * */
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uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */
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uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
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uint8_t tx_threshold; /* transmit threshold */
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uint8_t tbd_count; /* TBD number */
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//~ /* This constitutes two "TBD" entries: hdr and data */
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//~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
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//~ int32_t tx_buf_size0; /* Length of Tx hdr. */
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//~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
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//~ int32_t tx_buf_size1; /* Length of Tx data. */
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} eepro100_tx_t; |
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/* Receive frame descriptor. */
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typedef struct { |
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int16_t status; |
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uint16_t command; |
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uint32_t link; /* struct RxFD * */
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uint32_t rx_buf_addr; /* void * */
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uint16_t count; |
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uint16_t size; |
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char packet[MAX_ETH_FRAME_SIZE + 4]; |
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} eepro100_rx_t; |
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typedef struct { |
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uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, |
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tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, |
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tx_multiple_collisions, tx_total_collisions; |
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uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, |
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rx_resource_errors, rx_overrun_errors, rx_cdt_errors, |
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rx_short_frame_errors; |
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uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; |
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uint16_t xmt_tco_frames, rcv_tco_frames; |
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/* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
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uint32_t reserved[4];
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} eepro100_stats_t; |
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typedef enum { |
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cu_idle = 0,
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cu_suspended = 1,
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cu_active = 2,
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cu_lpq_active = 2,
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cu_hqp_active = 3
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} cu_state_t; |
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typedef enum { |
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ru_idle = 0,
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ru_suspended = 1,
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ru_no_resources = 2,
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ru_ready = 4
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} ru_state_t; |
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typedef struct { |
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PCIDevice dev; |
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uint8_t mult[8]; /* multicast mask array */ |
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int mmio_index;
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NICState *nic; |
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NICConf conf; |
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uint8_t scb_stat; /* SCB stat/ack byte */
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uint8_t int_stat; /* PCI interrupt status */
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/* region must not be saved by nic_save. */
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uint32_t region[3]; /* PCI region addresses */ |
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uint16_t mdimem[32];
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eeprom_t *eeprom; |
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uint32_t device; /* device variant */
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uint32_t pointer; |
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/* (cu_base + cu_offset) address the next command block in the command block list. */
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uint32_t cu_base; /* CU base address */
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uint32_t cu_offset; /* CU address offset */
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/* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
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uint32_t ru_base; /* RU base address */
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uint32_t ru_offset; /* RU address offset */
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uint32_t statsaddr; /* pointer to eepro100_stats_t */
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/* Statistical counters. Also used for wake-up packet (i82559). */
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eepro100_stats_t statistics; |
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#if 0
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uint16_t status;
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#endif
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/* Configuration bytes. */
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uint8_t configuration[22];
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/* Data in mem is always in the byte order of the controller (le). */
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uint8_t mem[PCI_MEM_SIZE]; |
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/* vmstate for each particular nic */
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VMStateDescription *vmstate; |
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/* Quasi static device properties (no need to save them). */
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uint16_t stats_size; |
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bool has_extended_tcb_support;
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} EEPRO100State; |
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/* Default values for MDI (PHY) registers */
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static const uint16_t eepro100_mdi_default[] = { |
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/* MDI Registers 0 - 6, 7 */
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0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, |
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/* MDI Registers 8 - 15 */
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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/* MDI Registers 16 - 31 */
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0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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}; |
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/* Readonly mask for MDI (PHY) registers */
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static const uint16_t eepro100_mdi_mask[] = { |
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0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, |
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, |
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0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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}; |
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/* XXX: optimize */
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static void stl_le_phys(target_phys_addr_t addr, uint32_t val) |
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{ |
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val = cpu_to_le32(val); |
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cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val)); |
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} |
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#define POLYNOMIAL 0x04c11db6 |
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/* From FreeBSD */
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/* XXX: optimize */
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static int compute_mcast_idx(const uint8_t * ep) |
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{ |
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uint32_t crc; |
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int carry, i, j;
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uint8_t b; |
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crc = 0xffffffff;
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for (i = 0; i < 6; i++) { |
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b = *ep++; |
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for (j = 0; j < 8; j++) { |
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carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
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crc <<= 1;
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b >>= 1;
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if (carry) {
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crc = ((crc ^ POLYNOMIAL) | carry); |
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} |
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} |
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} |
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return (crc >> 26); |
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} |
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#if defined(DEBUG_EEPRO100)
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static const char *nic_dump(const uint8_t * buf, unsigned size) |
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{ |
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static char dump[3 * 16 + 1]; |
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char *p = &dump[0]; |
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if (size > 16) { |
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size = 16;
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} |
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while (size-- > 0) { |
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p += sprintf(p, " %02x", *buf++);
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} |
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return dump;
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} |
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#endif /* DEBUG_EEPRO100 */ |
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enum scb_stat_ack {
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stat_ack_not_ours = 0x00,
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stat_ack_sw_gen = 0x04,
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stat_ack_rnr = 0x10,
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stat_ack_cu_idle = 0x20,
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stat_ack_frame_rx = 0x40,
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stat_ack_cu_cmd_done = 0x80,
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stat_ack_not_present = 0xFF,
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stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), |
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stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), |
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}; |
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static void disable_interrupt(EEPRO100State * s) |
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{ |
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if (s->int_stat) {
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TRACE(INT, logout("interrupt disabled\n"));
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qemu_irq_lower(s->dev.irq[0]);
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s->int_stat = 0;
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} |
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} |
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static void enable_interrupt(EEPRO100State * s) |
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{ |
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if (!s->int_stat) {
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TRACE(INT, logout("interrupt enabled\n"));
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qemu_irq_raise(s->dev.irq[0]);
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s->int_stat = 1;
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} |
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} |
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static void eepro100_acknowledge(EEPRO100State * s) |
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{ |
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s->scb_stat &= ~s->mem[SCBAck]; |
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s->mem[SCBAck] = s->scb_stat; |
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if (s->scb_stat == 0) { |
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disable_interrupt(s); |
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} |
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} |
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static void eepro100_interrupt(EEPRO100State * s, uint8_t stat) |
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{ |
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uint8_t mask = ~s->mem[SCBIntmask]; |
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s->mem[SCBAck] |= stat; |
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stat = s->scb_stat = s->mem[SCBAck]; |
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stat &= (mask | 0x0f);
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//~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
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if (stat && (mask & 0x01)) { |
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/* SCB mask and SCB Bit M do not disable interrupt. */
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enable_interrupt(s); |
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} else if (s->int_stat) { |
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disable_interrupt(s); |
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} |
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} |
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static void eepro100_cx_interrupt(EEPRO100State * s) |
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{ |
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/* CU completed action command. */
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/* Transmit not ok (82557 only, not in emulation). */
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eepro100_interrupt(s, 0x80);
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} |
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static void eepro100_cna_interrupt(EEPRO100State * s) |
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{ |
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/* CU left the active state. */
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eepro100_interrupt(s, 0x20);
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} |
368 |
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static void eepro100_fr_interrupt(EEPRO100State * s) |
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{ |
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/* RU received a complete frame. */
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eepro100_interrupt(s, 0x40);
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} |
374 |
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#if 0
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static void eepro100_rnr_interrupt(EEPRO100State * s)
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{
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/* RU is not ready. */
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eepro100_interrupt(s, 0x10);
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}
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#endif
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static void eepro100_mdi_interrupt(EEPRO100State * s) |
384 |
{ |
385 |
/* MDI completed read or write cycle. */
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eepro100_interrupt(s, 0x08);
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} |
388 |
|
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static void eepro100_swi_interrupt(EEPRO100State * s) |
390 |
{ |
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/* Software has requested an interrupt. */
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eepro100_interrupt(s, 0x04);
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} |
394 |
|
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#if 0
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static void eepro100_fcp_interrupt(EEPRO100State * s)
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{
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/* Flow control pause interrupt (82558 and later). */
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eepro100_interrupt(s, 0x01);
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}
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#endif
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|
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static void pci_reset(EEPRO100State * s) |
404 |
{ |
405 |
uint32_t device = s->device; |
406 |
uint8_t *pci_conf = s->dev.config; |
407 |
bool power_management = 1; |
408 |
|
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TRACE(OTHER, logout("%p\n", s));
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|
411 |
/* PCI Vendor ID */
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
413 |
/* PCI Device ID depends on device and is set below. */
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/* PCI Command */
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/* TODO: this is the default, do not override. */
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PCI_CONFIG_16(PCI_COMMAND, 0x0000);
|
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/* PCI Status */
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418 |
/* TODO: this seems to make no sense. */
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419 |
/* TODO: Value at RST# should be 0. */
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420 |
PCI_CONFIG_16(PCI_STATUS, |
421 |
PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_SIG_TARGET_ABORT); |
422 |
/* PCI Revision ID */
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423 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
|
424 |
/* TODO: this is the default, do not override. */
|
425 |
/* PCI Class Code */
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426 |
PCI_CONFIG_8(PCI_CLASS_PROG, 0x00);
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pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
428 |
/* PCI Cache Line Size */
|
429 |
/* check cache line size!!! */
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430 |
//~ PCI_CONFIG_8(0x0c, 0x00);
|
431 |
/* PCI Latency Timer */
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432 |
PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); // latency timer = 32 clocks |
433 |
/* PCI Header Type */
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434 |
/* BIST (built-in self test) */
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435 |
#if defined(TARGET_I386)
|
436 |
// !!! workaround for buggy bios
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//~ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0
|
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#endif
|
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#if 0
|
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/* PCI Base Address Registers */
|
441 |
/* CSR Memory Mapped Base Address */
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442 |
PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
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PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_MEM_PREFETCH);
|
445 |
/* CSR I/O Mapped Base Address */
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PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_SPACE_IO);
|
447 |
#if 0
|
448 |
/* Flash Memory Mapped Base Address */
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449 |
PCI_CONFIG_32(PCI_BASE_ADDRESS_2,
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0xfffe0000 | PCI_BASE_ADDRESS_SPACE_MEMORY);
|
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#endif
|
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#endif
|
453 |
/* Expansion ROM Base Address (depends on boot disable!!!) */
|
454 |
/* TODO: not needed, set when BAR is registered */
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PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY); |
456 |
/* Capability Pointer */
|
457 |
/* TODO: revisions with power_management 1 use this but
|
458 |
* do not set new capability list bit in status register. */
|
459 |
PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc);
|
460 |
/* Interrupt Line */
|
461 |
/* Interrupt Pin */
|
462 |
/* TODO: RST# value should be 0 */
|
463 |
PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); // interrupt pin 0 |
464 |
/* Minimum Grant */
|
465 |
PCI_CONFIG_8(PCI_MIN_GNT, 0x08);
|
466 |
/* Maximum Latency */
|
467 |
PCI_CONFIG_8(PCI_MAX_LAT, 0x18);
|
468 |
|
469 |
switch (device) {
|
470 |
case i82550:
|
471 |
// TODO: check device id.
|
472 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
473 |
/* Revision ID: 0x0c, 0x0d, 0x0e. */
|
474 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
|
475 |
// TODO: check size of statistical counters.
|
476 |
s->stats_size = 80;
|
477 |
// TODO: check extended tcb support.
|
478 |
s->has_extended_tcb_support = 1;
|
479 |
break;
|
480 |
case i82551:
|
481 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
482 |
/* Revision ID: 0x0f, 0x10. */
|
483 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
|
484 |
// TODO: check size of statistical counters.
|
485 |
s->stats_size = 80;
|
486 |
s->has_extended_tcb_support = 1;
|
487 |
break;
|
488 |
case i82557A:
|
489 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
490 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x01);
|
491 |
PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
|
492 |
power_management = 0;
|
493 |
break;
|
494 |
case i82557B:
|
495 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
496 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
|
497 |
PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
|
498 |
power_management = 0;
|
499 |
break;
|
500 |
case i82557C:
|
501 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
502 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
|
503 |
PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
|
504 |
power_management = 0;
|
505 |
break;
|
506 |
case i82558A:
|
507 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
508 |
PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
509 |
PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); |
510 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x04);
|
511 |
s->stats_size = 76;
|
512 |
s->has_extended_tcb_support = 1;
|
513 |
break;
|
514 |
case i82558B:
|
515 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
516 |
PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
517 |
PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); |
518 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
|
519 |
s->stats_size = 76;
|
520 |
s->has_extended_tcb_support = 1;
|
521 |
break;
|
522 |
case i82559A:
|
523 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
524 |
PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
525 |
PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); |
526 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x06);
|
527 |
s->stats_size = 80;
|
528 |
s->has_extended_tcb_support = 1;
|
529 |
break;
|
530 |
case i82559B:
|
531 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
532 |
PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
533 |
PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); |
534 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x07);
|
535 |
s->stats_size = 80;
|
536 |
s->has_extended_tcb_support = 1;
|
537 |
break;
|
538 |
case i82559C:
|
539 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
540 |
PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
541 |
PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); |
542 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
|
543 |
// TODO: Windows wants revision id 0x0c.
|
544 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
|
545 |
#if EEPROM_SIZE > 0 |
546 |
PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
|
547 |
PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040);
|
548 |
#endif
|
549 |
s->stats_size = 80;
|
550 |
s->has_extended_tcb_support = 1;
|
551 |
break;
|
552 |
case i82559ER:
|
553 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
554 |
PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
555 |
PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); |
556 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
|
557 |
s->stats_size = 80;
|
558 |
s->has_extended_tcb_support = 1;
|
559 |
break;
|
560 |
case i82562:
|
561 |
// TODO: check device id.
|
562 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
563 |
/* TODO: wrong revision id. */
|
564 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
|
565 |
s->stats_size = 80;
|
566 |
s->has_extended_tcb_support = 1;
|
567 |
break;
|
568 |
default:
|
569 |
logout("Device %X is undefined!\n", device);
|
570 |
} |
571 |
|
572 |
s->configuration[6] |= BIT(5); |
573 |
|
574 |
if (s->stats_size == 80) { |
575 |
/* TODO: check TCO Statistical Counters bit. Documentation not clear. */
|
576 |
if (s->configuration[6] & BIT(2)) { |
577 |
/* TCO statistical counters. */
|
578 |
assert(s->configuration[6] & BIT(5)); |
579 |
} else {
|
580 |
if (s->configuration[6] & BIT(5)) { |
581 |
/* No extended statistical counters, i82557 compatible. */
|
582 |
s->stats_size = 64;
|
583 |
} else {
|
584 |
/* i82558 compatible. */
|
585 |
s->stats_size = 76;
|
586 |
} |
587 |
} |
588 |
} else {
|
589 |
if (s->configuration[6] & BIT(5)) { |
590 |
/* No extended statistical counters. */
|
591 |
s->stats_size = 64;
|
592 |
} |
593 |
} |
594 |
assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics)); |
595 |
|
596 |
if (power_management) {
|
597 |
/* Power Management Capabilities */
|
598 |
PCI_CONFIG_8(0xdc, 0x01); |
599 |
/* Next Item Pointer */
|
600 |
/* Capability ID */
|
601 |
PCI_CONFIG_16(0xde, 0x7e21); |
602 |
/* TODO: Power Management Control / Status. */
|
603 |
/* TODO: Ethernet Power Consumption Registers (i82559 and later). */
|
604 |
} |
605 |
|
606 |
#if EEPROM_SIZE > 0 |
607 |
if (device == i82557C || device == i82558B || device == i82559C) {
|
608 |
// TODO: get vendor id from EEPROM for i82557C or later.
|
609 |
// TODO: get device id from EEPROM for i82557C or later.
|
610 |
// TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
|
611 |
// TODO: header type is determined by EEPROM for i82559.
|
612 |
// TODO: get subsystem id from EEPROM for i82557C or later.
|
613 |
// TODO: get subsystem vendor id from EEPROM for i82557C or later.
|
614 |
// TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
|
615 |
// TODO: capability pointer depends on EEPROM for i82558.
|
616 |
logout("Get device id and revision from EEPROM!!!\n");
|
617 |
} |
618 |
#endif /* EEPROM_SIZE > 0 */ |
619 |
} |
620 |
|
621 |
static void nic_selective_reset(EEPRO100State * s) |
622 |
{ |
623 |
size_t i; |
624 |
uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); |
625 |
//~ eeprom93xx_reset(s->eeprom);
|
626 |
memcpy(eeprom_contents, s->conf.macaddr.a, 6);
|
627 |
eeprom_contents[0xa] = 0x4000; |
628 |
if (s->device == i82557B || s->device == i82557C)
|
629 |
eeprom_contents[5] = 0x0100; |
630 |
uint16_t sum = 0;
|
631 |
for (i = 0; i < EEPROM_SIZE - 1; i++) { |
632 |
sum += eeprom_contents[i]; |
633 |
} |
634 |
eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; |
635 |
TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1])); |
636 |
|
637 |
memset(s->mem, 0, sizeof(s->mem)); |
638 |
uint32_t val = BIT(21);
|
639 |
memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
|
640 |
|
641 |
assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); |
642 |
memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); |
643 |
} |
644 |
|
645 |
static void nic_reset(void *opaque) |
646 |
{ |
647 |
EEPRO100State *s = opaque; |
648 |
TRACE(OTHER, logout("%p\n", s));
|
649 |
nic_selective_reset(s); |
650 |
} |
651 |
|
652 |
#if defined(DEBUG_EEPRO100)
|
653 |
static const char * const e100_reg[PCI_IO_SIZE / 4] = { |
654 |
"Command/Status",
|
655 |
"General Pointer",
|
656 |
"Port",
|
657 |
"EEPROM/Flash Control",
|
658 |
"MDI Control",
|
659 |
"Receive DMA Byte Count",
|
660 |
"Flow Control",
|
661 |
"General Status/Control"
|
662 |
}; |
663 |
|
664 |
static char *regname(uint32_t addr) |
665 |
{ |
666 |
static char buf[32]; |
667 |
if (addr < PCI_IO_SIZE) {
|
668 |
const char *r = e100_reg[addr / 4]; |
669 |
if (r != 0) { |
670 |
snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4); |
671 |
} else {
|
672 |
snprintf(buf, sizeof(buf), "0x%02x", addr); |
673 |
} |
674 |
} else {
|
675 |
snprintf(buf, sizeof(buf), "??? 0x%08x", addr); |
676 |
} |
677 |
return buf;
|
678 |
} |
679 |
#endif /* DEBUG_EEPRO100 */ |
680 |
|
681 |
#if 0
|
682 |
static uint16_t eepro100_read_status(EEPRO100State * s)
|
683 |
{
|
684 |
uint16_t val = s->status;
|
685 |
TRACE(OTHER, logout("val=0x%04x\n", val));
|
686 |
return val;
|
687 |
}
|
688 |
|
689 |
static void eepro100_write_status(EEPRO100State * s, uint16_t val)
|
690 |
{
|
691 |
TRACE(OTHER, logout("val=0x%04x\n", val));
|
692 |
s->status = val;
|
693 |
}
|
694 |
#endif
|
695 |
|
696 |
/*****************************************************************************
|
697 |
*
|
698 |
* Command emulation.
|
699 |
*
|
700 |
****************************************************************************/
|
701 |
|
702 |
#if 0
|
703 |
static uint16_t eepro100_read_command(EEPRO100State * s)
|
704 |
{
|
705 |
uint16_t val = 0xffff;
|
706 |
//~ TRACE(OTHER, logout("val=0x%04x\n", val));
|
707 |
return val;
|
708 |
}
|
709 |
#endif
|
710 |
|
711 |
/* Commands that can be put in a command list entry. */
|
712 |
enum commands {
|
713 |
CmdNOp = 0,
|
714 |
CmdIASetup = 1,
|
715 |
CmdConfigure = 2,
|
716 |
CmdMulticastList = 3,
|
717 |
CmdTx = 4,
|
718 |
CmdTDR = 5, /* load microcode */ |
719 |
CmdDump = 6,
|
720 |
CmdDiagnose = 7,
|
721 |
|
722 |
/* And some extra flags: */
|
723 |
CmdSuspend = 0x4000, /* Suspend after completion. */ |
724 |
CmdIntr = 0x2000, /* Interrupt after completion. */ |
725 |
CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ |
726 |
}; |
727 |
|
728 |
static cu_state_t get_cu_state(EEPRO100State * s)
|
729 |
{ |
730 |
return ((s->mem[SCBStatus] >> 6) & 0x03); |
731 |
} |
732 |
|
733 |
static void set_cu_state(EEPRO100State * s, cu_state_t state) |
734 |
{ |
735 |
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6); |
736 |
} |
737 |
|
738 |
static ru_state_t get_ru_state(EEPRO100State * s)
|
739 |
{ |
740 |
return ((s->mem[SCBStatus] >> 2) & 0x0f); |
741 |
} |
742 |
|
743 |
static void set_ru_state(EEPRO100State * s, ru_state_t state) |
744 |
{ |
745 |
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2); |
746 |
} |
747 |
|
748 |
static void dump_statistics(EEPRO100State * s) |
749 |
{ |
750 |
/* Dump statistical data. Most data is never changed by the emulation
|
751 |
* and always 0, so we first just copy the whole block and then those
|
752 |
* values which really matter.
|
753 |
* Number of data should check configuration!!!
|
754 |
*/
|
755 |
cpu_physical_memory_write(s->statsaddr, |
756 |
(uint8_t *) & s->statistics, s->stats_size); |
757 |
stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
|
758 |
stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
|
759 |
stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
|
760 |
stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
|
761 |
//~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
|
762 |
//~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
|
763 |
//~ missing("CU dump statistical counters");
|
764 |
} |
765 |
|
766 |
static void action_command(EEPRO100State *s) |
767 |
{ |
768 |
for (;;) {
|
769 |
uint32_t cb_address = s->cu_base + s->cu_offset; |
770 |
eepro100_tx_t tx; |
771 |
cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx));
|
772 |
uint16_t status = le16_to_cpu(tx.status); |
773 |
uint16_t command = le16_to_cpu(tx.command); |
774 |
logout |
775 |
("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
|
776 |
val, status, command, tx.link); |
777 |
bool bit_el = ((command & 0x8000) != 0); |
778 |
bool bit_s = ((command & 0x4000) != 0); |
779 |
bool bit_i = ((command & 0x2000) != 0); |
780 |
bool bit_nc = ((command & 0x0010) != 0); |
781 |
bool success = true; |
782 |
//~ bool bit_sf = ((command & 0x0008) != 0);
|
783 |
uint16_t cmd = command & 0x0007;
|
784 |
s->cu_offset = le32_to_cpu(tx.link); |
785 |
switch (cmd) {
|
786 |
case CmdNOp:
|
787 |
/* Do nothing. */
|
788 |
break;
|
789 |
case CmdIASetup:
|
790 |
cpu_physical_memory_read(cb_address + 8, &s->conf.macaddr.a[0], 6); |
791 |
TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6))); |
792 |
break;
|
793 |
case CmdConfigure:
|
794 |
cpu_physical_memory_read(cb_address + 8, &s->configuration[0], |
795 |
sizeof(s->configuration));
|
796 |
TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16))); |
797 |
break;
|
798 |
case CmdMulticastList:
|
799 |
//~ missing("multicast list");
|
800 |
break;
|
801 |
case CmdTx:
|
802 |
(void)0; |
803 |
uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr); |
804 |
uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff);
|
805 |
TRACE(RXTX, logout |
806 |
("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
|
807 |
tbd_array, tcb_bytes, tx.tbd_count)); |
808 |
|
809 |
if (bit_nc) {
|
810 |
missing("CmdTx: NC = 0");
|
811 |
success = false;
|
812 |
break;
|
813 |
} |
814 |
//~ assert(!bit_sf);
|
815 |
if (tcb_bytes > 2600) { |
816 |
logout("TCB byte count too large, using 2600\n");
|
817 |
tcb_bytes = 2600;
|
818 |
} |
819 |
/* Next assertion fails for local configuration. */
|
820 |
//~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
|
821 |
if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { |
822 |
logout |
823 |
("illegal values of TBD array address and TCB byte count!\n");
|
824 |
} |
825 |
// sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes
|
826 |
uint8_t buf[2600];
|
827 |
uint16_t size = 0;
|
828 |
uint32_t tbd_address = cb_address + 0x10;
|
829 |
assert(tcb_bytes <= sizeof(buf));
|
830 |
while (size < tcb_bytes) {
|
831 |
uint32_t tx_buffer_address = ldl_phys(tbd_address); |
832 |
uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
833 |
//~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
834 |
tbd_address += 8;
|
835 |
TRACE(RXTX, logout |
836 |
("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
|
837 |
tx_buffer_address, tx_buffer_size)); |
838 |
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
839 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
840 |
tx_buffer_size); |
841 |
size += tx_buffer_size; |
842 |
} |
843 |
if (tbd_array == 0xffffffff) { |
844 |
/* Simplified mode. Was already handled by code above. */
|
845 |
} else {
|
846 |
/* Flexible mode. */
|
847 |
uint8_t tbd_count = 0;
|
848 |
if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) { |
849 |
/* Extended Flexible TCB. */
|
850 |
for (; tbd_count < 2; tbd_count++) { |
851 |
uint32_t tx_buffer_address = ldl_phys(tbd_address); |
852 |
uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
853 |
uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
854 |
tbd_address += 8;
|
855 |
TRACE(RXTX, logout |
856 |
("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
|
857 |
tx_buffer_address, tx_buffer_size)); |
858 |
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
859 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
860 |
tx_buffer_size); |
861 |
size += tx_buffer_size; |
862 |
if (tx_buffer_el & 1) { |
863 |
break;
|
864 |
} |
865 |
} |
866 |
} |
867 |
tbd_address = tbd_array; |
868 |
for (; tbd_count < tx.tbd_count; tbd_count++) {
|
869 |
uint32_t tx_buffer_address = ldl_phys(tbd_address); |
870 |
uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
871 |
uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
872 |
tbd_address += 8;
|
873 |
TRACE(RXTX, logout |
874 |
("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
|
875 |
tx_buffer_address, tx_buffer_size)); |
876 |
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
877 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
878 |
tx_buffer_size); |
879 |
size += tx_buffer_size; |
880 |
if (tx_buffer_el & 1) { |
881 |
break;
|
882 |
} |
883 |
} |
884 |
} |
885 |
TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
|
886 |
qemu_send_packet(&s->nic->nc, buf, size); |
887 |
s->statistics.tx_good_frames++; |
888 |
/* Transmit with bad status would raise an CX/TNO interrupt.
|
889 |
* (82557 only). Emulation never has bad status. */
|
890 |
//~ eepro100_cx_interrupt(s);
|
891 |
break;
|
892 |
case CmdTDR:
|
893 |
TRACE(OTHER, logout("load microcode\n"));
|
894 |
/* Starting with offset 8, the command contains
|
895 |
* 64 dwords microcode which we just ignore here. */
|
896 |
break;
|
897 |
default:
|
898 |
missing("undefined command");
|
899 |
success = false;
|
900 |
break;
|
901 |
} |
902 |
/* Write new status. */
|
903 |
stw_phys(cb_address, status | 0x8000 | (success ? 0x2000 : 0)); |
904 |
if (bit_i) {
|
905 |
/* CU completed action. */
|
906 |
eepro100_cx_interrupt(s); |
907 |
} |
908 |
if (bit_el) {
|
909 |
/* CU becomes idle. Terminate command loop. */
|
910 |
set_cu_state(s, cu_idle); |
911 |
eepro100_cna_interrupt(s); |
912 |
break;
|
913 |
} else if (bit_s) { |
914 |
/* CU becomes suspended. Terminate command loop. */
|
915 |
set_cu_state(s, cu_suspended); |
916 |
eepro100_cna_interrupt(s); |
917 |
break;
|
918 |
} else {
|
919 |
/* More entries in list. */
|
920 |
TRACE(OTHER, logout("CU list with at least one more entry\n"));
|
921 |
} |
922 |
} |
923 |
TRACE(OTHER, logout("CU list empty\n"));
|
924 |
/* List is empty. Now CU is idle or suspended. */
|
925 |
} |
926 |
|
927 |
static void eepro100_cu_command(EEPRO100State * s, uint8_t val) |
928 |
{ |
929 |
switch (val) {
|
930 |
case CU_NOP:
|
931 |
/* No operation. */
|
932 |
break;
|
933 |
case CU_START:
|
934 |
if (get_cu_state(s) != cu_idle) {
|
935 |
/* Intel documentation says that CU must be idle for the CU
|
936 |
* start command. Intel driver for Linux also starts the CU
|
937 |
* from suspended state. */
|
938 |
logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
|
939 |
//~ assert(!"wrong CU state");
|
940 |
} |
941 |
set_cu_state(s, cu_active); |
942 |
s->cu_offset = s->pointer; |
943 |
action_command(s); |
944 |
break;
|
945 |
case CU_RESUME:
|
946 |
if (get_cu_state(s) != cu_suspended) {
|
947 |
logout("bad CU resume from CU state %u\n", get_cu_state(s));
|
948 |
/* Workaround for bad Linux eepro100 driver which resumes
|
949 |
* from idle state. */
|
950 |
//~ missing("cu resume");
|
951 |
set_cu_state(s, cu_suspended); |
952 |
} |
953 |
if (get_cu_state(s) == cu_suspended) {
|
954 |
TRACE(OTHER, logout("CU resuming\n"));
|
955 |
set_cu_state(s, cu_active); |
956 |
action_command(s); |
957 |
} |
958 |
break;
|
959 |
case CU_STATSADDR:
|
960 |
/* Load dump counters address. */
|
961 |
s->statsaddr = s->pointer; |
962 |
TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
|
963 |
break;
|
964 |
case CU_SHOWSTATS:
|
965 |
/* Dump statistical counters. */
|
966 |
TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
|
967 |
dump_statistics(s); |
968 |
stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
|
969 |
break;
|
970 |
case CU_CMD_BASE:
|
971 |
/* Load CU base. */
|
972 |
TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
|
973 |
s->cu_base = s->pointer; |
974 |
break;
|
975 |
case CU_DUMPSTATS:
|
976 |
/* Dump and reset statistical counters. */
|
977 |
TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
|
978 |
dump_statistics(s); |
979 |
stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
|
980 |
memset(&s->statistics, 0, sizeof(s->statistics)); |
981 |
break;
|
982 |
case CU_SRESUME:
|
983 |
/* CU static resume. */
|
984 |
missing("CU static resume");
|
985 |
break;
|
986 |
default:
|
987 |
missing("Undefined CU command");
|
988 |
} |
989 |
} |
990 |
|
991 |
static void eepro100_ru_command(EEPRO100State * s, uint8_t val) |
992 |
{ |
993 |
switch (val) {
|
994 |
case RU_NOP:
|
995 |
/* No operation. */
|
996 |
break;
|
997 |
case RX_START:
|
998 |
/* RU start. */
|
999 |
if (get_ru_state(s) != ru_idle) {
|
1000 |
logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
|
1001 |
//~ assert(!"wrong RU state");
|
1002 |
} |
1003 |
set_ru_state(s, ru_ready); |
1004 |
s->ru_offset = s->pointer; |
1005 |
TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
|
1006 |
break;
|
1007 |
case RX_RESUME:
|
1008 |
/* Restart RU. */
|
1009 |
if (get_ru_state(s) != ru_suspended) {
|
1010 |
logout("RU state is %u, should be %u\n", get_ru_state(s),
|
1011 |
ru_suspended); |
1012 |
//~ assert(!"wrong RU state");
|
1013 |
} |
1014 |
set_ru_state(s, ru_ready); |
1015 |
break;
|
1016 |
case RX_ADDR_LOAD:
|
1017 |
/* Load RU base. */
|
1018 |
TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
|
1019 |
s->ru_base = s->pointer; |
1020 |
break;
|
1021 |
default:
|
1022 |
logout("val=0x%02x (undefined RU command)\n", val);
|
1023 |
missing("Undefined SU command");
|
1024 |
} |
1025 |
} |
1026 |
|
1027 |
static void eepro100_write_command(EEPRO100State * s, uint8_t val) |
1028 |
{ |
1029 |
eepro100_ru_command(s, val & 0x0f);
|
1030 |
eepro100_cu_command(s, val & 0xf0);
|
1031 |
if ((val) == 0) { |
1032 |
TRACE(OTHER, logout("val=0x%02x\n", val));
|
1033 |
} |
1034 |
/* Clear command byte after command was accepted. */
|
1035 |
s->mem[SCBCmd] = 0;
|
1036 |
} |
1037 |
|
1038 |
/*****************************************************************************
|
1039 |
*
|
1040 |
* EEPROM emulation.
|
1041 |
*
|
1042 |
****************************************************************************/
|
1043 |
|
1044 |
#define EEPROM_CS 0x02 |
1045 |
#define EEPROM_SK 0x01 |
1046 |
#define EEPROM_DI 0x04 |
1047 |
#define EEPROM_DO 0x08 |
1048 |
|
1049 |
static uint16_t eepro100_read_eeprom(EEPRO100State * s)
|
1050 |
{ |
1051 |
uint16_t val; |
1052 |
memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
|
1053 |
if (eeprom93xx_read(s->eeprom)) {
|
1054 |
val |= EEPROM_DO; |
1055 |
} else {
|
1056 |
val &= ~EEPROM_DO; |
1057 |
} |
1058 |
TRACE(EEPROM, logout("val=0x%04x\n", val));
|
1059 |
return val;
|
1060 |
} |
1061 |
|
1062 |
static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) |
1063 |
{ |
1064 |
TRACE(EEPROM, logout("val=0x%02x\n", val));
|
1065 |
|
1066 |
/* mask unwriteable bits */
|
1067 |
//~ val = SET_MASKED(val, 0x31, eeprom->value);
|
1068 |
|
1069 |
int eecs = ((val & EEPROM_CS) != 0); |
1070 |
int eesk = ((val & EEPROM_SK) != 0); |
1071 |
int eedi = ((val & EEPROM_DI) != 0); |
1072 |
eeprom93xx_write(eeprom, eecs, eesk, eedi); |
1073 |
} |
1074 |
|
1075 |
static void eepro100_write_pointer(EEPRO100State * s, uint32_t val) |
1076 |
{ |
1077 |
s->pointer = le32_to_cpu(val); |
1078 |
TRACE(OTHER, logout("val=0x%08x\n", val));
|
1079 |
} |
1080 |
|
1081 |
/*****************************************************************************
|
1082 |
*
|
1083 |
* MDI emulation.
|
1084 |
*
|
1085 |
****************************************************************************/
|
1086 |
|
1087 |
#if defined(DEBUG_EEPRO100)
|
1088 |
static const char * const mdi_op_name[] = { |
1089 |
"opcode 0",
|
1090 |
"write",
|
1091 |
"read",
|
1092 |
"opcode 3"
|
1093 |
}; |
1094 |
|
1095 |
static const char * const mdi_reg_name[] = { |
1096 |
"Control",
|
1097 |
"Status",
|
1098 |
"PHY Identification (Word 1)",
|
1099 |
"PHY Identification (Word 2)",
|
1100 |
"Auto-Negotiation Advertisement",
|
1101 |
"Auto-Negotiation Link Partner Ability",
|
1102 |
"Auto-Negotiation Expansion"
|
1103 |
}; |
1104 |
|
1105 |
static const char *reg2name(uint8_t reg) |
1106 |
{ |
1107 |
static char buffer[10]; |
1108 |
const char *p = buffer; |
1109 |
if (reg < ARRAY_SIZE(mdi_reg_name)) {
|
1110 |
p = mdi_reg_name[reg]; |
1111 |
} else {
|
1112 |
snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg); |
1113 |
} |
1114 |
return p;
|
1115 |
} |
1116 |
#endif /* DEBUG_EEPRO100 */ |
1117 |
|
1118 |
static uint32_t eepro100_read_mdi(EEPRO100State * s)
|
1119 |
{ |
1120 |
uint32_t val; |
1121 |
memcpy(&val, &s->mem[0x10], sizeof(val)); |
1122 |
|
1123 |
#ifdef DEBUG_EEPRO100
|
1124 |
uint8_t raiseint = (val & BIT(29)) >> 29; |
1125 |
uint8_t opcode = (val & BITS(27, 26)) >> 26; |
1126 |
uint8_t phy = (val & BITS(25, 21)) >> 21; |
1127 |
uint8_t reg = (val & BITS(20, 16)) >> 16; |
1128 |
uint16_t data = (val & BITS(15, 0)); |
1129 |
#endif
|
1130 |
/* Emulation takes no time to finish MDI transaction. */
|
1131 |
val |= BIT(28);
|
1132 |
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
1133 |
val, raiseint, mdi_op_name[opcode], phy, |
1134 |
reg2name(reg), data)); |
1135 |
return val;
|
1136 |
} |
1137 |
|
1138 |
static void eepro100_write_mdi(EEPRO100State * s, uint32_t val) |
1139 |
{ |
1140 |
uint8_t raiseint = (val & BIT(29)) >> 29; |
1141 |
uint8_t opcode = (val & BITS(27, 26)) >> 26; |
1142 |
uint8_t phy = (val & BITS(25, 21)) >> 21; |
1143 |
uint8_t reg = (val & BITS(20, 16)) >> 16; |
1144 |
uint16_t data = (val & BITS(15, 0)); |
1145 |
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
1146 |
val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data)); |
1147 |
if (phy != 1) { |
1148 |
/* Unsupported PHY address. */
|
1149 |
//~ logout("phy must be 1 but is %u\n", phy);
|
1150 |
data = 0;
|
1151 |
} else if (opcode != 1 && opcode != 2) { |
1152 |
/* Unsupported opcode. */
|
1153 |
logout("opcode must be 1 or 2 but is %u\n", opcode);
|
1154 |
data = 0;
|
1155 |
} else if (reg > 6) { |
1156 |
/* Unsupported register. */
|
1157 |
logout("register must be 0...6 but is %u\n", reg);
|
1158 |
data = 0;
|
1159 |
} else {
|
1160 |
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
1161 |
val, raiseint, mdi_op_name[opcode], phy, |
1162 |
reg2name(reg), data)); |
1163 |
if (opcode == 1) { |
1164 |
/* MDI write */
|
1165 |
switch (reg) {
|
1166 |
case 0: /* Control Register */ |
1167 |
if (data & 0x8000) { |
1168 |
/* Reset status and control registers to default. */
|
1169 |
s->mdimem[0] = eepro100_mdi_default[0]; |
1170 |
s->mdimem[1] = eepro100_mdi_default[1]; |
1171 |
data = s->mdimem[reg]; |
1172 |
} else {
|
1173 |
/* Restart Auto Configuration = Normal Operation */
|
1174 |
data &= ~0x0200;
|
1175 |
} |
1176 |
break;
|
1177 |
case 1: /* Status Register */ |
1178 |
missing("not writable");
|
1179 |
data = s->mdimem[reg]; |
1180 |
break;
|
1181 |
case 2: /* PHY Identification Register (Word 1) */ |
1182 |
case 3: /* PHY Identification Register (Word 2) */ |
1183 |
missing("not implemented");
|
1184 |
break;
|
1185 |
case 4: /* Auto-Negotiation Advertisement Register */ |
1186 |
case 5: /* Auto-Negotiation Link Partner Ability Register */ |
1187 |
break;
|
1188 |
case 6: /* Auto-Negotiation Expansion Register */ |
1189 |
default:
|
1190 |
missing("not implemented");
|
1191 |
} |
1192 |
s->mdimem[reg] = data; |
1193 |
} else if (opcode == 2) { |
1194 |
/* MDI read */
|
1195 |
switch (reg) {
|
1196 |
case 0: /* Control Register */ |
1197 |
if (data & 0x8000) { |
1198 |
/* Reset status and control registers to default. */
|
1199 |
s->mdimem[0] = eepro100_mdi_default[0]; |
1200 |
s->mdimem[1] = eepro100_mdi_default[1]; |
1201 |
} |
1202 |
break;
|
1203 |
case 1: /* Status Register */ |
1204 |
s->mdimem[reg] |= 0x0020;
|
1205 |
break;
|
1206 |
case 2: /* PHY Identification Register (Word 1) */ |
1207 |
case 3: /* PHY Identification Register (Word 2) */ |
1208 |
case 4: /* Auto-Negotiation Advertisement Register */ |
1209 |
break;
|
1210 |
case 5: /* Auto-Negotiation Link Partner Ability Register */ |
1211 |
s->mdimem[reg] = 0x41fe;
|
1212 |
break;
|
1213 |
case 6: /* Auto-Negotiation Expansion Register */ |
1214 |
s->mdimem[reg] = 0x0001;
|
1215 |
break;
|
1216 |
} |
1217 |
data = s->mdimem[reg]; |
1218 |
} |
1219 |
/* Emulation takes no time to finish MDI transaction.
|
1220 |
* Set MDI bit in SCB status register. */
|
1221 |
s->mem[SCBAck] |= 0x08;
|
1222 |
val |= BIT(28);
|
1223 |
if (raiseint) {
|
1224 |
eepro100_mdi_interrupt(s); |
1225 |
} |
1226 |
} |
1227 |
val = (val & 0xffff0000) + data;
|
1228 |
memcpy(&s->mem[0x10], &val, sizeof(val)); |
1229 |
} |
1230 |
|
1231 |
/*****************************************************************************
|
1232 |
*
|
1233 |
* Port emulation.
|
1234 |
*
|
1235 |
****************************************************************************/
|
1236 |
|
1237 |
#define PORT_SOFTWARE_RESET 0 |
1238 |
#define PORT_SELFTEST 1 |
1239 |
#define PORT_SELECTIVE_RESET 2 |
1240 |
#define PORT_DUMP 3 |
1241 |
#define PORT_SELECTION_MASK 3 |
1242 |
|
1243 |
typedef struct { |
1244 |
uint32_t st_sign; /* Self Test Signature */
|
1245 |
uint32_t st_result; /* Self Test Results */
|
1246 |
} eepro100_selftest_t; |
1247 |
|
1248 |
static uint32_t eepro100_read_port(EEPRO100State * s)
|
1249 |
{ |
1250 |
return 0; |
1251 |
} |
1252 |
|
1253 |
static void eepro100_write_port(EEPRO100State * s, uint32_t val) |
1254 |
{ |
1255 |
val = le32_to_cpu(val); |
1256 |
uint32_t address = (val & ~PORT_SELECTION_MASK); |
1257 |
uint8_t selection = (val & PORT_SELECTION_MASK); |
1258 |
switch (selection) {
|
1259 |
case PORT_SOFTWARE_RESET:
|
1260 |
nic_reset(s); |
1261 |
break;
|
1262 |
case PORT_SELFTEST:
|
1263 |
TRACE(OTHER, logout("selftest address=0x%08x\n", address));
|
1264 |
eepro100_selftest_t data; |
1265 |
cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
|
1266 |
data.st_sign = 0xffffffff;
|
1267 |
data.st_result = 0;
|
1268 |
cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
|
1269 |
break;
|
1270 |
case PORT_SELECTIVE_RESET:
|
1271 |
TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
|
1272 |
nic_selective_reset(s); |
1273 |
break;
|
1274 |
default:
|
1275 |
logout("val=0x%08x\n", val);
|
1276 |
missing("unknown port selection");
|
1277 |
} |
1278 |
} |
1279 |
|
1280 |
/*****************************************************************************
|
1281 |
*
|
1282 |
* General hardware emulation.
|
1283 |
*
|
1284 |
****************************************************************************/
|
1285 |
|
1286 |
static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
|
1287 |
{ |
1288 |
uint8_t val; |
1289 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1290 |
memcpy(&val, &s->mem[addr], sizeof(val));
|
1291 |
} |
1292 |
|
1293 |
switch (addr) {
|
1294 |
case SCBStatus:
|
1295 |
//~ val = eepro100_read_status(s);
|
1296 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1297 |
break;
|
1298 |
case SCBAck:
|
1299 |
//~ val = eepro100_read_status(s);
|
1300 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1301 |
break;
|
1302 |
case SCBCmd:
|
1303 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1304 |
//~ val = eepro100_read_command(s);
|
1305 |
break;
|
1306 |
case SCBIntmask:
|
1307 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1308 |
break;
|
1309 |
case SCBPort + 3: |
1310 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1311 |
break;
|
1312 |
case SCBeeprom:
|
1313 |
val = eepro100_read_eeprom(s); |
1314 |
break;
|
1315 |
case 0x1b: /* PMDR (power management driver register) */ |
1316 |
val = 0;
|
1317 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1318 |
break;
|
1319 |
case 0x1d: /* general status register */ |
1320 |
/* 100 Mbps full duplex, valid link */
|
1321 |
val = 0x07;
|
1322 |
TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
|
1323 |
break;
|
1324 |
default:
|
1325 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1326 |
missing("unknown byte read");
|
1327 |
} |
1328 |
return val;
|
1329 |
} |
1330 |
|
1331 |
static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
|
1332 |
{ |
1333 |
uint16_t val; |
1334 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1335 |
memcpy(&val, &s->mem[addr], sizeof(val));
|
1336 |
} |
1337 |
|
1338 |
switch (addr) {
|
1339 |
case SCBStatus:
|
1340 |
//~ val = eepro100_read_status(s);
|
1341 |
case SCBCmd:
|
1342 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
1343 |
break;
|
1344 |
case SCBeeprom:
|
1345 |
val = eepro100_read_eeprom(s); |
1346 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
1347 |
break;
|
1348 |
default:
|
1349 |
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
1350 |
missing("unknown word read");
|
1351 |
} |
1352 |
return val;
|
1353 |
} |
1354 |
|
1355 |
static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
|
1356 |
{ |
1357 |
uint32_t val; |
1358 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1359 |
memcpy(&val, &s->mem[addr], sizeof(val));
|
1360 |
} |
1361 |
|
1362 |
switch (addr) {
|
1363 |
case SCBStatus:
|
1364 |
//~ val = eepro100_read_status(s);
|
1365 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
1366 |
break;
|
1367 |
case SCBPointer:
|
1368 |
//~ val = eepro100_read_pointer(s);
|
1369 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
1370 |
break;
|
1371 |
case SCBPort:
|
1372 |
val = eepro100_read_port(s); |
1373 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
1374 |
break;
|
1375 |
case SCBCtrlMDI:
|
1376 |
val = eepro100_read_mdi(s); |
1377 |
break;
|
1378 |
default:
|
1379 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1380 |
missing("unknown longword read");
|
1381 |
} |
1382 |
return val;
|
1383 |
} |
1384 |
|
1385 |
static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) |
1386 |
{ |
1387 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1388 |
memcpy(&s->mem[addr], &val, sizeof(val));
|
1389 |
} |
1390 |
|
1391 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1392 |
|
1393 |
switch (addr) {
|
1394 |
case SCBStatus:
|
1395 |
//~ eepro100_write_status(s, val);
|
1396 |
break;
|
1397 |
case SCBAck:
|
1398 |
eepro100_acknowledge(s); |
1399 |
break;
|
1400 |
case SCBCmd:
|
1401 |
eepro100_write_command(s, val); |
1402 |
break;
|
1403 |
case SCBIntmask:
|
1404 |
if (val & BIT(1)) { |
1405 |
eepro100_swi_interrupt(s); |
1406 |
} |
1407 |
eepro100_interrupt(s, 0);
|
1408 |
break;
|
1409 |
case SCBPort + 3: |
1410 |
case SCBFlow: /* does not exist on 82557 */ |
1411 |
case SCBFlow + 1: |
1412 |
case SCBFlow + 2: |
1413 |
case SCBFlow + 3: |
1414 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1415 |
break;
|
1416 |
case SCBeeprom:
|
1417 |
eepro100_write_eeprom(s->eeprom, val); |
1418 |
break;
|
1419 |
default:
|
1420 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1421 |
missing("unknown byte write");
|
1422 |
} |
1423 |
} |
1424 |
|
1425 |
static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) |
1426 |
{ |
1427 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1428 |
memcpy(&s->mem[addr], &val, sizeof(val));
|
1429 |
} |
1430 |
|
1431 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
1432 |
|
1433 |
switch (addr) {
|
1434 |
case SCBStatus:
|
1435 |
//~ eepro100_write_status(s, val);
|
1436 |
eepro100_acknowledge(s); |
1437 |
break;
|
1438 |
case SCBCmd:
|
1439 |
eepro100_write_command(s, val); |
1440 |
eepro100_write1(s, SCBIntmask, val >> 8);
|
1441 |
break;
|
1442 |
case SCBeeprom:
|
1443 |
eepro100_write_eeprom(s->eeprom, val); |
1444 |
break;
|
1445 |
default:
|
1446 |
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
1447 |
missing("unknown word write");
|
1448 |
} |
1449 |
} |
1450 |
|
1451 |
static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) |
1452 |
{ |
1453 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1454 |
memcpy(&s->mem[addr], &val, sizeof(val));
|
1455 |
} |
1456 |
|
1457 |
switch (addr) {
|
1458 |
case SCBPointer:
|
1459 |
eepro100_write_pointer(s, val); |
1460 |
break;
|
1461 |
case SCBPort:
|
1462 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
1463 |
eepro100_write_port(s, val); |
1464 |
break;
|
1465 |
case SCBCtrlMDI:
|
1466 |
eepro100_write_mdi(s, val); |
1467 |
break;
|
1468 |
default:
|
1469 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1470 |
missing("unknown longword write");
|
1471 |
} |
1472 |
} |
1473 |
|
1474 |
/*****************************************************************************
|
1475 |
*
|
1476 |
* Port mapped I/O.
|
1477 |
*
|
1478 |
****************************************************************************/
|
1479 |
|
1480 |
static uint32_t ioport_read1(void *opaque, uint32_t addr) |
1481 |
{ |
1482 |
EEPRO100State *s = opaque; |
1483 |
//~ logout("addr=%s\n", regname(addr));
|
1484 |
return eepro100_read1(s, addr - s->region[1]); |
1485 |
} |
1486 |
|
1487 |
static uint32_t ioport_read2(void *opaque, uint32_t addr) |
1488 |
{ |
1489 |
EEPRO100State *s = opaque; |
1490 |
return eepro100_read2(s, addr - s->region[1]); |
1491 |
} |
1492 |
|
1493 |
static uint32_t ioport_read4(void *opaque, uint32_t addr) |
1494 |
{ |
1495 |
EEPRO100State *s = opaque; |
1496 |
return eepro100_read4(s, addr - s->region[1]); |
1497 |
} |
1498 |
|
1499 |
static void ioport_write1(void *opaque, uint32_t addr, uint32_t val) |
1500 |
{ |
1501 |
EEPRO100State *s = opaque; |
1502 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1503 |
eepro100_write1(s, addr - s->region[1], val);
|
1504 |
} |
1505 |
|
1506 |
static void ioport_write2(void *opaque, uint32_t addr, uint32_t val) |
1507 |
{ |
1508 |
EEPRO100State *s = opaque; |
1509 |
eepro100_write2(s, addr - s->region[1], val);
|
1510 |
} |
1511 |
|
1512 |
static void ioport_write4(void *opaque, uint32_t addr, uint32_t val) |
1513 |
{ |
1514 |
EEPRO100State *s = opaque; |
1515 |
eepro100_write4(s, addr - s->region[1], val);
|
1516 |
} |
1517 |
|
1518 |
/***********************************************************/
|
1519 |
/* PCI EEPRO100 definitions */
|
1520 |
|
1521 |
static void pci_map(PCIDevice * pci_dev, int region_num, |
1522 |
pcibus_t addr, pcibus_t size, int type)
|
1523 |
{ |
1524 |
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
1525 |
|
1526 |
TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
1527 |
"size=0x%08"FMT_PCIBUS", type=%d\n", |
1528 |
region_num, addr, size, type)); |
1529 |
|
1530 |
assert(region_num == 1);
|
1531 |
register_ioport_write(addr, size, 1, ioport_write1, s);
|
1532 |
register_ioport_read(addr, size, 1, ioport_read1, s);
|
1533 |
register_ioport_write(addr, size, 2, ioport_write2, s);
|
1534 |
register_ioport_read(addr, size, 2, ioport_read2, s);
|
1535 |
register_ioport_write(addr, size, 4, ioport_write4, s);
|
1536 |
register_ioport_read(addr, size, 4, ioport_read4, s);
|
1537 |
|
1538 |
s->region[region_num] = addr; |
1539 |
} |
1540 |
|
1541 |
/*****************************************************************************
|
1542 |
*
|
1543 |
* Memory mapped I/O.
|
1544 |
*
|
1545 |
****************************************************************************/
|
1546 |
|
1547 |
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
1548 |
{ |
1549 |
EEPRO100State *s = opaque; |
1550 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1551 |
eepro100_write1(s, addr, val); |
1552 |
} |
1553 |
|
1554 |
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
1555 |
{ |
1556 |
EEPRO100State *s = opaque; |
1557 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1558 |
eepro100_write2(s, addr, val); |
1559 |
} |
1560 |
|
1561 |
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
1562 |
{ |
1563 |
EEPRO100State *s = opaque; |
1564 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1565 |
eepro100_write4(s, addr, val); |
1566 |
} |
1567 |
|
1568 |
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
1569 |
{ |
1570 |
EEPRO100State *s = opaque; |
1571 |
//~ logout("addr=%s\n", regname(addr));
|
1572 |
return eepro100_read1(s, addr);
|
1573 |
} |
1574 |
|
1575 |
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
1576 |
{ |
1577 |
EEPRO100State *s = opaque; |
1578 |
//~ logout("addr=%s\n", regname(addr));
|
1579 |
return eepro100_read2(s, addr);
|
1580 |
} |
1581 |
|
1582 |
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
1583 |
{ |
1584 |
EEPRO100State *s = opaque; |
1585 |
//~ logout("addr=%s\n", regname(addr));
|
1586 |
return eepro100_read4(s, addr);
|
1587 |
} |
1588 |
|
1589 |
static CPUWriteMemoryFunc * const pci_mmio_write[] = { |
1590 |
pci_mmio_writeb, |
1591 |
pci_mmio_writew, |
1592 |
pci_mmio_writel |
1593 |
}; |
1594 |
|
1595 |
static CPUReadMemoryFunc * const pci_mmio_read[] = { |
1596 |
pci_mmio_readb, |
1597 |
pci_mmio_readw, |
1598 |
pci_mmio_readl |
1599 |
}; |
1600 |
|
1601 |
static void pci_mmio_map(PCIDevice * pci_dev, int region_num, |
1602 |
pcibus_t addr, pcibus_t size, int type)
|
1603 |
{ |
1604 |
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
1605 |
|
1606 |
TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
1607 |
"size=0x%08"FMT_PCIBUS", type=%d\n", |
1608 |
region_num, addr, size, type)); |
1609 |
|
1610 |
if (region_num == 0) { |
1611 |
/* Map control / status registers. */
|
1612 |
cpu_register_physical_memory(addr, size, s->mmio_index); |
1613 |
s->region[region_num] = addr; |
1614 |
} |
1615 |
} |
1616 |
|
1617 |
static int nic_can_receive(VLANClientState *nc) |
1618 |
{ |
1619 |
EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
1620 |
TRACE(RXTX, logout("%p\n", s));
|
1621 |
return get_ru_state(s) == ru_ready;
|
1622 |
//~ return !eepro100_buffer_full(s);
|
1623 |
} |
1624 |
|
1625 |
static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size) |
1626 |
{ |
1627 |
/* TODO:
|
1628 |
* - Magic packets should set bit 30 in power management driver register.
|
1629 |
* - Interesting packets should set bit 29 in power management driver register.
|
1630 |
*/
|
1631 |
EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
1632 |
uint16_t rfd_status = 0xa000;
|
1633 |
static const uint8_t broadcast_macaddr[6] = |
1634 |
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
1635 |
|
1636 |
/* TODO: check multiple IA bit. */
|
1637 |
if (s->configuration[20] & BIT(6)) { |
1638 |
missing("Multiple IA bit");
|
1639 |
return -1; |
1640 |
} |
1641 |
|
1642 |
if (s->configuration[8] & 0x80) { |
1643 |
/* CSMA is disabled. */
|
1644 |
logout("%p received while CSMA is disabled\n", s);
|
1645 |
return -1; |
1646 |
} else if (size < 64 && (s->configuration[7] & 1)) { |
1647 |
/* Short frame and configuration byte 7/0 (discard short receive) set:
|
1648 |
* Short frame is discarded */
|
1649 |
logout("%p received short frame (%zu byte)\n", s, size);
|
1650 |
s->statistics.rx_short_frame_errors++; |
1651 |
//~ return -1;
|
1652 |
} else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) { |
1653 |
/* Long frame and configuration byte 18/3 (long receive ok) not set:
|
1654 |
* Long frames are discarded. */
|
1655 |
logout("%p received long frame (%zu byte), ignored\n", s, size);
|
1656 |
return -1; |
1657 |
} else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!! |
1658 |
/* Frame matches individual address. */
|
1659 |
/* TODO: check configuration byte 15/4 (ignore U/L). */
|
1660 |
TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
|
1661 |
} else if (memcmp(buf, broadcast_macaddr, 6) == 0) { |
1662 |
/* Broadcast frame. */
|
1663 |
TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
|
1664 |
rfd_status |= 0x0002;
|
1665 |
} else if (buf[0] & 0x01) { // !!! |
1666 |
/* Multicast frame. */
|
1667 |
TRACE(RXTX, logout("%p received multicast, len=%zu\n", s, size));
|
1668 |
/* TODO: check multicast all bit. */
|
1669 |
if (s->configuration[21] & BIT(3)) { |
1670 |
missing("Multicast All bit");
|
1671 |
} |
1672 |
int mcast_idx = compute_mcast_idx(buf);
|
1673 |
if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) { |
1674 |
return size;
|
1675 |
} |
1676 |
rfd_status |= 0x0002;
|
1677 |
} else if (s->configuration[15] & 1) { |
1678 |
/* Promiscuous: receive all. */
|
1679 |
TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
|
1680 |
rfd_status |= 0x0004;
|
1681 |
} else {
|
1682 |
TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
|
1683 |
nic_dump(buf, size))); |
1684 |
return size;
|
1685 |
} |
1686 |
|
1687 |
if (get_ru_state(s) != ru_ready) {
|
1688 |
/* No resources available. */
|
1689 |
logout("no resources, state=%u\n", get_ru_state(s));
|
1690 |
s->statistics.rx_resource_errors++; |
1691 |
//~ assert(!"no resources");
|
1692 |
return -1; |
1693 |
} |
1694 |
//~ !!!
|
1695 |
//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
|
1696 |
eepro100_rx_t rx; |
1697 |
cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, |
1698 |
offsetof(eepro100_rx_t, packet)); |
1699 |
uint16_t rfd_command = le16_to_cpu(rx.command); |
1700 |
uint16_t rfd_size = le16_to_cpu(rx.size); |
1701 |
|
1702 |
if (size > rfd_size) {
|
1703 |
logout("Receive buffer (%" PRId16 " bytes) too small for data " |
1704 |
"(%zu bytes); data truncated\n", rfd_size, size);
|
1705 |
size = rfd_size; |
1706 |
} |
1707 |
if (size < 64) { |
1708 |
rfd_status |= 0x0080;
|
1709 |
} |
1710 |
TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
|
1711 |
rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); |
1712 |
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), |
1713 |
rfd_status); |
1714 |
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); |
1715 |
/* Early receive interrupt not supported. */
|
1716 |
//~ eepro100_er_interrupt(s);
|
1717 |
/* Receive CRC Transfer not supported. */
|
1718 |
if (s->configuration[18] & 4) { |
1719 |
missing("Receive CRC Transfer");
|
1720 |
return -1; |
1721 |
} |
1722 |
/* TODO: check stripping enable bit. */
|
1723 |
//~ assert(!(s->configuration[17] & 1));
|
1724 |
cpu_physical_memory_write(s->ru_base + s->ru_offset + |
1725 |
offsetof(eepro100_rx_t, packet), buf, size); |
1726 |
s->statistics.rx_good_frames++; |
1727 |
eepro100_fr_interrupt(s); |
1728 |
s->ru_offset = le32_to_cpu(rx.link); |
1729 |
if (rfd_command & 0x8000) { |
1730 |
/* EL bit is set, so this was the last frame. */
|
1731 |
logout("receive: Running out of frames\n");
|
1732 |
set_ru_state(s, ru_suspended); |
1733 |
} |
1734 |
if (rfd_command & 0x4000) { |
1735 |
/* S bit is set. */
|
1736 |
set_ru_state(s, ru_suspended); |
1737 |
} |
1738 |
return size;
|
1739 |
} |
1740 |
|
1741 |
static const VMStateDescription vmstate_eepro100 = { |
1742 |
.version_id = 3,
|
1743 |
.minimum_version_id = 2,
|
1744 |
.minimum_version_id_old = 2,
|
1745 |
.fields = (VMStateField []) { |
1746 |
VMSTATE_PCI_DEVICE(dev, EEPRO100State), |
1747 |
VMSTATE_UNUSED(32),
|
1748 |
VMSTATE_BUFFER(mult, EEPRO100State), |
1749 |
VMSTATE_BUFFER(mem, EEPRO100State), |
1750 |
/* Save all members of struct between scb_stat and mem. */
|
1751 |
VMSTATE_UINT8(scb_stat, EEPRO100State), |
1752 |
VMSTATE_UINT8(int_stat, EEPRO100State), |
1753 |
VMSTATE_UNUSED(3*4), |
1754 |
VMSTATE_MACADDR(conf.macaddr, EEPRO100State), |
1755 |
VMSTATE_UNUSED(19*4), |
1756 |
VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
|
1757 |
/* The eeprom should be saved and restored by its own routines. */
|
1758 |
VMSTATE_UINT32(device, EEPRO100State), |
1759 |
/* TODO check device. */
|
1760 |
VMSTATE_UINT32(pointer, EEPRO100State), |
1761 |
VMSTATE_UINT32(cu_base, EEPRO100State), |
1762 |
VMSTATE_UINT32(cu_offset, EEPRO100State), |
1763 |
VMSTATE_UINT32(ru_base, EEPRO100State), |
1764 |
VMSTATE_UINT32(ru_offset, EEPRO100State), |
1765 |
VMSTATE_UINT32(statsaddr, EEPRO100State), |
1766 |
/* Save eepro100_stats_t statistics. */
|
1767 |
VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State), |
1768 |
VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State), |
1769 |
VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State), |
1770 |
VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State), |
1771 |
VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State), |
1772 |
VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State), |
1773 |
VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State), |
1774 |
VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State), |
1775 |
VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State), |
1776 |
VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State), |
1777 |
VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State), |
1778 |
VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State), |
1779 |
VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State), |
1780 |
VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State), |
1781 |
VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State), |
1782 |
VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State), |
1783 |
VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State), |
1784 |
VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State), |
1785 |
VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State), |
1786 |
VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State), |
1787 |
VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State), |
1788 |
#if 0
|
1789 |
VMSTATE_UINT16(status, EEPRO100State),
|
1790 |
#endif
|
1791 |
/* Configuration bytes. */
|
1792 |
VMSTATE_BUFFER(configuration, EEPRO100State), |
1793 |
VMSTATE_END_OF_LIST() |
1794 |
} |
1795 |
}; |
1796 |
|
1797 |
static void nic_cleanup(VLANClientState *nc) |
1798 |
{ |
1799 |
EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
1800 |
|
1801 |
s->nic = NULL;
|
1802 |
} |
1803 |
|
1804 |
static int pci_nic_uninit(PCIDevice *pci_dev) |
1805 |
{ |
1806 |
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
1807 |
|
1808 |
cpu_unregister_io_memory(s->mmio_index); |
1809 |
vmstate_unregister(s->vmstate, s); |
1810 |
eeprom93xx_free(s->eeprom); |
1811 |
qemu_del_vlan_client(&s->nic->nc); |
1812 |
return 0; |
1813 |
} |
1814 |
|
1815 |
static NetClientInfo net_eepro100_info = {
|
1816 |
.type = NET_CLIENT_TYPE_NIC, |
1817 |
.size = sizeof(NICState),
|
1818 |
.can_receive = nic_can_receive, |
1819 |
.receive = nic_receive, |
1820 |
.cleanup = nic_cleanup, |
1821 |
}; |
1822 |
|
1823 |
static int nic_init(PCIDevice *pci_dev, uint32_t device) |
1824 |
{ |
1825 |
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
1826 |
|
1827 |
TRACE(OTHER, logout("\n"));
|
1828 |
|
1829 |
s->device = device; |
1830 |
|
1831 |
pci_reset(s); |
1832 |
|
1833 |
/* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
|
1834 |
* i82559 and later support 64 or 256 word EEPROM. */
|
1835 |
s->eeprom = eeprom93xx_new(EEPROM_SIZE); |
1836 |
|
1837 |
/* Handler for memory-mapped I/O */
|
1838 |
s->mmio_index = |
1839 |
cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s); |
1840 |
|
1841 |
pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
|
1842 |
PCI_BASE_ADDRESS_SPACE_MEMORY | |
1843 |
PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map); |
1844 |
pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
|
1845 |
pci_map); |
1846 |
pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
|
1847 |
pci_mmio_map); |
1848 |
|
1849 |
qemu_macaddr_default_if_unset(&s->conf.macaddr); |
1850 |
logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)); |
1851 |
assert(s->region[1] == 0); |
1852 |
|
1853 |
nic_reset(s); |
1854 |
|
1855 |
s->nic = qemu_new_nic(&net_eepro100_info, &s->conf, |
1856 |
pci_dev->qdev.info->name, pci_dev->qdev.id, s); |
1857 |
|
1858 |
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
1859 |
TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
|
1860 |
|
1861 |
qemu_register_reset(nic_reset, s); |
1862 |
|
1863 |
s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
|
1864 |
memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
|
1865 |
s->vmstate->name = s->nic->nc.model; |
1866 |
vmstate_register(-1, s->vmstate, s);
|
1867 |
|
1868 |
if (!pci_dev->qdev.hotplugged) {
|
1869 |
static int loaded = 0; |
1870 |
if (!loaded) {
|
1871 |
char fname[32]; |
1872 |
snprintf(fname, sizeof(fname), "pxe-%s.bin", s->nic->nc.model); |
1873 |
rom_add_option(fname); |
1874 |
loaded = 1;
|
1875 |
} |
1876 |
} |
1877 |
return 0; |
1878 |
} |
1879 |
|
1880 |
static int pci_i82550_init(PCIDevice *pci_dev) |
1881 |
{ |
1882 |
return nic_init(pci_dev, i82550);
|
1883 |
} |
1884 |
|
1885 |
static int pci_i82551_init(PCIDevice *pci_dev) |
1886 |
{ |
1887 |
return nic_init(pci_dev, i82551);
|
1888 |
} |
1889 |
|
1890 |
static int pci_i82557a_init(PCIDevice *pci_dev) |
1891 |
{ |
1892 |
return nic_init(pci_dev, i82557A);
|
1893 |
} |
1894 |
|
1895 |
static int pci_i82557b_init(PCIDevice *pci_dev) |
1896 |
{ |
1897 |
return nic_init(pci_dev, i82557B);
|
1898 |
} |
1899 |
|
1900 |
static int pci_i82557c_init(PCIDevice *pci_dev) |
1901 |
{ |
1902 |
return nic_init(pci_dev, i82557C);
|
1903 |
} |
1904 |
|
1905 |
static int pci_i82558a_init(PCIDevice *pci_dev) |
1906 |
{ |
1907 |
return nic_init(pci_dev, i82558A);
|
1908 |
} |
1909 |
|
1910 |
static int pci_i82558b_init(PCIDevice *pci_dev) |
1911 |
{ |
1912 |
return nic_init(pci_dev, i82558B);
|
1913 |
} |
1914 |
|
1915 |
static int pci_i82559a_init(PCIDevice *pci_dev) |
1916 |
{ |
1917 |
return nic_init(pci_dev, i82559A);
|
1918 |
} |
1919 |
|
1920 |
static int pci_i82559b_init(PCIDevice *pci_dev) |
1921 |
{ |
1922 |
return nic_init(pci_dev, i82559B);
|
1923 |
} |
1924 |
|
1925 |
static int pci_i82559c_init(PCIDevice *pci_dev) |
1926 |
{ |
1927 |
return nic_init(pci_dev, i82559C);
|
1928 |
} |
1929 |
|
1930 |
static int pci_i82559er_init(PCIDevice *pci_dev) |
1931 |
{ |
1932 |
return nic_init(pci_dev, i82559ER);
|
1933 |
} |
1934 |
|
1935 |
static int pci_i82562_init(PCIDevice *pci_dev) |
1936 |
{ |
1937 |
return nic_init(pci_dev, i82562);
|
1938 |
} |
1939 |
|
1940 |
static PCIDeviceInfo eepro100_info[] = {
|
1941 |
{ |
1942 |
.qdev.name = "i82550",
|
1943 |
.qdev.size = sizeof(EEPRO100State),
|
1944 |
.init = pci_i82550_init, |
1945 |
.exit = pci_nic_uninit, |
1946 |
.qdev.props = (Property[]) { |
1947 |
DEFINE_NIC_PROPERTIES(EEPRO100State, conf), |
1948 |
DEFINE_PROP_END_OF_LIST(), |
1949 |
}, |
1950 |
},{ |
1951 |
.qdev.name = "i82551",
|
1952 |
.qdev.size = sizeof(EEPRO100State),
|
1953 |
.init = pci_i82551_init, |
1954 |
.exit = pci_nic_uninit, |
1955 |
.qdev.props = (Property[]) { |
1956 |
DEFINE_NIC_PROPERTIES(EEPRO100State, conf), |
1957 |
DEFINE_PROP_END_OF_LIST(), |
1958 |
}, |
1959 |
},{ |
1960 |
.qdev.name = "i82557a",
|
1961 |
.qdev.size = sizeof(EEPRO100State),
|
1962 |
.init = pci_i82557a_init, |
1963 |
.exit = pci_nic_uninit, |
1964 |
.qdev.props = (Property[]) { |
1965 |
DEFINE_NIC_PROPERTIES(EEPRO100State, conf), |
1966 |
DEFINE_PROP_END_OF_LIST(), |
1967 |
}, |
1968 |
},{ |
1969 |
.qdev.name = "i82557b",
|
1970 |
.qdev.size = sizeof(EEPRO100State),
|
1971 |
.init = pci_i82557b_init, |
1972 |
.exit = pci_nic_uninit, |
1973 |
.qdev.props = (Property[]) { |
1974 |
DEFINE_NIC_PROPERTIES(EEPRO100State, conf), |
1975 |
DEFINE_PROP_END_OF_LIST(), |
1976 |
}, |
1977 |
},{ |
1978 |
.qdev.name = "i82557c",
|
1979 |
.qdev.size = sizeof(EEPRO100State),
|
1980 |
.init = pci_i82557c_init, |
1981 |
.exit = pci_nic_uninit, |
1982 |
.qdev.props = (Property[]) { |
1983 |
DEFINE_NIC_PROPERTIES(EEPRO100State, conf), |
1984 |
DEFINE_PROP_END_OF_LIST(), |
1985 |
}, |
1986 |
},{ |
1987 |
.qdev.name = "i82558a",
|
1988 |
.qdev.size = sizeof(EEPRO100State),
|
1989 |
.init = pci_i82558a_init, |
1990 |
.exit = pci_nic_uninit, |
1991 |
.qdev.props = (Property[]) { |
1992 |
DEFINE_NIC_PROPERTIES(EEPRO100State, conf), |
1993 |
DEFINE_PROP_END_OF_LIST(), |
1994 |
}, |
1995 |
},{ |
1996 |
.qdev.name = "i82558b",
|
1997 |
.qdev.size = sizeof(EEPRO100State),
|
1998 |
.init = pci_i82558b_init, |
1999 |
.exit = pci_nic_uninit, |
2000 |
.qdev.props = (Property[]) { |
2001 |
DEFINE_NIC_PROPERTIES(EEPRO100State, conf), |
2002 |
DEFINE_PROP_END_OF_LIST(), |
2003 |
}, |
2004 |
},{ |
2005 |
.qdev.name = "i82559a",
|
2006 |
.qdev.size = sizeof(EEPRO100State),
|
2007 |
.init = pci_i82559a_init, |
2008 |
.exit = pci_nic_uninit, |
2009 |
.qdev.props = (Property[]) { |
2010 |
DEFINE_NIC_PROPERTIES(EEPRO100State, conf), |
2011 |
DEFINE_PROP_END_OF_LIST(), |
2012 |
}, |
2013 |
},{ |
2014 |
.qdev.name = "i82559b",
|
2015 |
.qdev.size = sizeof(EEPRO100State),
|
2016 |
.init = pci_i82559b_init, |
2017 |
.exit = pci_nic_uninit, |
2018 |
.qdev.props = (Property[]) { |
2019 |
DEFINE_NIC_PROPERTIES(EEPRO100State, conf), |
2020 |
DEFINE_PROP_END_OF_LIST(), |
2021 |
}, |
2022 |
},{ |
2023 |
.qdev.name = "i82559c",
|
2024 |
.qdev.size = sizeof(EEPRO100State),
|
2025 |
.init = pci_i82559c_init, |
2026 |
.exit = pci_nic_uninit, |
2027 |
.qdev.props = (Property[]) { |
2028 |
DEFINE_NIC_PROPERTIES(EEPRO100State, conf), |
2029 |
DEFINE_PROP_END_OF_LIST(), |
2030 |
}, |
2031 |
},{ |
2032 |
.qdev.name = "i82559er",
|
2033 |
.qdev.size = sizeof(EEPRO100State),
|
2034 |
.init = pci_i82559er_init, |
2035 |
.exit = pci_nic_uninit, |
2036 |
.qdev.props = (Property[]) { |
2037 |
DEFINE_NIC_PROPERTIES(EEPRO100State, conf), |
2038 |
DEFINE_PROP_END_OF_LIST(), |
2039 |
}, |
2040 |
},{ |
2041 |
.qdev.name = "i82562",
|
2042 |
.qdev.size = sizeof(EEPRO100State),
|
2043 |
.init = pci_i82562_init, |
2044 |
.exit = pci_nic_uninit, |
2045 |
.qdev.props = (Property[]) { |
2046 |
DEFINE_NIC_PROPERTIES(EEPRO100State, conf), |
2047 |
DEFINE_PROP_END_OF_LIST(), |
2048 |
}, |
2049 |
},{ |
2050 |
/* end of list */
|
2051 |
} |
2052 |
}; |
2053 |
|
2054 |
static void eepro100_register_devices(void) |
2055 |
{ |
2056 |
pci_qdev_register_many(eepro100_info); |
2057 |
} |
2058 |
|
2059 |
device_init(eepro100_register_devices) |