Revision 40c4ed3f
| b/hw/ide/core.c | ||
|---|---|---|
| 56 | 56 |
}; |
| 57 | 57 |
|
| 58 | 58 |
static int ide_handle_rw_error(IDEState *s, int error, int op); |
| 59 |
static void ide_dummy_transfer_stop(IDEState *s); |
|
| 59 | 60 |
|
| 60 | 61 |
static void padstr(char *str, const char *src, int len) |
| 61 | 62 |
{
|
| ... | ... | |
| 1532 | 1533 |
bus->cmd = val; |
| 1533 | 1534 |
} |
| 1534 | 1535 |
|
| 1536 |
/* |
|
| 1537 |
* Returns true if the running PIO transfer is a PIO out (i.e. data is |
|
| 1538 |
* transferred from the device to the guest), false if it's a PIO in |
|
| 1539 |
*/ |
|
| 1540 |
static bool ide_is_pio_out(IDEState *s) |
|
| 1541 |
{
|
|
| 1542 |
if (s->end_transfer_func == ide_sector_write || |
|
| 1543 |
s->end_transfer_func == ide_atapi_cmd) {
|
|
| 1544 |
return false; |
|
| 1545 |
} else if (s->end_transfer_func == ide_sector_read || |
|
| 1546 |
s->end_transfer_func == ide_transfer_stop || |
|
| 1547 |
s->end_transfer_func == ide_atapi_cmd_reply_end || |
|
| 1548 |
s->end_transfer_func == ide_dummy_transfer_stop) {
|
|
| 1549 |
return true; |
|
| 1550 |
} |
|
| 1551 |
|
|
| 1552 |
abort(); |
|
| 1553 |
} |
|
| 1554 |
|
|
| 1535 | 1555 |
void ide_data_writew(void *opaque, uint32_t addr, uint32_t val) |
| 1536 | 1556 |
{
|
| 1537 | 1557 |
IDEBus *bus = opaque; |
| 1538 | 1558 |
IDEState *s = idebus_active_if(bus); |
| 1539 | 1559 |
uint8_t *p; |
| 1540 | 1560 |
|
| 1541 |
/* PIO data access allowed only when DRQ bit is set */ |
|
| 1542 |
if (!(s->status & DRQ_STAT)) |
|
| 1561 |
/* PIO data access allowed only when DRQ bit is set. The result of a write |
|
| 1562 |
* during PIO out is indeterminate, just ignore it. */ |
|
| 1563 |
if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
|
|
| 1543 | 1564 |
return; |
| 1565 |
} |
|
| 1544 | 1566 |
|
| 1545 | 1567 |
p = s->data_ptr; |
| 1546 | 1568 |
*(uint16_t *)p = le16_to_cpu(val); |
| ... | ... | |
| 1557 | 1579 |
uint8_t *p; |
| 1558 | 1580 |
int ret; |
| 1559 | 1581 |
|
| 1560 |
/* PIO data access allowed only when DRQ bit is set */ |
|
| 1561 |
if (!(s->status & DRQ_STAT)) |
|
| 1582 |
/* PIO data access allowed only when DRQ bit is set. The result of a read |
|
| 1583 |
* during PIO in is indeterminate, return 0 and don't move forward. */ |
|
| 1584 |
if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
|
|
| 1562 | 1585 |
return 0; |
| 1586 |
} |
|
| 1563 | 1587 |
|
| 1564 | 1588 |
p = s->data_ptr; |
| 1565 | 1589 |
ret = cpu_to_le16(*(uint16_t *)p); |
| ... | ... | |
| 1576 | 1600 |
IDEState *s = idebus_active_if(bus); |
| 1577 | 1601 |
uint8_t *p; |
| 1578 | 1602 |
|
| 1579 |
/* PIO data access allowed only when DRQ bit is set */ |
|
| 1580 |
if (!(s->status & DRQ_STAT)) |
|
| 1603 |
/* PIO data access allowed only when DRQ bit is set. The result of a write |
|
| 1604 |
* during PIO out is indeterminate, just ignore it. */ |
|
| 1605 |
if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
|
|
| 1581 | 1606 |
return; |
| 1607 |
} |
|
| 1582 | 1608 |
|
| 1583 | 1609 |
p = s->data_ptr; |
| 1584 | 1610 |
*(uint32_t *)p = le32_to_cpu(val); |
| ... | ... | |
| 1595 | 1621 |
uint8_t *p; |
| 1596 | 1622 |
int ret; |
| 1597 | 1623 |
|
| 1598 |
/* PIO data access allowed only when DRQ bit is set */ |
|
| 1599 |
if (!(s->status & DRQ_STAT)) |
|
| 1624 |
/* PIO data access allowed only when DRQ bit is set. The result of a read |
|
| 1625 |
* during PIO in is indeterminate, return 0 and don't move forward. */ |
|
| 1626 |
if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
|
|
| 1600 | 1627 |
return 0; |
| 1628 |
} |
|
| 1601 | 1629 |
|
| 1602 | 1630 |
p = s->data_ptr; |
| 1603 | 1631 |
ret = cpu_to_le32(*(uint32_t *)p); |
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