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/*
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* sparc helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <signal.h> |
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#include <assert.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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//#define DEBUG_MMU
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/* Sparc MMU emulation */
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|
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/* thread support */
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spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
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void cpu_lock(void) |
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{ |
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spin_lock(&global_cpu_lock); |
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} |
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|
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void cpu_unlock(void) |
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{ |
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spin_unlock(&global_cpu_lock); |
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} |
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#if defined(CONFIG_USER_ONLY)
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int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
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int is_user, int is_softmmu) |
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{ |
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if (rw & 2) |
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env->exception_index = TT_TFAULT; |
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else
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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|
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#else
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#ifndef TARGET_SPARC64
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/*
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* Sparc V8 Reference MMU (SRMMU)
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*/
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static const int access_table[8][8] = { |
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{ 0, 0, 0, 0, 2, 0, 3, 3 }, |
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{ 0, 0, 0, 0, 2, 0, 0, 0 }, |
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{ 2, 2, 0, 0, 0, 2, 3, 3 }, |
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{ 2, 2, 0, 0, 0, 2, 0, 0 }, |
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{ 2, 0, 2, 0, 2, 2, 3, 3 }, |
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{ 2, 0, 2, 0, 2, 0, 2, 0 }, |
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{ 2, 2, 2, 0, 2, 2, 3, 3 }, |
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{ 2, 2, 2, 0, 2, 2, 2, 0 } |
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}; |
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static const int perm_table[2][8] = { |
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{ |
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PAGE_READ, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
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PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC |
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}, |
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{ |
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PAGE_READ, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
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PAGE_EXEC, |
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PAGE_READ, |
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0,
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0,
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} |
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}; |
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int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot, |
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int *access_index, target_ulong address, int rw, |
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int is_user)
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{ |
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int access_perms = 0; |
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target_phys_addr_t pde_ptr; |
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uint32_t pde; |
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target_ulong virt_addr; |
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int error_code = 0, is_dirty; |
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unsigned long page_offset; |
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virt_addr = address & TARGET_PAGE_MASK; |
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if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
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// Boot mode: instruction fetches are taken from PROM
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if (rw == 2 && (env->mmuregs[0] & MMU_BM)) { |
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*physical = 0xff0000000ULL | (address & 0x3ffffULL); |
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*prot = PAGE_READ | PAGE_EXEC; |
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return 0; |
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} |
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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return 0; |
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} |
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|
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
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*physical = 0xffffffffffff0000ULL;
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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/* Context base + context number */
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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/* Ctx pde */
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return 1 << 2; |
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case 2: /* L0 PTE, maybe should not happen? */ |
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case 3: /* Reserved */ |
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return 4 << 2; |
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case 1: /* L0 PDE */ |
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (1 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (1 << 8) | (4 << 2); |
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case 1: /* L1 PDE */ |
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (2 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (2 << 8) | (4 << 2); |
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case 1: /* L2 PDE */ |
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (3 << 8) | (1 << 2); |
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case 1: /* PDE, should not happen */ |
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case 3: /* Reserved */ |
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return (3 << 8) | (4 << 2); |
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case 2: /* L3 PTE */ |
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virt_addr = address & TARGET_PAGE_MASK; |
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page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
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} |
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break;
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case 2: /* L2 PTE */ |
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virt_addr = address & ~0x3ffff;
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page_offset = address & 0x3ffff;
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} |
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break;
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case 2: /* L1 PTE */ |
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virt_addr = address & ~0xffffff;
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page_offset = address & 0xffffff;
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} |
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} |
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/* update page modified and dirty bits */
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is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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pde |= PG_ACCESSED_MASK; |
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if (is_dirty)
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pde |= PG_MODIFIED_MASK; |
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stl_phys_notdirty(pde_ptr, pde); |
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} |
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/* check access */
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access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
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error_code = access_table[*access_index][access_perms]; |
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if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) |
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return error_code;
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/* the page can be put in the TLB */
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*prot = perm_table[is_user][access_perms]; |
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if (!(pde & PG_MODIFIED_MASK)) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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*prot &= ~PAGE_WRITE; |
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} |
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/* Even if large ptes, we map only one 4KB page in the cache to
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avoid filling it too fast */
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*physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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return error_code;
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} |
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/* Perform address translation */
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int is_user, int is_softmmu) |
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{ |
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target_phys_addr_t paddr; |
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target_ulong vaddr; |
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int error_code = 0, prot, ret = 0, access_index; |
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error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user); |
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if (error_code == 0) { |
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vaddr = address & TARGET_PAGE_MASK; |
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paddr &= TARGET_PAGE_MASK; |
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#ifdef DEBUG_MMU
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printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " |
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TARGET_FMT_lx "\n", address, paddr, vaddr);
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#endif
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ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu); |
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return ret;
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} |
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if (env->mmuregs[3]) /* Fault status register */ |
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env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
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env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
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env->mmuregs[4] = address; /* Fault address register */ |
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if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
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// No fault mode: if a mapping is available, just override
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// permissions. If no mapping is available, redirect accesses to
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// neverland. Fake/overridden mappings will be flushed when
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// switching to normal mode.
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vaddr = address & TARGET_PAGE_MASK; |
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu); |
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return ret;
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} else {
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if (rw & 2) |
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env->exception_index = TT_TFAULT; |
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else
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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} |
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target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
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{ |
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target_phys_addr_t pde_ptr; |
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uint32_t pde; |
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/* Context base + context number */
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pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + |
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(env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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case 2: /* PTE, maybe should not happen? */ |
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case 3: /* Reserved */ |
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return 0; |
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case 1: /* L1 PDE */ |
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if (mmulev == 3) |
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return pde;
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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case 3: /* Reserved */ |
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return 0; |
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case 2: /* L1 PTE */ |
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return pde;
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case 1: /* L2 PDE */ |
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if (mmulev == 2) |
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return pde;
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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case 3: /* Reserved */ |
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return 0; |
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case 2: /* L2 PTE */ |
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return pde;
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case 1: /* L3 PDE */ |
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if (mmulev == 1) |
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return pde;
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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case 1: /* PDE, should not happen */ |
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case 3: /* Reserved */ |
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return 0; |
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case 2: /* L3 PTE */ |
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return pde;
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} |
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} |
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} |
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} |
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return 0; |
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} |
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|
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#ifdef DEBUG_MMU
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void dump_mmu(CPUState *env)
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{ |
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target_ulong va, va1, va2; |
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unsigned int n, m, o; |
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target_phys_addr_t pde_ptr, pa; |
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uint32_t pde; |
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printf("MMU dump:\n");
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", |
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(target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); |
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for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
337 |
pde = mmu_probe(env, va, 2);
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if (pde) {
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pa = cpu_get_phys_page_debug(env, va); |
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printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
341 |
" PDE: " TARGET_FMT_lx "\n", va, pa, pde); |
342 |
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
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pde = mmu_probe(env, va1, 1);
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if (pde) {
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pa = cpu_get_phys_page_debug(env, va1); |
346 |
printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
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" PDE: " TARGET_FMT_lx "\n", va1, pa, pde); |
348 |
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
349 |
pde = mmu_probe(env, va2, 0);
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350 |
if (pde) {
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pa = cpu_get_phys_page_debug(env, va2); |
352 |
printf(" VA: " TARGET_FMT_lx ", PA: " |
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TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n", |
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va2, pa, pde); |
355 |
} |
356 |
} |
357 |
} |
358 |
} |
359 |
} |
360 |
} |
361 |
printf("MMU dump ends\n");
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} |
363 |
#endif /* DEBUG_MMU */ |
364 |
|
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#else /* !TARGET_SPARC64 */ |
366 |
/*
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* UltraSparc IIi I/DMMUs
|
368 |
*/
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369 |
static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot, |
370 |
int *access_index, target_ulong address, int rw, |
371 |
int is_user)
|
372 |
{ |
373 |
target_ulong mask; |
374 |
unsigned int i; |
375 |
|
376 |
if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ |
377 |
*physical = address; |
378 |
*prot = PAGE_READ | PAGE_WRITE; |
379 |
return 0; |
380 |
} |
381 |
|
382 |
for (i = 0; i < 64; i++) { |
383 |
switch ((env->dtlb_tte[i] >> 61) & 3) { |
384 |
default:
|
385 |
case 0x0: // 8k |
386 |
mask = 0xffffffffffffe000ULL;
|
387 |
break;
|
388 |
case 0x1: // 64k |
389 |
mask = 0xffffffffffff0000ULL;
|
390 |
break;
|
391 |
case 0x2: // 512k |
392 |
mask = 0xfffffffffff80000ULL;
|
393 |
break;
|
394 |
case 0x3: // 4M |
395 |
mask = 0xffffffffffc00000ULL;
|
396 |
break;
|
397 |
} |
398 |
// ctx match, vaddr match?
|
399 |
if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && |
400 |
(address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
|
401 |
// valid, access ok?
|
402 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 || |
403 |
((env->dtlb_tte[i] & 0x4) && is_user) ||
|
404 |
(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) { |
405 |
if (env->dmmuregs[3]) /* Fault status register */ |
406 |
env->dmmuregs[3] = 2; /* overflow (not read before another fault) */ |
407 |
env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1; |
408 |
env->dmmuregs[4] = address; /* Fault address register */ |
409 |
env->exception_index = TT_DFAULT; |
410 |
#ifdef DEBUG_MMU
|
411 |
printf("DFAULT at 0x%" PRIx64 "\n", address); |
412 |
#endif
|
413 |
return 1; |
414 |
} |
415 |
*physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); |
416 |
*prot = PAGE_READ; |
417 |
if (env->dtlb_tte[i] & 0x2) |
418 |
*prot |= PAGE_WRITE; |
419 |
return 0; |
420 |
} |
421 |
} |
422 |
#ifdef DEBUG_MMU
|
423 |
printf("DMISS at 0x%" PRIx64 "\n", address); |
424 |
#endif
|
425 |
env->exception_index = TT_DMISS; |
426 |
return 1; |
427 |
} |
428 |
|
429 |
static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot, |
430 |
int *access_index, target_ulong address, int rw, |
431 |
int is_user)
|
432 |
{ |
433 |
target_ulong mask; |
434 |
unsigned int i; |
435 |
|
436 |
if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */ |
437 |
*physical = address; |
438 |
*prot = PAGE_EXEC; |
439 |
return 0; |
440 |
} |
441 |
|
442 |
for (i = 0; i < 64; i++) { |
443 |
switch ((env->itlb_tte[i] >> 61) & 3) { |
444 |
default:
|
445 |
case 0x0: // 8k |
446 |
mask = 0xffffffffffffe000ULL;
|
447 |
break;
|
448 |
case 0x1: // 64k |
449 |
mask = 0xffffffffffff0000ULL;
|
450 |
break;
|
451 |
case 0x2: // 512k |
452 |
mask = 0xfffffffffff80000ULL;
|
453 |
break;
|
454 |
case 0x3: // 4M |
455 |
mask = 0xffffffffffc00000ULL;
|
456 |
break;
|
457 |
} |
458 |
// ctx match, vaddr match?
|
459 |
if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) && |
460 |
(address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
|
461 |
// valid, access ok?
|
462 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 || |
463 |
((env->itlb_tte[i] & 0x4) && is_user)) {
|
464 |
if (env->immuregs[3]) /* Fault status register */ |
465 |
env->immuregs[3] = 2; /* overflow (not read before another fault) */ |
466 |
env->immuregs[3] |= (is_user << 3) | 1; |
467 |
env->exception_index = TT_TFAULT; |
468 |
#ifdef DEBUG_MMU
|
469 |
printf("TFAULT at 0x%" PRIx64 "\n", address); |
470 |
#endif
|
471 |
return 1; |
472 |
} |
473 |
*physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); |
474 |
*prot = PAGE_EXEC; |
475 |
return 0; |
476 |
} |
477 |
} |
478 |
#ifdef DEBUG_MMU
|
479 |
printf("TMISS at 0x%" PRIx64 "\n", address); |
480 |
#endif
|
481 |
env->exception_index = TT_TMISS; |
482 |
return 1; |
483 |
} |
484 |
|
485 |
int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot, |
486 |
int *access_index, target_ulong address, int rw, |
487 |
int is_user)
|
488 |
{ |
489 |
if (rw == 2) |
490 |
return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
|
491 |
else
|
492 |
return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
|
493 |
} |
494 |
|
495 |
/* Perform address translation */
|
496 |
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
497 |
int is_user, int is_softmmu) |
498 |
{ |
499 |
target_ulong virt_addr, vaddr; |
500 |
target_phys_addr_t paddr; |
501 |
int error_code = 0, prot, ret = 0, access_index; |
502 |
|
503 |
error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user); |
504 |
if (error_code == 0) { |
505 |
virt_addr = address & TARGET_PAGE_MASK; |
506 |
vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
|
507 |
#ifdef DEBUG_MMU
|
508 |
printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr); |
509 |
#endif
|
510 |
ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu); |
511 |
return ret;
|
512 |
} |
513 |
// XXX
|
514 |
return 1; |
515 |
} |
516 |
|
517 |
#ifdef DEBUG_MMU
|
518 |
void dump_mmu(CPUState *env)
|
519 |
{ |
520 |
unsigned int i; |
521 |
const char *mask; |
522 |
|
523 |
printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]); |
524 |
if ((env->lsu & DMMU_E) == 0) { |
525 |
printf("DMMU disabled\n");
|
526 |
} else {
|
527 |
printf("DMMU dump:\n");
|
528 |
for (i = 0; i < 64; i++) { |
529 |
switch ((env->dtlb_tte[i] >> 61) & 3) { |
530 |
default:
|
531 |
case 0x0: |
532 |
mask = " 8k";
|
533 |
break;
|
534 |
case 0x1: |
535 |
mask = " 64k";
|
536 |
break;
|
537 |
case 0x2: |
538 |
mask = "512k";
|
539 |
break;
|
540 |
case 0x3: |
541 |
mask = " 4M";
|
542 |
break;
|
543 |
} |
544 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) { |
545 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n", |
546 |
env->dtlb_tag[i] & ~0x1fffULL,
|
547 |
env->dtlb_tte[i] & 0x1ffffffe000ULL,
|
548 |
mask, |
549 |
env->dtlb_tte[i] & 0x4? "priv": "user", |
550 |
env->dtlb_tte[i] & 0x2? "RW": "RO", |
551 |
env->dtlb_tte[i] & 0x40? "locked": "unlocked", |
552 |
env->dtlb_tag[i] & 0x1fffULL);
|
553 |
} |
554 |
} |
555 |
} |
556 |
if ((env->lsu & IMMU_E) == 0) { |
557 |
printf("IMMU disabled\n");
|
558 |
} else {
|
559 |
printf("IMMU dump:\n");
|
560 |
for (i = 0; i < 64; i++) { |
561 |
switch ((env->itlb_tte[i] >> 61) & 3) { |
562 |
default:
|
563 |
case 0x0: |
564 |
mask = " 8k";
|
565 |
break;
|
566 |
case 0x1: |
567 |
mask = " 64k";
|
568 |
break;
|
569 |
case 0x2: |
570 |
mask = "512k";
|
571 |
break;
|
572 |
case 0x3: |
573 |
mask = " 4M";
|
574 |
break;
|
575 |
} |
576 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) { |
577 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n", |
578 |
env->itlb_tag[i] & ~0x1fffULL,
|
579 |
env->itlb_tte[i] & 0x1ffffffe000ULL,
|
580 |
mask, |
581 |
env->itlb_tte[i] & 0x4? "priv": "user", |
582 |
env->itlb_tte[i] & 0x40? "locked": "unlocked", |
583 |
env->itlb_tag[i] & 0x1fffULL);
|
584 |
} |
585 |
} |
586 |
} |
587 |
} |
588 |
#endif /* DEBUG_MMU */ |
589 |
|
590 |
#endif /* TARGET_SPARC64 */ |
591 |
#endif /* !CONFIG_USER_ONLY */ |
592 |
|
593 |
void memcpy32(target_ulong *dst, const target_ulong *src) |
594 |
{ |
595 |
dst[0] = src[0]; |
596 |
dst[1] = src[1]; |
597 |
dst[2] = src[2]; |
598 |
dst[3] = src[3]; |
599 |
dst[4] = src[4]; |
600 |
dst[5] = src[5]; |
601 |
dst[6] = src[6]; |
602 |
dst[7] = src[7]; |
603 |
} |