1339 |
1339 |
gen_##name(ctx, 1, 1); \
|
1340 |
1340 |
}
|
1341 |
1341 |
|
|
1342 |
static inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
|
|
1343 |
{
|
|
1344 |
if (mask >> 32)
|
|
1345 |
gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
|
|
1346 |
else
|
|
1347 |
gen_op_andi_T0(mask);
|
|
1348 |
}
|
|
1349 |
|
|
1350 |
static inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
|
|
1351 |
{
|
|
1352 |
if (mask >> 32)
|
|
1353 |
gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
|
|
1354 |
else
|
|
1355 |
gen_op_andi_T1(mask);
|
|
1356 |
}
|
|
1357 |
|
1342 |
1358 |
static inline void gen_rldinm (DisasContext *ctx, uint32_t mb, uint32_t me,
|
1343 |
1359 |
uint32_t sh)
|
1344 |
1360 |
{
|
... | ... | |
1348 |
1364 |
}
|
1349 |
1365 |
if (likely(mb == 0)) {
|
1350 |
1366 |
if (likely(me == 63)) {
|
1351 |
|
gen_op_rotli32_T0(sh);
|
|
1367 |
gen_op_rotli64_T0(sh);
|
1352 |
1368 |
goto do_store;
|
1353 |
1369 |
} else if (likely(me == (63 - sh))) {
|
1354 |
1370 |
gen_op_sli_T0(sh);
|
... | ... | |
1356 |
1372 |
}
|
1357 |
1373 |
} else if (likely(me == 63)) {
|
1358 |
1374 |
if (likely(sh == (64 - mb))) {
|
1359 |
|
gen_op_srli_T0(mb);
|
|
1375 |
gen_op_srli_T0_64(mb);
|
1360 |
1376 |
goto do_store;
|
1361 |
1377 |
}
|
1362 |
1378 |
}
|
1363 |
1379 |
gen_op_rotli64_T0(sh);
|
1364 |
1380 |
do_mask:
|
1365 |
|
gen_op_andi_T0(MASK(mb, me));
|
|
1381 |
gen_andi_T0_64(ctx, MASK(mb, me));
|
1366 |
1382 |
do_store:
|
1367 |
1383 |
gen_op_store_T0_gpr(rA(ctx->opcode));
|
1368 |
1384 |
if (unlikely(Rc(ctx->opcode) != 0))
|
... | ... | |
1405 |
1421 |
gen_op_load_gpr_T1(rB(ctx->opcode));
|
1406 |
1422 |
gen_op_rotl64_T0_T1();
|
1407 |
1423 |
if (unlikely(mb != 0 || me != 63)) {
|
1408 |
|
gen_op_andi_T0(MASK(mb, me));
|
|
1424 |
gen_andi_T0_64(ctx, MASK(mb, me));
|
1409 |
1425 |
}
|
1410 |
1426 |
gen_op_store_T0_gpr(rA(ctx->opcode));
|
1411 |
1427 |
if (unlikely(Rc(ctx->opcode) != 0))
|
... | ... | |
1452 |
1468 |
}
|
1453 |
1469 |
gen_op_load_gpr_T0(rS(ctx->opcode));
|
1454 |
1470 |
gen_op_load_gpr_T1(rA(ctx->opcode));
|
1455 |
|
gen_op_rotli64_T0(SH(ctx->opcode));
|
|
1471 |
gen_op_rotli64_T0(sh);
|
1456 |
1472 |
do_mask:
|
1457 |
1473 |
mask = MASK(mb, 63 - sh);
|
1458 |
|
gen_op_andi_T0(mask);
|
1459 |
|
gen_op_andi_T1(~mask);
|
|
1474 |
gen_andi_T0_64(ctx, mask);
|
|
1475 |
gen_andi_T1_64(ctx, ~mask);
|
1460 |
1476 |
gen_op_or();
|
1461 |
1477 |
do_store:
|
1462 |
1478 |
gen_op_store_T0_gpr(rA(ctx->opcode));
|