root / hw / mcf_fec.c @ 4118a970
History | View | Annotate | Download (11.6 kB)
1 | 5fafdf24 | ths | /*
|
---|---|---|---|
2 | 7e049b8a | pbrook | * ColdFire Fast Ethernet Controller emulation.
|
3 | 7e049b8a | pbrook | *
|
4 | 7e049b8a | pbrook | * Copyright (c) 2007 CodeSourcery.
|
5 | 7e049b8a | pbrook | *
|
6 | 7e049b8a | pbrook | * This code is licenced under the GPL
|
7 | 7e049b8a | pbrook | */
|
8 | 7e049b8a | pbrook | #include "vl.h" |
9 | 7e049b8a | pbrook | /* For crc32 */
|
10 | 7e049b8a | pbrook | #include <zlib.h> |
11 | 7e049b8a | pbrook | |
12 | 7e049b8a | pbrook | //#define DEBUG_FEC 1
|
13 | 7e049b8a | pbrook | |
14 | 7e049b8a | pbrook | #ifdef DEBUG_FEC
|
15 | 7e049b8a | pbrook | #define DPRINTF(fmt, args...) \
|
16 | 7e049b8a | pbrook | do { printf("mcf_fec: " fmt , ##args); } while (0) |
17 | 7e049b8a | pbrook | #else
|
18 | 7e049b8a | pbrook | #define DPRINTF(fmt, args...) do {} while(0) |
19 | 7e049b8a | pbrook | #endif
|
20 | 7e049b8a | pbrook | |
21 | 7e049b8a | pbrook | #define FEC_MAX_FRAME_SIZE 2032 |
22 | 7e049b8a | pbrook | |
23 | 7e049b8a | pbrook | typedef struct { |
24 | 7e049b8a | pbrook | qemu_irq *irq; |
25 | 7e049b8a | pbrook | VLANClientState *vc; |
26 | 7e049b8a | pbrook | uint32_t irq_state; |
27 | 7e049b8a | pbrook | uint32_t eir; |
28 | 7e049b8a | pbrook | uint32_t eimr; |
29 | 7e049b8a | pbrook | int rx_enabled;
|
30 | 7e049b8a | pbrook | uint32_t rx_descriptor; |
31 | 7e049b8a | pbrook | uint32_t tx_descriptor; |
32 | 7e049b8a | pbrook | uint32_t ecr; |
33 | 7e049b8a | pbrook | uint32_t mmfr; |
34 | 7e049b8a | pbrook | uint32_t mscr; |
35 | 7e049b8a | pbrook | uint32_t rcr; |
36 | 7e049b8a | pbrook | uint32_t tcr; |
37 | 7e049b8a | pbrook | uint32_t tfwr; |
38 | 7e049b8a | pbrook | uint32_t rfsr; |
39 | 7e049b8a | pbrook | uint32_t erdsr; |
40 | 7e049b8a | pbrook | uint32_t etdsr; |
41 | 7e049b8a | pbrook | uint32_t emrbr; |
42 | 7e049b8a | pbrook | uint8_t macaddr[6];
|
43 | 7e049b8a | pbrook | } mcf_fec_state; |
44 | 7e049b8a | pbrook | |
45 | 7e049b8a | pbrook | #define FEC_INT_HB 0x80000000 |
46 | 7e049b8a | pbrook | #define FEC_INT_BABR 0x40000000 |
47 | 7e049b8a | pbrook | #define FEC_INT_BABT 0x20000000 |
48 | 7e049b8a | pbrook | #define FEC_INT_GRA 0x10000000 |
49 | 7e049b8a | pbrook | #define FEC_INT_TXF 0x08000000 |
50 | 7e049b8a | pbrook | #define FEC_INT_TXB 0x04000000 |
51 | 7e049b8a | pbrook | #define FEC_INT_RXF 0x02000000 |
52 | 7e049b8a | pbrook | #define FEC_INT_RXB 0x01000000 |
53 | 7e049b8a | pbrook | #define FEC_INT_MII 0x00800000 |
54 | 7e049b8a | pbrook | #define FEC_INT_EB 0x00400000 |
55 | 7e049b8a | pbrook | #define FEC_INT_LC 0x00200000 |
56 | 7e049b8a | pbrook | #define FEC_INT_RL 0x00100000 |
57 | 7e049b8a | pbrook | #define FEC_INT_UN 0x00080000 |
58 | 7e049b8a | pbrook | |
59 | 7e049b8a | pbrook | #define FEC_EN 2 |
60 | 7e049b8a | pbrook | #define FEC_RESET 1 |
61 | 7e049b8a | pbrook | |
62 | 7e049b8a | pbrook | /* Map interrupt flags onto IRQ lines. */
|
63 | 7e049b8a | pbrook | #define FEC_NUM_IRQ 13 |
64 | 7e049b8a | pbrook | static const uint32_t mcf_fec_irq_map[FEC_NUM_IRQ] = { |
65 | 7e049b8a | pbrook | FEC_INT_TXF, |
66 | 7e049b8a | pbrook | FEC_INT_TXB, |
67 | 7e049b8a | pbrook | FEC_INT_UN, |
68 | 7e049b8a | pbrook | FEC_INT_RL, |
69 | 7e049b8a | pbrook | FEC_INT_RXF, |
70 | 7e049b8a | pbrook | FEC_INT_RXB, |
71 | 7e049b8a | pbrook | FEC_INT_MII, |
72 | 7e049b8a | pbrook | FEC_INT_LC, |
73 | 7e049b8a | pbrook | FEC_INT_HB, |
74 | 7e049b8a | pbrook | FEC_INT_GRA, |
75 | 7e049b8a | pbrook | FEC_INT_EB, |
76 | 7e049b8a | pbrook | FEC_INT_BABT, |
77 | 7e049b8a | pbrook | FEC_INT_BABR |
78 | 7e049b8a | pbrook | }; |
79 | 7e049b8a | pbrook | |
80 | 7e049b8a | pbrook | /* Buffer Descriptor. */
|
81 | 7e049b8a | pbrook | typedef struct { |
82 | 7e049b8a | pbrook | uint16_t flags; |
83 | 7e049b8a | pbrook | uint16_t length; |
84 | 7e049b8a | pbrook | uint32_t data; |
85 | 7e049b8a | pbrook | } mcf_fec_bd; |
86 | 7e049b8a | pbrook | |
87 | 7e049b8a | pbrook | #define FEC_BD_R 0x8000 |
88 | 7e049b8a | pbrook | #define FEC_BD_E 0x8000 |
89 | 7e049b8a | pbrook | #define FEC_BD_O1 0x4000 |
90 | 7e049b8a | pbrook | #define FEC_BD_W 0x2000 |
91 | 7e049b8a | pbrook | #define FEC_BD_O2 0x1000 |
92 | 7e049b8a | pbrook | #define FEC_BD_L 0x0800 |
93 | 7e049b8a | pbrook | #define FEC_BD_TC 0x0400 |
94 | 7e049b8a | pbrook | #define FEC_BD_ABC 0x0200 |
95 | 7e049b8a | pbrook | #define FEC_BD_M 0x0100 |
96 | 7e049b8a | pbrook | #define FEC_BD_BC 0x0080 |
97 | 7e049b8a | pbrook | #define FEC_BD_MC 0x0040 |
98 | 7e049b8a | pbrook | #define FEC_BD_LG 0x0020 |
99 | 7e049b8a | pbrook | #define FEC_BD_NO 0x0010 |
100 | 7e049b8a | pbrook | #define FEC_BD_CR 0x0004 |
101 | 7e049b8a | pbrook | #define FEC_BD_OV 0x0002 |
102 | 7e049b8a | pbrook | #define FEC_BD_TR 0x0001 |
103 | 7e049b8a | pbrook | |
104 | 7e049b8a | pbrook | static void mcf_fec_read_bd(mcf_fec_bd *bd, uint32_t addr) |
105 | 7e049b8a | pbrook | { |
106 | 7e049b8a | pbrook | cpu_physical_memory_read(addr, (uint8_t *)bd, sizeof(*bd));
|
107 | 7e049b8a | pbrook | be16_to_cpus(&bd->flags); |
108 | 7e049b8a | pbrook | be16_to_cpus(&bd->length); |
109 | 7e049b8a | pbrook | be32_to_cpus(&bd->data); |
110 | 7e049b8a | pbrook | } |
111 | 7e049b8a | pbrook | |
112 | 7e049b8a | pbrook | static void mcf_fec_write_bd(mcf_fec_bd *bd, uint32_t addr) |
113 | 7e049b8a | pbrook | { |
114 | 7e049b8a | pbrook | mcf_fec_bd tmp; |
115 | 7e049b8a | pbrook | tmp.flags = cpu_to_be16(bd->flags); |
116 | 7e049b8a | pbrook | tmp.length = cpu_to_be16(bd->length); |
117 | 7e049b8a | pbrook | tmp.data = cpu_to_be32(bd->data); |
118 | 7e049b8a | pbrook | cpu_physical_memory_write(addr, (uint8_t *)&tmp, sizeof(tmp));
|
119 | 7e049b8a | pbrook | } |
120 | 7e049b8a | pbrook | |
121 | 7e049b8a | pbrook | static void mcf_fec_update(mcf_fec_state *s) |
122 | 7e049b8a | pbrook | { |
123 | 7e049b8a | pbrook | uint32_t active; |
124 | 7e049b8a | pbrook | uint32_t changed; |
125 | 7e049b8a | pbrook | uint32_t mask; |
126 | 7e049b8a | pbrook | int i;
|
127 | 7e049b8a | pbrook | |
128 | 7e049b8a | pbrook | active = s->eir & s->eimr; |
129 | 7e049b8a | pbrook | changed = active ^s->irq_state; |
130 | 7e049b8a | pbrook | for (i = 0; i < FEC_NUM_IRQ; i++) { |
131 | 7e049b8a | pbrook | mask = mcf_fec_irq_map[i]; |
132 | 7e049b8a | pbrook | if (changed & mask) {
|
133 | 7e049b8a | pbrook | DPRINTF("IRQ %d = %d\n", i, (active & mask) != 0); |
134 | 7e049b8a | pbrook | qemu_set_irq(s->irq[i], (active & mask) != 0);
|
135 | 7e049b8a | pbrook | } |
136 | 7e049b8a | pbrook | } |
137 | 7e049b8a | pbrook | s->irq_state = active; |
138 | 7e049b8a | pbrook | } |
139 | 7e049b8a | pbrook | |
140 | 7e049b8a | pbrook | static void mcf_fec_do_tx(mcf_fec_state *s) |
141 | 7e049b8a | pbrook | { |
142 | 7e049b8a | pbrook | uint32_t addr; |
143 | 7e049b8a | pbrook | mcf_fec_bd bd; |
144 | 7e049b8a | pbrook | int frame_size;
|
145 | 7e049b8a | pbrook | int len;
|
146 | 7e049b8a | pbrook | uint8_t frame[FEC_MAX_FRAME_SIZE]; |
147 | 7e049b8a | pbrook | uint8_t *ptr; |
148 | 7e049b8a | pbrook | |
149 | 7e049b8a | pbrook | DPRINTF("do_tx\n");
|
150 | 7e049b8a | pbrook | ptr = frame; |
151 | 7e049b8a | pbrook | frame_size = 0;
|
152 | 7e049b8a | pbrook | addr = s->tx_descriptor; |
153 | 7e049b8a | pbrook | while (1) { |
154 | 7e049b8a | pbrook | mcf_fec_read_bd(&bd, addr); |
155 | 7e049b8a | pbrook | DPRINTF("tx_bd %x flags %04x len %d data %08x\n",
|
156 | 7e049b8a | pbrook | addr, bd.flags, bd.length, bd.data); |
157 | 7e049b8a | pbrook | if ((bd.flags & FEC_BD_R) == 0) { |
158 | 7e049b8a | pbrook | /* Run out of descriptors to transmit. */
|
159 | 7e049b8a | pbrook | break;
|
160 | 7e049b8a | pbrook | } |
161 | 7e049b8a | pbrook | len = bd.length; |
162 | 7e049b8a | pbrook | if (frame_size + len > FEC_MAX_FRAME_SIZE) {
|
163 | 7e049b8a | pbrook | len = FEC_MAX_FRAME_SIZE - frame_size; |
164 | 7e049b8a | pbrook | s->eir |= FEC_INT_BABT; |
165 | 7e049b8a | pbrook | } |
166 | 7e049b8a | pbrook | cpu_physical_memory_read(bd.data, ptr, len); |
167 | 7e049b8a | pbrook | ptr += len; |
168 | 7e049b8a | pbrook | frame_size += len; |
169 | 7e049b8a | pbrook | if (bd.flags & FEC_BD_L) {
|
170 | 7e049b8a | pbrook | /* Last buffer in frame. */
|
171 | 7e049b8a | pbrook | DPRINTF("Sending packet\n");
|
172 | 7e049b8a | pbrook | qemu_send_packet(s->vc, frame, len); |
173 | 7e049b8a | pbrook | ptr = frame; |
174 | 7e049b8a | pbrook | frame_size = 0;
|
175 | 7e049b8a | pbrook | s->eir |= FEC_INT_TXF; |
176 | 7e049b8a | pbrook | } |
177 | 7e049b8a | pbrook | s->eir |= FEC_INT_TXB; |
178 | 7e049b8a | pbrook | bd.flags &= ~FEC_BD_R; |
179 | 7e049b8a | pbrook | /* Write back the modified descriptor. */
|
180 | 7e049b8a | pbrook | mcf_fec_write_bd(&bd, addr); |
181 | 7e049b8a | pbrook | /* Advance to the next descriptor. */
|
182 | 7e049b8a | pbrook | if ((bd.flags & FEC_BD_W) != 0) { |
183 | 7e049b8a | pbrook | addr = s->etdsr; |
184 | 7e049b8a | pbrook | } else {
|
185 | 7e049b8a | pbrook | addr += 8;
|
186 | 7e049b8a | pbrook | } |
187 | 7e049b8a | pbrook | } |
188 | 7e049b8a | pbrook | s->tx_descriptor = addr; |
189 | 7e049b8a | pbrook | } |
190 | 7e049b8a | pbrook | |
191 | 4fdcd8d4 | pbrook | static void mcf_fec_enable_rx(mcf_fec_state *s) |
192 | 7e049b8a | pbrook | { |
193 | 7e049b8a | pbrook | mcf_fec_bd bd; |
194 | 7e049b8a | pbrook | |
195 | 7e049b8a | pbrook | mcf_fec_read_bd(&bd, s->rx_descriptor); |
196 | 7e049b8a | pbrook | s->rx_enabled = ((bd.flags & FEC_BD_E) != 0);
|
197 | 7e049b8a | pbrook | if (!s->rx_enabled)
|
198 | 7e049b8a | pbrook | DPRINTF("RX buffer full\n");
|
199 | 7e049b8a | pbrook | } |
200 | 7e049b8a | pbrook | |
201 | 7e049b8a | pbrook | static void mcf_fec_reset(mcf_fec_state *s) |
202 | 7e049b8a | pbrook | { |
203 | 7e049b8a | pbrook | s->eir = 0;
|
204 | 7e049b8a | pbrook | s->eimr = 0;
|
205 | 7e049b8a | pbrook | s->rx_enabled = 0;
|
206 | 7e049b8a | pbrook | s->ecr = 0;
|
207 | 7e049b8a | pbrook | s->mscr = 0;
|
208 | 7e049b8a | pbrook | s->rcr = 0x05ee0001;
|
209 | 7e049b8a | pbrook | s->tcr = 0;
|
210 | 7e049b8a | pbrook | s->tfwr = 0;
|
211 | 7e049b8a | pbrook | s->rfsr = 0x500;
|
212 | 7e049b8a | pbrook | } |
213 | 7e049b8a | pbrook | |
214 | 7e049b8a | pbrook | static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr) |
215 | 7e049b8a | pbrook | { |
216 | 7e049b8a | pbrook | mcf_fec_state *s = (mcf_fec_state *)opaque; |
217 | 7e049b8a | pbrook | switch (addr & 0x3ff) { |
218 | 7e049b8a | pbrook | case 0x004: return s->eir; |
219 | 7e049b8a | pbrook | case 0x008: return s->eimr; |
220 | 7e049b8a | pbrook | case 0x010: return s->rx_enabled ? (1 << 24) : 0; /* RDAR */ |
221 | 7e049b8a | pbrook | case 0x014: return 0; /* TDAR */ |
222 | 7e049b8a | pbrook | case 0x024: return s->ecr; |
223 | 7e049b8a | pbrook | case 0x040: return s->mmfr; |
224 | 7e049b8a | pbrook | case 0x044: return s->mscr; |
225 | 7e049b8a | pbrook | case 0x064: return 0; /* MIBC */ |
226 | 7e049b8a | pbrook | case 0x084: return s->rcr; |
227 | 7e049b8a | pbrook | case 0x0c4: return s->tcr; |
228 | 7e049b8a | pbrook | case 0x0e4: /* PALR */ |
229 | 7e049b8a | pbrook | return (s->macaddr[0] << 24) | (s->macaddr[1] << 16) |
230 | 7e049b8a | pbrook | | (s->macaddr[2] << 8) | s->macaddr[3]; |
231 | 7e049b8a | pbrook | break;
|
232 | 7e049b8a | pbrook | case 0x0e8: /* PAUR */ |
233 | 7e049b8a | pbrook | return (s->macaddr[4] << 24) | (s->macaddr[5] << 16) | 0x8808; |
234 | 7e049b8a | pbrook | case 0x0ec: return 0x10000; /* OPD */ |
235 | 7e049b8a | pbrook | case 0x118: return 0; |
236 | 7e049b8a | pbrook | case 0x11c: return 0; |
237 | 7e049b8a | pbrook | case 0x120: return 0; |
238 | 7e049b8a | pbrook | case 0x124: return 0; |
239 | 7e049b8a | pbrook | case 0x144: return s->tfwr; |
240 | 7e049b8a | pbrook | case 0x14c: return 0x600; |
241 | 7e049b8a | pbrook | case 0x150: return s->rfsr; |
242 | 7e049b8a | pbrook | case 0x180: return s->erdsr; |
243 | 7e049b8a | pbrook | case 0x184: return s->etdsr; |
244 | 7e049b8a | pbrook | case 0x188: return s->emrbr; |
245 | 7e049b8a | pbrook | default:
|
246 | 7e049b8a | pbrook | cpu_abort(cpu_single_env, "mcf_fec_read: Bad address 0x%x\n",
|
247 | 7e049b8a | pbrook | (int)addr);
|
248 | 7e049b8a | pbrook | return 0; |
249 | 7e049b8a | pbrook | } |
250 | 7e049b8a | pbrook | } |
251 | 7e049b8a | pbrook | |
252 | 7e049b8a | pbrook | void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value) |
253 | 7e049b8a | pbrook | { |
254 | 7e049b8a | pbrook | mcf_fec_state *s = (mcf_fec_state *)opaque; |
255 | 7e049b8a | pbrook | switch (addr & 0x3ff) { |
256 | 7e049b8a | pbrook | case 0x004: |
257 | 7e049b8a | pbrook | s->eir &= ~value; |
258 | 7e049b8a | pbrook | break;
|
259 | 7e049b8a | pbrook | case 0x008: |
260 | 7e049b8a | pbrook | s->eimr = value; |
261 | 7e049b8a | pbrook | break;
|
262 | 7e049b8a | pbrook | case 0x010: /* RDAR */ |
263 | 7e049b8a | pbrook | if ((s->ecr & FEC_EN) && !s->rx_enabled) {
|
264 | 7e049b8a | pbrook | DPRINTF("RX enable\n");
|
265 | 7e049b8a | pbrook | mcf_fec_enable_rx(s); |
266 | 7e049b8a | pbrook | } |
267 | 7e049b8a | pbrook | break;
|
268 | 7e049b8a | pbrook | case 0x014: /* TDAR */ |
269 | 7e049b8a | pbrook | if (s->ecr & FEC_EN) {
|
270 | 7e049b8a | pbrook | mcf_fec_do_tx(s); |
271 | 7e049b8a | pbrook | } |
272 | 7e049b8a | pbrook | break;
|
273 | 7e049b8a | pbrook | case 0x024: |
274 | 7e049b8a | pbrook | s->ecr = value; |
275 | 7e049b8a | pbrook | if (value & FEC_RESET) {
|
276 | 7e049b8a | pbrook | DPRINTF("Reset\n");
|
277 | 7e049b8a | pbrook | mcf_fec_reset(s); |
278 | 7e049b8a | pbrook | } |
279 | 7e049b8a | pbrook | if ((s->ecr & FEC_EN) == 0) { |
280 | 7e049b8a | pbrook | s->rx_enabled = 0;
|
281 | 7e049b8a | pbrook | } |
282 | 7e049b8a | pbrook | break;
|
283 | 7e049b8a | pbrook | case 0x040: |
284 | 7e049b8a | pbrook | /* TODO: Implement MII. */
|
285 | 7e049b8a | pbrook | s->mmfr = value; |
286 | 7e049b8a | pbrook | break;
|
287 | 7e049b8a | pbrook | case 0x044: |
288 | 7e049b8a | pbrook | s->mscr = value & 0xfe;
|
289 | 7e049b8a | pbrook | break;
|
290 | 7e049b8a | pbrook | case 0x064: |
291 | 7e049b8a | pbrook | /* TODO: Implement MIB. */
|
292 | 7e049b8a | pbrook | break;
|
293 | 7e049b8a | pbrook | case 0x084: |
294 | 7e049b8a | pbrook | s->rcr = value & 0x07ff003f;
|
295 | 7e049b8a | pbrook | /* TODO: Implement LOOP mode. */
|
296 | 7e049b8a | pbrook | break;
|
297 | 7e049b8a | pbrook | case 0x0c4: /* TCR */ |
298 | 7e049b8a | pbrook | /* We transmit immediately, so raise GRA immediately. */
|
299 | 7e049b8a | pbrook | s->tcr = value; |
300 | 7e049b8a | pbrook | if (value & 1) |
301 | 7e049b8a | pbrook | s->eir |= FEC_INT_GRA; |
302 | 7e049b8a | pbrook | break;
|
303 | 7e049b8a | pbrook | case 0x0e4: /* PALR */ |
304 | 7e049b8a | pbrook | s->macaddr[0] = value >> 24; |
305 | 7e049b8a | pbrook | s->macaddr[1] = value >> 16; |
306 | 7e049b8a | pbrook | s->macaddr[2] = value >> 8; |
307 | 7e049b8a | pbrook | s->macaddr[3] = value;
|
308 | 7e049b8a | pbrook | break;
|
309 | 7e049b8a | pbrook | case 0x0e8: /* PAUR */ |
310 | 7e049b8a | pbrook | s->macaddr[4] = value >> 24; |
311 | 7e049b8a | pbrook | s->macaddr[5] = value >> 16; |
312 | 7e049b8a | pbrook | break;
|
313 | 7e049b8a | pbrook | case 0x0ec: |
314 | 7e049b8a | pbrook | /* OPD */
|
315 | 7e049b8a | pbrook | break;
|
316 | 7e049b8a | pbrook | case 0x118: |
317 | 7e049b8a | pbrook | case 0x11c: |
318 | 7e049b8a | pbrook | case 0x120: |
319 | 7e049b8a | pbrook | case 0x124: |
320 | 7e049b8a | pbrook | /* TODO: implement MAC hash filtering. */
|
321 | 7e049b8a | pbrook | break;
|
322 | 7e049b8a | pbrook | case 0x144: |
323 | 7e049b8a | pbrook | s->tfwr = value & 3;
|
324 | 7e049b8a | pbrook | break;
|
325 | 7e049b8a | pbrook | case 0x14c: |
326 | 7e049b8a | pbrook | /* FRBR writes ignored. */
|
327 | 7e049b8a | pbrook | break;
|
328 | 7e049b8a | pbrook | case 0x150: |
329 | 7e049b8a | pbrook | s->rfsr = (value & 0x3fc) | 0x400; |
330 | 7e049b8a | pbrook | break;
|
331 | 7e049b8a | pbrook | case 0x180: |
332 | 7e049b8a | pbrook | s->erdsr = value & ~3;
|
333 | 7e049b8a | pbrook | s->rx_descriptor = s->erdsr; |
334 | 7e049b8a | pbrook | break;
|
335 | 7e049b8a | pbrook | case 0x184: |
336 | 7e049b8a | pbrook | s->etdsr = value & ~3;
|
337 | 7e049b8a | pbrook | s->tx_descriptor = s->etdsr; |
338 | 7e049b8a | pbrook | break;
|
339 | 7e049b8a | pbrook | case 0x188: |
340 | 7e049b8a | pbrook | s->emrbr = value & 0x7f0;
|
341 | 7e049b8a | pbrook | break;
|
342 | 7e049b8a | pbrook | default:
|
343 | 7e049b8a | pbrook | cpu_abort(cpu_single_env, "mcf_fec_write Bad address 0x%x\n",
|
344 | 7e049b8a | pbrook | (int)addr);
|
345 | 7e049b8a | pbrook | } |
346 | 7e049b8a | pbrook | mcf_fec_update(s); |
347 | 7e049b8a | pbrook | } |
348 | 7e049b8a | pbrook | |
349 | 7e049b8a | pbrook | static int mcf_fec_can_receive(void *opaque) |
350 | 7e049b8a | pbrook | { |
351 | 7e049b8a | pbrook | mcf_fec_state *s = (mcf_fec_state *)opaque; |
352 | 7e049b8a | pbrook | return s->rx_enabled;
|
353 | 7e049b8a | pbrook | } |
354 | 7e049b8a | pbrook | |
355 | 7e049b8a | pbrook | static void mcf_fec_receive(void *opaque, const uint8_t *buf, int size) |
356 | 7e049b8a | pbrook | { |
357 | 7e049b8a | pbrook | mcf_fec_state *s = (mcf_fec_state *)opaque; |
358 | 7e049b8a | pbrook | mcf_fec_bd bd; |
359 | 7e049b8a | pbrook | uint32_t flags = 0;
|
360 | 7e049b8a | pbrook | uint32_t addr; |
361 | 7e049b8a | pbrook | uint32_t crc; |
362 | 7e049b8a | pbrook | uint32_t buf_addr; |
363 | 7e049b8a | pbrook | uint8_t *crc_ptr; |
364 | 7e049b8a | pbrook | unsigned int buf_len; |
365 | 7e049b8a | pbrook | |
366 | 7e049b8a | pbrook | DPRINTF("do_rx len %d\n", size);
|
367 | 7e049b8a | pbrook | if (!s->rx_enabled) {
|
368 | 7e049b8a | pbrook | fprintf(stderr, "mcf_fec_receive: Unexpected packet\n");
|
369 | 7e049b8a | pbrook | } |
370 | 7e049b8a | pbrook | /* 4 bytes for the CRC. */
|
371 | 7e049b8a | pbrook | size += 4;
|
372 | 7e049b8a | pbrook | crc = cpu_to_be32(crc32(~0, buf, size));
|
373 | 7e049b8a | pbrook | crc_ptr = (uint8_t *)&crc; |
374 | 7e049b8a | pbrook | /* Huge frames are truncted. */
|
375 | 7e049b8a | pbrook | if (size > FEC_MAX_FRAME_SIZE) {
|
376 | 7e049b8a | pbrook | size = FEC_MAX_FRAME_SIZE; |
377 | 7e049b8a | pbrook | flags |= FEC_BD_TR | FEC_BD_LG; |
378 | 7e049b8a | pbrook | } |
379 | 7e049b8a | pbrook | /* Frames larger than the user limit just set error flags. */
|
380 | 7e049b8a | pbrook | if (size > (s->rcr >> 16)) { |
381 | 7e049b8a | pbrook | flags |= FEC_BD_LG; |
382 | 7e049b8a | pbrook | } |
383 | 7e049b8a | pbrook | addr = s->rx_descriptor; |
384 | 7e049b8a | pbrook | while (size > 0) { |
385 | 7e049b8a | pbrook | mcf_fec_read_bd(&bd, addr); |
386 | 7e049b8a | pbrook | if ((bd.flags & FEC_BD_E) == 0) { |
387 | 7e049b8a | pbrook | /* No descriptors available. Bail out. */
|
388 | 7e049b8a | pbrook | /* FIXME: This is wrong. We should probably either save the
|
389 | 7e049b8a | pbrook | remainder for when more RX buffers are available, or
|
390 | 7e049b8a | pbrook | flag an error. */
|
391 | 7e049b8a | pbrook | fprintf(stderr, "mcf_fec: Lost end of frame\n");
|
392 | 7e049b8a | pbrook | break;
|
393 | 7e049b8a | pbrook | } |
394 | 7e049b8a | pbrook | buf_len = (size <= s->emrbr) ? size: s->emrbr; |
395 | 7e049b8a | pbrook | bd.length = buf_len; |
396 | 7e049b8a | pbrook | size -= buf_len; |
397 | 7e049b8a | pbrook | DPRINTF("rx_bd %x length %d\n", addr, bd.length);
|
398 | 7e049b8a | pbrook | /* The last 4 bytes are the CRC. */
|
399 | 7e049b8a | pbrook | if (size < 4) |
400 | 7e049b8a | pbrook | buf_len += size - 4;
|
401 | 7e049b8a | pbrook | buf_addr = bd.data; |
402 | 7e049b8a | pbrook | cpu_physical_memory_write(buf_addr, buf, buf_len); |
403 | 7e049b8a | pbrook | buf += buf_len; |
404 | 7e049b8a | pbrook | if (size < 4) { |
405 | 7e049b8a | pbrook | cpu_physical_memory_write(buf_addr + buf_len, crc_ptr, 4 - size);
|
406 | 7e049b8a | pbrook | crc_ptr += 4 - size;
|
407 | 7e049b8a | pbrook | } |
408 | 7e049b8a | pbrook | bd.flags &= ~FEC_BD_E; |
409 | 7e049b8a | pbrook | if (size == 0) { |
410 | 7e049b8a | pbrook | /* Last buffer in frame. */
|
411 | 7e049b8a | pbrook | bd.flags |= flags | FEC_BD_L; |
412 | 7e049b8a | pbrook | DPRINTF("rx frame flags %04x\n", bd.flags);
|
413 | 7e049b8a | pbrook | s->eir |= FEC_INT_RXF; |
414 | 7e049b8a | pbrook | } else {
|
415 | 7e049b8a | pbrook | s->eir |= FEC_INT_RXB; |
416 | 7e049b8a | pbrook | } |
417 | 7e049b8a | pbrook | mcf_fec_write_bd(&bd, addr); |
418 | 7e049b8a | pbrook | /* Advance to the next descriptor. */
|
419 | 7e049b8a | pbrook | if ((bd.flags & FEC_BD_W) != 0) { |
420 | 7e049b8a | pbrook | addr = s->erdsr; |
421 | 7e049b8a | pbrook | } else {
|
422 | 7e049b8a | pbrook | addr += 8;
|
423 | 7e049b8a | pbrook | } |
424 | 7e049b8a | pbrook | } |
425 | 7e049b8a | pbrook | s->rx_descriptor = addr; |
426 | 7e049b8a | pbrook | mcf_fec_enable_rx(s); |
427 | 7e049b8a | pbrook | mcf_fec_update(s); |
428 | 7e049b8a | pbrook | } |
429 | 7e049b8a | pbrook | |
430 | 7e049b8a | pbrook | static CPUReadMemoryFunc *mcf_fec_readfn[] = {
|
431 | 7e049b8a | pbrook | mcf_fec_read, |
432 | 7e049b8a | pbrook | mcf_fec_read, |
433 | 7e049b8a | pbrook | mcf_fec_read |
434 | 7e049b8a | pbrook | }; |
435 | 7e049b8a | pbrook | |
436 | 7e049b8a | pbrook | static CPUWriteMemoryFunc *mcf_fec_writefn[] = {
|
437 | 7e049b8a | pbrook | mcf_fec_write, |
438 | 7e049b8a | pbrook | mcf_fec_write, |
439 | 7e049b8a | pbrook | mcf_fec_write |
440 | 7e049b8a | pbrook | }; |
441 | 7e049b8a | pbrook | |
442 | 7e049b8a | pbrook | void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq)
|
443 | 7e049b8a | pbrook | { |
444 | 7e049b8a | pbrook | mcf_fec_state *s; |
445 | 7e049b8a | pbrook | int iomemtype;
|
446 | 7e049b8a | pbrook | |
447 | 7e049b8a | pbrook | s = (mcf_fec_state *)qemu_mallocz(sizeof(mcf_fec_state));
|
448 | 7e049b8a | pbrook | s->irq = irq; |
449 | 7e049b8a | pbrook | iomemtype = cpu_register_io_memory(0, mcf_fec_readfn,
|
450 | 7e049b8a | pbrook | mcf_fec_writefn, s); |
451 | 7e049b8a | pbrook | cpu_register_physical_memory(base, 0x400, iomemtype);
|
452 | 7e049b8a | pbrook | |
453 | 7e049b8a | pbrook | s->vc = qemu_new_vlan_client(nd->vlan, mcf_fec_receive, |
454 | 7e049b8a | pbrook | mcf_fec_can_receive, s); |
455 | 7e049b8a | pbrook | memcpy(s->macaddr, nd->macaddr, 6);
|
456 | 7e049b8a | pbrook | } |