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1 | c3d2689d | balrog | /*
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2 | c3d2689d | balrog | * TI OMAP processors emulation.
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3 | c3d2689d | balrog | *
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4 | c3d2689d | balrog | * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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5 | c3d2689d | balrog | *
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6 | c3d2689d | balrog | * This program is free software; you can redistribute it and/or
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7 | c3d2689d | balrog | * modify it under the terms of the GNU General Public License as
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8 | c3d2689d | balrog | * published by the Free Software Foundation; either version 2 of
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9 | c3d2689d | balrog | * the License, or (at your option) any later version.
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10 | c3d2689d | balrog | *
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11 | c3d2689d | balrog | * This program is distributed in the hope that it will be useful,
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12 | c3d2689d | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | c3d2689d | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | c3d2689d | balrog | * GNU General Public License for more details.
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15 | c3d2689d | balrog | *
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16 | c3d2689d | balrog | * You should have received a copy of the GNU General Public License
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17 | c3d2689d | balrog | * along with this program; if not, write to the Free Software
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18 | c3d2689d | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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19 | c3d2689d | balrog | * MA 02111-1307 USA
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20 | c3d2689d | balrog | */
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21 | c3d2689d | balrog | #include "vl.h" |
22 | c3d2689d | balrog | #include "arm_pic.h" |
23 | c3d2689d | balrog | |
24 | c3d2689d | balrog | /* Should signal the TCMI */
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25 | b30bb3a2 | balrog | uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
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26 | c3d2689d | balrog | { |
27 | c3d2689d | balrog | OMAP_16B_REG(addr); |
28 | c3d2689d | balrog | return 0; |
29 | c3d2689d | balrog | } |
30 | c3d2689d | balrog | |
31 | b30bb3a2 | balrog | void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
32 | c3d2689d | balrog | uint32_t value) |
33 | c3d2689d | balrog | { |
34 | c3d2689d | balrog | OMAP_16B_REG(addr); |
35 | c3d2689d | balrog | } |
36 | c3d2689d | balrog | |
37 | b30bb3a2 | balrog | uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
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38 | c3d2689d | balrog | { |
39 | c3d2689d | balrog | OMAP_32B_REG(addr); |
40 | c3d2689d | balrog | return 0; |
41 | c3d2689d | balrog | } |
42 | c3d2689d | balrog | |
43 | b30bb3a2 | balrog | void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
44 | c3d2689d | balrog | uint32_t value) |
45 | c3d2689d | balrog | { |
46 | c3d2689d | balrog | OMAP_32B_REG(addr); |
47 | c3d2689d | balrog | } |
48 | c3d2689d | balrog | |
49 | c3d2689d | balrog | /* Interrupt Handlers */
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50 | c3d2689d | balrog | struct omap_intr_handler_s {
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51 | c3d2689d | balrog | qemu_irq *pins; |
52 | c3d2689d | balrog | qemu_irq *parent_pic; |
53 | c3d2689d | balrog | target_phys_addr_t base; |
54 | c3d2689d | balrog | |
55 | c3d2689d | balrog | /* state */
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56 | c3d2689d | balrog | uint32_t irqs; |
57 | c3d2689d | balrog | uint32_t mask; |
58 | c3d2689d | balrog | uint32_t sens_edge; |
59 | c3d2689d | balrog | uint32_t fiq; |
60 | c3d2689d | balrog | int priority[32]; |
61 | c3d2689d | balrog | uint32_t new_irq_agr; |
62 | c3d2689d | balrog | uint32_t new_fiq_agr; |
63 | c3d2689d | balrog | int sir_irq;
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64 | c3d2689d | balrog | int sir_fiq;
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65 | c3d2689d | balrog | int stats[32]; |
66 | c3d2689d | balrog | }; |
67 | c3d2689d | balrog | |
68 | c3d2689d | balrog | static void omap_inth_update(struct omap_intr_handler_s *s) |
69 | c3d2689d | balrog | { |
70 | cfa0b71d | balrog | uint32_t irq = s->irqs & ~s->mask & ~s->fiq; |
71 | cfa0b71d | balrog | uint32_t fiq = s->irqs & ~s->mask & s->fiq; |
72 | c3d2689d | balrog | |
73 | cfa0b71d | balrog | if (s->new_irq_agr || !irq) {
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74 | cfa0b71d | balrog | qemu_set_irq(s->parent_pic[ARM_PIC_CPU_IRQ], irq); |
75 | cfa0b71d | balrog | if (irq)
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76 | cfa0b71d | balrog | s->new_irq_agr = 0;
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77 | cfa0b71d | balrog | } |
78 | c3d2689d | balrog | |
79 | cfa0b71d | balrog | if (s->new_fiq_agr || !irq) {
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80 | cfa0b71d | balrog | qemu_set_irq(s->parent_pic[ARM_PIC_CPU_FIQ], fiq); |
81 | cfa0b71d | balrog | if (fiq)
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82 | cfa0b71d | balrog | s->new_fiq_agr = 0;
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83 | cfa0b71d | balrog | } |
84 | c3d2689d | balrog | } |
85 | c3d2689d | balrog | |
86 | c3d2689d | balrog | static void omap_inth_sir_update(struct omap_intr_handler_s *s) |
87 | c3d2689d | balrog | { |
88 | c3d2689d | balrog | int i, intr_irq, intr_fiq, p_irq, p_fiq, p, f;
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89 | c3d2689d | balrog | uint32_t level = s->irqs & ~s->mask; |
90 | c3d2689d | balrog | |
91 | c3d2689d | balrog | intr_irq = 0;
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92 | c3d2689d | balrog | intr_fiq = 0;
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93 | c3d2689d | balrog | p_irq = -1;
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94 | c3d2689d | balrog | p_fiq = -1;
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95 | c3d2689d | balrog | /* Find the interrupt line with the highest dynamic priority */
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96 | c3d2689d | balrog | for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, level >>= f) { |
97 | c3d2689d | balrog | p = s->priority[i]; |
98 | c3d2689d | balrog | if (s->fiq & (1 << i)) { |
99 | c3d2689d | balrog | if (p > p_fiq) {
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100 | c3d2689d | balrog | p_fiq = p; |
101 | c3d2689d | balrog | intr_fiq = i; |
102 | c3d2689d | balrog | } |
103 | c3d2689d | balrog | } else {
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104 | c3d2689d | balrog | if (p > p_irq) {
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105 | c3d2689d | balrog | p_irq = p; |
106 | c3d2689d | balrog | intr_irq = i; |
107 | c3d2689d | balrog | } |
108 | c3d2689d | balrog | } |
109 | c3d2689d | balrog | |
110 | c3d2689d | balrog | f = ffs(level >> 1);
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111 | c3d2689d | balrog | } |
112 | c3d2689d | balrog | |
113 | c3d2689d | balrog | s->sir_irq = intr_irq; |
114 | c3d2689d | balrog | s->sir_fiq = intr_fiq; |
115 | c3d2689d | balrog | } |
116 | c3d2689d | balrog | |
117 | c3d2689d | balrog | #define INT_FALLING_EDGE 0 |
118 | c3d2689d | balrog | #define INT_LOW_LEVEL 1 |
119 | c3d2689d | balrog | |
120 | c3d2689d | balrog | static void omap_set_intr(void *opaque, int irq, int req) |
121 | c3d2689d | balrog | { |
122 | c3d2689d | balrog | struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
123 | c3d2689d | balrog | uint32_t rise; |
124 | c3d2689d | balrog | |
125 | c3d2689d | balrog | if (req) {
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126 | c3d2689d | balrog | rise = ~ih->irqs & (1 << irq);
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127 | c3d2689d | balrog | ih->irqs |= rise; |
128 | cfa0b71d | balrog | ih->stats[irq] += !!rise; |
129 | c3d2689d | balrog | } else {
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130 | c3d2689d | balrog | rise = ih->sens_edge & ih->irqs & (1 << irq);
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131 | c3d2689d | balrog | ih->irqs &= ~rise; |
132 | c3d2689d | balrog | } |
133 | c3d2689d | balrog | |
134 | c3d2689d | balrog | if (rise & ~ih->mask) {
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135 | c3d2689d | balrog | omap_inth_sir_update(ih); |
136 | c3d2689d | balrog | |
137 | c3d2689d | balrog | omap_inth_update(ih); |
138 | c3d2689d | balrog | } |
139 | c3d2689d | balrog | } |
140 | c3d2689d | balrog | |
141 | c3d2689d | balrog | static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) |
142 | c3d2689d | balrog | { |
143 | c3d2689d | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
144 | c3d2689d | balrog | int i, offset = addr - s->base;
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145 | c3d2689d | balrog | |
146 | c3d2689d | balrog | switch (offset) {
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147 | c3d2689d | balrog | case 0x00: /* ITR */ |
148 | c3d2689d | balrog | return s->irqs;
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149 | c3d2689d | balrog | |
150 | c3d2689d | balrog | case 0x04: /* MIR */ |
151 | c3d2689d | balrog | return s->mask;
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152 | c3d2689d | balrog | |
153 | c3d2689d | balrog | case 0x10: /* SIR_IRQ_CODE */ |
154 | c3d2689d | balrog | i = s->sir_irq; |
155 | c3d2689d | balrog | if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) { |
156 | c3d2689d | balrog | s->irqs &= ~(1 << i);
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157 | c3d2689d | balrog | omap_inth_sir_update(s); |
158 | c3d2689d | balrog | omap_inth_update(s); |
159 | c3d2689d | balrog | } |
160 | c3d2689d | balrog | return i;
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161 | c3d2689d | balrog | |
162 | c3d2689d | balrog | case 0x14: /* SIR_FIQ_CODE */ |
163 | c3d2689d | balrog | i = s->sir_fiq; |
164 | c3d2689d | balrog | if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) { |
165 | c3d2689d | balrog | s->irqs &= ~(1 << i);
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166 | c3d2689d | balrog | omap_inth_sir_update(s); |
167 | c3d2689d | balrog | omap_inth_update(s); |
168 | c3d2689d | balrog | } |
169 | c3d2689d | balrog | return i;
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170 | c3d2689d | balrog | |
171 | c3d2689d | balrog | case 0x18: /* CONTROL_REG */ |
172 | c3d2689d | balrog | return 0; |
173 | c3d2689d | balrog | |
174 | c3d2689d | balrog | case 0x1c: /* ILR0 */ |
175 | c3d2689d | balrog | case 0x20: /* ILR1 */ |
176 | c3d2689d | balrog | case 0x24: /* ILR2 */ |
177 | c3d2689d | balrog | case 0x28: /* ILR3 */ |
178 | c3d2689d | balrog | case 0x2c: /* ILR4 */ |
179 | c3d2689d | balrog | case 0x30: /* ILR5 */ |
180 | c3d2689d | balrog | case 0x34: /* ILR6 */ |
181 | c3d2689d | balrog | case 0x38: /* ILR7 */ |
182 | c3d2689d | balrog | case 0x3c: /* ILR8 */ |
183 | c3d2689d | balrog | case 0x40: /* ILR9 */ |
184 | c3d2689d | balrog | case 0x44: /* ILR10 */ |
185 | c3d2689d | balrog | case 0x48: /* ILR11 */ |
186 | c3d2689d | balrog | case 0x4c: /* ILR12 */ |
187 | c3d2689d | balrog | case 0x50: /* ILR13 */ |
188 | c3d2689d | balrog | case 0x54: /* ILR14 */ |
189 | c3d2689d | balrog | case 0x58: /* ILR15 */ |
190 | c3d2689d | balrog | case 0x5c: /* ILR16 */ |
191 | c3d2689d | balrog | case 0x60: /* ILR17 */ |
192 | c3d2689d | balrog | case 0x64: /* ILR18 */ |
193 | c3d2689d | balrog | case 0x68: /* ILR19 */ |
194 | c3d2689d | balrog | case 0x6c: /* ILR20 */ |
195 | c3d2689d | balrog | case 0x70: /* ILR21 */ |
196 | c3d2689d | balrog | case 0x74: /* ILR22 */ |
197 | c3d2689d | balrog | case 0x78: /* ILR23 */ |
198 | c3d2689d | balrog | case 0x7c: /* ILR24 */ |
199 | c3d2689d | balrog | case 0x80: /* ILR25 */ |
200 | c3d2689d | balrog | case 0x84: /* ILR26 */ |
201 | c3d2689d | balrog | case 0x88: /* ILR27 */ |
202 | c3d2689d | balrog | case 0x8c: /* ILR28 */ |
203 | c3d2689d | balrog | case 0x90: /* ILR29 */ |
204 | c3d2689d | balrog | case 0x94: /* ILR30 */ |
205 | c3d2689d | balrog | case 0x98: /* ILR31 */ |
206 | c3d2689d | balrog | i = (offset - 0x1c) >> 2; |
207 | c3d2689d | balrog | return (s->priority[i] << 2) | |
208 | c3d2689d | balrog | (((s->sens_edge >> i) & 1) << 1) | |
209 | c3d2689d | balrog | ((s->fiq >> i) & 1);
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210 | c3d2689d | balrog | |
211 | c3d2689d | balrog | case 0x9c: /* ISR */ |
212 | c3d2689d | balrog | return 0x00000000; |
213 | c3d2689d | balrog | |
214 | c3d2689d | balrog | default:
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215 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
216 | c3d2689d | balrog | break;
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217 | c3d2689d | balrog | } |
218 | c3d2689d | balrog | return 0; |
219 | c3d2689d | balrog | } |
220 | c3d2689d | balrog | |
221 | c3d2689d | balrog | static void omap_inth_write(void *opaque, target_phys_addr_t addr, |
222 | c3d2689d | balrog | uint32_t value) |
223 | c3d2689d | balrog | { |
224 | c3d2689d | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
225 | c3d2689d | balrog | int i, offset = addr - s->base;
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226 | c3d2689d | balrog | |
227 | c3d2689d | balrog | switch (offset) {
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228 | c3d2689d | balrog | case 0x00: /* ITR */ |
229 | c3d2689d | balrog | s->irqs &= value; |
230 | c3d2689d | balrog | omap_inth_sir_update(s); |
231 | c3d2689d | balrog | omap_inth_update(s); |
232 | c3d2689d | balrog | return;
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233 | c3d2689d | balrog | |
234 | c3d2689d | balrog | case 0x04: /* MIR */ |
235 | c3d2689d | balrog | s->mask = value; |
236 | c3d2689d | balrog | omap_inth_sir_update(s); |
237 | c3d2689d | balrog | omap_inth_update(s); |
238 | c3d2689d | balrog | return;
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239 | c3d2689d | balrog | |
240 | c3d2689d | balrog | case 0x10: /* SIR_IRQ_CODE */ |
241 | c3d2689d | balrog | case 0x14: /* SIR_FIQ_CODE */ |
242 | c3d2689d | balrog | OMAP_RO_REG(addr); |
243 | c3d2689d | balrog | break;
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244 | c3d2689d | balrog | |
245 | c3d2689d | balrog | case 0x18: /* CONTROL_REG */ |
246 | c3d2689d | balrog | if (value & 2) |
247 | c3d2689d | balrog | s->new_fiq_agr = ~0;
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248 | c3d2689d | balrog | if (value & 1) |
249 | c3d2689d | balrog | s->new_irq_agr = ~0;
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250 | c3d2689d | balrog | omap_inth_update(s); |
251 | c3d2689d | balrog | return;
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252 | c3d2689d | balrog | |
253 | c3d2689d | balrog | case 0x1c: /* ILR0 */ |
254 | c3d2689d | balrog | case 0x20: /* ILR1 */ |
255 | c3d2689d | balrog | case 0x24: /* ILR2 */ |
256 | c3d2689d | balrog | case 0x28: /* ILR3 */ |
257 | c3d2689d | balrog | case 0x2c: /* ILR4 */ |
258 | c3d2689d | balrog | case 0x30: /* ILR5 */ |
259 | c3d2689d | balrog | case 0x34: /* ILR6 */ |
260 | c3d2689d | balrog | case 0x38: /* ILR7 */ |
261 | c3d2689d | balrog | case 0x3c: /* ILR8 */ |
262 | c3d2689d | balrog | case 0x40: /* ILR9 */ |
263 | c3d2689d | balrog | case 0x44: /* ILR10 */ |
264 | c3d2689d | balrog | case 0x48: /* ILR11 */ |
265 | c3d2689d | balrog | case 0x4c: /* ILR12 */ |
266 | c3d2689d | balrog | case 0x50: /* ILR13 */ |
267 | c3d2689d | balrog | case 0x54: /* ILR14 */ |
268 | c3d2689d | balrog | case 0x58: /* ILR15 */ |
269 | c3d2689d | balrog | case 0x5c: /* ILR16 */ |
270 | c3d2689d | balrog | case 0x60: /* ILR17 */ |
271 | c3d2689d | balrog | case 0x64: /* ILR18 */ |
272 | c3d2689d | balrog | case 0x68: /* ILR19 */ |
273 | c3d2689d | balrog | case 0x6c: /* ILR20 */ |
274 | c3d2689d | balrog | case 0x70: /* ILR21 */ |
275 | c3d2689d | balrog | case 0x74: /* ILR22 */ |
276 | c3d2689d | balrog | case 0x78: /* ILR23 */ |
277 | c3d2689d | balrog | case 0x7c: /* ILR24 */ |
278 | c3d2689d | balrog | case 0x80: /* ILR25 */ |
279 | c3d2689d | balrog | case 0x84: /* ILR26 */ |
280 | c3d2689d | balrog | case 0x88: /* ILR27 */ |
281 | c3d2689d | balrog | case 0x8c: /* ILR28 */ |
282 | c3d2689d | balrog | case 0x90: /* ILR29 */ |
283 | c3d2689d | balrog | case 0x94: /* ILR30 */ |
284 | c3d2689d | balrog | case 0x98: /* ILR31 */ |
285 | c3d2689d | balrog | i = (offset - 0x1c) >> 2; |
286 | c3d2689d | balrog | s->priority[i] = (value >> 2) & 0x1f; |
287 | c3d2689d | balrog | s->sens_edge &= ~(1 << i);
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288 | c3d2689d | balrog | s->sens_edge |= ((value >> 1) & 1) << i; |
289 | c3d2689d | balrog | s->fiq &= ~(1 << i);
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290 | c3d2689d | balrog | s->fiq |= (value & 1) << i;
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291 | c3d2689d | balrog | return;
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292 | c3d2689d | balrog | |
293 | c3d2689d | balrog | case 0x9c: /* ISR */ |
294 | c3d2689d | balrog | for (i = 0; i < 32; i ++) |
295 | c3d2689d | balrog | if (value & (1 << i)) { |
296 | c3d2689d | balrog | omap_set_intr(s, i, 1);
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297 | c3d2689d | balrog | return;
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298 | c3d2689d | balrog | } |
299 | c3d2689d | balrog | return;
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300 | c3d2689d | balrog | |
301 | c3d2689d | balrog | default:
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302 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
303 | c3d2689d | balrog | } |
304 | c3d2689d | balrog | } |
305 | c3d2689d | balrog | |
306 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_inth_readfn[] = {
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307 | c3d2689d | balrog | omap_badwidth_read32, |
308 | c3d2689d | balrog | omap_badwidth_read32, |
309 | c3d2689d | balrog | omap_inth_read, |
310 | c3d2689d | balrog | }; |
311 | c3d2689d | balrog | |
312 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_inth_writefn[] = {
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313 | c3d2689d | balrog | omap_inth_write, |
314 | c3d2689d | balrog | omap_inth_write, |
315 | c3d2689d | balrog | omap_inth_write, |
316 | c3d2689d | balrog | }; |
317 | c3d2689d | balrog | |
318 | c3d2689d | balrog | static void omap_inth_reset(struct omap_intr_handler_s *s) |
319 | c3d2689d | balrog | { |
320 | c3d2689d | balrog | s->irqs = 0x00000000;
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321 | c3d2689d | balrog | s->mask = 0xffffffff;
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322 | c3d2689d | balrog | s->sens_edge = 0x00000000;
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323 | c3d2689d | balrog | s->fiq = 0x00000000;
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324 | c3d2689d | balrog | memset(s->priority, 0, sizeof(s->priority)); |
325 | c3d2689d | balrog | s->new_irq_agr = ~0;
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326 | c3d2689d | balrog | s->new_fiq_agr = ~0;
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327 | c3d2689d | balrog | s->sir_irq = 0;
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328 | c3d2689d | balrog | s->sir_fiq = 0;
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329 | c3d2689d | balrog | |
330 | c3d2689d | balrog | omap_inth_update(s); |
331 | c3d2689d | balrog | } |
332 | c3d2689d | balrog | |
333 | c3d2689d | balrog | struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
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334 | c3d2689d | balrog | unsigned long size, qemu_irq parent[2], omap_clk clk) |
335 | c3d2689d | balrog | { |
336 | c3d2689d | balrog | int iomemtype;
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337 | c3d2689d | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
338 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_intr_handler_s)); |
339 | c3d2689d | balrog | |
340 | c3d2689d | balrog | s->parent_pic = parent; |
341 | c3d2689d | balrog | s->base = base; |
342 | c3d2689d | balrog | s->pins = qemu_allocate_irqs(omap_set_intr, s, 32);
|
343 | c3d2689d | balrog | omap_inth_reset(s); |
344 | c3d2689d | balrog | |
345 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
|
346 | c3d2689d | balrog | omap_inth_writefn, s); |
347 | c3d2689d | balrog | cpu_register_physical_memory(s->base, size, iomemtype); |
348 | c3d2689d | balrog | |
349 | c3d2689d | balrog | return s;
|
350 | c3d2689d | balrog | } |
351 | c3d2689d | balrog | |
352 | c3d2689d | balrog | /* OMAP1 DMA module */
|
353 | c3d2689d | balrog | typedef enum { |
354 | c3d2689d | balrog | constant = 0,
|
355 | c3d2689d | balrog | post_incremented, |
356 | c3d2689d | balrog | single_index, |
357 | c3d2689d | balrog | double_index, |
358 | c3d2689d | balrog | } omap_dma_addressing_t; |
359 | c3d2689d | balrog | |
360 | c3d2689d | balrog | struct omap_dma_channel_s {
|
361 | c3d2689d | balrog | int burst[2]; |
362 | c3d2689d | balrog | int pack[2]; |
363 | c3d2689d | balrog | enum omap_dma_port port[2]; |
364 | c3d2689d | balrog | target_phys_addr_t addr[2];
|
365 | c3d2689d | balrog | omap_dma_addressing_t mode[2];
|
366 | c3d2689d | balrog | int data_type;
|
367 | c3d2689d | balrog | int end_prog;
|
368 | c3d2689d | balrog | int repeat;
|
369 | c3d2689d | balrog | int auto_init;
|
370 | c3d2689d | balrog | int priority;
|
371 | c3d2689d | balrog | int fs;
|
372 | c3d2689d | balrog | int sync;
|
373 | c3d2689d | balrog | int running;
|
374 | c3d2689d | balrog | int interrupts;
|
375 | c3d2689d | balrog | int status;
|
376 | c3d2689d | balrog | int signalled;
|
377 | c3d2689d | balrog | int post_sync;
|
378 | c3d2689d | balrog | int transfer;
|
379 | c3d2689d | balrog | uint16_t elements; |
380 | c3d2689d | balrog | uint16_t frames; |
381 | c3d2689d | balrog | uint16_t frame_index; |
382 | c3d2689d | balrog | uint16_t element_index; |
383 | c3d2689d | balrog | uint16_t cpc; |
384 | c3d2689d | balrog | |
385 | c3d2689d | balrog | struct omap_dma_reg_set_s {
|
386 | c3d2689d | balrog | target_phys_addr_t src, dest; |
387 | c3d2689d | balrog | int frame;
|
388 | c3d2689d | balrog | int element;
|
389 | c3d2689d | balrog | int frame_delta[2]; |
390 | c3d2689d | balrog | int elem_delta[2]; |
391 | c3d2689d | balrog | int frames;
|
392 | c3d2689d | balrog | int elements;
|
393 | c3d2689d | balrog | } active_set; |
394 | c3d2689d | balrog | }; |
395 | c3d2689d | balrog | |
396 | c3d2689d | balrog | struct omap_dma_s {
|
397 | c3d2689d | balrog | qemu_irq *ih; |
398 | c3d2689d | balrog | QEMUTimer *tm; |
399 | c3d2689d | balrog | struct omap_mpu_state_s *mpu;
|
400 | c3d2689d | balrog | target_phys_addr_t base; |
401 | c3d2689d | balrog | omap_clk clk; |
402 | c3d2689d | balrog | int64_t delay; |
403 | 1af2b62d | balrog | uint32_t drq; |
404 | c3d2689d | balrog | |
405 | c3d2689d | balrog | uint16_t gcr; |
406 | c3d2689d | balrog | int run_count;
|
407 | c3d2689d | balrog | |
408 | c3d2689d | balrog | int chans;
|
409 | c3d2689d | balrog | struct omap_dma_channel_s ch[16]; |
410 | c3d2689d | balrog | struct omap_dma_lcd_channel_s lcd_ch;
|
411 | c3d2689d | balrog | }; |
412 | c3d2689d | balrog | |
413 | c3d2689d | balrog | static void omap_dma_interrupts_update(struct omap_dma_s *s) |
414 | c3d2689d | balrog | { |
415 | c3d2689d | balrog | /* First three interrupts are shared between two channels each. */
|
416 | c3d2689d | balrog | qemu_set_irq(s->ih[OMAP_INT_DMA_CH0_6], |
417 | c3d2689d | balrog | (s->ch[0].status | s->ch[6].status) & 0x3f); |
418 | c3d2689d | balrog | qemu_set_irq(s->ih[OMAP_INT_DMA_CH1_7], |
419 | c3d2689d | balrog | (s->ch[1].status | s->ch[7].status) & 0x3f); |
420 | c3d2689d | balrog | qemu_set_irq(s->ih[OMAP_INT_DMA_CH2_8], |
421 | c3d2689d | balrog | (s->ch[2].status | s->ch[8].status) & 0x3f); |
422 | c3d2689d | balrog | qemu_set_irq(s->ih[OMAP_INT_DMA_CH3], |
423 | c3d2689d | balrog | (s->ch[3].status) & 0x3f); |
424 | c3d2689d | balrog | qemu_set_irq(s->ih[OMAP_INT_DMA_CH4], |
425 | c3d2689d | balrog | (s->ch[4].status) & 0x3f); |
426 | c3d2689d | balrog | qemu_set_irq(s->ih[OMAP_INT_DMA_CH5], |
427 | c3d2689d | balrog | (s->ch[5].status) & 0x3f); |
428 | c3d2689d | balrog | } |
429 | c3d2689d | balrog | |
430 | c3d2689d | balrog | static void omap_dma_channel_load(struct omap_dma_s *s, int ch) |
431 | c3d2689d | balrog | { |
432 | c3d2689d | balrog | struct omap_dma_reg_set_s *a = &s->ch[ch].active_set;
|
433 | c3d2689d | balrog | int i;
|
434 | c3d2689d | balrog | |
435 | c3d2689d | balrog | /*
|
436 | c3d2689d | balrog | * TODO: verify address ranges and alignment
|
437 | c3d2689d | balrog | * TODO: port endianness
|
438 | c3d2689d | balrog | */
|
439 | c3d2689d | balrog | |
440 | c3d2689d | balrog | a->src = s->ch[ch].addr[0];
|
441 | c3d2689d | balrog | a->dest = s->ch[ch].addr[1];
|
442 | c3d2689d | balrog | a->frames = s->ch[ch].frames; |
443 | c3d2689d | balrog | a->elements = s->ch[ch].elements; |
444 | c3d2689d | balrog | a->frame = 0;
|
445 | c3d2689d | balrog | a->element = 0;
|
446 | c3d2689d | balrog | |
447 | c3d2689d | balrog | if (unlikely(!s->ch[ch].elements || !s->ch[ch].frames)) {
|
448 | c3d2689d | balrog | printf("%s: bad DMA request\n", __FUNCTION__);
|
449 | c3d2689d | balrog | return;
|
450 | c3d2689d | balrog | } |
451 | c3d2689d | balrog | |
452 | c3d2689d | balrog | for (i = 0; i < 2; i ++) |
453 | c3d2689d | balrog | switch (s->ch[ch].mode[i]) {
|
454 | c3d2689d | balrog | case constant:
|
455 | c3d2689d | balrog | a->elem_delta[i] = 0;
|
456 | c3d2689d | balrog | a->frame_delta[i] = 0;
|
457 | c3d2689d | balrog | break;
|
458 | c3d2689d | balrog | case post_incremented:
|
459 | c3d2689d | balrog | a->elem_delta[i] = s->ch[ch].data_type; |
460 | c3d2689d | balrog | a->frame_delta[i] = 0;
|
461 | c3d2689d | balrog | break;
|
462 | c3d2689d | balrog | case single_index:
|
463 | c3d2689d | balrog | a->elem_delta[i] = s->ch[ch].data_type + |
464 | c3d2689d | balrog | s->ch[ch].element_index - 1;
|
465 | c3d2689d | balrog | if (s->ch[ch].element_index > 0x7fff) |
466 | c3d2689d | balrog | a->elem_delta[i] -= 0x10000;
|
467 | c3d2689d | balrog | a->frame_delta[i] = 0;
|
468 | c3d2689d | balrog | break;
|
469 | c3d2689d | balrog | case double_index:
|
470 | c3d2689d | balrog | a->elem_delta[i] = s->ch[ch].data_type + |
471 | c3d2689d | balrog | s->ch[ch].element_index - 1;
|
472 | c3d2689d | balrog | if (s->ch[ch].element_index > 0x7fff) |
473 | c3d2689d | balrog | a->elem_delta[i] -= 0x10000;
|
474 | c3d2689d | balrog | a->frame_delta[i] = s->ch[ch].frame_index - |
475 | c3d2689d | balrog | s->ch[ch].element_index; |
476 | c3d2689d | balrog | if (s->ch[ch].frame_index > 0x7fff) |
477 | c3d2689d | balrog | a->frame_delta[i] -= 0x10000;
|
478 | c3d2689d | balrog | break;
|
479 | c3d2689d | balrog | default:
|
480 | c3d2689d | balrog | break;
|
481 | c3d2689d | balrog | } |
482 | c3d2689d | balrog | } |
483 | c3d2689d | balrog | |
484 | c3d2689d | balrog | static inline void omap_dma_request_run(struct omap_dma_s *s, |
485 | c3d2689d | balrog | int channel, int request) |
486 | c3d2689d | balrog | { |
487 | c3d2689d | balrog | next_channel:
|
488 | c3d2689d | balrog | if (request > 0) |
489 | c3d2689d | balrog | for (; channel < 9; channel ++) |
490 | c3d2689d | balrog | if (s->ch[channel].sync == request && s->ch[channel].running)
|
491 | c3d2689d | balrog | break;
|
492 | c3d2689d | balrog | if (channel >= 9) |
493 | c3d2689d | balrog | return;
|
494 | c3d2689d | balrog | |
495 | c3d2689d | balrog | if (s->ch[channel].transfer) {
|
496 | c3d2689d | balrog | if (request > 0) { |
497 | c3d2689d | balrog | s->ch[channel ++].post_sync = request; |
498 | c3d2689d | balrog | goto next_channel;
|
499 | c3d2689d | balrog | } |
500 | c3d2689d | balrog | s->ch[channel].status |= 0x02; /* Synchronisation drop */ |
501 | c3d2689d | balrog | omap_dma_interrupts_update(s); |
502 | c3d2689d | balrog | return;
|
503 | c3d2689d | balrog | } |
504 | c3d2689d | balrog | |
505 | c3d2689d | balrog | if (!s->ch[channel].signalled)
|
506 | c3d2689d | balrog | s->run_count ++; |
507 | c3d2689d | balrog | s->ch[channel].signalled = 1;
|
508 | c3d2689d | balrog | |
509 | c3d2689d | balrog | if (request > 0) |
510 | c3d2689d | balrog | s->ch[channel].status |= 0x40; /* External request */ |
511 | c3d2689d | balrog | |
512 | 1af2b62d | balrog | if (s->delay && !qemu_timer_pending(s->tm))
|
513 | c3d2689d | balrog | qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
514 | c3d2689d | balrog | |
515 | c3d2689d | balrog | if (request > 0) { |
516 | c3d2689d | balrog | channel ++; |
517 | c3d2689d | balrog | goto next_channel;
|
518 | c3d2689d | balrog | } |
519 | c3d2689d | balrog | } |
520 | c3d2689d | balrog | |
521 | c3d2689d | balrog | static inline void omap_dma_request_stop(struct omap_dma_s *s, int channel) |
522 | c3d2689d | balrog | { |
523 | c3d2689d | balrog | if (s->ch[channel].signalled)
|
524 | c3d2689d | balrog | s->run_count --; |
525 | c3d2689d | balrog | s->ch[channel].signalled = 0;
|
526 | c3d2689d | balrog | |
527 | c3d2689d | balrog | if (!s->run_count)
|
528 | c3d2689d | balrog | qemu_del_timer(s->tm); |
529 | c3d2689d | balrog | } |
530 | c3d2689d | balrog | |
531 | c3d2689d | balrog | static void omap_dma_channel_run(struct omap_dma_s *s) |
532 | c3d2689d | balrog | { |
533 | c3d2689d | balrog | int ch;
|
534 | c3d2689d | balrog | uint16_t status; |
535 | c3d2689d | balrog | uint8_t value[4];
|
536 | c3d2689d | balrog | struct omap_dma_port_if_s *src_p, *dest_p;
|
537 | c3d2689d | balrog | struct omap_dma_reg_set_s *a;
|
538 | c3d2689d | balrog | |
539 | c3d2689d | balrog | for (ch = 0; ch < 9; ch ++) { |
540 | c3d2689d | balrog | a = &s->ch[ch].active_set; |
541 | c3d2689d | balrog | |
542 | c3d2689d | balrog | src_p = &s->mpu->port[s->ch[ch].port[0]];
|
543 | c3d2689d | balrog | dest_p = &s->mpu->port[s->ch[ch].port[1]];
|
544 | c3d2689d | balrog | if (s->ch[ch].signalled && (!src_p->addr_valid(s->mpu, a->src) ||
|
545 | c3d2689d | balrog | !dest_p->addr_valid(s->mpu, a->dest))) { |
546 | c3d2689d | balrog | #if 0
|
547 | c3d2689d | balrog | /* Bus time-out */
|
548 | c3d2689d | balrog | if (s->ch[ch].interrupts & 0x01)
|
549 | c3d2689d | balrog | s->ch[ch].status |= 0x01;
|
550 | c3d2689d | balrog | omap_dma_request_stop(s, ch);
|
551 | c3d2689d | balrog | continue;
|
552 | c3d2689d | balrog | #endif
|
553 | c3d2689d | balrog | printf("%s: Bus time-out in DMA%i operation\n", __FUNCTION__, ch);
|
554 | c3d2689d | balrog | } |
555 | c3d2689d | balrog | |
556 | c3d2689d | balrog | status = s->ch[ch].status; |
557 | c3d2689d | balrog | while (status == s->ch[ch].status && s->ch[ch].signalled) {
|
558 | c3d2689d | balrog | /* Transfer a single element */
|
559 | c3d2689d | balrog | s->ch[ch].transfer = 1;
|
560 | c3d2689d | balrog | cpu_physical_memory_read(a->src, value, s->ch[ch].data_type); |
561 | c3d2689d | balrog | cpu_physical_memory_write(a->dest, value, s->ch[ch].data_type); |
562 | c3d2689d | balrog | s->ch[ch].transfer = 0;
|
563 | c3d2689d | balrog | |
564 | c3d2689d | balrog | a->src += a->elem_delta[0];
|
565 | c3d2689d | balrog | a->dest += a->elem_delta[1];
|
566 | c3d2689d | balrog | a->element ++; |
567 | c3d2689d | balrog | |
568 | c3d2689d | balrog | /* Check interrupt conditions */
|
569 | c3d2689d | balrog | if (a->element == a->elements) {
|
570 | c3d2689d | balrog | a->element = 0;
|
571 | c3d2689d | balrog | a->src += a->frame_delta[0];
|
572 | c3d2689d | balrog | a->dest += a->frame_delta[1];
|
573 | c3d2689d | balrog | a->frame ++; |
574 | c3d2689d | balrog | |
575 | c3d2689d | balrog | if (a->frame == a->frames) {
|
576 | c3d2689d | balrog | if (!s->ch[ch].repeat || !s->ch[ch].auto_init)
|
577 | c3d2689d | balrog | s->ch[ch].running = 0;
|
578 | c3d2689d | balrog | |
579 | c3d2689d | balrog | if (s->ch[ch].auto_init &&
|
580 | c3d2689d | balrog | (s->ch[ch].repeat || |
581 | c3d2689d | balrog | s->ch[ch].end_prog)) |
582 | c3d2689d | balrog | omap_dma_channel_load(s, ch); |
583 | c3d2689d | balrog | |
584 | c3d2689d | balrog | if (s->ch[ch].interrupts & 0x20) |
585 | c3d2689d | balrog | s->ch[ch].status |= 0x20;
|
586 | c3d2689d | balrog | |
587 | c3d2689d | balrog | if (!s->ch[ch].sync)
|
588 | c3d2689d | balrog | omap_dma_request_stop(s, ch); |
589 | c3d2689d | balrog | } |
590 | c3d2689d | balrog | |
591 | c3d2689d | balrog | if (s->ch[ch].interrupts & 0x08) |
592 | c3d2689d | balrog | s->ch[ch].status |= 0x08;
|
593 | c3d2689d | balrog | |
594 | 1af2b62d | balrog | if (s->ch[ch].sync && s->ch[ch].fs &&
|
595 | 1af2b62d | balrog | !(s->drq & (1 << s->ch[ch].sync))) {
|
596 | c3d2689d | balrog | s->ch[ch].status &= ~0x40;
|
597 | c3d2689d | balrog | omap_dma_request_stop(s, ch); |
598 | c3d2689d | balrog | } |
599 | c3d2689d | balrog | } |
600 | c3d2689d | balrog | |
601 | c3d2689d | balrog | if (a->element == 1 && a->frame == a->frames - 1) |
602 | c3d2689d | balrog | if (s->ch[ch].interrupts & 0x10) |
603 | c3d2689d | balrog | s->ch[ch].status |= 0x10;
|
604 | c3d2689d | balrog | |
605 | c3d2689d | balrog | if (a->element == (a->elements >> 1)) |
606 | c3d2689d | balrog | if (s->ch[ch].interrupts & 0x04) |
607 | c3d2689d | balrog | s->ch[ch].status |= 0x04;
|
608 | c3d2689d | balrog | |
609 | 1af2b62d | balrog | if (s->ch[ch].sync && !s->ch[ch].fs &&
|
610 | 1af2b62d | balrog | !(s->drq & (1 << s->ch[ch].sync))) {
|
611 | c3d2689d | balrog | s->ch[ch].status &= ~0x40;
|
612 | c3d2689d | balrog | omap_dma_request_stop(s, ch); |
613 | c3d2689d | balrog | } |
614 | c3d2689d | balrog | |
615 | c3d2689d | balrog | /*
|
616 | c3d2689d | balrog | * Process requests made while the element was
|
617 | c3d2689d | balrog | * being transferred.
|
618 | c3d2689d | balrog | */
|
619 | c3d2689d | balrog | if (s->ch[ch].post_sync) {
|
620 | c3d2689d | balrog | omap_dma_request_run(s, 0, s->ch[ch].post_sync);
|
621 | c3d2689d | balrog | s->ch[ch].post_sync = 0;
|
622 | c3d2689d | balrog | } |
623 | c3d2689d | balrog | |
624 | c3d2689d | balrog | #if 0
|
625 | c3d2689d | balrog | break;
|
626 | c3d2689d | balrog | #endif
|
627 | c3d2689d | balrog | } |
628 | c3d2689d | balrog | |
629 | c3d2689d | balrog | s->ch[ch].cpc = a->dest & 0x0000ffff;
|
630 | c3d2689d | balrog | } |
631 | c3d2689d | balrog | |
632 | c3d2689d | balrog | omap_dma_interrupts_update(s); |
633 | c3d2689d | balrog | if (s->run_count && s->delay)
|
634 | c3d2689d | balrog | qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
635 | c3d2689d | balrog | } |
636 | c3d2689d | balrog | |
637 | c3d2689d | balrog | static int omap_dma_ch_reg_read(struct omap_dma_s *s, |
638 | c3d2689d | balrog | int ch, int reg, uint16_t *value) { |
639 | c3d2689d | balrog | switch (reg) {
|
640 | c3d2689d | balrog | case 0x00: /* SYS_DMA_CSDP_CH0 */ |
641 | c3d2689d | balrog | *value = (s->ch[ch].burst[1] << 14) | |
642 | c3d2689d | balrog | (s->ch[ch].pack[1] << 13) | |
643 | c3d2689d | balrog | (s->ch[ch].port[1] << 9) | |
644 | c3d2689d | balrog | (s->ch[ch].burst[0] << 7) | |
645 | c3d2689d | balrog | (s->ch[ch].pack[0] << 6) | |
646 | c3d2689d | balrog | (s->ch[ch].port[0] << 2) | |
647 | c3d2689d | balrog | (s->ch[ch].data_type >> 1);
|
648 | c3d2689d | balrog | break;
|
649 | c3d2689d | balrog | |
650 | c3d2689d | balrog | case 0x02: /* SYS_DMA_CCR_CH0 */ |
651 | c3d2689d | balrog | *value = (s->ch[ch].mode[1] << 14) | |
652 | c3d2689d | balrog | (s->ch[ch].mode[0] << 12) | |
653 | c3d2689d | balrog | (s->ch[ch].end_prog << 11) |
|
654 | c3d2689d | balrog | (s->ch[ch].repeat << 9) |
|
655 | c3d2689d | balrog | (s->ch[ch].auto_init << 8) |
|
656 | c3d2689d | balrog | (s->ch[ch].running << 7) |
|
657 | c3d2689d | balrog | (s->ch[ch].priority << 6) |
|
658 | c3d2689d | balrog | (s->ch[ch].fs << 5) | s->ch[ch].sync;
|
659 | c3d2689d | balrog | break;
|
660 | c3d2689d | balrog | |
661 | c3d2689d | balrog | case 0x04: /* SYS_DMA_CICR_CH0 */ |
662 | c3d2689d | balrog | *value = s->ch[ch].interrupts; |
663 | c3d2689d | balrog | break;
|
664 | c3d2689d | balrog | |
665 | c3d2689d | balrog | case 0x06: /* SYS_DMA_CSR_CH0 */ |
666 | c3d2689d | balrog | /* FIXME: shared CSR for channels sharing the interrupts */
|
667 | c3d2689d | balrog | *value = s->ch[ch].status; |
668 | c3d2689d | balrog | s->ch[ch].status &= 0x40;
|
669 | c3d2689d | balrog | omap_dma_interrupts_update(s); |
670 | c3d2689d | balrog | break;
|
671 | c3d2689d | balrog | |
672 | c3d2689d | balrog | case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
673 | c3d2689d | balrog | *value = s->ch[ch].addr[0] & 0x0000ffff; |
674 | c3d2689d | balrog | break;
|
675 | c3d2689d | balrog | |
676 | c3d2689d | balrog | case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
677 | c3d2689d | balrog | *value = s->ch[ch].addr[0] >> 16; |
678 | c3d2689d | balrog | break;
|
679 | c3d2689d | balrog | |
680 | c3d2689d | balrog | case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
681 | c3d2689d | balrog | *value = s->ch[ch].addr[1] & 0x0000ffff; |
682 | c3d2689d | balrog | break;
|
683 | c3d2689d | balrog | |
684 | c3d2689d | balrog | case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
685 | c3d2689d | balrog | *value = s->ch[ch].addr[1] >> 16; |
686 | c3d2689d | balrog | break;
|
687 | c3d2689d | balrog | |
688 | c3d2689d | balrog | case 0x10: /* SYS_DMA_CEN_CH0 */ |
689 | c3d2689d | balrog | *value = s->ch[ch].elements; |
690 | c3d2689d | balrog | break;
|
691 | c3d2689d | balrog | |
692 | c3d2689d | balrog | case 0x12: /* SYS_DMA_CFN_CH0 */ |
693 | c3d2689d | balrog | *value = s->ch[ch].frames; |
694 | c3d2689d | balrog | break;
|
695 | c3d2689d | balrog | |
696 | c3d2689d | balrog | case 0x14: /* SYS_DMA_CFI_CH0 */ |
697 | c3d2689d | balrog | *value = s->ch[ch].frame_index; |
698 | c3d2689d | balrog | break;
|
699 | c3d2689d | balrog | |
700 | c3d2689d | balrog | case 0x16: /* SYS_DMA_CEI_CH0 */ |
701 | c3d2689d | balrog | *value = s->ch[ch].element_index; |
702 | c3d2689d | balrog | break;
|
703 | c3d2689d | balrog | |
704 | c3d2689d | balrog | case 0x18: /* SYS_DMA_CPC_CH0 */ |
705 | c3d2689d | balrog | *value = s->ch[ch].cpc; |
706 | c3d2689d | balrog | break;
|
707 | c3d2689d | balrog | |
708 | c3d2689d | balrog | default:
|
709 | c3d2689d | balrog | return 1; |
710 | c3d2689d | balrog | } |
711 | c3d2689d | balrog | return 0; |
712 | c3d2689d | balrog | } |
713 | c3d2689d | balrog | |
714 | c3d2689d | balrog | static int omap_dma_ch_reg_write(struct omap_dma_s *s, |
715 | c3d2689d | balrog | int ch, int reg, uint16_t value) { |
716 | c3d2689d | balrog | switch (reg) {
|
717 | c3d2689d | balrog | case 0x00: /* SYS_DMA_CSDP_CH0 */ |
718 | c3d2689d | balrog | s->ch[ch].burst[1] = (value & 0xc000) >> 14; |
719 | c3d2689d | balrog | s->ch[ch].pack[1] = (value & 0x2000) >> 13; |
720 | c3d2689d | balrog | s->ch[ch].port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); |
721 | c3d2689d | balrog | s->ch[ch].burst[0] = (value & 0x0180) >> 7; |
722 | c3d2689d | balrog | s->ch[ch].pack[0] = (value & 0x0040) >> 6; |
723 | c3d2689d | balrog | s->ch[ch].port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); |
724 | c3d2689d | balrog | s->ch[ch].data_type = (1 << (value & 3)); |
725 | c3d2689d | balrog | if (s->ch[ch].port[0] >= omap_dma_port_last) |
726 | c3d2689d | balrog | printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
727 | c3d2689d | balrog | s->ch[ch].port[0]);
|
728 | c3d2689d | balrog | if (s->ch[ch].port[1] >= omap_dma_port_last) |
729 | c3d2689d | balrog | printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
730 | c3d2689d | balrog | s->ch[ch].port[1]);
|
731 | c3d2689d | balrog | if ((value & 3) == 3) |
732 | c3d2689d | balrog | printf("%s: bad data_type for DMA channel %i\n", __FUNCTION__, ch);
|
733 | c3d2689d | balrog | break;
|
734 | c3d2689d | balrog | |
735 | c3d2689d | balrog | case 0x02: /* SYS_DMA_CCR_CH0 */ |
736 | c3d2689d | balrog | s->ch[ch].mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); |
737 | c3d2689d | balrog | s->ch[ch].mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); |
738 | c3d2689d | balrog | s->ch[ch].end_prog = (value & 0x0800) >> 11; |
739 | c3d2689d | balrog | s->ch[ch].repeat = (value & 0x0200) >> 9; |
740 | c3d2689d | balrog | s->ch[ch].auto_init = (value & 0x0100) >> 8; |
741 | c3d2689d | balrog | s->ch[ch].priority = (value & 0x0040) >> 6; |
742 | c3d2689d | balrog | s->ch[ch].fs = (value & 0x0020) >> 5; |
743 | c3d2689d | balrog | s->ch[ch].sync = value & 0x001f;
|
744 | c3d2689d | balrog | if (value & 0x0080) { |
745 | c3d2689d | balrog | if (s->ch[ch].running) {
|
746 | c3d2689d | balrog | if (!s->ch[ch].signalled &&
|
747 | c3d2689d | balrog | s->ch[ch].auto_init && s->ch[ch].end_prog) |
748 | c3d2689d | balrog | omap_dma_channel_load(s, ch); |
749 | c3d2689d | balrog | } else {
|
750 | c3d2689d | balrog | s->ch[ch].running = 1;
|
751 | c3d2689d | balrog | omap_dma_channel_load(s, ch); |
752 | c3d2689d | balrog | } |
753 | 1af2b62d | balrog | if (!s->ch[ch].sync || (s->drq & (1 << s->ch[ch].sync))) |
754 | c3d2689d | balrog | omap_dma_request_run(s, ch, 0);
|
755 | c3d2689d | balrog | } else {
|
756 | c3d2689d | balrog | s->ch[ch].running = 0;
|
757 | c3d2689d | balrog | omap_dma_request_stop(s, ch); |
758 | c3d2689d | balrog | } |
759 | c3d2689d | balrog | break;
|
760 | c3d2689d | balrog | |
761 | c3d2689d | balrog | case 0x04: /* SYS_DMA_CICR_CH0 */ |
762 | c3d2689d | balrog | s->ch[ch].interrupts = value & 0x003f;
|
763 | c3d2689d | balrog | break;
|
764 | c3d2689d | balrog | |
765 | c3d2689d | balrog | case 0x06: /* SYS_DMA_CSR_CH0 */ |
766 | c3d2689d | balrog | return 1; |
767 | c3d2689d | balrog | |
768 | c3d2689d | balrog | case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
769 | c3d2689d | balrog | s->ch[ch].addr[0] &= 0xffff0000; |
770 | c3d2689d | balrog | s->ch[ch].addr[0] |= value;
|
771 | c3d2689d | balrog | break;
|
772 | c3d2689d | balrog | |
773 | c3d2689d | balrog | case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
774 | c3d2689d | balrog | s->ch[ch].addr[0] &= 0x0000ffff; |
775 | c3d2689d | balrog | s->ch[ch].addr[0] |= value << 16; |
776 | c3d2689d | balrog | break;
|
777 | c3d2689d | balrog | |
778 | c3d2689d | balrog | case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
779 | c3d2689d | balrog | s->ch[ch].addr[1] &= 0xffff0000; |
780 | c3d2689d | balrog | s->ch[ch].addr[1] |= value;
|
781 | c3d2689d | balrog | break;
|
782 | c3d2689d | balrog | |
783 | c3d2689d | balrog | case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
784 | c3d2689d | balrog | s->ch[ch].addr[1] &= 0x0000ffff; |
785 | c3d2689d | balrog | s->ch[ch].addr[1] |= value << 16; |
786 | c3d2689d | balrog | break;
|
787 | c3d2689d | balrog | |
788 | c3d2689d | balrog | case 0x10: /* SYS_DMA_CEN_CH0 */ |
789 | c3d2689d | balrog | s->ch[ch].elements = value & 0xffff;
|
790 | c3d2689d | balrog | break;
|
791 | c3d2689d | balrog | |
792 | c3d2689d | balrog | case 0x12: /* SYS_DMA_CFN_CH0 */ |
793 | c3d2689d | balrog | s->ch[ch].frames = value & 0xffff;
|
794 | c3d2689d | balrog | break;
|
795 | c3d2689d | balrog | |
796 | c3d2689d | balrog | case 0x14: /* SYS_DMA_CFI_CH0 */ |
797 | c3d2689d | balrog | s->ch[ch].frame_index = value & 0xffff;
|
798 | c3d2689d | balrog | break;
|
799 | c3d2689d | balrog | |
800 | c3d2689d | balrog | case 0x16: /* SYS_DMA_CEI_CH0 */ |
801 | c3d2689d | balrog | s->ch[ch].element_index = value & 0xffff;
|
802 | c3d2689d | balrog | break;
|
803 | c3d2689d | balrog | |
804 | c3d2689d | balrog | case 0x18: /* SYS_DMA_CPC_CH0 */ |
805 | c3d2689d | balrog | return 1; |
806 | c3d2689d | balrog | |
807 | c3d2689d | balrog | default:
|
808 | c3d2689d | balrog | OMAP_BAD_REG((unsigned long) reg); |
809 | c3d2689d | balrog | } |
810 | c3d2689d | balrog | return 0; |
811 | c3d2689d | balrog | } |
812 | c3d2689d | balrog | |
813 | c3d2689d | balrog | static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) |
814 | c3d2689d | balrog | { |
815 | c3d2689d | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
816 | c3d2689d | balrog | int i, reg, ch, offset = addr - s->base;
|
817 | c3d2689d | balrog | uint16_t ret; |
818 | c3d2689d | balrog | |
819 | c3d2689d | balrog | switch (offset) {
|
820 | c3d2689d | balrog | case 0x000 ... 0x2fe: |
821 | c3d2689d | balrog | reg = offset & 0x3f;
|
822 | c3d2689d | balrog | ch = (offset >> 6) & 0x0f; |
823 | c3d2689d | balrog | if (omap_dma_ch_reg_read(s, ch, reg, &ret))
|
824 | c3d2689d | balrog | break;
|
825 | c3d2689d | balrog | return ret;
|
826 | c3d2689d | balrog | |
827 | c3d2689d | balrog | case 0x300: /* SYS_DMA_LCD_CTRL */ |
828 | c3d2689d | balrog | i = s->lcd_ch.condition; |
829 | c3d2689d | balrog | s->lcd_ch.condition = 0;
|
830 | c3d2689d | balrog | qemu_irq_lower(s->lcd_ch.irq); |
831 | c3d2689d | balrog | return ((s->lcd_ch.src == imif) << 6) | (i << 3) | |
832 | c3d2689d | balrog | (s->lcd_ch.interrupts << 1) | s->lcd_ch.dual;
|
833 | c3d2689d | balrog | |
834 | c3d2689d | balrog | case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
835 | c3d2689d | balrog | return s->lcd_ch.src_f1_top & 0xffff; |
836 | c3d2689d | balrog | |
837 | c3d2689d | balrog | case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
838 | c3d2689d | balrog | return s->lcd_ch.src_f1_top >> 16; |
839 | c3d2689d | balrog | |
840 | c3d2689d | balrog | case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
841 | c3d2689d | balrog | return s->lcd_ch.src_f1_bottom & 0xffff; |
842 | c3d2689d | balrog | |
843 | c3d2689d | balrog | case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
844 | c3d2689d | balrog | return s->lcd_ch.src_f1_bottom >> 16; |
845 | c3d2689d | balrog | |
846 | c3d2689d | balrog | case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
847 | c3d2689d | balrog | return s->lcd_ch.src_f2_top & 0xffff; |
848 | c3d2689d | balrog | |
849 | c3d2689d | balrog | case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
850 | c3d2689d | balrog | return s->lcd_ch.src_f2_top >> 16; |
851 | c3d2689d | balrog | |
852 | c3d2689d | balrog | case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
853 | c3d2689d | balrog | return s->lcd_ch.src_f2_bottom & 0xffff; |
854 | c3d2689d | balrog | |
855 | c3d2689d | balrog | case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
856 | c3d2689d | balrog | return s->lcd_ch.src_f2_bottom >> 16; |
857 | c3d2689d | balrog | |
858 | c3d2689d | balrog | case 0x400: /* SYS_DMA_GCR */ |
859 | c3d2689d | balrog | return s->gcr;
|
860 | c3d2689d | balrog | } |
861 | c3d2689d | balrog | |
862 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
863 | c3d2689d | balrog | return 0; |
864 | c3d2689d | balrog | } |
865 | c3d2689d | balrog | |
866 | c3d2689d | balrog | static void omap_dma_write(void *opaque, target_phys_addr_t addr, |
867 | c3d2689d | balrog | uint32_t value) |
868 | c3d2689d | balrog | { |
869 | c3d2689d | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
870 | c3d2689d | balrog | int reg, ch, offset = addr - s->base;
|
871 | c3d2689d | balrog | |
872 | c3d2689d | balrog | switch (offset) {
|
873 | c3d2689d | balrog | case 0x000 ... 0x2fe: |
874 | c3d2689d | balrog | reg = offset & 0x3f;
|
875 | c3d2689d | balrog | ch = (offset >> 6) & 0x0f; |
876 | c3d2689d | balrog | if (omap_dma_ch_reg_write(s, ch, reg, value))
|
877 | c3d2689d | balrog | OMAP_RO_REG(addr); |
878 | c3d2689d | balrog | break;
|
879 | c3d2689d | balrog | |
880 | c3d2689d | balrog | case 0x300: /* SYS_DMA_LCD_CTRL */ |
881 | c3d2689d | balrog | s->lcd_ch.src = (value & 0x40) ? imif : emiff;
|
882 | c3d2689d | balrog | s->lcd_ch.condition = 0;
|
883 | c3d2689d | balrog | /* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
884 | c3d2689d | balrog | s->lcd_ch.interrupts = (value >> 1) & 1; |
885 | c3d2689d | balrog | s->lcd_ch.dual = value & 1;
|
886 | c3d2689d | balrog | break;
|
887 | c3d2689d | balrog | |
888 | c3d2689d | balrog | case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
889 | c3d2689d | balrog | s->lcd_ch.src_f1_top &= 0xffff0000;
|
890 | c3d2689d | balrog | s->lcd_ch.src_f1_top |= 0x0000ffff & value;
|
891 | c3d2689d | balrog | break;
|
892 | c3d2689d | balrog | |
893 | c3d2689d | balrog | case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
894 | c3d2689d | balrog | s->lcd_ch.src_f1_top &= 0x0000ffff;
|
895 | c3d2689d | balrog | s->lcd_ch.src_f1_top |= value << 16;
|
896 | c3d2689d | balrog | break;
|
897 | c3d2689d | balrog | |
898 | c3d2689d | balrog | case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
899 | c3d2689d | balrog | s->lcd_ch.src_f1_bottom &= 0xffff0000;
|
900 | c3d2689d | balrog | s->lcd_ch.src_f1_bottom |= 0x0000ffff & value;
|
901 | c3d2689d | balrog | break;
|
902 | c3d2689d | balrog | |
903 | c3d2689d | balrog | case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
904 | c3d2689d | balrog | s->lcd_ch.src_f1_bottom &= 0x0000ffff;
|
905 | c3d2689d | balrog | s->lcd_ch.src_f1_bottom |= value << 16;
|
906 | c3d2689d | balrog | break;
|
907 | c3d2689d | balrog | |
908 | c3d2689d | balrog | case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
909 | c3d2689d | balrog | s->lcd_ch.src_f2_top &= 0xffff0000;
|
910 | c3d2689d | balrog | s->lcd_ch.src_f2_top |= 0x0000ffff & value;
|
911 | c3d2689d | balrog | break;
|
912 | c3d2689d | balrog | |
913 | c3d2689d | balrog | case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
914 | c3d2689d | balrog | s->lcd_ch.src_f2_top &= 0x0000ffff;
|
915 | c3d2689d | balrog | s->lcd_ch.src_f2_top |= value << 16;
|
916 | c3d2689d | balrog | break;
|
917 | c3d2689d | balrog | |
918 | c3d2689d | balrog | case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
919 | c3d2689d | balrog | s->lcd_ch.src_f2_bottom &= 0xffff0000;
|
920 | c3d2689d | balrog | s->lcd_ch.src_f2_bottom |= 0x0000ffff & value;
|
921 | c3d2689d | balrog | break;
|
922 | c3d2689d | balrog | |
923 | c3d2689d | balrog | case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
924 | c3d2689d | balrog | s->lcd_ch.src_f2_bottom &= 0x0000ffff;
|
925 | c3d2689d | balrog | s->lcd_ch.src_f2_bottom |= value << 16;
|
926 | c3d2689d | balrog | break;
|
927 | c3d2689d | balrog | |
928 | c3d2689d | balrog | case 0x400: /* SYS_DMA_GCR */ |
929 | c3d2689d | balrog | s->gcr = value & 0x000c;
|
930 | c3d2689d | balrog | break;
|
931 | c3d2689d | balrog | |
932 | c3d2689d | balrog | default:
|
933 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
934 | c3d2689d | balrog | } |
935 | c3d2689d | balrog | } |
936 | c3d2689d | balrog | |
937 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_dma_readfn[] = {
|
938 | c3d2689d | balrog | omap_badwidth_read16, |
939 | c3d2689d | balrog | omap_dma_read, |
940 | c3d2689d | balrog | omap_badwidth_read16, |
941 | c3d2689d | balrog | }; |
942 | c3d2689d | balrog | |
943 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_dma_writefn[] = {
|
944 | c3d2689d | balrog | omap_badwidth_write16, |
945 | c3d2689d | balrog | omap_dma_write, |
946 | c3d2689d | balrog | omap_badwidth_write16, |
947 | c3d2689d | balrog | }; |
948 | c3d2689d | balrog | |
949 | c3d2689d | balrog | static void omap_dma_request(void *opaque, int drq, int req) |
950 | c3d2689d | balrog | { |
951 | c3d2689d | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
952 | 1af2b62d | balrog | /* The request pins are level triggered. */
|
953 | 1af2b62d | balrog | if (req) {
|
954 | 1af2b62d | balrog | if (~s->drq & (1 << drq)) { |
955 | 1af2b62d | balrog | s->drq |= 1 << drq;
|
956 | 1af2b62d | balrog | omap_dma_request_run(s, 0, drq);
|
957 | 1af2b62d | balrog | } |
958 | 1af2b62d | balrog | } else
|
959 | 1af2b62d | balrog | s->drq &= ~(1 << drq);
|
960 | c3d2689d | balrog | } |
961 | c3d2689d | balrog | |
962 | c3d2689d | balrog | static void omap_dma_clk_update(void *opaque, int line, int on) |
963 | c3d2689d | balrog | { |
964 | c3d2689d | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
965 | c3d2689d | balrog | |
966 | c3d2689d | balrog | if (on) {
|
967 | c3d2689d | balrog | s->delay = ticks_per_sec >> 5;
|
968 | c3d2689d | balrog | if (s->run_count)
|
969 | c3d2689d | balrog | qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
970 | c3d2689d | balrog | } else {
|
971 | c3d2689d | balrog | s->delay = 0;
|
972 | c3d2689d | balrog | qemu_del_timer(s->tm); |
973 | c3d2689d | balrog | } |
974 | c3d2689d | balrog | } |
975 | c3d2689d | balrog | |
976 | c3d2689d | balrog | static void omap_dma_reset(struct omap_dma_s *s) |
977 | c3d2689d | balrog | { |
978 | c3d2689d | balrog | int i;
|
979 | c3d2689d | balrog | |
980 | c3d2689d | balrog | qemu_del_timer(s->tm); |
981 | c3d2689d | balrog | s->gcr = 0x0004;
|
982 | 1af2b62d | balrog | s->drq = 0x00000000;
|
983 | c3d2689d | balrog | s->run_count = 0;
|
984 | c3d2689d | balrog | s->lcd_ch.src = emiff; |
985 | c3d2689d | balrog | s->lcd_ch.condition = 0;
|
986 | c3d2689d | balrog | s->lcd_ch.interrupts = 0;
|
987 | c3d2689d | balrog | s->lcd_ch.dual = 0;
|
988 | c3d2689d | balrog | memset(s->ch, 0, sizeof(s->ch)); |
989 | c3d2689d | balrog | for (i = 0; i < s->chans; i ++) |
990 | c3d2689d | balrog | s->ch[i].interrupts = 0x0003;
|
991 | c3d2689d | balrog | } |
992 | c3d2689d | balrog | |
993 | c3d2689d | balrog | struct omap_dma_s *omap_dma_init(target_phys_addr_t base,
|
994 | c3d2689d | balrog | qemu_irq pic[], struct omap_mpu_state_s *mpu, omap_clk clk)
|
995 | c3d2689d | balrog | { |
996 | c3d2689d | balrog | int iomemtype;
|
997 | c3d2689d | balrog | struct omap_dma_s *s = (struct omap_dma_s *) |
998 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_dma_s)); |
999 | c3d2689d | balrog | |
1000 | c3d2689d | balrog | s->ih = pic; |
1001 | c3d2689d | balrog | s->base = base; |
1002 | c3d2689d | balrog | s->chans = 9;
|
1003 | c3d2689d | balrog | s->mpu = mpu; |
1004 | c3d2689d | balrog | s->clk = clk; |
1005 | c3d2689d | balrog | s->lcd_ch.irq = pic[OMAP_INT_DMA_LCD]; |
1006 | c3d2689d | balrog | s->lcd_ch.mpu = mpu; |
1007 | c3d2689d | balrog | s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s); |
1008 | c3d2689d | balrog | omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
1009 | c3d2689d | balrog | mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
|
1010 | c3d2689d | balrog | omap_dma_reset(s); |
1011 | 1af2b62d | balrog | omap_dma_clk_update(s, 0, 1); |
1012 | c3d2689d | balrog | |
1013 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
|
1014 | c3d2689d | balrog | omap_dma_writefn, s); |
1015 | c3d2689d | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
1016 | c3d2689d | balrog | |
1017 | c3d2689d | balrog | return s;
|
1018 | c3d2689d | balrog | } |
1019 | c3d2689d | balrog | |
1020 | c3d2689d | balrog | /* DMA ports */
|
1021 | c3d2689d | balrog | int omap_validate_emiff_addr(struct omap_mpu_state_s *s, |
1022 | c3d2689d | balrog | target_phys_addr_t addr) |
1023 | c3d2689d | balrog | { |
1024 | c3d2689d | balrog | return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
|
1025 | c3d2689d | balrog | } |
1026 | c3d2689d | balrog | |
1027 | c3d2689d | balrog | int omap_validate_emifs_addr(struct omap_mpu_state_s *s, |
1028 | c3d2689d | balrog | target_phys_addr_t addr) |
1029 | c3d2689d | balrog | { |
1030 | c3d2689d | balrog | return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
|
1031 | c3d2689d | balrog | } |
1032 | c3d2689d | balrog | |
1033 | c3d2689d | balrog | int omap_validate_imif_addr(struct omap_mpu_state_s *s, |
1034 | c3d2689d | balrog | target_phys_addr_t addr) |
1035 | c3d2689d | balrog | { |
1036 | c3d2689d | balrog | return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
|
1037 | c3d2689d | balrog | } |
1038 | c3d2689d | balrog | |
1039 | c3d2689d | balrog | int omap_validate_tipb_addr(struct omap_mpu_state_s *s, |
1040 | c3d2689d | balrog | target_phys_addr_t addr) |
1041 | c3d2689d | balrog | { |
1042 | c3d2689d | balrog | return addr >= 0xfffb0000 && addr < 0xffff0000; |
1043 | c3d2689d | balrog | } |
1044 | c3d2689d | balrog | |
1045 | c3d2689d | balrog | int omap_validate_local_addr(struct omap_mpu_state_s *s, |
1046 | c3d2689d | balrog | target_phys_addr_t addr) |
1047 | c3d2689d | balrog | { |
1048 | c3d2689d | balrog | return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000; |
1049 | c3d2689d | balrog | } |
1050 | c3d2689d | balrog | |
1051 | c3d2689d | balrog | int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, |
1052 | c3d2689d | balrog | target_phys_addr_t addr) |
1053 | c3d2689d | balrog | { |
1054 | c3d2689d | balrog | return addr >= 0xe1010000 && addr < 0xe1020004; |
1055 | c3d2689d | balrog | } |
1056 | c3d2689d | balrog | |
1057 | c3d2689d | balrog | /* MPU OS timers */
|
1058 | c3d2689d | balrog | struct omap_mpu_timer_s {
|
1059 | c3d2689d | balrog | qemu_irq irq; |
1060 | c3d2689d | balrog | omap_clk clk; |
1061 | c3d2689d | balrog | target_phys_addr_t base; |
1062 | c3d2689d | balrog | uint32_t val; |
1063 | c3d2689d | balrog | int64_t time; |
1064 | c3d2689d | balrog | QEMUTimer *timer; |
1065 | c3d2689d | balrog | int64_t rate; |
1066 | c3d2689d | balrog | int it_ena;
|
1067 | c3d2689d | balrog | |
1068 | c3d2689d | balrog | int enable;
|
1069 | c3d2689d | balrog | int ptv;
|
1070 | c3d2689d | balrog | int ar;
|
1071 | c3d2689d | balrog | int st;
|
1072 | c3d2689d | balrog | uint32_t reset_val; |
1073 | c3d2689d | balrog | }; |
1074 | c3d2689d | balrog | |
1075 | c3d2689d | balrog | static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) |
1076 | c3d2689d | balrog | { |
1077 | c3d2689d | balrog | uint64_t distance = qemu_get_clock(vm_clock) - timer->time; |
1078 | c3d2689d | balrog | |
1079 | c3d2689d | balrog | if (timer->st && timer->enable && timer->rate)
|
1080 | c3d2689d | balrog | return timer->val - muldiv64(distance >> (timer->ptv + 1), |
1081 | c3d2689d | balrog | timer->rate, ticks_per_sec); |
1082 | c3d2689d | balrog | else
|
1083 | c3d2689d | balrog | return timer->val;
|
1084 | c3d2689d | balrog | } |
1085 | c3d2689d | balrog | |
1086 | c3d2689d | balrog | static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) |
1087 | c3d2689d | balrog | { |
1088 | c3d2689d | balrog | timer->val = omap_timer_read(timer); |
1089 | c3d2689d | balrog | timer->time = qemu_get_clock(vm_clock); |
1090 | c3d2689d | balrog | } |
1091 | c3d2689d | balrog | |
1092 | c3d2689d | balrog | static inline void omap_timer_update(struct omap_mpu_timer_s *timer) |
1093 | c3d2689d | balrog | { |
1094 | c3d2689d | balrog | int64_t expires; |
1095 | c3d2689d | balrog | |
1096 | c3d2689d | balrog | if (timer->enable && timer->st && timer->rate) {
|
1097 | c3d2689d | balrog | timer->val = timer->reset_val; /* Should skip this on clk enable */
|
1098 | c3d2689d | balrog | expires = timer->time + muldiv64(timer->val << (timer->ptv + 1),
|
1099 | c3d2689d | balrog | ticks_per_sec, timer->rate); |
1100 | c3d2689d | balrog | qemu_mod_timer(timer->timer, expires); |
1101 | c3d2689d | balrog | } else
|
1102 | c3d2689d | balrog | qemu_del_timer(timer->timer); |
1103 | c3d2689d | balrog | } |
1104 | c3d2689d | balrog | |
1105 | c3d2689d | balrog | static void omap_timer_tick(void *opaque) |
1106 | c3d2689d | balrog | { |
1107 | c3d2689d | balrog | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
1108 | c3d2689d | balrog | omap_timer_sync(timer); |
1109 | c3d2689d | balrog | |
1110 | c3d2689d | balrog | if (!timer->ar) {
|
1111 | c3d2689d | balrog | timer->val = 0;
|
1112 | c3d2689d | balrog | timer->st = 0;
|
1113 | c3d2689d | balrog | } |
1114 | c3d2689d | balrog | |
1115 | c3d2689d | balrog | if (timer->it_ena)
|
1116 | c3d2689d | balrog | qemu_irq_raise(timer->irq); |
1117 | c3d2689d | balrog | omap_timer_update(timer); |
1118 | c3d2689d | balrog | } |
1119 | c3d2689d | balrog | |
1120 | c3d2689d | balrog | static void omap_timer_clk_update(void *opaque, int line, int on) |
1121 | c3d2689d | balrog | { |
1122 | c3d2689d | balrog | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
1123 | c3d2689d | balrog | |
1124 | c3d2689d | balrog | omap_timer_sync(timer); |
1125 | c3d2689d | balrog | timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
|
1126 | c3d2689d | balrog | omap_timer_update(timer); |
1127 | c3d2689d | balrog | } |
1128 | c3d2689d | balrog | |
1129 | c3d2689d | balrog | static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) |
1130 | c3d2689d | balrog | { |
1131 | c3d2689d | balrog | omap_clk_adduser(timer->clk, |
1132 | c3d2689d | balrog | qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]); |
1133 | c3d2689d | balrog | timer->rate = omap_clk_getrate(timer->clk); |
1134 | c3d2689d | balrog | } |
1135 | c3d2689d | balrog | |
1136 | c3d2689d | balrog | static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr) |
1137 | c3d2689d | balrog | { |
1138 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
1139 | c3d2689d | balrog | int offset = addr - s->base;
|
1140 | c3d2689d | balrog | |
1141 | c3d2689d | balrog | switch (offset) {
|
1142 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
1143 | c3d2689d | balrog | return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; |
1144 | c3d2689d | balrog | |
1145 | c3d2689d | balrog | case 0x04: /* LOAD_TIM */ |
1146 | c3d2689d | balrog | break;
|
1147 | c3d2689d | balrog | |
1148 | c3d2689d | balrog | case 0x08: /* READ_TIM */ |
1149 | c3d2689d | balrog | return omap_timer_read(s);
|
1150 | c3d2689d | balrog | } |
1151 | c3d2689d | balrog | |
1152 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1153 | c3d2689d | balrog | return 0; |
1154 | c3d2689d | balrog | } |
1155 | c3d2689d | balrog | |
1156 | c3d2689d | balrog | static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr, |
1157 | c3d2689d | balrog | uint32_t value) |
1158 | c3d2689d | balrog | { |
1159 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
1160 | c3d2689d | balrog | int offset = addr - s->base;
|
1161 | c3d2689d | balrog | |
1162 | c3d2689d | balrog | switch (offset) {
|
1163 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
1164 | c3d2689d | balrog | omap_timer_sync(s); |
1165 | c3d2689d | balrog | s->enable = (value >> 5) & 1; |
1166 | c3d2689d | balrog | s->ptv = (value >> 2) & 7; |
1167 | c3d2689d | balrog | s->ar = (value >> 1) & 1; |
1168 | c3d2689d | balrog | s->st = value & 1;
|
1169 | c3d2689d | balrog | omap_timer_update(s); |
1170 | c3d2689d | balrog | return;
|
1171 | c3d2689d | balrog | |
1172 | c3d2689d | balrog | case 0x04: /* LOAD_TIM */ |
1173 | c3d2689d | balrog | s->reset_val = value; |
1174 | c3d2689d | balrog | return;
|
1175 | c3d2689d | balrog | |
1176 | c3d2689d | balrog | case 0x08: /* READ_TIM */ |
1177 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1178 | c3d2689d | balrog | break;
|
1179 | c3d2689d | balrog | |
1180 | c3d2689d | balrog | default:
|
1181 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1182 | c3d2689d | balrog | } |
1183 | c3d2689d | balrog | } |
1184 | c3d2689d | balrog | |
1185 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
|
1186 | c3d2689d | balrog | omap_badwidth_read32, |
1187 | c3d2689d | balrog | omap_badwidth_read32, |
1188 | c3d2689d | balrog | omap_mpu_timer_read, |
1189 | c3d2689d | balrog | }; |
1190 | c3d2689d | balrog | |
1191 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
|
1192 | c3d2689d | balrog | omap_badwidth_write32, |
1193 | c3d2689d | balrog | omap_badwidth_write32, |
1194 | c3d2689d | balrog | omap_mpu_timer_write, |
1195 | c3d2689d | balrog | }; |
1196 | c3d2689d | balrog | |
1197 | c3d2689d | balrog | static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) |
1198 | c3d2689d | balrog | { |
1199 | c3d2689d | balrog | qemu_del_timer(s->timer); |
1200 | c3d2689d | balrog | s->enable = 0;
|
1201 | c3d2689d | balrog | s->reset_val = 31337;
|
1202 | c3d2689d | balrog | s->val = 0;
|
1203 | c3d2689d | balrog | s->ptv = 0;
|
1204 | c3d2689d | balrog | s->ar = 0;
|
1205 | c3d2689d | balrog | s->st = 0;
|
1206 | c3d2689d | balrog | s->it_ena = 1;
|
1207 | c3d2689d | balrog | } |
1208 | c3d2689d | balrog | |
1209 | c3d2689d | balrog | struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
|
1210 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
1211 | c3d2689d | balrog | { |
1212 | c3d2689d | balrog | int iomemtype;
|
1213 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) |
1214 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_mpu_timer_s)); |
1215 | c3d2689d | balrog | |
1216 | c3d2689d | balrog | s->irq = irq; |
1217 | c3d2689d | balrog | s->clk = clk; |
1218 | c3d2689d | balrog | s->base = base; |
1219 | c3d2689d | balrog | s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s); |
1220 | c3d2689d | balrog | omap_mpu_timer_reset(s); |
1221 | c3d2689d | balrog | omap_timer_clk_setup(s); |
1222 | c3d2689d | balrog | |
1223 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
|
1224 | c3d2689d | balrog | omap_mpu_timer_writefn, s); |
1225 | c3d2689d | balrog | cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
1226 | c3d2689d | balrog | |
1227 | c3d2689d | balrog | return s;
|
1228 | c3d2689d | balrog | } |
1229 | c3d2689d | balrog | |
1230 | c3d2689d | balrog | /* Watchdog timer */
|
1231 | c3d2689d | balrog | struct omap_watchdog_timer_s {
|
1232 | c3d2689d | balrog | struct omap_mpu_timer_s timer;
|
1233 | c3d2689d | balrog | uint8_t last_wr; |
1234 | c3d2689d | balrog | int mode;
|
1235 | c3d2689d | balrog | int free;
|
1236 | c3d2689d | balrog | int reset;
|
1237 | c3d2689d | balrog | }; |
1238 | c3d2689d | balrog | |
1239 | c3d2689d | balrog | static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr) |
1240 | c3d2689d | balrog | { |
1241 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
1242 | c3d2689d | balrog | int offset = addr - s->timer.base;
|
1243 | c3d2689d | balrog | |
1244 | c3d2689d | balrog | switch (offset) {
|
1245 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
1246 | c3d2689d | balrog | return (s->timer.ptv << 9) | (s->timer.ar << 8) | |
1247 | c3d2689d | balrog | (s->timer.st << 7) | (s->free << 1); |
1248 | c3d2689d | balrog | |
1249 | c3d2689d | balrog | case 0x04: /* READ_TIMER */ |
1250 | c3d2689d | balrog | return omap_timer_read(&s->timer);
|
1251 | c3d2689d | balrog | |
1252 | c3d2689d | balrog | case 0x08: /* TIMER_MODE */ |
1253 | c3d2689d | balrog | return s->mode << 15; |
1254 | c3d2689d | balrog | } |
1255 | c3d2689d | balrog | |
1256 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1257 | c3d2689d | balrog | return 0; |
1258 | c3d2689d | balrog | } |
1259 | c3d2689d | balrog | |
1260 | c3d2689d | balrog | static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr, |
1261 | c3d2689d | balrog | uint32_t value) |
1262 | c3d2689d | balrog | { |
1263 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
1264 | c3d2689d | balrog | int offset = addr - s->timer.base;
|
1265 | c3d2689d | balrog | |
1266 | c3d2689d | balrog | switch (offset) {
|
1267 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
1268 | c3d2689d | balrog | omap_timer_sync(&s->timer); |
1269 | c3d2689d | balrog | s->timer.ptv = (value >> 9) & 7; |
1270 | c3d2689d | balrog | s->timer.ar = (value >> 8) & 1; |
1271 | c3d2689d | balrog | s->timer.st = (value >> 7) & 1; |
1272 | c3d2689d | balrog | s->free = (value >> 1) & 1; |
1273 | c3d2689d | balrog | omap_timer_update(&s->timer); |
1274 | c3d2689d | balrog | break;
|
1275 | c3d2689d | balrog | |
1276 | c3d2689d | balrog | case 0x04: /* LOAD_TIMER */ |
1277 | c3d2689d | balrog | s->timer.reset_val = value & 0xffff;
|
1278 | c3d2689d | balrog | break;
|
1279 | c3d2689d | balrog | |
1280 | c3d2689d | balrog | case 0x08: /* TIMER_MODE */ |
1281 | c3d2689d | balrog | if (!s->mode && ((value >> 15) & 1)) |
1282 | c3d2689d | balrog | omap_clk_get(s->timer.clk); |
1283 | c3d2689d | balrog | s->mode |= (value >> 15) & 1; |
1284 | c3d2689d | balrog | if (s->last_wr == 0xf5) { |
1285 | c3d2689d | balrog | if ((value & 0xff) == 0xa0) { |
1286 | c3d2689d | balrog | s->mode = 0;
|
1287 | c3d2689d | balrog | omap_clk_put(s->timer.clk); |
1288 | c3d2689d | balrog | } else {
|
1289 | c3d2689d | balrog | /* XXX: on T|E hardware somehow this has no effect,
|
1290 | c3d2689d | balrog | * on Zire 71 it works as specified. */
|
1291 | c3d2689d | balrog | s->reset = 1;
|
1292 | c3d2689d | balrog | qemu_system_reset_request(); |
1293 | c3d2689d | balrog | } |
1294 | c3d2689d | balrog | } |
1295 | c3d2689d | balrog | s->last_wr = value & 0xff;
|
1296 | c3d2689d | balrog | break;
|
1297 | c3d2689d | balrog | |
1298 | c3d2689d | balrog | default:
|
1299 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1300 | c3d2689d | balrog | } |
1301 | c3d2689d | balrog | } |
1302 | c3d2689d | balrog | |
1303 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
|
1304 | c3d2689d | balrog | omap_badwidth_read16, |
1305 | c3d2689d | balrog | omap_wd_timer_read, |
1306 | c3d2689d | balrog | omap_badwidth_read16, |
1307 | c3d2689d | balrog | }; |
1308 | c3d2689d | balrog | |
1309 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
|
1310 | c3d2689d | balrog | omap_badwidth_write16, |
1311 | c3d2689d | balrog | omap_wd_timer_write, |
1312 | c3d2689d | balrog | omap_badwidth_write16, |
1313 | c3d2689d | balrog | }; |
1314 | c3d2689d | balrog | |
1315 | c3d2689d | balrog | static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) |
1316 | c3d2689d | balrog | { |
1317 | c3d2689d | balrog | qemu_del_timer(s->timer.timer); |
1318 | c3d2689d | balrog | if (!s->mode)
|
1319 | c3d2689d | balrog | omap_clk_get(s->timer.clk); |
1320 | c3d2689d | balrog | s->mode = 1;
|
1321 | c3d2689d | balrog | s->free = 1;
|
1322 | c3d2689d | balrog | s->reset = 0;
|
1323 | c3d2689d | balrog | s->timer.enable = 1;
|
1324 | c3d2689d | balrog | s->timer.it_ena = 1;
|
1325 | c3d2689d | balrog | s->timer.reset_val = 0xffff;
|
1326 | c3d2689d | balrog | s->timer.val = 0;
|
1327 | c3d2689d | balrog | s->timer.st = 0;
|
1328 | c3d2689d | balrog | s->timer.ptv = 0;
|
1329 | c3d2689d | balrog | s->timer.ar = 0;
|
1330 | c3d2689d | balrog | omap_timer_update(&s->timer); |
1331 | c3d2689d | balrog | } |
1332 | c3d2689d | balrog | |
1333 | c3d2689d | balrog | struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
|
1334 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
1335 | c3d2689d | balrog | { |
1336 | c3d2689d | balrog | int iomemtype;
|
1337 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) |
1338 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_watchdog_timer_s)); |
1339 | c3d2689d | balrog | |
1340 | c3d2689d | balrog | s->timer.irq = irq; |
1341 | c3d2689d | balrog | s->timer.clk = clk; |
1342 | c3d2689d | balrog | s->timer.base = base; |
1343 | c3d2689d | balrog | s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
1344 | c3d2689d | balrog | omap_wd_timer_reset(s); |
1345 | c3d2689d | balrog | omap_timer_clk_setup(&s->timer); |
1346 | c3d2689d | balrog | |
1347 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
|
1348 | c3d2689d | balrog | omap_wd_timer_writefn, s); |
1349 | c3d2689d | balrog | cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
|
1350 | c3d2689d | balrog | |
1351 | c3d2689d | balrog | return s;
|
1352 | c3d2689d | balrog | } |
1353 | c3d2689d | balrog | |
1354 | c3d2689d | balrog | /* 32-kHz timer */
|
1355 | c3d2689d | balrog | struct omap_32khz_timer_s {
|
1356 | c3d2689d | balrog | struct omap_mpu_timer_s timer;
|
1357 | c3d2689d | balrog | }; |
1358 | c3d2689d | balrog | |
1359 | c3d2689d | balrog | static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr) |
1360 | c3d2689d | balrog | { |
1361 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
1362 | c3d2689d | balrog | int offset = addr - s->timer.base;
|
1363 | c3d2689d | balrog | |
1364 | c3d2689d | balrog | switch (offset) {
|
1365 | c3d2689d | balrog | case 0x00: /* TVR */ |
1366 | c3d2689d | balrog | return s->timer.reset_val;
|
1367 | c3d2689d | balrog | |
1368 | c3d2689d | balrog | case 0x04: /* TCR */ |
1369 | c3d2689d | balrog | return omap_timer_read(&s->timer);
|
1370 | c3d2689d | balrog | |
1371 | c3d2689d | balrog | case 0x08: /* CR */ |
1372 | c3d2689d | balrog | return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; |
1373 | c3d2689d | balrog | |
1374 | c3d2689d | balrog | default:
|
1375 | c3d2689d | balrog | break;
|
1376 | c3d2689d | balrog | } |
1377 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1378 | c3d2689d | balrog | return 0; |
1379 | c3d2689d | balrog | } |
1380 | c3d2689d | balrog | |
1381 | c3d2689d | balrog | static void omap_os_timer_write(void *opaque, target_phys_addr_t addr, |
1382 | c3d2689d | balrog | uint32_t value) |
1383 | c3d2689d | balrog | { |
1384 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
1385 | c3d2689d | balrog | int offset = addr - s->timer.base;
|
1386 | c3d2689d | balrog | |
1387 | c3d2689d | balrog | switch (offset) {
|
1388 | c3d2689d | balrog | case 0x00: /* TVR */ |
1389 | c3d2689d | balrog | s->timer.reset_val = value & 0x00ffffff;
|
1390 | c3d2689d | balrog | break;
|
1391 | c3d2689d | balrog | |
1392 | c3d2689d | balrog | case 0x04: /* TCR */ |
1393 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1394 | c3d2689d | balrog | break;
|
1395 | c3d2689d | balrog | |
1396 | c3d2689d | balrog | case 0x08: /* CR */ |
1397 | c3d2689d | balrog | s->timer.ar = (value >> 3) & 1; |
1398 | c3d2689d | balrog | s->timer.it_ena = (value >> 2) & 1; |
1399 | c3d2689d | balrog | if (s->timer.st != (value & 1) || (value & 2)) { |
1400 | c3d2689d | balrog | omap_timer_sync(&s->timer); |
1401 | c3d2689d | balrog | s->timer.enable = value & 1;
|
1402 | c3d2689d | balrog | s->timer.st = value & 1;
|
1403 | c3d2689d | balrog | omap_timer_update(&s->timer); |
1404 | c3d2689d | balrog | } |
1405 | c3d2689d | balrog | break;
|
1406 | c3d2689d | balrog | |
1407 | c3d2689d | balrog | default:
|
1408 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1409 | c3d2689d | balrog | } |
1410 | c3d2689d | balrog | } |
1411 | c3d2689d | balrog | |
1412 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
|
1413 | c3d2689d | balrog | omap_badwidth_read32, |
1414 | c3d2689d | balrog | omap_badwidth_read32, |
1415 | c3d2689d | balrog | omap_os_timer_read, |
1416 | c3d2689d | balrog | }; |
1417 | c3d2689d | balrog | |
1418 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
|
1419 | c3d2689d | balrog | omap_badwidth_write32, |
1420 | c3d2689d | balrog | omap_badwidth_write32, |
1421 | c3d2689d | balrog | omap_os_timer_write, |
1422 | c3d2689d | balrog | }; |
1423 | c3d2689d | balrog | |
1424 | c3d2689d | balrog | static void omap_os_timer_reset(struct omap_32khz_timer_s *s) |
1425 | c3d2689d | balrog | { |
1426 | c3d2689d | balrog | qemu_del_timer(s->timer.timer); |
1427 | c3d2689d | balrog | s->timer.enable = 0;
|
1428 | c3d2689d | balrog | s->timer.it_ena = 0;
|
1429 | c3d2689d | balrog | s->timer.reset_val = 0x00ffffff;
|
1430 | c3d2689d | balrog | s->timer.val = 0;
|
1431 | c3d2689d | balrog | s->timer.st = 0;
|
1432 | c3d2689d | balrog | s->timer.ptv = 0;
|
1433 | c3d2689d | balrog | s->timer.ar = 1;
|
1434 | c3d2689d | balrog | } |
1435 | c3d2689d | balrog | |
1436 | c3d2689d | balrog | struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
|
1437 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
1438 | c3d2689d | balrog | { |
1439 | c3d2689d | balrog | int iomemtype;
|
1440 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) |
1441 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_32khz_timer_s)); |
1442 | c3d2689d | balrog | |
1443 | c3d2689d | balrog | s->timer.irq = irq; |
1444 | c3d2689d | balrog | s->timer.clk = clk; |
1445 | c3d2689d | balrog | s->timer.base = base; |
1446 | c3d2689d | balrog | s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
1447 | c3d2689d | balrog | omap_os_timer_reset(s); |
1448 | c3d2689d | balrog | omap_timer_clk_setup(&s->timer); |
1449 | c3d2689d | balrog | |
1450 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
|
1451 | c3d2689d | balrog | omap_os_timer_writefn, s); |
1452 | c3d2689d | balrog | cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
|
1453 | c3d2689d | balrog | |
1454 | c3d2689d | balrog | return s;
|
1455 | c3d2689d | balrog | } |
1456 | c3d2689d | balrog | |
1457 | c3d2689d | balrog | /* Ultra Low-Power Device Module */
|
1458 | c3d2689d | balrog | static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr) |
1459 | c3d2689d | balrog | { |
1460 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1461 | c3d2689d | balrog | int offset = addr - s->ulpd_pm_base;
|
1462 | c3d2689d | balrog | uint16_t ret; |
1463 | c3d2689d | balrog | |
1464 | c3d2689d | balrog | switch (offset) {
|
1465 | c3d2689d | balrog | case 0x14: /* IT_STATUS */ |
1466 | c3d2689d | balrog | ret = s->ulpd_pm_regs[offset >> 2];
|
1467 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = 0; |
1468 | c3d2689d | balrog | qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
|
1469 | c3d2689d | balrog | return ret;
|
1470 | c3d2689d | balrog | |
1471 | c3d2689d | balrog | case 0x18: /* Reserved */ |
1472 | c3d2689d | balrog | case 0x1c: /* Reserved */ |
1473 | c3d2689d | balrog | case 0x20: /* Reserved */ |
1474 | c3d2689d | balrog | case 0x28: /* Reserved */ |
1475 | c3d2689d | balrog | case 0x2c: /* Reserved */ |
1476 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1477 | c3d2689d | balrog | case 0x00: /* COUNTER_32_LSB */ |
1478 | c3d2689d | balrog | case 0x04: /* COUNTER_32_MSB */ |
1479 | c3d2689d | balrog | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
1480 | c3d2689d | balrog | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
1481 | c3d2689d | balrog | case 0x10: /* GAUGING_CTRL */ |
1482 | c3d2689d | balrog | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
1483 | c3d2689d | balrog | case 0x30: /* CLOCK_CTRL */ |
1484 | c3d2689d | balrog | case 0x34: /* SOFT_REQ */ |
1485 | c3d2689d | balrog | case 0x38: /* COUNTER_32_FIQ */ |
1486 | c3d2689d | balrog | case 0x3c: /* DPLL_CTRL */ |
1487 | c3d2689d | balrog | case 0x40: /* STATUS_REQ */ |
1488 | c3d2689d | balrog | /* XXX: check clk::usecount state for every clock */
|
1489 | c3d2689d | balrog | case 0x48: /* LOCL_TIME */ |
1490 | c3d2689d | balrog | case 0x4c: /* APLL_CTRL */ |
1491 | c3d2689d | balrog | case 0x50: /* POWER_CTRL */ |
1492 | c3d2689d | balrog | return s->ulpd_pm_regs[offset >> 2]; |
1493 | c3d2689d | balrog | } |
1494 | c3d2689d | balrog | |
1495 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1496 | c3d2689d | balrog | return 0; |
1497 | c3d2689d | balrog | } |
1498 | c3d2689d | balrog | |
1499 | c3d2689d | balrog | static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, |
1500 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1501 | c3d2689d | balrog | { |
1502 | c3d2689d | balrog | if (diff & (1 << 4)) /* USB_MCLK_EN */ |
1503 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); |
1504 | c3d2689d | balrog | if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ |
1505 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); |
1506 | c3d2689d | balrog | } |
1507 | c3d2689d | balrog | |
1508 | c3d2689d | balrog | static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, |
1509 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1510 | c3d2689d | balrog | { |
1511 | c3d2689d | balrog | if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ |
1512 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); |
1513 | c3d2689d | balrog | if (diff & (1 << 1)) /* SOFT_COM_REQ */ |
1514 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); |
1515 | c3d2689d | balrog | if (diff & (1 << 2)) /* SOFT_SDW_REQ */ |
1516 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); |
1517 | c3d2689d | balrog | if (diff & (1 << 3)) /* SOFT_USB_REQ */ |
1518 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); |
1519 | c3d2689d | balrog | } |
1520 | c3d2689d | balrog | |
1521 | c3d2689d | balrog | static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr, |
1522 | c3d2689d | balrog | uint32_t value) |
1523 | c3d2689d | balrog | { |
1524 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1525 | c3d2689d | balrog | int offset = addr - s->ulpd_pm_base;
|
1526 | c3d2689d | balrog | int64_t now, ticks; |
1527 | c3d2689d | balrog | int div, mult;
|
1528 | c3d2689d | balrog | static const int bypass_div[4] = { 1, 2, 4, 4 }; |
1529 | c3d2689d | balrog | uint16_t diff; |
1530 | c3d2689d | balrog | |
1531 | c3d2689d | balrog | switch (offset) {
|
1532 | c3d2689d | balrog | case 0x00: /* COUNTER_32_LSB */ |
1533 | c3d2689d | balrog | case 0x04: /* COUNTER_32_MSB */ |
1534 | c3d2689d | balrog | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
1535 | c3d2689d | balrog | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
1536 | c3d2689d | balrog | case 0x14: /* IT_STATUS */ |
1537 | c3d2689d | balrog | case 0x40: /* STATUS_REQ */ |
1538 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1539 | c3d2689d | balrog | break;
|
1540 | c3d2689d | balrog | |
1541 | c3d2689d | balrog | case 0x10: /* GAUGING_CTRL */ |
1542 | c3d2689d | balrog | /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
|
1543 | c3d2689d | balrog | if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) { |
1544 | c3d2689d | balrog | now = qemu_get_clock(vm_clock); |
1545 | c3d2689d | balrog | |
1546 | c3d2689d | balrog | if (value & 1) |
1547 | c3d2689d | balrog | s->ulpd_gauge_start = now; |
1548 | c3d2689d | balrog | else {
|
1549 | c3d2689d | balrog | now -= s->ulpd_gauge_start; |
1550 | c3d2689d | balrog | |
1551 | c3d2689d | balrog | /* 32-kHz ticks */
|
1552 | c3d2689d | balrog | ticks = muldiv64(now, 32768, ticks_per_sec);
|
1553 | c3d2689d | balrog | s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; |
1554 | c3d2689d | balrog | s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; |
1555 | c3d2689d | balrog | if (ticks >> 32) /* OVERFLOW_32K */ |
1556 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; |
1557 | c3d2689d | balrog | |
1558 | c3d2689d | balrog | /* High frequency ticks */
|
1559 | c3d2689d | balrog | ticks = muldiv64(now, 12000000, ticks_per_sec);
|
1560 | c3d2689d | balrog | s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; |
1561 | c3d2689d | balrog | s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; |
1562 | c3d2689d | balrog | if (ticks >> 32) /* OVERFLOW_HI_FREQ */ |
1563 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; |
1564 | c3d2689d | balrog | |
1565 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ |
1566 | c3d2689d | balrog | qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
|
1567 | c3d2689d | balrog | } |
1568 | c3d2689d | balrog | } |
1569 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value;
|
1570 | c3d2689d | balrog | break;
|
1571 | c3d2689d | balrog | |
1572 | c3d2689d | balrog | case 0x18: /* Reserved */ |
1573 | c3d2689d | balrog | case 0x1c: /* Reserved */ |
1574 | c3d2689d | balrog | case 0x20: /* Reserved */ |
1575 | c3d2689d | balrog | case 0x28: /* Reserved */ |
1576 | c3d2689d | balrog | case 0x2c: /* Reserved */ |
1577 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1578 | c3d2689d | balrog | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
1579 | c3d2689d | balrog | case 0x38: /* COUNTER_32_FIQ */ |
1580 | c3d2689d | balrog | case 0x48: /* LOCL_TIME */ |
1581 | c3d2689d | balrog | case 0x50: /* POWER_CTRL */ |
1582 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value;
|
1583 | c3d2689d | balrog | break;
|
1584 | c3d2689d | balrog | |
1585 | c3d2689d | balrog | case 0x30: /* CLOCK_CTRL */ |
1586 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] ^ value;
|
1587 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0x3f; |
1588 | c3d2689d | balrog | omap_ulpd_clk_update(s, diff, value); |
1589 | c3d2689d | balrog | break;
|
1590 | c3d2689d | balrog | |
1591 | c3d2689d | balrog | case 0x34: /* SOFT_REQ */ |
1592 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] ^ value;
|
1593 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0x1f; |
1594 | c3d2689d | balrog | omap_ulpd_req_update(s, diff, value); |
1595 | c3d2689d | balrog | break;
|
1596 | c3d2689d | balrog | |
1597 | c3d2689d | balrog | case 0x3c: /* DPLL_CTRL */ |
1598 | c3d2689d | balrog | /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
|
1599 | c3d2689d | balrog | * omitted altogether, probably a typo. */
|
1600 | c3d2689d | balrog | /* This register has identical semantics with DPLL(1:3) control
|
1601 | c3d2689d | balrog | * registers, see omap_dpll_write() */
|
1602 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] & value;
|
1603 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0x2fff; |
1604 | c3d2689d | balrog | if (diff & (0x3ff << 2)) { |
1605 | c3d2689d | balrog | if (value & (1 << 4)) { /* PLL_ENABLE */ |
1606 | c3d2689d | balrog | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
1607 | c3d2689d | balrog | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
1608 | c3d2689d | balrog | } else {
|
1609 | c3d2689d | balrog | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
1610 | c3d2689d | balrog | mult = 1;
|
1611 | c3d2689d | balrog | } |
1612 | c3d2689d | balrog | omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
|
1613 | c3d2689d | balrog | } |
1614 | c3d2689d | balrog | |
1615 | c3d2689d | balrog | /* Enter the desired mode. */
|
1616 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] =
|
1617 | c3d2689d | balrog | (s->ulpd_pm_regs[offset >> 2] & 0xfffe) | |
1618 | c3d2689d | balrog | ((s->ulpd_pm_regs[offset >> 2] >> 4) & 1); |
1619 | c3d2689d | balrog | |
1620 | c3d2689d | balrog | /* Act as if the lock is restored. */
|
1621 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] |= 2; |
1622 | c3d2689d | balrog | break;
|
1623 | c3d2689d | balrog | |
1624 | c3d2689d | balrog | case 0x4c: /* APLL_CTRL */ |
1625 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] & value;
|
1626 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0xf; |
1627 | c3d2689d | balrog | if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ |
1628 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
|
1629 | c3d2689d | balrog | (value & (1 << 0)) ? "apll" : "dpll4")); |
1630 | c3d2689d | balrog | break;
|
1631 | c3d2689d | balrog | |
1632 | c3d2689d | balrog | default:
|
1633 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1634 | c3d2689d | balrog | } |
1635 | c3d2689d | balrog | } |
1636 | c3d2689d | balrog | |
1637 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
|
1638 | c3d2689d | balrog | omap_badwidth_read16, |
1639 | c3d2689d | balrog | omap_ulpd_pm_read, |
1640 | c3d2689d | balrog | omap_badwidth_read16, |
1641 | c3d2689d | balrog | }; |
1642 | c3d2689d | balrog | |
1643 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
|
1644 | c3d2689d | balrog | omap_badwidth_write16, |
1645 | c3d2689d | balrog | omap_ulpd_pm_write, |
1646 | c3d2689d | balrog | omap_badwidth_write16, |
1647 | c3d2689d | balrog | }; |
1648 | c3d2689d | balrog | |
1649 | c3d2689d | balrog | static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) |
1650 | c3d2689d | balrog | { |
1651 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; |
1652 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; |
1653 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; |
1654 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; |
1655 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; |
1656 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; |
1657 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; |
1658 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; |
1659 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; |
1660 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; |
1661 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; |
1662 | c3d2689d | balrog | omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); |
1663 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; |
1664 | c3d2689d | balrog | omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); |
1665 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; |
1666 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; |
1667 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; |
1668 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ |
1669 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; |
1670 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; |
1671 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; |
1672 | c3d2689d | balrog | omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); |
1673 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); |
1674 | c3d2689d | balrog | } |
1675 | c3d2689d | balrog | |
1676 | c3d2689d | balrog | static void omap_ulpd_pm_init(target_phys_addr_t base, |
1677 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1678 | c3d2689d | balrog | { |
1679 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn, |
1680 | c3d2689d | balrog | omap_ulpd_pm_writefn, mpu); |
1681 | c3d2689d | balrog | |
1682 | c3d2689d | balrog | mpu->ulpd_pm_base = base; |
1683 | c3d2689d | balrog | cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
|
1684 | c3d2689d | balrog | omap_ulpd_pm_reset(mpu); |
1685 | c3d2689d | balrog | } |
1686 | c3d2689d | balrog | |
1687 | c3d2689d | balrog | /* OMAP Pin Configuration */
|
1688 | c3d2689d | balrog | static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr) |
1689 | c3d2689d | balrog | { |
1690 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1691 | c3d2689d | balrog | int offset = addr - s->pin_cfg_base;
|
1692 | c3d2689d | balrog | |
1693 | c3d2689d | balrog | switch (offset) {
|
1694 | c3d2689d | balrog | case 0x00: /* FUNC_MUX_CTRL_0 */ |
1695 | c3d2689d | balrog | case 0x04: /* FUNC_MUX_CTRL_1 */ |
1696 | c3d2689d | balrog | case 0x08: /* FUNC_MUX_CTRL_2 */ |
1697 | c3d2689d | balrog | return s->func_mux_ctrl[offset >> 2]; |
1698 | c3d2689d | balrog | |
1699 | c3d2689d | balrog | case 0x0c: /* COMP_MODE_CTRL_0 */ |
1700 | c3d2689d | balrog | return s->comp_mode_ctrl[0]; |
1701 | c3d2689d | balrog | |
1702 | c3d2689d | balrog | case 0x10: /* FUNC_MUX_CTRL_3 */ |
1703 | c3d2689d | balrog | case 0x14: /* FUNC_MUX_CTRL_4 */ |
1704 | c3d2689d | balrog | case 0x18: /* FUNC_MUX_CTRL_5 */ |
1705 | c3d2689d | balrog | case 0x1c: /* FUNC_MUX_CTRL_6 */ |
1706 | c3d2689d | balrog | case 0x20: /* FUNC_MUX_CTRL_7 */ |
1707 | c3d2689d | balrog | case 0x24: /* FUNC_MUX_CTRL_8 */ |
1708 | c3d2689d | balrog | case 0x28: /* FUNC_MUX_CTRL_9 */ |
1709 | c3d2689d | balrog | case 0x2c: /* FUNC_MUX_CTRL_A */ |
1710 | c3d2689d | balrog | case 0x30: /* FUNC_MUX_CTRL_B */ |
1711 | c3d2689d | balrog | case 0x34: /* FUNC_MUX_CTRL_C */ |
1712 | c3d2689d | balrog | case 0x38: /* FUNC_MUX_CTRL_D */ |
1713 | c3d2689d | balrog | return s->func_mux_ctrl[(offset >> 2) - 1]; |
1714 | c3d2689d | balrog | |
1715 | c3d2689d | balrog | case 0x40: /* PULL_DWN_CTRL_0 */ |
1716 | c3d2689d | balrog | case 0x44: /* PULL_DWN_CTRL_1 */ |
1717 | c3d2689d | balrog | case 0x48: /* PULL_DWN_CTRL_2 */ |
1718 | c3d2689d | balrog | case 0x4c: /* PULL_DWN_CTRL_3 */ |
1719 | c3d2689d | balrog | return s->pull_dwn_ctrl[(offset & 0xf) >> 2]; |
1720 | c3d2689d | balrog | |
1721 | c3d2689d | balrog | case 0x50: /* GATE_INH_CTRL_0 */ |
1722 | c3d2689d | balrog | return s->gate_inh_ctrl[0]; |
1723 | c3d2689d | balrog | |
1724 | c3d2689d | balrog | case 0x60: /* VOLTAGE_CTRL_0 */ |
1725 | c3d2689d | balrog | return s->voltage_ctrl[0]; |
1726 | c3d2689d | balrog | |
1727 | c3d2689d | balrog | case 0x70: /* TEST_DBG_CTRL_0 */ |
1728 | c3d2689d | balrog | return s->test_dbg_ctrl[0]; |
1729 | c3d2689d | balrog | |
1730 | c3d2689d | balrog | case 0x80: /* MOD_CONF_CTRL_0 */ |
1731 | c3d2689d | balrog | return s->mod_conf_ctrl[0]; |
1732 | c3d2689d | balrog | } |
1733 | c3d2689d | balrog | |
1734 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1735 | c3d2689d | balrog | return 0; |
1736 | c3d2689d | balrog | } |
1737 | c3d2689d | balrog | |
1738 | c3d2689d | balrog | static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, |
1739 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
1740 | c3d2689d | balrog | { |
1741 | c3d2689d | balrog | if (s->compat1509) {
|
1742 | c3d2689d | balrog | if (diff & (1 << 9)) /* BLUETOOTH */ |
1743 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
|
1744 | c3d2689d | balrog | (~value >> 9) & 1); |
1745 | c3d2689d | balrog | if (diff & (1 << 7)) /* USB.CLKO */ |
1746 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb.clko"),
|
1747 | c3d2689d | balrog | (value >> 7) & 1); |
1748 | c3d2689d | balrog | } |
1749 | c3d2689d | balrog | } |
1750 | c3d2689d | balrog | |
1751 | c3d2689d | balrog | static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, |
1752 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
1753 | c3d2689d | balrog | { |
1754 | c3d2689d | balrog | if (s->compat1509) {
|
1755 | c3d2689d | balrog | if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */ |
1756 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
|
1757 | c3d2689d | balrog | (value >> 31) & 1); |
1758 | c3d2689d | balrog | if (diff & (1 << 1)) /* CLK32K */ |
1759 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "clk32k_out"),
|
1760 | c3d2689d | balrog | (~value >> 1) & 1); |
1761 | c3d2689d | balrog | } |
1762 | c3d2689d | balrog | } |
1763 | c3d2689d | balrog | |
1764 | c3d2689d | balrog | static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, |
1765 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
1766 | c3d2689d | balrog | { |
1767 | c3d2689d | balrog | if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */ |
1768 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart3_ck"),
|
1769 | c3d2689d | balrog | omap_findclk(s, ((value >> 31) & 1) ? |
1770 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1771 | c3d2689d | balrog | if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ |
1772 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart2_ck"),
|
1773 | c3d2689d | balrog | omap_findclk(s, ((value >> 30) & 1) ? |
1774 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1775 | c3d2689d | balrog | if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ |
1776 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart1_ck"),
|
1777 | c3d2689d | balrog | omap_findclk(s, ((value >> 29) & 1) ? |
1778 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1779 | c3d2689d | balrog | if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ |
1780 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "mmc_ck"),
|
1781 | c3d2689d | balrog | omap_findclk(s, ((value >> 23) & 1) ? |
1782 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1783 | c3d2689d | balrog | if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ |
1784 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
|
1785 | c3d2689d | balrog | omap_findclk(s, ((value >> 12) & 1) ? |
1786 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1787 | c3d2689d | balrog | if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ |
1788 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); |
1789 | c3d2689d | balrog | } |
1790 | c3d2689d | balrog | |
1791 | c3d2689d | balrog | static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr, |
1792 | c3d2689d | balrog | uint32_t value) |
1793 | c3d2689d | balrog | { |
1794 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1795 | c3d2689d | balrog | int offset = addr - s->pin_cfg_base;
|
1796 | c3d2689d | balrog | uint32_t diff; |
1797 | c3d2689d | balrog | |
1798 | c3d2689d | balrog | switch (offset) {
|
1799 | c3d2689d | balrog | case 0x00: /* FUNC_MUX_CTRL_0 */ |
1800 | c3d2689d | balrog | diff = s->func_mux_ctrl[offset >> 2] ^ value;
|
1801 | c3d2689d | balrog | s->func_mux_ctrl[offset >> 2] = value;
|
1802 | c3d2689d | balrog | omap_pin_funcmux0_update(s, diff, value); |
1803 | c3d2689d | balrog | return;
|
1804 | c3d2689d | balrog | |
1805 | c3d2689d | balrog | case 0x04: /* FUNC_MUX_CTRL_1 */ |
1806 | c3d2689d | balrog | diff = s->func_mux_ctrl[offset >> 2] ^ value;
|
1807 | c3d2689d | balrog | s->func_mux_ctrl[offset >> 2] = value;
|
1808 | c3d2689d | balrog | omap_pin_funcmux1_update(s, diff, value); |
1809 | c3d2689d | balrog | return;
|
1810 | c3d2689d | balrog | |
1811 | c3d2689d | balrog | case 0x08: /* FUNC_MUX_CTRL_2 */ |
1812 | c3d2689d | balrog | s->func_mux_ctrl[offset >> 2] = value;
|
1813 | c3d2689d | balrog | return;
|
1814 | c3d2689d | balrog | |
1815 | c3d2689d | balrog | case 0x0c: /* COMP_MODE_CTRL_0 */ |
1816 | c3d2689d | balrog | s->comp_mode_ctrl[0] = value;
|
1817 | c3d2689d | balrog | s->compat1509 = (value != 0x0000eaef);
|
1818 | c3d2689d | balrog | omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); |
1819 | c3d2689d | balrog | omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); |
1820 | c3d2689d | balrog | return;
|
1821 | c3d2689d | balrog | |
1822 | c3d2689d | balrog | case 0x10: /* FUNC_MUX_CTRL_3 */ |
1823 | c3d2689d | balrog | case 0x14: /* FUNC_MUX_CTRL_4 */ |
1824 | c3d2689d | balrog | case 0x18: /* FUNC_MUX_CTRL_5 */ |
1825 | c3d2689d | balrog | case 0x1c: /* FUNC_MUX_CTRL_6 */ |
1826 | c3d2689d | balrog | case 0x20: /* FUNC_MUX_CTRL_7 */ |
1827 | c3d2689d | balrog | case 0x24: /* FUNC_MUX_CTRL_8 */ |
1828 | c3d2689d | balrog | case 0x28: /* FUNC_MUX_CTRL_9 */ |
1829 | c3d2689d | balrog | case 0x2c: /* FUNC_MUX_CTRL_A */ |
1830 | c3d2689d | balrog | case 0x30: /* FUNC_MUX_CTRL_B */ |
1831 | c3d2689d | balrog | case 0x34: /* FUNC_MUX_CTRL_C */ |
1832 | c3d2689d | balrog | case 0x38: /* FUNC_MUX_CTRL_D */ |
1833 | c3d2689d | balrog | s->func_mux_ctrl[(offset >> 2) - 1] = value; |
1834 | c3d2689d | balrog | return;
|
1835 | c3d2689d | balrog | |
1836 | c3d2689d | balrog | case 0x40: /* PULL_DWN_CTRL_0 */ |
1837 | c3d2689d | balrog | case 0x44: /* PULL_DWN_CTRL_1 */ |
1838 | c3d2689d | balrog | case 0x48: /* PULL_DWN_CTRL_2 */ |
1839 | c3d2689d | balrog | case 0x4c: /* PULL_DWN_CTRL_3 */ |
1840 | c3d2689d | balrog | s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value; |
1841 | c3d2689d | balrog | return;
|
1842 | c3d2689d | balrog | |
1843 | c3d2689d | balrog | case 0x50: /* GATE_INH_CTRL_0 */ |
1844 | c3d2689d | balrog | s->gate_inh_ctrl[0] = value;
|
1845 | c3d2689d | balrog | return;
|
1846 | c3d2689d | balrog | |
1847 | c3d2689d | balrog | case 0x60: /* VOLTAGE_CTRL_0 */ |
1848 | c3d2689d | balrog | s->voltage_ctrl[0] = value;
|
1849 | c3d2689d | balrog | return;
|
1850 | c3d2689d | balrog | |
1851 | c3d2689d | balrog | case 0x70: /* TEST_DBG_CTRL_0 */ |
1852 | c3d2689d | balrog | s->test_dbg_ctrl[0] = value;
|
1853 | c3d2689d | balrog | return;
|
1854 | c3d2689d | balrog | |
1855 | c3d2689d | balrog | case 0x80: /* MOD_CONF_CTRL_0 */ |
1856 | c3d2689d | balrog | diff = s->mod_conf_ctrl[0] ^ value;
|
1857 | c3d2689d | balrog | s->mod_conf_ctrl[0] = value;
|
1858 | c3d2689d | balrog | omap_pin_modconf1_update(s, diff, value); |
1859 | c3d2689d | balrog | return;
|
1860 | c3d2689d | balrog | |
1861 | c3d2689d | balrog | default:
|
1862 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1863 | c3d2689d | balrog | } |
1864 | c3d2689d | balrog | } |
1865 | c3d2689d | balrog | |
1866 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
|
1867 | c3d2689d | balrog | omap_badwidth_read32, |
1868 | c3d2689d | balrog | omap_badwidth_read32, |
1869 | c3d2689d | balrog | omap_pin_cfg_read, |
1870 | c3d2689d | balrog | }; |
1871 | c3d2689d | balrog | |
1872 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
|
1873 | c3d2689d | balrog | omap_badwidth_write32, |
1874 | c3d2689d | balrog | omap_badwidth_write32, |
1875 | c3d2689d | balrog | omap_pin_cfg_write, |
1876 | c3d2689d | balrog | }; |
1877 | c3d2689d | balrog | |
1878 | c3d2689d | balrog | static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) |
1879 | c3d2689d | balrog | { |
1880 | c3d2689d | balrog | /* Start in Compatibility Mode. */
|
1881 | c3d2689d | balrog | mpu->compat1509 = 1;
|
1882 | c3d2689d | balrog | omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); |
1883 | c3d2689d | balrog | omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); |
1884 | c3d2689d | balrog | omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); |
1885 | c3d2689d | balrog | memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); |
1886 | c3d2689d | balrog | memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); |
1887 | c3d2689d | balrog | memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); |
1888 | c3d2689d | balrog | memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); |
1889 | c3d2689d | balrog | memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); |
1890 | c3d2689d | balrog | memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); |
1891 | c3d2689d | balrog | memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); |
1892 | c3d2689d | balrog | } |
1893 | c3d2689d | balrog | |
1894 | c3d2689d | balrog | static void omap_pin_cfg_init(target_phys_addr_t base, |
1895 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1896 | c3d2689d | balrog | { |
1897 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn, |
1898 | c3d2689d | balrog | omap_pin_cfg_writefn, mpu); |
1899 | c3d2689d | balrog | |
1900 | c3d2689d | balrog | mpu->pin_cfg_base = base; |
1901 | c3d2689d | balrog | cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
|
1902 | c3d2689d | balrog | omap_pin_cfg_reset(mpu); |
1903 | c3d2689d | balrog | } |
1904 | c3d2689d | balrog | |
1905 | c3d2689d | balrog | /* Device Identification, Die Identification */
|
1906 | c3d2689d | balrog | static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr) |
1907 | c3d2689d | balrog | { |
1908 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1909 | c3d2689d | balrog | |
1910 | c3d2689d | balrog | switch (addr) {
|
1911 | c3d2689d | balrog | case 0xfffe1800: /* DIE_ID_LSB */ |
1912 | c3d2689d | balrog | return 0xc9581f0e; |
1913 | c3d2689d | balrog | case 0xfffe1804: /* DIE_ID_MSB */ |
1914 | c3d2689d | balrog | return 0xa8858bfa; |
1915 | c3d2689d | balrog | |
1916 | c3d2689d | balrog | case 0xfffe2000: /* PRODUCT_ID_LSB */ |
1917 | c3d2689d | balrog | return 0x00aaaafc; |
1918 | c3d2689d | balrog | case 0xfffe2004: /* PRODUCT_ID_MSB */ |
1919 | c3d2689d | balrog | return 0xcafeb574; |
1920 | c3d2689d | balrog | |
1921 | c3d2689d | balrog | case 0xfffed400: /* JTAG_ID_LSB */ |
1922 | c3d2689d | balrog | switch (s->mpu_model) {
|
1923 | c3d2689d | balrog | case omap310:
|
1924 | c3d2689d | balrog | return 0x03310315; |
1925 | c3d2689d | balrog | case omap1510:
|
1926 | c3d2689d | balrog | return 0x03310115; |
1927 | c3d2689d | balrog | } |
1928 | c3d2689d | balrog | break;
|
1929 | c3d2689d | balrog | |
1930 | c3d2689d | balrog | case 0xfffed404: /* JTAG_ID_MSB */ |
1931 | c3d2689d | balrog | switch (s->mpu_model) {
|
1932 | c3d2689d | balrog | case omap310:
|
1933 | c3d2689d | balrog | return 0xfb57402f; |
1934 | c3d2689d | balrog | case omap1510:
|
1935 | c3d2689d | balrog | return 0xfb47002f; |
1936 | c3d2689d | balrog | } |
1937 | c3d2689d | balrog | break;
|
1938 | c3d2689d | balrog | } |
1939 | c3d2689d | balrog | |
1940 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1941 | c3d2689d | balrog | return 0; |
1942 | c3d2689d | balrog | } |
1943 | c3d2689d | balrog | |
1944 | c3d2689d | balrog | static void omap_id_write(void *opaque, target_phys_addr_t addr, |
1945 | c3d2689d | balrog | uint32_t value) |
1946 | c3d2689d | balrog | { |
1947 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1948 | c3d2689d | balrog | } |
1949 | c3d2689d | balrog | |
1950 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_id_readfn[] = {
|
1951 | c3d2689d | balrog | omap_badwidth_read32, |
1952 | c3d2689d | balrog | omap_badwidth_read32, |
1953 | c3d2689d | balrog | omap_id_read, |
1954 | c3d2689d | balrog | }; |
1955 | c3d2689d | balrog | |
1956 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_id_writefn[] = {
|
1957 | c3d2689d | balrog | omap_badwidth_write32, |
1958 | c3d2689d | balrog | omap_badwidth_write32, |
1959 | c3d2689d | balrog | omap_id_write, |
1960 | c3d2689d | balrog | }; |
1961 | c3d2689d | balrog | |
1962 | c3d2689d | balrog | static void omap_id_init(struct omap_mpu_state_s *mpu) |
1963 | c3d2689d | balrog | { |
1964 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_id_readfn, |
1965 | c3d2689d | balrog | omap_id_writefn, mpu); |
1966 | c3d2689d | balrog | cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype); |
1967 | c3d2689d | balrog | cpu_register_physical_memory(0xfffed400, 0x100, iomemtype); |
1968 | c3d2689d | balrog | if (!cpu_is_omap15xx(mpu))
|
1969 | c3d2689d | balrog | cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype); |
1970 | c3d2689d | balrog | } |
1971 | c3d2689d | balrog | |
1972 | c3d2689d | balrog | /* MPUI Control (Dummy) */
|
1973 | c3d2689d | balrog | static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr) |
1974 | c3d2689d | balrog | { |
1975 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1976 | c3d2689d | balrog | int offset = addr - s->mpui_base;
|
1977 | c3d2689d | balrog | |
1978 | c3d2689d | balrog | switch (offset) {
|
1979 | c3d2689d | balrog | case 0x00: /* CTRL */ |
1980 | c3d2689d | balrog | return s->mpui_ctrl;
|
1981 | c3d2689d | balrog | case 0x04: /* DEBUG_ADDR */ |
1982 | c3d2689d | balrog | return 0x01ffffff; |
1983 | c3d2689d | balrog | case 0x08: /* DEBUG_DATA */ |
1984 | c3d2689d | balrog | return 0xffffffff; |
1985 | c3d2689d | balrog | case 0x0c: /* DEBUG_FLAG */ |
1986 | c3d2689d | balrog | return 0x00000800; |
1987 | c3d2689d | balrog | case 0x10: /* STATUS */ |
1988 | c3d2689d | balrog | return 0x00000000; |
1989 | c3d2689d | balrog | |
1990 | c3d2689d | balrog | /* Not in OMAP310 */
|
1991 | c3d2689d | balrog | case 0x14: /* DSP_STATUS */ |
1992 | c3d2689d | balrog | case 0x18: /* DSP_BOOT_CONFIG */ |
1993 | c3d2689d | balrog | return 0x00000000; |
1994 | c3d2689d | balrog | case 0x1c: /* DSP_MPUI_CONFIG */ |
1995 | c3d2689d | balrog | return 0x0000ffff; |
1996 | c3d2689d | balrog | } |
1997 | c3d2689d | balrog | |
1998 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1999 | c3d2689d | balrog | return 0; |
2000 | c3d2689d | balrog | } |
2001 | c3d2689d | balrog | |
2002 | c3d2689d | balrog | static void omap_mpui_write(void *opaque, target_phys_addr_t addr, |
2003 | c3d2689d | balrog | uint32_t value) |
2004 | c3d2689d | balrog | { |
2005 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2006 | c3d2689d | balrog | int offset = addr - s->mpui_base;
|
2007 | c3d2689d | balrog | |
2008 | c3d2689d | balrog | switch (offset) {
|
2009 | c3d2689d | balrog | case 0x00: /* CTRL */ |
2010 | c3d2689d | balrog | s->mpui_ctrl = value & 0x007fffff;
|
2011 | c3d2689d | balrog | break;
|
2012 | c3d2689d | balrog | |
2013 | c3d2689d | balrog | case 0x04: /* DEBUG_ADDR */ |
2014 | c3d2689d | balrog | case 0x08: /* DEBUG_DATA */ |
2015 | c3d2689d | balrog | case 0x0c: /* DEBUG_FLAG */ |
2016 | c3d2689d | balrog | case 0x10: /* STATUS */ |
2017 | c3d2689d | balrog | /* Not in OMAP310 */
|
2018 | c3d2689d | balrog | case 0x14: /* DSP_STATUS */ |
2019 | c3d2689d | balrog | OMAP_RO_REG(addr); |
2020 | c3d2689d | balrog | case 0x18: /* DSP_BOOT_CONFIG */ |
2021 | c3d2689d | balrog | case 0x1c: /* DSP_MPUI_CONFIG */ |
2022 | c3d2689d | balrog | break;
|
2023 | c3d2689d | balrog | |
2024 | c3d2689d | balrog | default:
|
2025 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2026 | c3d2689d | balrog | } |
2027 | c3d2689d | balrog | } |
2028 | c3d2689d | balrog | |
2029 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_mpui_readfn[] = {
|
2030 | c3d2689d | balrog | omap_badwidth_read32, |
2031 | c3d2689d | balrog | omap_badwidth_read32, |
2032 | c3d2689d | balrog | omap_mpui_read, |
2033 | c3d2689d | balrog | }; |
2034 | c3d2689d | balrog | |
2035 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
|
2036 | c3d2689d | balrog | omap_badwidth_write32, |
2037 | c3d2689d | balrog | omap_badwidth_write32, |
2038 | c3d2689d | balrog | omap_mpui_write, |
2039 | c3d2689d | balrog | }; |
2040 | c3d2689d | balrog | |
2041 | c3d2689d | balrog | static void omap_mpui_reset(struct omap_mpu_state_s *s) |
2042 | c3d2689d | balrog | { |
2043 | c3d2689d | balrog | s->mpui_ctrl = 0x0003ff1b;
|
2044 | c3d2689d | balrog | } |
2045 | c3d2689d | balrog | |
2046 | c3d2689d | balrog | static void omap_mpui_init(target_phys_addr_t base, |
2047 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
2048 | c3d2689d | balrog | { |
2049 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn, |
2050 | c3d2689d | balrog | omap_mpui_writefn, mpu); |
2051 | c3d2689d | balrog | |
2052 | c3d2689d | balrog | mpu->mpui_base = base; |
2053 | c3d2689d | balrog | cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
|
2054 | c3d2689d | balrog | |
2055 | c3d2689d | balrog | omap_mpui_reset(mpu); |
2056 | c3d2689d | balrog | } |
2057 | c3d2689d | balrog | |
2058 | c3d2689d | balrog | /* TIPB Bridges */
|
2059 | c3d2689d | balrog | struct omap_tipb_bridge_s {
|
2060 | c3d2689d | balrog | target_phys_addr_t base; |
2061 | c3d2689d | balrog | qemu_irq abort; |
2062 | c3d2689d | balrog | |
2063 | c3d2689d | balrog | int width_intr;
|
2064 | c3d2689d | balrog | uint16_t control; |
2065 | c3d2689d | balrog | uint16_t alloc; |
2066 | c3d2689d | balrog | uint16_t buffer; |
2067 | c3d2689d | balrog | uint16_t enh_control; |
2068 | c3d2689d | balrog | }; |
2069 | c3d2689d | balrog | |
2070 | c3d2689d | balrog | static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr) |
2071 | c3d2689d | balrog | { |
2072 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
2073 | c3d2689d | balrog | int offset = addr - s->base;
|
2074 | c3d2689d | balrog | |
2075 | c3d2689d | balrog | switch (offset) {
|
2076 | c3d2689d | balrog | case 0x00: /* TIPB_CNTL */ |
2077 | c3d2689d | balrog | return s->control;
|
2078 | c3d2689d | balrog | case 0x04: /* TIPB_BUS_ALLOC */ |
2079 | c3d2689d | balrog | return s->alloc;
|
2080 | c3d2689d | balrog | case 0x08: /* MPU_TIPB_CNTL */ |
2081 | c3d2689d | balrog | return s->buffer;
|
2082 | c3d2689d | balrog | case 0x0c: /* ENHANCED_TIPB_CNTL */ |
2083 | c3d2689d | balrog | return s->enh_control;
|
2084 | c3d2689d | balrog | case 0x10: /* ADDRESS_DBG */ |
2085 | c3d2689d | balrog | case 0x14: /* DATA_DEBUG_LOW */ |
2086 | c3d2689d | balrog | case 0x18: /* DATA_DEBUG_HIGH */ |
2087 | c3d2689d | balrog | return 0xffff; |
2088 | c3d2689d | balrog | case 0x1c: /* DEBUG_CNTR_SIG */ |
2089 | c3d2689d | balrog | return 0x00f8; |
2090 | c3d2689d | balrog | } |
2091 | c3d2689d | balrog | |
2092 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2093 | c3d2689d | balrog | return 0; |
2094 | c3d2689d | balrog | } |
2095 | c3d2689d | balrog | |
2096 | c3d2689d | balrog | static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr, |
2097 | c3d2689d | balrog | uint32_t value) |
2098 | c3d2689d | balrog | { |
2099 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
2100 | c3d2689d | balrog | int offset = addr - s->base;
|
2101 | c3d2689d | balrog | |
2102 | c3d2689d | balrog | switch (offset) {
|
2103 | c3d2689d | balrog | case 0x00: /* TIPB_CNTL */ |
2104 | c3d2689d | balrog | s->control = value & 0xffff;
|
2105 | c3d2689d | balrog | break;
|
2106 | c3d2689d | balrog | |
2107 | c3d2689d | balrog | case 0x04: /* TIPB_BUS_ALLOC */ |
2108 | c3d2689d | balrog | s->alloc = value & 0x003f;
|
2109 | c3d2689d | balrog | break;
|
2110 | c3d2689d | balrog | |
2111 | c3d2689d | balrog | case 0x08: /* MPU_TIPB_CNTL */ |
2112 | c3d2689d | balrog | s->buffer = value & 0x0003;
|
2113 | c3d2689d | balrog | break;
|
2114 | c3d2689d | balrog | |
2115 | c3d2689d | balrog | case 0x0c: /* ENHANCED_TIPB_CNTL */ |
2116 | c3d2689d | balrog | s->width_intr = !(value & 2);
|
2117 | c3d2689d | balrog | s->enh_control = value & 0x000f;
|
2118 | c3d2689d | balrog | break;
|
2119 | c3d2689d | balrog | |
2120 | c3d2689d | balrog | case 0x10: /* ADDRESS_DBG */ |
2121 | c3d2689d | balrog | case 0x14: /* DATA_DEBUG_LOW */ |
2122 | c3d2689d | balrog | case 0x18: /* DATA_DEBUG_HIGH */ |
2123 | c3d2689d | balrog | case 0x1c: /* DEBUG_CNTR_SIG */ |
2124 | c3d2689d | balrog | OMAP_RO_REG(addr); |
2125 | c3d2689d | balrog | break;
|
2126 | c3d2689d | balrog | |
2127 | c3d2689d | balrog | default:
|
2128 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2129 | c3d2689d | balrog | } |
2130 | c3d2689d | balrog | } |
2131 | c3d2689d | balrog | |
2132 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
|
2133 | c3d2689d | balrog | omap_badwidth_read16, |
2134 | c3d2689d | balrog | omap_tipb_bridge_read, |
2135 | c3d2689d | balrog | omap_tipb_bridge_read, |
2136 | c3d2689d | balrog | }; |
2137 | c3d2689d | balrog | |
2138 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
|
2139 | c3d2689d | balrog | omap_badwidth_write16, |
2140 | c3d2689d | balrog | omap_tipb_bridge_write, |
2141 | c3d2689d | balrog | omap_tipb_bridge_write, |
2142 | c3d2689d | balrog | }; |
2143 | c3d2689d | balrog | |
2144 | c3d2689d | balrog | static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) |
2145 | c3d2689d | balrog | { |
2146 | c3d2689d | balrog | s->control = 0xffff;
|
2147 | c3d2689d | balrog | s->alloc = 0x0009;
|
2148 | c3d2689d | balrog | s->buffer = 0x0000;
|
2149 | c3d2689d | balrog | s->enh_control = 0x000f;
|
2150 | c3d2689d | balrog | } |
2151 | c3d2689d | balrog | |
2152 | c3d2689d | balrog | struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
|
2153 | c3d2689d | balrog | qemu_irq abort_irq, omap_clk clk) |
2154 | c3d2689d | balrog | { |
2155 | c3d2689d | balrog | int iomemtype;
|
2156 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) |
2157 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_tipb_bridge_s)); |
2158 | c3d2689d | balrog | |
2159 | c3d2689d | balrog | s->abort = abort_irq; |
2160 | c3d2689d | balrog | s->base = base; |
2161 | c3d2689d | balrog | omap_tipb_bridge_reset(s); |
2162 | c3d2689d | balrog | |
2163 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
|
2164 | c3d2689d | balrog | omap_tipb_bridge_writefn, s); |
2165 | c3d2689d | balrog | cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
2166 | c3d2689d | balrog | |
2167 | c3d2689d | balrog | return s;
|
2168 | c3d2689d | balrog | } |
2169 | c3d2689d | balrog | |
2170 | c3d2689d | balrog | /* Dummy Traffic Controller's Memory Interface */
|
2171 | c3d2689d | balrog | static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr) |
2172 | c3d2689d | balrog | { |
2173 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2174 | c3d2689d | balrog | int offset = addr - s->tcmi_base;
|
2175 | c3d2689d | balrog | uint32_t ret; |
2176 | c3d2689d | balrog | |
2177 | c3d2689d | balrog | switch (offset) {
|
2178 | c3d2689d | balrog | case 0xfffecc00: /* IMIF_PRIO */ |
2179 | c3d2689d | balrog | case 0xfffecc04: /* EMIFS_PRIO */ |
2180 | c3d2689d | balrog | case 0xfffecc08: /* EMIFF_PRIO */ |
2181 | c3d2689d | balrog | case 0xfffecc0c: /* EMIFS_CONFIG */ |
2182 | c3d2689d | balrog | case 0xfffecc10: /* EMIFS_CS0_CONFIG */ |
2183 | c3d2689d | balrog | case 0xfffecc14: /* EMIFS_CS1_CONFIG */ |
2184 | c3d2689d | balrog | case 0xfffecc18: /* EMIFS_CS2_CONFIG */ |
2185 | c3d2689d | balrog | case 0xfffecc1c: /* EMIFS_CS3_CONFIG */ |
2186 | c3d2689d | balrog | case 0xfffecc24: /* EMIFF_MRS */ |
2187 | c3d2689d | balrog | case 0xfffecc28: /* TIMEOUT1 */ |
2188 | c3d2689d | balrog | case 0xfffecc2c: /* TIMEOUT2 */ |
2189 | c3d2689d | balrog | case 0xfffecc30: /* TIMEOUT3 */ |
2190 | c3d2689d | balrog | case 0xfffecc3c: /* EMIFF_SDRAM_CONFIG_2 */ |
2191 | c3d2689d | balrog | case 0xfffecc40: /* EMIFS_CFG_DYN_WAIT */ |
2192 | c3d2689d | balrog | return s->tcmi_regs[offset >> 2]; |
2193 | c3d2689d | balrog | |
2194 | c3d2689d | balrog | case 0xfffecc20: /* EMIFF_SDRAM_CONFIG */ |
2195 | c3d2689d | balrog | ret = s->tcmi_regs[offset >> 2];
|
2196 | c3d2689d | balrog | s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ |
2197 | c3d2689d | balrog | /* XXX: We can try using the VGA_DIRTY flag for this */
|
2198 | c3d2689d | balrog | return ret;
|
2199 | c3d2689d | balrog | } |
2200 | c3d2689d | balrog | |
2201 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2202 | c3d2689d | balrog | return 0; |
2203 | c3d2689d | balrog | } |
2204 | c3d2689d | balrog | |
2205 | c3d2689d | balrog | static void omap_tcmi_write(void *opaque, target_phys_addr_t addr, |
2206 | c3d2689d | balrog | uint32_t value) |
2207 | c3d2689d | balrog | { |
2208 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2209 | c3d2689d | balrog | int offset = addr - s->tcmi_base;
|
2210 | c3d2689d | balrog | |
2211 | c3d2689d | balrog | switch (offset) {
|
2212 | c3d2689d | balrog | case 0xfffecc00: /* IMIF_PRIO */ |
2213 | c3d2689d | balrog | case 0xfffecc04: /* EMIFS_PRIO */ |
2214 | c3d2689d | balrog | case 0xfffecc08: /* EMIFF_PRIO */ |
2215 | c3d2689d | balrog | case 0xfffecc10: /* EMIFS_CS0_CONFIG */ |
2216 | c3d2689d | balrog | case 0xfffecc14: /* EMIFS_CS1_CONFIG */ |
2217 | c3d2689d | balrog | case 0xfffecc18: /* EMIFS_CS2_CONFIG */ |
2218 | c3d2689d | balrog | case 0xfffecc1c: /* EMIFS_CS3_CONFIG */ |
2219 | c3d2689d | balrog | case 0xfffecc20: /* EMIFF_SDRAM_CONFIG */ |
2220 | c3d2689d | balrog | case 0xfffecc24: /* EMIFF_MRS */ |
2221 | c3d2689d | balrog | case 0xfffecc28: /* TIMEOUT1 */ |
2222 | c3d2689d | balrog | case 0xfffecc2c: /* TIMEOUT2 */ |
2223 | c3d2689d | balrog | case 0xfffecc30: /* TIMEOUT3 */ |
2224 | c3d2689d | balrog | case 0xfffecc3c: /* EMIFF_SDRAM_CONFIG_2 */ |
2225 | c3d2689d | balrog | case 0xfffecc40: /* EMIFS_CFG_DYN_WAIT */ |
2226 | c3d2689d | balrog | s->tcmi_regs[offset >> 2] = value;
|
2227 | c3d2689d | balrog | break;
|
2228 | c3d2689d | balrog | case 0xfffecc0c: /* EMIFS_CONFIG */ |
2229 | c3d2689d | balrog | s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4); |
2230 | c3d2689d | balrog | break;
|
2231 | c3d2689d | balrog | |
2232 | c3d2689d | balrog | default:
|
2233 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2234 | c3d2689d | balrog | } |
2235 | c3d2689d | balrog | } |
2236 | c3d2689d | balrog | |
2237 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
|
2238 | c3d2689d | balrog | omap_badwidth_read32, |
2239 | c3d2689d | balrog | omap_badwidth_read32, |
2240 | c3d2689d | balrog | omap_tcmi_read, |
2241 | c3d2689d | balrog | }; |
2242 | c3d2689d | balrog | |
2243 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
|
2244 | c3d2689d | balrog | omap_badwidth_write32, |
2245 | c3d2689d | balrog | omap_badwidth_write32, |
2246 | c3d2689d | balrog | omap_tcmi_write, |
2247 | c3d2689d | balrog | }; |
2248 | c3d2689d | balrog | |
2249 | c3d2689d | balrog | static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) |
2250 | c3d2689d | balrog | { |
2251 | c3d2689d | balrog | mpu->tcmi_regs[0x00 >> 2] = 0x00000000; |
2252 | c3d2689d | balrog | mpu->tcmi_regs[0x04 >> 2] = 0x00000000; |
2253 | c3d2689d | balrog | mpu->tcmi_regs[0x08 >> 2] = 0x00000000; |
2254 | c3d2689d | balrog | mpu->tcmi_regs[0x0c >> 2] = 0x00000010; |
2255 | c3d2689d | balrog | mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; |
2256 | c3d2689d | balrog | mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; |
2257 | c3d2689d | balrog | mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; |
2258 | c3d2689d | balrog | mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; |
2259 | c3d2689d | balrog | mpu->tcmi_regs[0x20 >> 2] = 0x00618800; |
2260 | c3d2689d | balrog | mpu->tcmi_regs[0x24 >> 2] = 0x00000037; |
2261 | c3d2689d | balrog | mpu->tcmi_regs[0x28 >> 2] = 0x00000000; |
2262 | c3d2689d | balrog | mpu->tcmi_regs[0x2c >> 2] = 0x00000000; |
2263 | c3d2689d | balrog | mpu->tcmi_regs[0x30 >> 2] = 0x00000000; |
2264 | c3d2689d | balrog | mpu->tcmi_regs[0x3c >> 2] = 0x00000003; |
2265 | c3d2689d | balrog | mpu->tcmi_regs[0x40 >> 2] = 0x00000000; |
2266 | c3d2689d | balrog | } |
2267 | c3d2689d | balrog | |
2268 | c3d2689d | balrog | static void omap_tcmi_init(target_phys_addr_t base, |
2269 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
2270 | c3d2689d | balrog | { |
2271 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn, |
2272 | c3d2689d | balrog | omap_tcmi_writefn, mpu); |
2273 | c3d2689d | balrog | |
2274 | c3d2689d | balrog | mpu->tcmi_base = base; |
2275 | c3d2689d | balrog | cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
|
2276 | c3d2689d | balrog | omap_tcmi_reset(mpu); |
2277 | c3d2689d | balrog | } |
2278 | c3d2689d | balrog | |
2279 | c3d2689d | balrog | /* Digital phase-locked loops control */
|
2280 | c3d2689d | balrog | static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr) |
2281 | c3d2689d | balrog | { |
2282 | c3d2689d | balrog | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
2283 | c3d2689d | balrog | int offset = addr - s->base;
|
2284 | c3d2689d | balrog | |
2285 | c3d2689d | balrog | if (offset == 0x00) /* CTL_REG */ |
2286 | c3d2689d | balrog | return s->mode;
|
2287 | c3d2689d | balrog | |
2288 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2289 | c3d2689d | balrog | return 0; |
2290 | c3d2689d | balrog | } |
2291 | c3d2689d | balrog | |
2292 | c3d2689d | balrog | static void omap_dpll_write(void *opaque, target_phys_addr_t addr, |
2293 | c3d2689d | balrog | uint32_t value) |
2294 | c3d2689d | balrog | { |
2295 | c3d2689d | balrog | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
2296 | c3d2689d | balrog | uint16_t diff; |
2297 | c3d2689d | balrog | int offset = addr - s->base;
|
2298 | c3d2689d | balrog | static const int bypass_div[4] = { 1, 2, 4, 4 }; |
2299 | c3d2689d | balrog | int div, mult;
|
2300 | c3d2689d | balrog | |
2301 | c3d2689d | balrog | if (offset == 0x00) { /* CTL_REG */ |
2302 | c3d2689d | balrog | /* See omap_ulpd_pm_write() too */
|
2303 | c3d2689d | balrog | diff = s->mode & value; |
2304 | c3d2689d | balrog | s->mode = value & 0x2fff;
|
2305 | c3d2689d | balrog | if (diff & (0x3ff << 2)) { |
2306 | c3d2689d | balrog | if (value & (1 << 4)) { /* PLL_ENABLE */ |
2307 | c3d2689d | balrog | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
2308 | c3d2689d | balrog | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
2309 | c3d2689d | balrog | } else {
|
2310 | c3d2689d | balrog | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
2311 | c3d2689d | balrog | mult = 1;
|
2312 | c3d2689d | balrog | } |
2313 | c3d2689d | balrog | omap_clk_setrate(s->dpll, div, mult); |
2314 | c3d2689d | balrog | } |
2315 | c3d2689d | balrog | |
2316 | c3d2689d | balrog | /* Enter the desired mode. */
|
2317 | c3d2689d | balrog | s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); |
2318 | c3d2689d | balrog | |
2319 | c3d2689d | balrog | /* Act as if the lock is restored. */
|
2320 | c3d2689d | balrog | s->mode |= 2;
|
2321 | c3d2689d | balrog | } else {
|
2322 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2323 | c3d2689d | balrog | } |
2324 | c3d2689d | balrog | } |
2325 | c3d2689d | balrog | |
2326 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_dpll_readfn[] = {
|
2327 | c3d2689d | balrog | omap_badwidth_read16, |
2328 | c3d2689d | balrog | omap_dpll_read, |
2329 | c3d2689d | balrog | omap_badwidth_read16, |
2330 | c3d2689d | balrog | }; |
2331 | c3d2689d | balrog | |
2332 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
|
2333 | c3d2689d | balrog | omap_badwidth_write16, |
2334 | c3d2689d | balrog | omap_dpll_write, |
2335 | c3d2689d | balrog | omap_badwidth_write16, |
2336 | c3d2689d | balrog | }; |
2337 | c3d2689d | balrog | |
2338 | c3d2689d | balrog | static void omap_dpll_reset(struct dpll_ctl_s *s) |
2339 | c3d2689d | balrog | { |
2340 | c3d2689d | balrog | s->mode = 0x2002;
|
2341 | c3d2689d | balrog | omap_clk_setrate(s->dpll, 1, 1); |
2342 | c3d2689d | balrog | } |
2343 | c3d2689d | balrog | |
2344 | c3d2689d | balrog | static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base, |
2345 | c3d2689d | balrog | omap_clk clk) |
2346 | c3d2689d | balrog | { |
2347 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn, |
2348 | c3d2689d | balrog | omap_dpll_writefn, s); |
2349 | c3d2689d | balrog | |
2350 | c3d2689d | balrog | s->base = base; |
2351 | c3d2689d | balrog | s->dpll = clk; |
2352 | c3d2689d | balrog | omap_dpll_reset(s); |
2353 | c3d2689d | balrog | |
2354 | c3d2689d | balrog | cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
2355 | c3d2689d | balrog | } |
2356 | c3d2689d | balrog | |
2357 | c3d2689d | balrog | /* UARTs */
|
2358 | c3d2689d | balrog | struct omap_uart_s {
|
2359 | c3d2689d | balrog | SerialState *serial; /* TODO */
|
2360 | c3d2689d | balrog | }; |
2361 | c3d2689d | balrog | |
2362 | c3d2689d | balrog | static void omap_uart_reset(struct omap_uart_s *s) |
2363 | c3d2689d | balrog | { |
2364 | c3d2689d | balrog | } |
2365 | c3d2689d | balrog | |
2366 | c3d2689d | balrog | struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
|
2367 | c3d2689d | balrog | qemu_irq irq, omap_clk clk, CharDriverState *chr) |
2368 | c3d2689d | balrog | { |
2369 | c3d2689d | balrog | struct omap_uart_s *s = (struct omap_uart_s *) |
2370 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_uart_s)); |
2371 | c3d2689d | balrog | if (chr)
|
2372 | c3d2689d | balrog | s->serial = serial_mm_init(base, 2, irq, chr, 1); |
2373 | c3d2689d | balrog | return s;
|
2374 | c3d2689d | balrog | } |
2375 | c3d2689d | balrog | |
2376 | c3d2689d | balrog | /* MPU Clock/Reset/Power Mode Control */
|
2377 | c3d2689d | balrog | static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr) |
2378 | c3d2689d | balrog | { |
2379 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2380 | c3d2689d | balrog | int offset = addr - s->clkm.mpu_base;
|
2381 | c3d2689d | balrog | |
2382 | c3d2689d | balrog | switch (offset) {
|
2383 | c3d2689d | balrog | case 0x00: /* ARM_CKCTL */ |
2384 | c3d2689d | balrog | return s->clkm.arm_ckctl;
|
2385 | c3d2689d | balrog | |
2386 | c3d2689d | balrog | case 0x04: /* ARM_IDLECT1 */ |
2387 | c3d2689d | balrog | return s->clkm.arm_idlect1;
|
2388 | c3d2689d | balrog | |
2389 | c3d2689d | balrog | case 0x08: /* ARM_IDLECT2 */ |
2390 | c3d2689d | balrog | return s->clkm.arm_idlect2;
|
2391 | c3d2689d | balrog | |
2392 | c3d2689d | balrog | case 0x0c: /* ARM_EWUPCT */ |
2393 | c3d2689d | balrog | return s->clkm.arm_ewupct;
|
2394 | c3d2689d | balrog | |
2395 | c3d2689d | balrog | case 0x10: /* ARM_RSTCT1 */ |
2396 | c3d2689d | balrog | return s->clkm.arm_rstct1;
|
2397 | c3d2689d | balrog | |
2398 | c3d2689d | balrog | case 0x14: /* ARM_RSTCT2 */ |
2399 | c3d2689d | balrog | return s->clkm.arm_rstct2;
|
2400 | c3d2689d | balrog | |
2401 | c3d2689d | balrog | case 0x18: /* ARM_SYSST */ |
2402 | c3d2689d | balrog | return (s->clkm.clocking_scheme < 11) | s->clkm.cold_start; |
2403 | c3d2689d | balrog | |
2404 | c3d2689d | balrog | case 0x1c: /* ARM_CKOUT1 */ |
2405 | c3d2689d | balrog | return s->clkm.arm_ckout1;
|
2406 | c3d2689d | balrog | |
2407 | c3d2689d | balrog | case 0x20: /* ARM_CKOUT2 */ |
2408 | c3d2689d | balrog | break;
|
2409 | c3d2689d | balrog | } |
2410 | c3d2689d | balrog | |
2411 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2412 | c3d2689d | balrog | return 0; |
2413 | c3d2689d | balrog | } |
2414 | c3d2689d | balrog | |
2415 | c3d2689d | balrog | static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, |
2416 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2417 | c3d2689d | balrog | { |
2418 | c3d2689d | balrog | omap_clk clk; |
2419 | c3d2689d | balrog | |
2420 | c3d2689d | balrog | if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ |
2421 | c3d2689d | balrog | if (value & (1 << 14)) |
2422 | c3d2689d | balrog | /* Reserved */;
|
2423 | c3d2689d | balrog | else {
|
2424 | c3d2689d | balrog | clk = omap_findclk(s, "arminth_ck");
|
2425 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
2426 | c3d2689d | balrog | } |
2427 | c3d2689d | balrog | } |
2428 | c3d2689d | balrog | if (diff & (1 << 12)) { /* ARM_TIMXO */ |
2429 | c3d2689d | balrog | clk = omap_findclk(s, "armtim_ck");
|
2430 | c3d2689d | balrog | if (value & (1 << 12)) |
2431 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "clkin"));
|
2432 | c3d2689d | balrog | else
|
2433 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
2434 | c3d2689d | balrog | } |
2435 | c3d2689d | balrog | /* XXX: en_dspck */
|
2436 | c3d2689d | balrog | if (diff & (3 << 10)) { /* DSPMMUDIV */ |
2437 | c3d2689d | balrog | clk = omap_findclk(s, "dspmmu_ck");
|
2438 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); |
2439 | c3d2689d | balrog | } |
2440 | c3d2689d | balrog | if (diff & (3 << 8)) { /* TCDIV */ |
2441 | c3d2689d | balrog | clk = omap_findclk(s, "tc_ck");
|
2442 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); |
2443 | c3d2689d | balrog | } |
2444 | c3d2689d | balrog | if (diff & (3 << 6)) { /* DSPDIV */ |
2445 | c3d2689d | balrog | clk = omap_findclk(s, "dsp_ck");
|
2446 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); |
2447 | c3d2689d | balrog | } |
2448 | c3d2689d | balrog | if (diff & (3 << 4)) { /* ARMDIV */ |
2449 | c3d2689d | balrog | clk = omap_findclk(s, "arm_ck");
|
2450 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); |
2451 | c3d2689d | balrog | } |
2452 | c3d2689d | balrog | if (diff & (3 << 2)) { /* LCDDIV */ |
2453 | c3d2689d | balrog | clk = omap_findclk(s, "lcd_ck");
|
2454 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); |
2455 | c3d2689d | balrog | } |
2456 | c3d2689d | balrog | if (diff & (3 << 0)) { /* PERDIV */ |
2457 | c3d2689d | balrog | clk = omap_findclk(s, "armper_ck");
|
2458 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); |
2459 | c3d2689d | balrog | } |
2460 | c3d2689d | balrog | } |
2461 | c3d2689d | balrog | |
2462 | c3d2689d | balrog | static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, |
2463 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2464 | c3d2689d | balrog | { |
2465 | c3d2689d | balrog | omap_clk clk; |
2466 | c3d2689d | balrog | |
2467 | c3d2689d | balrog | if (value & (1 << 11)) /* SETARM_IDLE */ |
2468 | c3d2689d | balrog | cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
2469 | c3d2689d | balrog | if (!(value & (1 << 10))) /* WKUP_MODE */ |
2470 | c3d2689d | balrog | qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
|
2471 | c3d2689d | balrog | |
2472 | c3d2689d | balrog | #define SET_CANIDLE(clock, bit) \
|
2473 | c3d2689d | balrog | if (diff & (1 << bit)) { \ |
2474 | c3d2689d | balrog | clk = omap_findclk(s, clock); \ |
2475 | c3d2689d | balrog | omap_clk_canidle(clk, (value >> bit) & 1); \
|
2476 | c3d2689d | balrog | } |
2477 | c3d2689d | balrog | SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ |
2478 | c3d2689d | balrog | SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ |
2479 | c3d2689d | balrog | SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ |
2480 | c3d2689d | balrog | SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ |
2481 | c3d2689d | balrog | SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ |
2482 | c3d2689d | balrog | SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ |
2483 | c3d2689d | balrog | SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ |
2484 | c3d2689d | balrog | SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ |
2485 | c3d2689d | balrog | SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ |
2486 | c3d2689d | balrog | SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ |
2487 | c3d2689d | balrog | SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ |
2488 | c3d2689d | balrog | SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ |
2489 | c3d2689d | balrog | SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ |
2490 | c3d2689d | balrog | SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ |
2491 | c3d2689d | balrog | } |
2492 | c3d2689d | balrog | |
2493 | c3d2689d | balrog | static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, |
2494 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2495 | c3d2689d | balrog | { |
2496 | c3d2689d | balrog | omap_clk clk; |
2497 | c3d2689d | balrog | |
2498 | c3d2689d | balrog | #define SET_ONOFF(clock, bit) \
|
2499 | c3d2689d | balrog | if (diff & (1 << bit)) { \ |
2500 | c3d2689d | balrog | clk = omap_findclk(s, clock); \ |
2501 | c3d2689d | balrog | omap_clk_onoff(clk, (value >> bit) & 1); \
|
2502 | c3d2689d | balrog | } |
2503 | c3d2689d | balrog | SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ |
2504 | c3d2689d | balrog | SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ |
2505 | c3d2689d | balrog | SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ |
2506 | c3d2689d | balrog | SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ |
2507 | c3d2689d | balrog | SET_ONOFF("lb_ck", 4) /* EN_LBCK */ |
2508 | c3d2689d | balrog | SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ |
2509 | c3d2689d | balrog | SET_ONOFF("mpui_ck", 6) /* EN_APICK */ |
2510 | c3d2689d | balrog | SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ |
2511 | c3d2689d | balrog | SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ |
2512 | c3d2689d | balrog | SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ |
2513 | c3d2689d | balrog | SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ |
2514 | c3d2689d | balrog | } |
2515 | c3d2689d | balrog | |
2516 | c3d2689d | balrog | static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, |
2517 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2518 | c3d2689d | balrog | { |
2519 | c3d2689d | balrog | omap_clk clk; |
2520 | c3d2689d | balrog | |
2521 | c3d2689d | balrog | if (diff & (3 << 4)) { /* TCLKOUT */ |
2522 | c3d2689d | balrog | clk = omap_findclk(s, "tclk_out");
|
2523 | c3d2689d | balrog | switch ((value >> 4) & 3) { |
2524 | c3d2689d | balrog | case 1: |
2525 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
|
2526 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2527 | c3d2689d | balrog | break;
|
2528 | c3d2689d | balrog | case 2: |
2529 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
2530 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2531 | c3d2689d | balrog | break;
|
2532 | c3d2689d | balrog | default:
|
2533 | c3d2689d | balrog | omap_clk_onoff(clk, 0);
|
2534 | c3d2689d | balrog | } |
2535 | c3d2689d | balrog | } |
2536 | c3d2689d | balrog | if (diff & (3 << 2)) { /* DCLKOUT */ |
2537 | c3d2689d | balrog | clk = omap_findclk(s, "dclk_out");
|
2538 | c3d2689d | balrog | switch ((value >> 2) & 3) { |
2539 | c3d2689d | balrog | case 0: |
2540 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
|
2541 | c3d2689d | balrog | break;
|
2542 | c3d2689d | balrog | case 1: |
2543 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
|
2544 | c3d2689d | balrog | break;
|
2545 | c3d2689d | balrog | case 2: |
2546 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
|
2547 | c3d2689d | balrog | break;
|
2548 | c3d2689d | balrog | case 3: |
2549 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
2550 | c3d2689d | balrog | break;
|
2551 | c3d2689d | balrog | } |
2552 | c3d2689d | balrog | } |
2553 | c3d2689d | balrog | if (diff & (3 << 0)) { /* ACLKOUT */ |
2554 | c3d2689d | balrog | clk = omap_findclk(s, "aclk_out");
|
2555 | c3d2689d | balrog | switch ((value >> 0) & 3) { |
2556 | c3d2689d | balrog | case 1: |
2557 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
2558 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2559 | c3d2689d | balrog | break;
|
2560 | c3d2689d | balrog | case 2: |
2561 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
|
2562 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2563 | c3d2689d | balrog | break;
|
2564 | c3d2689d | balrog | case 3: |
2565 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
2566 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2567 | c3d2689d | balrog | break;
|
2568 | c3d2689d | balrog | default:
|
2569 | c3d2689d | balrog | omap_clk_onoff(clk, 0);
|
2570 | c3d2689d | balrog | } |
2571 | c3d2689d | balrog | } |
2572 | c3d2689d | balrog | } |
2573 | c3d2689d | balrog | |
2574 | c3d2689d | balrog | static void omap_clkm_write(void *opaque, target_phys_addr_t addr, |
2575 | c3d2689d | balrog | uint32_t value) |
2576 | c3d2689d | balrog | { |
2577 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2578 | c3d2689d | balrog | int offset = addr - s->clkm.mpu_base;
|
2579 | c3d2689d | balrog | uint16_t diff; |
2580 | c3d2689d | balrog | omap_clk clk; |
2581 | c3d2689d | balrog | static const char *clkschemename[8] = { |
2582 | c3d2689d | balrog | "fully synchronous", "fully asynchronous", "synchronous scalable", |
2583 | c3d2689d | balrog | "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", |
2584 | c3d2689d | balrog | }; |
2585 | c3d2689d | balrog | |
2586 | c3d2689d | balrog | switch (offset) {
|
2587 | c3d2689d | balrog | case 0x00: /* ARM_CKCTL */ |
2588 | c3d2689d | balrog | diff = s->clkm.arm_ckctl ^ value; |
2589 | c3d2689d | balrog | s->clkm.arm_ckctl = value & 0x7fff;
|
2590 | c3d2689d | balrog | omap_clkm_ckctl_update(s, diff, value); |
2591 | c3d2689d | balrog | return;
|
2592 | c3d2689d | balrog | |
2593 | c3d2689d | balrog | case 0x04: /* ARM_IDLECT1 */ |
2594 | c3d2689d | balrog | diff = s->clkm.arm_idlect1 ^ value; |
2595 | c3d2689d | balrog | s->clkm.arm_idlect1 = value & 0x0fff;
|
2596 | c3d2689d | balrog | omap_clkm_idlect1_update(s, diff, value); |
2597 | c3d2689d | balrog | return;
|
2598 | c3d2689d | balrog | |
2599 | c3d2689d | balrog | case 0x08: /* ARM_IDLECT2 */ |
2600 | c3d2689d | balrog | diff = s->clkm.arm_idlect2 ^ value; |
2601 | c3d2689d | balrog | s->clkm.arm_idlect2 = value & 0x07ff;
|
2602 | c3d2689d | balrog | omap_clkm_idlect2_update(s, diff, value); |
2603 | c3d2689d | balrog | return;
|
2604 | c3d2689d | balrog | |
2605 | c3d2689d | balrog | case 0x0c: /* ARM_EWUPCT */ |
2606 | c3d2689d | balrog | diff = s->clkm.arm_ewupct ^ value; |
2607 | c3d2689d | balrog | s->clkm.arm_ewupct = value & 0x003f;
|
2608 | c3d2689d | balrog | return;
|
2609 | c3d2689d | balrog | |
2610 | c3d2689d | balrog | case 0x10: /* ARM_RSTCT1 */ |
2611 | c3d2689d | balrog | diff = s->clkm.arm_rstct1 ^ value; |
2612 | c3d2689d | balrog | s->clkm.arm_rstct1 = value & 0x0007;
|
2613 | c3d2689d | balrog | if (value & 9) { |
2614 | c3d2689d | balrog | qemu_system_reset_request(); |
2615 | c3d2689d | balrog | s->clkm.cold_start = 0xa;
|
2616 | c3d2689d | balrog | } |
2617 | c3d2689d | balrog | if (diff & ~value & 4) { /* DSP_RST */ |
2618 | c3d2689d | balrog | omap_mpui_reset(s); |
2619 | c3d2689d | balrog | omap_tipb_bridge_reset(s->private_tipb); |
2620 | c3d2689d | balrog | omap_tipb_bridge_reset(s->public_tipb); |
2621 | c3d2689d | balrog | } |
2622 | c3d2689d | balrog | if (diff & 2) { /* DSP_EN */ |
2623 | c3d2689d | balrog | clk = omap_findclk(s, "dsp_ck");
|
2624 | c3d2689d | balrog | omap_clk_canidle(clk, (~value >> 1) & 1); |
2625 | c3d2689d | balrog | } |
2626 | c3d2689d | balrog | return;
|
2627 | c3d2689d | balrog | |
2628 | c3d2689d | balrog | case 0x14: /* ARM_RSTCT2 */ |
2629 | c3d2689d | balrog | s->clkm.arm_rstct2 = value & 0x0001;
|
2630 | c3d2689d | balrog | return;
|
2631 | c3d2689d | balrog | |
2632 | c3d2689d | balrog | case 0x18: /* ARM_SYSST */ |
2633 | c3d2689d | balrog | if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { |
2634 | c3d2689d | balrog | s->clkm.clocking_scheme = (value >> 11) & 7; |
2635 | c3d2689d | balrog | printf("%s: clocking scheme set to %s\n", __FUNCTION__,
|
2636 | c3d2689d | balrog | clkschemename[s->clkm.clocking_scheme]); |
2637 | c3d2689d | balrog | } |
2638 | c3d2689d | balrog | s->clkm.cold_start &= value & 0x3f;
|
2639 | c3d2689d | balrog | return;
|
2640 | c3d2689d | balrog | |
2641 | c3d2689d | balrog | case 0x1c: /* ARM_CKOUT1 */ |
2642 | c3d2689d | balrog | diff = s->clkm.arm_ckout1 ^ value; |
2643 | c3d2689d | balrog | s->clkm.arm_ckout1 = value & 0x003f;
|
2644 | c3d2689d | balrog | omap_clkm_ckout1_update(s, diff, value); |
2645 | c3d2689d | balrog | return;
|
2646 | c3d2689d | balrog | |
2647 | c3d2689d | balrog | case 0x20: /* ARM_CKOUT2 */ |
2648 | c3d2689d | balrog | default:
|
2649 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2650 | c3d2689d | balrog | } |
2651 | c3d2689d | balrog | } |
2652 | c3d2689d | balrog | |
2653 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_clkm_readfn[] = {
|
2654 | c3d2689d | balrog | omap_badwidth_read16, |
2655 | c3d2689d | balrog | omap_clkm_read, |
2656 | c3d2689d | balrog | omap_badwidth_read16, |
2657 | c3d2689d | balrog | }; |
2658 | c3d2689d | balrog | |
2659 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
|
2660 | c3d2689d | balrog | omap_badwidth_write16, |
2661 | c3d2689d | balrog | omap_clkm_write, |
2662 | c3d2689d | balrog | omap_badwidth_write16, |
2663 | c3d2689d | balrog | }; |
2664 | c3d2689d | balrog | |
2665 | c3d2689d | balrog | static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr) |
2666 | c3d2689d | balrog | { |
2667 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2668 | c3d2689d | balrog | int offset = addr - s->clkm.dsp_base;
|
2669 | c3d2689d | balrog | |
2670 | c3d2689d | balrog | switch (offset) {
|
2671 | c3d2689d | balrog | case 0x04: /* DSP_IDLECT1 */ |
2672 | c3d2689d | balrog | return s->clkm.dsp_idlect1;
|
2673 | c3d2689d | balrog | |
2674 | c3d2689d | balrog | case 0x08: /* DSP_IDLECT2 */ |
2675 | c3d2689d | balrog | return s->clkm.dsp_idlect2;
|
2676 | c3d2689d | balrog | |
2677 | c3d2689d | balrog | case 0x14: /* DSP_RSTCT2 */ |
2678 | c3d2689d | balrog | return s->clkm.dsp_rstct2;
|
2679 | c3d2689d | balrog | |
2680 | c3d2689d | balrog | case 0x18: /* DSP_SYSST */ |
2681 | c3d2689d | balrog | return (s->clkm.clocking_scheme < 11) | s->clkm.cold_start | |
2682 | c3d2689d | balrog | (s->env->halted << 6); /* Quite useless... */ |
2683 | c3d2689d | balrog | } |
2684 | c3d2689d | balrog | |
2685 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2686 | c3d2689d | balrog | return 0; |
2687 | c3d2689d | balrog | } |
2688 | c3d2689d | balrog | |
2689 | c3d2689d | balrog | static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, |
2690 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2691 | c3d2689d | balrog | { |
2692 | c3d2689d | balrog | omap_clk clk; |
2693 | c3d2689d | balrog | |
2694 | c3d2689d | balrog | SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ |
2695 | c3d2689d | balrog | } |
2696 | c3d2689d | balrog | |
2697 | c3d2689d | balrog | static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, |
2698 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2699 | c3d2689d | balrog | { |
2700 | c3d2689d | balrog | omap_clk clk; |
2701 | c3d2689d | balrog | |
2702 | c3d2689d | balrog | SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ |
2703 | c3d2689d | balrog | } |
2704 | c3d2689d | balrog | |
2705 | c3d2689d | balrog | static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr, |
2706 | c3d2689d | balrog | uint32_t value) |
2707 | c3d2689d | balrog | { |
2708 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2709 | c3d2689d | balrog | int offset = addr - s->clkm.dsp_base;
|
2710 | c3d2689d | balrog | uint16_t diff; |
2711 | c3d2689d | balrog | |
2712 | c3d2689d | balrog | switch (offset) {
|
2713 | c3d2689d | balrog | case 0x04: /* DSP_IDLECT1 */ |
2714 | c3d2689d | balrog | diff = s->clkm.dsp_idlect1 ^ value; |
2715 | c3d2689d | balrog | s->clkm.dsp_idlect1 = value & 0x01f7;
|
2716 | c3d2689d | balrog | omap_clkdsp_idlect1_update(s, diff, value); |
2717 | c3d2689d | balrog | break;
|
2718 | c3d2689d | balrog | |
2719 | c3d2689d | balrog | case 0x08: /* DSP_IDLECT2 */ |
2720 | c3d2689d | balrog | s->clkm.dsp_idlect2 = value & 0x0037;
|
2721 | c3d2689d | balrog | diff = s->clkm.dsp_idlect1 ^ value; |
2722 | c3d2689d | balrog | omap_clkdsp_idlect2_update(s, diff, value); |
2723 | c3d2689d | balrog | break;
|
2724 | c3d2689d | balrog | |
2725 | c3d2689d | balrog | case 0x14: /* DSP_RSTCT2 */ |
2726 | c3d2689d | balrog | s->clkm.dsp_rstct2 = value & 0x0001;
|
2727 | c3d2689d | balrog | break;
|
2728 | c3d2689d | balrog | |
2729 | c3d2689d | balrog | case 0x18: /* DSP_SYSST */ |
2730 | c3d2689d | balrog | s->clkm.cold_start &= value & 0x3f;
|
2731 | c3d2689d | balrog | break;
|
2732 | c3d2689d | balrog | |
2733 | c3d2689d | balrog | default:
|
2734 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2735 | c3d2689d | balrog | } |
2736 | c3d2689d | balrog | } |
2737 | c3d2689d | balrog | |
2738 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
|
2739 | c3d2689d | balrog | omap_badwidth_read16, |
2740 | c3d2689d | balrog | omap_clkdsp_read, |
2741 | c3d2689d | balrog | omap_badwidth_read16, |
2742 | c3d2689d | balrog | }; |
2743 | c3d2689d | balrog | |
2744 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
|
2745 | c3d2689d | balrog | omap_badwidth_write16, |
2746 | c3d2689d | balrog | omap_clkdsp_write, |
2747 | c3d2689d | balrog | omap_badwidth_write16, |
2748 | c3d2689d | balrog | }; |
2749 | c3d2689d | balrog | |
2750 | c3d2689d | balrog | static void omap_clkm_reset(struct omap_mpu_state_s *s) |
2751 | c3d2689d | balrog | { |
2752 | c3d2689d | balrog | if (s->wdt && s->wdt->reset)
|
2753 | c3d2689d | balrog | s->clkm.cold_start = 0x6;
|
2754 | c3d2689d | balrog | s->clkm.clocking_scheme = 0;
|
2755 | c3d2689d | balrog | omap_clkm_ckctl_update(s, ~0, 0x3000); |
2756 | c3d2689d | balrog | s->clkm.arm_ckctl = 0x3000;
|
2757 | c3d2689d | balrog | omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 & 0x0400, 0x0400); |
2758 | c3d2689d | balrog | s->clkm.arm_idlect1 = 0x0400;
|
2759 | c3d2689d | balrog | omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 & 0x0100, 0x0100); |
2760 | c3d2689d | balrog | s->clkm.arm_idlect2 = 0x0100;
|
2761 | c3d2689d | balrog | s->clkm.arm_ewupct = 0x003f;
|
2762 | c3d2689d | balrog | s->clkm.arm_rstct1 = 0x0000;
|
2763 | c3d2689d | balrog | s->clkm.arm_rstct2 = 0x0000;
|
2764 | c3d2689d | balrog | s->clkm.arm_ckout1 = 0x0015;
|
2765 | c3d2689d | balrog | s->clkm.dpll1_mode = 0x2002;
|
2766 | c3d2689d | balrog | omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); |
2767 | c3d2689d | balrog | s->clkm.dsp_idlect1 = 0x0040;
|
2768 | c3d2689d | balrog | omap_clkdsp_idlect2_update(s, ~0, 0x0000); |
2769 | c3d2689d | balrog | s->clkm.dsp_idlect2 = 0x0000;
|
2770 | c3d2689d | balrog | s->clkm.dsp_rstct2 = 0x0000;
|
2771 | c3d2689d | balrog | } |
2772 | c3d2689d | balrog | |
2773 | c3d2689d | balrog | static void omap_clkm_init(target_phys_addr_t mpu_base, |
2774 | c3d2689d | balrog | target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
|
2775 | c3d2689d | balrog | { |
2776 | c3d2689d | balrog | int iomemtype[2] = { |
2777 | c3d2689d | balrog | cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
|
2778 | c3d2689d | balrog | cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
|
2779 | c3d2689d | balrog | }; |
2780 | c3d2689d | balrog | |
2781 | c3d2689d | balrog | s->clkm.mpu_base = mpu_base; |
2782 | c3d2689d | balrog | s->clkm.dsp_base = dsp_base; |
2783 | c3d2689d | balrog | s->clkm.cold_start = 0x3a;
|
2784 | c3d2689d | balrog | omap_clkm_reset(s); |
2785 | c3d2689d | balrog | |
2786 | c3d2689d | balrog | cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]); |
2787 | c3d2689d | balrog | cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]); |
2788 | c3d2689d | balrog | } |
2789 | c3d2689d | balrog | |
2790 | c3d2689d | balrog | /* General chip reset */
|
2791 | c3d2689d | balrog | static void omap_mpu_reset(void *opaque) |
2792 | c3d2689d | balrog | { |
2793 | c3d2689d | balrog | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
2794 | c3d2689d | balrog | |
2795 | c3d2689d | balrog | omap_clkm_reset(mpu); |
2796 | c3d2689d | balrog | omap_inth_reset(mpu->ih[0]);
|
2797 | c3d2689d | balrog | omap_inth_reset(mpu->ih[1]);
|
2798 | c3d2689d | balrog | omap_dma_reset(mpu->dma); |
2799 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[0]);
|
2800 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[1]);
|
2801 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[2]);
|
2802 | c3d2689d | balrog | omap_wd_timer_reset(mpu->wdt); |
2803 | c3d2689d | balrog | omap_os_timer_reset(mpu->os_timer); |
2804 | c3d2689d | balrog | omap_lcdc_reset(mpu->lcd); |
2805 | c3d2689d | balrog | omap_ulpd_pm_reset(mpu); |
2806 | c3d2689d | balrog | omap_pin_cfg_reset(mpu); |
2807 | c3d2689d | balrog | omap_mpui_reset(mpu); |
2808 | c3d2689d | balrog | omap_tipb_bridge_reset(mpu->private_tipb); |
2809 | c3d2689d | balrog | omap_tipb_bridge_reset(mpu->public_tipb); |
2810 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[0]);
|
2811 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[1]);
|
2812 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[2]);
|
2813 | c3d2689d | balrog | omap_uart_reset(mpu->uart1); |
2814 | c3d2689d | balrog | omap_uart_reset(mpu->uart2); |
2815 | c3d2689d | balrog | omap_uart_reset(mpu->uart3); |
2816 | b30bb3a2 | balrog | omap_mmc_reset(mpu->mmc); |
2817 | c3d2689d | balrog | cpu_reset(mpu->env); |
2818 | c3d2689d | balrog | } |
2819 | c3d2689d | balrog | |
2820 | c3d2689d | balrog | static void omap_mpu_wakeup(void *opaque, int irq, int req) |
2821 | c3d2689d | balrog | { |
2822 | c3d2689d | balrog | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
2823 | c3d2689d | balrog | |
2824 | c3d2689d | balrog | cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB); |
2825 | c3d2689d | balrog | } |
2826 | c3d2689d | balrog | |
2827 | c3d2689d | balrog | struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, |
2828 | c3d2689d | balrog | DisplayState *ds, const char *core) |
2829 | c3d2689d | balrog | { |
2830 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) |
2831 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_mpu_state_s)); |
2832 | c3d2689d | balrog | ram_addr_t imif_base, emiff_base; |
2833 | c3d2689d | balrog | |
2834 | c3d2689d | balrog | /* Core */
|
2835 | c3d2689d | balrog | s->mpu_model = omap310; |
2836 | c3d2689d | balrog | s->env = cpu_init(); |
2837 | c3d2689d | balrog | s->sdram_size = sdram_size; |
2838 | c3d2689d | balrog | s->sram_size = OMAP15XX_SRAM_SIZE; |
2839 | c3d2689d | balrog | |
2840 | c3d2689d | balrog | cpu_arm_set_model(s->env, core ?: "ti925t");
|
2841 | c3d2689d | balrog | |
2842 | c3d2689d | balrog | /* Clocks */
|
2843 | c3d2689d | balrog | omap_clk_init(s); |
2844 | c3d2689d | balrog | |
2845 | c3d2689d | balrog | /* Memory-mapped stuff */
|
2846 | c3d2689d | balrog | cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size, |
2847 | c3d2689d | balrog | (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM); |
2848 | c3d2689d | balrog | cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size, |
2849 | c3d2689d | balrog | (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM); |
2850 | c3d2689d | balrog | |
2851 | c3d2689d | balrog | omap_clkm_init(0xfffece00, 0xe1008000, s); |
2852 | c3d2689d | balrog | |
2853 | c3d2689d | balrog | s->ih[0] = omap_inth_init(0xfffecb00, 0x100, |
2854 | c3d2689d | balrog | arm_pic_init_cpu(s->env), |
2855 | c3d2689d | balrog | omap_findclk(s, "arminth_ck"));
|
2856 | c3d2689d | balrog | s->ih[1] = omap_inth_init(0xfffe0000, 0x800, |
2857 | c3d2689d | balrog | &s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ],
|
2858 | c3d2689d | balrog | omap_findclk(s, "arminth_ck"));
|
2859 | c3d2689d | balrog | s->irq[0] = s->ih[0]->pins; |
2860 | c3d2689d | balrog | s->irq[1] = s->ih[1]->pins; |
2861 | c3d2689d | balrog | |
2862 | c3d2689d | balrog | s->dma = omap_dma_init(0xfffed800, s->irq[0], s, |
2863 | c3d2689d | balrog | omap_findclk(s, "dma_ck"));
|
2864 | c3d2689d | balrog | s->port[emiff ].addr_valid = omap_validate_emiff_addr; |
2865 | c3d2689d | balrog | s->port[emifs ].addr_valid = omap_validate_emifs_addr; |
2866 | c3d2689d | balrog | s->port[imif ].addr_valid = omap_validate_imif_addr; |
2867 | c3d2689d | balrog | s->port[tipb ].addr_valid = omap_validate_tipb_addr; |
2868 | c3d2689d | balrog | s->port[local ].addr_valid = omap_validate_local_addr; |
2869 | c3d2689d | balrog | s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; |
2870 | c3d2689d | balrog | |
2871 | c3d2689d | balrog | s->timer[0] = omap_mpu_timer_init(0xfffec500, |
2872 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER1],
|
2873 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
2874 | c3d2689d | balrog | s->timer[1] = omap_mpu_timer_init(0xfffec600, |
2875 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER2],
|
2876 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
2877 | c3d2689d | balrog | s->timer[2] = omap_mpu_timer_init(0xfffec700, |
2878 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER3],
|
2879 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
2880 | c3d2689d | balrog | |
2881 | c3d2689d | balrog | s->wdt = omap_wd_timer_init(0xfffec800,
|
2882 | c3d2689d | balrog | s->irq[0][OMAP_INT_WD_TIMER],
|
2883 | c3d2689d | balrog | omap_findclk(s, "armwdt_ck"));
|
2884 | c3d2689d | balrog | |
2885 | c3d2689d | balrog | s->os_timer = omap_os_timer_init(0xfffb9000,
|
2886 | c3d2689d | balrog | s->irq[1][OMAP_INT_OS_TIMER],
|
2887 | c3d2689d | balrog | omap_findclk(s, "clk32-kHz"));
|
2888 | c3d2689d | balrog | |
2889 | c3d2689d | balrog | s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL], |
2890 | c3d2689d | balrog | &s->dma->lcd_ch, ds, imif_base, emiff_base, |
2891 | c3d2689d | balrog | omap_findclk(s, "lcd_ck"));
|
2892 | c3d2689d | balrog | |
2893 | c3d2689d | balrog | omap_ulpd_pm_init(0xfffe0800, s);
|
2894 | c3d2689d | balrog | omap_pin_cfg_init(0xfffe1000, s);
|
2895 | c3d2689d | balrog | omap_id_init(s); |
2896 | c3d2689d | balrog | |
2897 | c3d2689d | balrog | omap_mpui_init(0xfffec900, s);
|
2898 | c3d2689d | balrog | |
2899 | c3d2689d | balrog | s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
|
2900 | c3d2689d | balrog | s->irq[0][OMAP_INT_BRIDGE_PRIV],
|
2901 | c3d2689d | balrog | omap_findclk(s, "tipb_ck"));
|
2902 | c3d2689d | balrog | s->public_tipb = omap_tipb_bridge_init(0xfffed300,
|
2903 | c3d2689d | balrog | s->irq[0][OMAP_INT_BRIDGE_PUB],
|
2904 | c3d2689d | balrog | omap_findclk(s, "tipb_ck"));
|
2905 | c3d2689d | balrog | |
2906 | c3d2689d | balrog | omap_tcmi_init(0xfffecc00, s);
|
2907 | c3d2689d | balrog | |
2908 | c3d2689d | balrog | s->uart1 = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1], |
2909 | c3d2689d | balrog | omap_findclk(s, "uart1_ck"),
|
2910 | c3d2689d | balrog | serial_hds[0]);
|
2911 | c3d2689d | balrog | s->uart2 = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2], |
2912 | c3d2689d | balrog | omap_findclk(s, "uart2_ck"),
|
2913 | c3d2689d | balrog | serial_hds[0] ? serial_hds[1] : 0); |
2914 | c3d2689d | balrog | s->uart3 = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3], |
2915 | c3d2689d | balrog | omap_findclk(s, "uart3_ck"),
|
2916 | c3d2689d | balrog | serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0); |
2917 | c3d2689d | balrog | |
2918 | c3d2689d | balrog | omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1")); |
2919 | c3d2689d | balrog | omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2")); |
2920 | c3d2689d | balrog | omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3")); |
2921 | c3d2689d | balrog | |
2922 | b30bb3a2 | balrog | s->mmc = omap_mmc_init(0xfffb7800, s->irq[1][OMAP_INT_OQN], |
2923 | b30bb3a2 | balrog | &s->drq[OMAP_DMA_MMC_TX], omap_findclk(s, "mmc_ck"));
|
2924 | b30bb3a2 | balrog | |
2925 | c3d2689d | balrog | qemu_register_reset(omap_mpu_reset, s); |
2926 | c3d2689d | balrog | s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; |
2927 | c3d2689d | balrog | |
2928 | c3d2689d | balrog | return s;
|
2929 | c3d2689d | balrog | } |