root / hw / ppc405.h @ 4118a970
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1 | 04f20795 | j_mayer | /*
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2 | 04f20795 | j_mayer | * QEMU PowerPC 405 shared definitions
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3 | 5fafdf24 | ths | *
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4 | 04f20795 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | 04f20795 | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 04f20795 | j_mayer | * of this software and associated documentation files (the "Software"), to deal
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8 | 04f20795 | j_mayer | * in the Software without restriction, including without limitation the rights
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9 | 04f20795 | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 04f20795 | j_mayer | * copies of the Software, and to permit persons to whom the Software is
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11 | 04f20795 | j_mayer | * furnished to do so, subject to the following conditions:
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12 | 04f20795 | j_mayer | *
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13 | 04f20795 | j_mayer | * The above copyright notice and this permission notice shall be included in
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14 | 04f20795 | j_mayer | * all copies or substantial portions of the Software.
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15 | 04f20795 | j_mayer | *
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16 | 04f20795 | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 04f20795 | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 04f20795 | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 04f20795 | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 04f20795 | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 04f20795 | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 04f20795 | j_mayer | * THE SOFTWARE.
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23 | 04f20795 | j_mayer | */
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24 | 04f20795 | j_mayer | |
25 | 04f20795 | j_mayer | #if !defined(PPC_405_H)
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26 | 04f20795 | j_mayer | #define PPC_405_H
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27 | 04f20795 | j_mayer | |
28 | 04f20795 | j_mayer | /* Bootinfo as set-up by u-boot */
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29 | 04f20795 | j_mayer | typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t; |
30 | 04f20795 | j_mayer | struct ppc4xx_bd_info_t {
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31 | 04f20795 | j_mayer | uint32_t bi_memstart; |
32 | 04f20795 | j_mayer | uint32_t bi_memsize; |
33 | 04f20795 | j_mayer | uint32_t bi_flashstart; |
34 | 04f20795 | j_mayer | uint32_t bi_flashsize; |
35 | 04f20795 | j_mayer | uint32_t bi_flashoffset; /* 0x10 */
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36 | 04f20795 | j_mayer | uint32_t bi_sramstart; |
37 | 04f20795 | j_mayer | uint32_t bi_sramsize; |
38 | 04f20795 | j_mayer | uint32_t bi_bootflags; |
39 | 04f20795 | j_mayer | uint32_t bi_ipaddr; /* 0x20 */
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40 | 04f20795 | j_mayer | uint8_t bi_enetaddr[6];
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41 | 04f20795 | j_mayer | uint16_t bi_ethspeed; |
42 | 04f20795 | j_mayer | uint32_t bi_intfreq; |
43 | 04f20795 | j_mayer | uint32_t bi_busfreq; /* 0x30 */
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44 | 04f20795 | j_mayer | uint32_t bi_baudrate; |
45 | 04f20795 | j_mayer | uint8_t bi_s_version[4];
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46 | 04f20795 | j_mayer | uint8_t bi_r_version[32];
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47 | 04f20795 | j_mayer | uint32_t bi_procfreq; |
48 | 04f20795 | j_mayer | uint32_t bi_plb_busfreq; |
49 | 04f20795 | j_mayer | uint32_t bi_pci_busfreq; |
50 | 04f20795 | j_mayer | uint8_t bi_pci_enetaddr[6];
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51 | 04f20795 | j_mayer | uint32_t bi_pci_enetaddr2[6];
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52 | 04f20795 | j_mayer | uint32_t bi_opbfreq; |
53 | 04f20795 | j_mayer | uint32_t bi_iic_fast[2];
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54 | 04f20795 | j_mayer | }; |
55 | 04f20795 | j_mayer | |
56 | 04f20795 | j_mayer | /* PowerPC 405 core */
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57 | 04f20795 | j_mayer | CPUState *ppc405_init (const unsigned char *cpu_model, |
58 | 04f20795 | j_mayer | clk_setup_t *cpu_clk, clk_setup_t *tb_clk, |
59 | 04f20795 | j_mayer | uint32_t sysclk); |
60 | b8d3f5d1 | j_mayer | ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, |
61 | b8d3f5d1 | j_mayer | uint32_t flags); |
62 | 04f20795 | j_mayer | |
63 | 04f20795 | j_mayer | /* */
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64 | 04f20795 | j_mayer | typedef struct ppc4xx_mmio_t ppc4xx_mmio_t; |
65 | 04f20795 | j_mayer | int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
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66 | 9c02f1a2 | j_mayer | target_phys_addr_t offset, uint32_t len, |
67 | 04f20795 | j_mayer | CPUReadMemoryFunc **mem_read, |
68 | 04f20795 | j_mayer | CPUWriteMemoryFunc **mem_write, void *opaque);
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69 | 9c02f1a2 | j_mayer | ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base); |
70 | 04f20795 | j_mayer | /* PowerPC 4xx peripheral local bus arbitrer */
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71 | 04f20795 | j_mayer | void ppc4xx_plb_init (CPUState *env);
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72 | 04f20795 | j_mayer | /* PLB to OPB bridge */
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73 | 04f20795 | j_mayer | void ppc4xx_pob_init (CPUState *env);
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74 | 04f20795 | j_mayer | /* OPB arbitrer */
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75 | 9c02f1a2 | j_mayer | void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
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76 | 9c02f1a2 | j_mayer | target_phys_addr_t offset); |
77 | 04f20795 | j_mayer | /* PowerPC 4xx universal interrupt controller */
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78 | 04f20795 | j_mayer | enum {
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79 | 04f20795 | j_mayer | PPCUIC_OUTPUT_INT = 0,
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80 | 04f20795 | j_mayer | PPCUIC_OUTPUT_CINT = 1,
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81 | 04f20795 | j_mayer | PPCUIC_OUTPUT_NB, |
82 | 04f20795 | j_mayer | }; |
83 | 04f20795 | j_mayer | qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, |
84 | 04f20795 | j_mayer | uint32_t dcr_base, int has_ssr, int has_vr); |
85 | 04f20795 | j_mayer | /* SDRAM controller */
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86 | 04f20795 | j_mayer | void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, |
87 | 71db710f | blueswir1 | target_phys_addr_t *ram_bases, |
88 | 71db710f | blueswir1 | target_phys_addr_t *ram_sizes, |
89 | 04f20795 | j_mayer | int do_init);
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90 | 04f20795 | j_mayer | /* Peripheral controller */
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91 | 04f20795 | j_mayer | void ppc405_ebc_init (CPUState *env);
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92 | 04f20795 | j_mayer | /* DMA controller */
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93 | 04f20795 | j_mayer | void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]); |
94 | 04f20795 | j_mayer | /* GPIO */
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95 | 9c02f1a2 | j_mayer | void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
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96 | 9c02f1a2 | j_mayer | target_phys_addr_t offset); |
97 | 04f20795 | j_mayer | /* Serial ports */
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98 | 04f20795 | j_mayer | void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
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99 | 9c02f1a2 | j_mayer | target_phys_addr_t offset, qemu_irq irq, |
100 | 04f20795 | j_mayer | CharDriverState *chr); |
101 | 04f20795 | j_mayer | /* On Chip Memory */
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102 | 04f20795 | j_mayer | void ppc405_ocm_init (CPUState *env, unsigned long offset); |
103 | 04f20795 | j_mayer | /* I2C controller */
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104 | 9c02f1a2 | j_mayer | void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
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105 | 9c02f1a2 | j_mayer | target_phys_addr_t offset, qemu_irq irq); |
106 | 9c02f1a2 | j_mayer | /* General purpose timers */
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107 | 9c02f1a2 | j_mayer | void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
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108 | 9c02f1a2 | j_mayer | target_phys_addr_t offset, qemu_irq irq[5]);
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109 | 9c02f1a2 | j_mayer | /* Memory access layer */
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110 | 9c02f1a2 | j_mayer | void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]); |
111 | 04f20795 | j_mayer | /* PowerPC 405 microcontrollers */
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112 | 71db710f | blueswir1 | CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
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113 | 71db710f | blueswir1 | target_phys_addr_t ram_sizes[4],
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114 | 04f20795 | j_mayer | uint32_t sysclk, qemu_irq **picp, |
115 | 04f20795 | j_mayer | ram_addr_t *offsetp, int do_init);
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116 | 71db710f | blueswir1 | CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
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117 | 71db710f | blueswir1 | target_phys_addr_t ram_sizes[2],
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118 | 04f20795 | j_mayer | uint32_t sysclk, qemu_irq **picp, |
119 | 04f20795 | j_mayer | ram_addr_t *offsetp, int do_init);
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120 | 04f20795 | j_mayer | /* IBM STBxxx microcontrollers */
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121 | 71db710f | blueswir1 | CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2],
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122 | 71db710f | blueswir1 | target_phys_addr_t ram_sizes[2],
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123 | 04f20795 | j_mayer | uint32_t sysclk, qemu_irq **picp, |
124 | 04f20795 | j_mayer | ram_addr_t *offsetp); |
125 | 04f20795 | j_mayer | |
126 | 04f20795 | j_mayer | #endif /* !defined(PPC_405_H) */ |