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1 | 420557e8 | bellard | /*
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2 | 6f7e9aec | bellard | * QEMU TCX Frame buffer
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3 | 5fafdf24 | ths | *
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4 | 6f7e9aec | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 420557e8 | bellard | #include "vl.h" |
25 | 94470844 | blueswir1 | #include "pixel_ops.h" |
26 | 420557e8 | bellard | |
27 | 420557e8 | bellard | #define MAXX 1024 |
28 | 420557e8 | bellard | #define MAXY 768 |
29 | 6f7e9aec | bellard | #define TCX_DAC_NREGS 16 |
30 | 8508b89e | blueswir1 | #define TCX_THC_NREGS_8 0x081c |
31 | 8508b89e | blueswir1 | #define TCX_THC_NREGS_24 0x1000 |
32 | 8508b89e | blueswir1 | #define TCX_TEC_NREGS 0x1000 |
33 | 420557e8 | bellard | |
34 | 420557e8 | bellard | typedef struct TCXState { |
35 | 5dcb6b91 | blueswir1 | target_phys_addr_t addr; |
36 | 420557e8 | bellard | DisplayState *ds; |
37 | 8d5f07fa | bellard | uint8_t *vram; |
38 | eee0b836 | blueswir1 | uint32_t *vram24, *cplane; |
39 | eee0b836 | blueswir1 | ram_addr_t vram_offset, vram24_offset, cplane_offset; |
40 | eee0b836 | blueswir1 | uint16_t width, height, depth; |
41 | e80cfcfc | bellard | uint8_t r[256], g[256], b[256]; |
42 | 21206a10 | bellard | uint32_t palette[256];
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43 | 6f7e9aec | bellard | uint8_t dac_index, dac_state; |
44 | 420557e8 | bellard | } TCXState; |
45 | 420557e8 | bellard | |
46 | 95219897 | pbrook | static void tcx_screen_dump(void *opaque, const char *filename); |
47 | eee0b836 | blueswir1 | static void tcx24_screen_dump(void *opaque, const char *filename); |
48 | 97e7df27 | blueswir1 | static void tcx_invalidate_display(void *opaque); |
49 | 97e7df27 | blueswir1 | static void tcx24_invalidate_display(void *opaque); |
50 | 95219897 | pbrook | |
51 | 21206a10 | bellard | static void update_palette_entries(TCXState *s, int start, int end) |
52 | 21206a10 | bellard | { |
53 | 21206a10 | bellard | int i;
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54 | 21206a10 | bellard | for(i = start; i < end; i++) {
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55 | 21206a10 | bellard | switch(s->ds->depth) {
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56 | 21206a10 | bellard | default:
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57 | 21206a10 | bellard | case 8: |
58 | 21206a10 | bellard | s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); |
59 | 21206a10 | bellard | break;
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60 | 21206a10 | bellard | case 15: |
61 | b29169d2 | blueswir1 | if (s->ds->bgr)
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62 | b29169d2 | blueswir1 | s->palette[i] = rgb_to_pixel15bgr(s->r[i], s->g[i], s->b[i]); |
63 | b29169d2 | blueswir1 | else
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64 | b29169d2 | blueswir1 | s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); |
65 | 21206a10 | bellard | break;
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66 | 21206a10 | bellard | case 16: |
67 | b29169d2 | blueswir1 | if (s->ds->bgr)
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68 | b29169d2 | blueswir1 | s->palette[i] = rgb_to_pixel16bgr(s->r[i], s->g[i], s->b[i]); |
69 | b29169d2 | blueswir1 | else
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70 | b29169d2 | blueswir1 | s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); |
71 | 21206a10 | bellard | break;
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72 | 21206a10 | bellard | case 32: |
73 | b29169d2 | blueswir1 | if (s->ds->bgr)
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74 | b29169d2 | blueswir1 | s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); |
75 | b29169d2 | blueswir1 | else
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76 | b29169d2 | blueswir1 | s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); |
77 | 21206a10 | bellard | break;
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78 | 21206a10 | bellard | } |
79 | 21206a10 | bellard | } |
80 | 97e7df27 | blueswir1 | if (s->depth == 24) |
81 | 97e7df27 | blueswir1 | tcx24_invalidate_display(s); |
82 | 97e7df27 | blueswir1 | else
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83 | 97e7df27 | blueswir1 | tcx_invalidate_display(s); |
84 | 21206a10 | bellard | } |
85 | 21206a10 | bellard | |
86 | 5fafdf24 | ths | static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
87 | e80cfcfc | bellard | const uint8_t *s, int width) |
88 | 420557e8 | bellard | { |
89 | e80cfcfc | bellard | int x;
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90 | e80cfcfc | bellard | uint8_t val; |
91 | 8bdc2159 | ths | uint32_t *p = (uint32_t *)d; |
92 | e80cfcfc | bellard | |
93 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
94 | e80cfcfc | bellard | val = *s++; |
95 | 8bdc2159 | ths | *p++ = s1->palette[val]; |
96 | e80cfcfc | bellard | } |
97 | 420557e8 | bellard | } |
98 | 420557e8 | bellard | |
99 | 5fafdf24 | ths | static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
100 | e80cfcfc | bellard | const uint8_t *s, int width) |
101 | e80cfcfc | bellard | { |
102 | e80cfcfc | bellard | int x;
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103 | e80cfcfc | bellard | uint8_t val; |
104 | 8bdc2159 | ths | uint16_t *p = (uint16_t *)d; |
105 | 8d5f07fa | bellard | |
106 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
107 | e80cfcfc | bellard | val = *s++; |
108 | 8bdc2159 | ths | *p++ = s1->palette[val]; |
109 | e80cfcfc | bellard | } |
110 | e80cfcfc | bellard | } |
111 | e80cfcfc | bellard | |
112 | 5fafdf24 | ths | static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
113 | e80cfcfc | bellard | const uint8_t *s, int width) |
114 | 420557e8 | bellard | { |
115 | e80cfcfc | bellard | int x;
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116 | e80cfcfc | bellard | uint8_t val; |
117 | e80cfcfc | bellard | |
118 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
119 | e80cfcfc | bellard | val = *s++; |
120 | 21206a10 | bellard | *d++ = s1->palette[val]; |
121 | 420557e8 | bellard | } |
122 | 420557e8 | bellard | } |
123 | 420557e8 | bellard | |
124 | eee0b836 | blueswir1 | static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
125 | eee0b836 | blueswir1 | const uint8_t *s, int width, |
126 | eee0b836 | blueswir1 | const uint32_t *cplane,
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127 | eee0b836 | blueswir1 | const uint32_t *s24)
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128 | eee0b836 | blueswir1 | { |
129 | eee0b836 | blueswir1 | int x;
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130 | eee0b836 | blueswir1 | uint8_t val; |
131 | eee0b836 | blueswir1 | uint32_t *p = (uint32_t *)d; |
132 | eee0b836 | blueswir1 | uint32_t dval; |
133 | eee0b836 | blueswir1 | |
134 | eee0b836 | blueswir1 | for(x = 0; x < width; x++, s++, s24++) { |
135 | eee0b836 | blueswir1 | if ((bswap32(*cplane++) & 0xff000000) == 0x03000000) { // 24-bit direct |
136 | eee0b836 | blueswir1 | dval = bswap32(*s24) & 0x00ffffff;
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137 | eee0b836 | blueswir1 | } else {
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138 | eee0b836 | blueswir1 | val = *s; |
139 | eee0b836 | blueswir1 | dval = s1->palette[val]; |
140 | eee0b836 | blueswir1 | } |
141 | eee0b836 | blueswir1 | *p++ = dval; |
142 | eee0b836 | blueswir1 | } |
143 | eee0b836 | blueswir1 | } |
144 | eee0b836 | blueswir1 | |
145 | eee0b836 | blueswir1 | static inline int check_dirty(TCXState *ts, ram_addr_t page, ram_addr_t page24, |
146 | eee0b836 | blueswir1 | ram_addr_t cpage) |
147 | eee0b836 | blueswir1 | { |
148 | eee0b836 | blueswir1 | int ret;
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149 | eee0b836 | blueswir1 | unsigned int off; |
150 | eee0b836 | blueswir1 | |
151 | eee0b836 | blueswir1 | ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG); |
152 | eee0b836 | blueswir1 | for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) { |
153 | eee0b836 | blueswir1 | ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG); |
154 | eee0b836 | blueswir1 | ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG); |
155 | eee0b836 | blueswir1 | } |
156 | eee0b836 | blueswir1 | return ret;
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157 | eee0b836 | blueswir1 | } |
158 | eee0b836 | blueswir1 | |
159 | eee0b836 | blueswir1 | static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, |
160 | eee0b836 | blueswir1 | ram_addr_t page_max, ram_addr_t page24, |
161 | eee0b836 | blueswir1 | ram_addr_t cpage) |
162 | eee0b836 | blueswir1 | { |
163 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
164 | eee0b836 | blueswir1 | VGA_DIRTY_FLAG); |
165 | eee0b836 | blueswir1 | page_min -= ts->vram_offset; |
166 | eee0b836 | blueswir1 | page_max -= ts->vram_offset; |
167 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(page24 + page_min * 4,
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168 | eee0b836 | blueswir1 | page24 + page_max * 4 + TARGET_PAGE_SIZE,
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169 | eee0b836 | blueswir1 | VGA_DIRTY_FLAG); |
170 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(cpage + page_min * 4,
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171 | eee0b836 | blueswir1 | cpage + page_max * 4 + TARGET_PAGE_SIZE,
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172 | eee0b836 | blueswir1 | VGA_DIRTY_FLAG); |
173 | eee0b836 | blueswir1 | } |
174 | eee0b836 | blueswir1 | |
175 | e80cfcfc | bellard | /* Fixed line length 1024 allows us to do nice tricks not possible on
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176 | e80cfcfc | bellard | VGA... */
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177 | 95219897 | pbrook | static void tcx_update_display(void *opaque) |
178 | 420557e8 | bellard | { |
179 | e80cfcfc | bellard | TCXState *ts = opaque; |
180 | 550be127 | bellard | ram_addr_t page, page_min, page_max; |
181 | 550be127 | bellard | int y, y_start, dd, ds;
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182 | e80cfcfc | bellard | uint8_t *d, *s; |
183 | b3ceef24 | blueswir1 | void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
184 | e80cfcfc | bellard | |
185 | e80cfcfc | bellard | if (ts->ds->depth == 0) |
186 | e80cfcfc | bellard | return;
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187 | 6f7e9aec | bellard | page = ts->vram_offset; |
188 | e80cfcfc | bellard | y_start = -1;
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189 | 550be127 | bellard | page_min = 0xffffffff;
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190 | 550be127 | bellard | page_max = 0;
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191 | e80cfcfc | bellard | d = ts->ds->data; |
192 | 6f7e9aec | bellard | s = ts->vram; |
193 | e80cfcfc | bellard | dd = ts->ds->linesize; |
194 | e80cfcfc | bellard | ds = 1024;
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195 | e80cfcfc | bellard | |
196 | e80cfcfc | bellard | switch (ts->ds->depth) {
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197 | e80cfcfc | bellard | case 32: |
198 | e80cfcfc | bellard | f = tcx_draw_line32; |
199 | e80cfcfc | bellard | break;
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200 | 21206a10 | bellard | case 15: |
201 | 21206a10 | bellard | case 16: |
202 | 21206a10 | bellard | f = tcx_draw_line16; |
203 | e80cfcfc | bellard | break;
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204 | e80cfcfc | bellard | default:
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205 | e80cfcfc | bellard | case 8: |
206 | e80cfcfc | bellard | f = tcx_draw_line8; |
207 | e80cfcfc | bellard | break;
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208 | e80cfcfc | bellard | case 0: |
209 | e80cfcfc | bellard | return;
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210 | e80cfcfc | bellard | } |
211 | 3b46e624 | ths | |
212 | 6f7e9aec | bellard | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
213 | 0a962c02 | bellard | if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
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214 | e80cfcfc | bellard | if (y_start < 0) |
215 | e80cfcfc | bellard | y_start = y; |
216 | e80cfcfc | bellard | if (page < page_min)
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217 | e80cfcfc | bellard | page_min = page; |
218 | e80cfcfc | bellard | if (page > page_max)
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219 | e80cfcfc | bellard | page_max = page; |
220 | 6f7e9aec | bellard | f(ts, d, s, ts->width); |
221 | e80cfcfc | bellard | d += dd; |
222 | e80cfcfc | bellard | s += ds; |
223 | 6f7e9aec | bellard | f(ts, d, s, ts->width); |
224 | e80cfcfc | bellard | d += dd; |
225 | e80cfcfc | bellard | s += ds; |
226 | 6f7e9aec | bellard | f(ts, d, s, ts->width); |
227 | e80cfcfc | bellard | d += dd; |
228 | e80cfcfc | bellard | s += ds; |
229 | 6f7e9aec | bellard | f(ts, d, s, ts->width); |
230 | e80cfcfc | bellard | d += dd; |
231 | e80cfcfc | bellard | s += ds; |
232 | e80cfcfc | bellard | } else {
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233 | e80cfcfc | bellard | if (y_start >= 0) { |
234 | e80cfcfc | bellard | /* flush to display */
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235 | 5fafdf24 | ths | dpy_update(ts->ds, 0, y_start,
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236 | 6f7e9aec | bellard | ts->width, y - y_start); |
237 | e80cfcfc | bellard | y_start = -1;
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238 | e80cfcfc | bellard | } |
239 | e80cfcfc | bellard | d += dd * 4;
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240 | e80cfcfc | bellard | s += ds * 4;
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241 | e80cfcfc | bellard | } |
242 | e80cfcfc | bellard | } |
243 | e80cfcfc | bellard | if (y_start >= 0) { |
244 | e80cfcfc | bellard | /* flush to display */
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245 | 5fafdf24 | ths | dpy_update(ts->ds, 0, y_start,
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246 | 6f7e9aec | bellard | ts->width, y - y_start); |
247 | e80cfcfc | bellard | } |
248 | e80cfcfc | bellard | /* reset modified pages */
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249 | 550be127 | bellard | if (page_min <= page_max) {
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250 | 0a962c02 | bellard | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
251 | 0a962c02 | bellard | VGA_DIRTY_FLAG); |
252 | e80cfcfc | bellard | } |
253 | 420557e8 | bellard | } |
254 | 420557e8 | bellard | |
255 | eee0b836 | blueswir1 | static void tcx24_update_display(void *opaque) |
256 | eee0b836 | blueswir1 | { |
257 | eee0b836 | blueswir1 | TCXState *ts = opaque; |
258 | eee0b836 | blueswir1 | ram_addr_t page, page_min, page_max, cpage, page24; |
259 | eee0b836 | blueswir1 | int y, y_start, dd, ds;
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260 | eee0b836 | blueswir1 | uint8_t *d, *s; |
261 | eee0b836 | blueswir1 | uint32_t *cptr, *s24; |
262 | eee0b836 | blueswir1 | |
263 | eee0b836 | blueswir1 | if (ts->ds->depth != 32) |
264 | eee0b836 | blueswir1 | return;
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265 | eee0b836 | blueswir1 | page = ts->vram_offset; |
266 | eee0b836 | blueswir1 | page24 = ts->vram24_offset; |
267 | eee0b836 | blueswir1 | cpage = ts->cplane_offset; |
268 | eee0b836 | blueswir1 | y_start = -1;
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269 | eee0b836 | blueswir1 | page_min = 0xffffffff;
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270 | eee0b836 | blueswir1 | page_max = 0;
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271 | eee0b836 | blueswir1 | d = ts->ds->data; |
272 | eee0b836 | blueswir1 | s = ts->vram; |
273 | eee0b836 | blueswir1 | s24 = ts->vram24; |
274 | eee0b836 | blueswir1 | cptr = ts->cplane; |
275 | eee0b836 | blueswir1 | dd = ts->ds->linesize; |
276 | eee0b836 | blueswir1 | ds = 1024;
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277 | eee0b836 | blueswir1 | |
278 | eee0b836 | blueswir1 | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, |
279 | eee0b836 | blueswir1 | page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { |
280 | eee0b836 | blueswir1 | if (check_dirty(ts, page, page24, cpage)) {
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281 | eee0b836 | blueswir1 | if (y_start < 0) |
282 | eee0b836 | blueswir1 | y_start = y; |
283 | eee0b836 | blueswir1 | if (page < page_min)
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284 | eee0b836 | blueswir1 | page_min = page; |
285 | eee0b836 | blueswir1 | if (page > page_max)
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286 | eee0b836 | blueswir1 | page_max = page; |
287 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
288 | eee0b836 | blueswir1 | d += dd; |
289 | eee0b836 | blueswir1 | s += ds; |
290 | eee0b836 | blueswir1 | cptr += ds; |
291 | eee0b836 | blueswir1 | s24 += ds; |
292 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
293 | eee0b836 | blueswir1 | d += dd; |
294 | eee0b836 | blueswir1 | s += ds; |
295 | eee0b836 | blueswir1 | cptr += ds; |
296 | eee0b836 | blueswir1 | s24 += ds; |
297 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
298 | eee0b836 | blueswir1 | d += dd; |
299 | eee0b836 | blueswir1 | s += ds; |
300 | eee0b836 | blueswir1 | cptr += ds; |
301 | eee0b836 | blueswir1 | s24 += ds; |
302 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
303 | eee0b836 | blueswir1 | d += dd; |
304 | eee0b836 | blueswir1 | s += ds; |
305 | eee0b836 | blueswir1 | cptr += ds; |
306 | eee0b836 | blueswir1 | s24 += ds; |
307 | eee0b836 | blueswir1 | } else {
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308 | eee0b836 | blueswir1 | if (y_start >= 0) { |
309 | eee0b836 | blueswir1 | /* flush to display */
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310 | eee0b836 | blueswir1 | dpy_update(ts->ds, 0, y_start,
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311 | eee0b836 | blueswir1 | ts->width, y - y_start); |
312 | eee0b836 | blueswir1 | y_start = -1;
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313 | eee0b836 | blueswir1 | } |
314 | eee0b836 | blueswir1 | d += dd * 4;
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315 | eee0b836 | blueswir1 | s += ds * 4;
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316 | eee0b836 | blueswir1 | cptr += ds * 4;
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317 | eee0b836 | blueswir1 | s24 += ds * 4;
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318 | eee0b836 | blueswir1 | } |
319 | eee0b836 | blueswir1 | } |
320 | eee0b836 | blueswir1 | if (y_start >= 0) { |
321 | eee0b836 | blueswir1 | /* flush to display */
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322 | eee0b836 | blueswir1 | dpy_update(ts->ds, 0, y_start,
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323 | eee0b836 | blueswir1 | ts->width, y - y_start); |
324 | eee0b836 | blueswir1 | } |
325 | eee0b836 | blueswir1 | /* reset modified pages */
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326 | eee0b836 | blueswir1 | if (page_min <= page_max) {
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327 | eee0b836 | blueswir1 | reset_dirty(ts, page_min, page_max, page24, cpage); |
328 | eee0b836 | blueswir1 | } |
329 | eee0b836 | blueswir1 | } |
330 | eee0b836 | blueswir1 | |
331 | 95219897 | pbrook | static void tcx_invalidate_display(void *opaque) |
332 | 420557e8 | bellard | { |
333 | e80cfcfc | bellard | TCXState *s = opaque; |
334 | e80cfcfc | bellard | int i;
|
335 | e80cfcfc | bellard | |
336 | e80cfcfc | bellard | for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) { |
337 | e80cfcfc | bellard | cpu_physical_memory_set_dirty(s->vram_offset + i); |
338 | e80cfcfc | bellard | } |
339 | 420557e8 | bellard | } |
340 | 420557e8 | bellard | |
341 | eee0b836 | blueswir1 | static void tcx24_invalidate_display(void *opaque) |
342 | eee0b836 | blueswir1 | { |
343 | eee0b836 | blueswir1 | TCXState *s = opaque; |
344 | eee0b836 | blueswir1 | int i;
|
345 | eee0b836 | blueswir1 | |
346 | eee0b836 | blueswir1 | tcx_invalidate_display(s); |
347 | eee0b836 | blueswir1 | for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) { |
348 | eee0b836 | blueswir1 | cpu_physical_memory_set_dirty(s->vram24_offset + i); |
349 | eee0b836 | blueswir1 | cpu_physical_memory_set_dirty(s->cplane_offset + i); |
350 | eee0b836 | blueswir1 | } |
351 | eee0b836 | blueswir1 | } |
352 | eee0b836 | blueswir1 | |
353 | e80cfcfc | bellard | static void tcx_save(QEMUFile *f, void *opaque) |
354 | 420557e8 | bellard | { |
355 | 420557e8 | bellard | TCXState *s = opaque; |
356 | 3b46e624 | ths | |
357 | 6f7e9aec | bellard | qemu_put_be16s(f, (uint16_t *)&s->height); |
358 | 6f7e9aec | bellard | qemu_put_be16s(f, (uint16_t *)&s->width); |
359 | eee0b836 | blueswir1 | qemu_put_be16s(f, (uint16_t *)&s->depth); |
360 | e80cfcfc | bellard | qemu_put_buffer(f, s->r, 256);
|
361 | e80cfcfc | bellard | qemu_put_buffer(f, s->g, 256);
|
362 | e80cfcfc | bellard | qemu_put_buffer(f, s->b, 256);
|
363 | 6f7e9aec | bellard | qemu_put_8s(f, &s->dac_index); |
364 | 6f7e9aec | bellard | qemu_put_8s(f, &s->dac_state); |
365 | 420557e8 | bellard | } |
366 | 420557e8 | bellard | |
367 | e80cfcfc | bellard | static int tcx_load(QEMUFile *f, void *opaque, int version_id) |
368 | 420557e8 | bellard | { |
369 | e80cfcfc | bellard | TCXState *s = opaque; |
370 | fda77c2d | blueswir1 | uint32_t dummy; |
371 | fda77c2d | blueswir1 | |
372 | fda77c2d | blueswir1 | if (version_id != 3 && version_id != 4) |
373 | e80cfcfc | bellard | return -EINVAL;
|
374 | e80cfcfc | bellard | |
375 | fda77c2d | blueswir1 | if (version_id == 3) { |
376 | fda77c2d | blueswir1 | qemu_get_be32s(f, (uint32_t *)&dummy); |
377 | fda77c2d | blueswir1 | qemu_get_be32s(f, (uint32_t *)&dummy); |
378 | fda77c2d | blueswir1 | qemu_get_be32s(f, (uint32_t *)&dummy); |
379 | fda77c2d | blueswir1 | } |
380 | 6f7e9aec | bellard | qemu_get_be16s(f, (uint16_t *)&s->height); |
381 | 6f7e9aec | bellard | qemu_get_be16s(f, (uint16_t *)&s->width); |
382 | eee0b836 | blueswir1 | qemu_get_be16s(f, (uint16_t *)&s->depth); |
383 | e80cfcfc | bellard | qemu_get_buffer(f, s->r, 256);
|
384 | e80cfcfc | bellard | qemu_get_buffer(f, s->g, 256);
|
385 | e80cfcfc | bellard | qemu_get_buffer(f, s->b, 256);
|
386 | 6f7e9aec | bellard | qemu_get_8s(f, &s->dac_index); |
387 | 6f7e9aec | bellard | qemu_get_8s(f, &s->dac_state); |
388 | 21206a10 | bellard | update_palette_entries(s, 0, 256); |
389 | 97e7df27 | blueswir1 | if (s->depth == 24) |
390 | 97e7df27 | blueswir1 | tcx24_invalidate_display(s); |
391 | 97e7df27 | blueswir1 | else
|
392 | 97e7df27 | blueswir1 | tcx_invalidate_display(s); |
393 | 5425a216 | blueswir1 | |
394 | e80cfcfc | bellard | return 0; |
395 | 420557e8 | bellard | } |
396 | 420557e8 | bellard | |
397 | e80cfcfc | bellard | static void tcx_reset(void *opaque) |
398 | 420557e8 | bellard | { |
399 | e80cfcfc | bellard | TCXState *s = opaque; |
400 | e80cfcfc | bellard | |
401 | e80cfcfc | bellard | /* Initialize palette */
|
402 | e80cfcfc | bellard | memset(s->r, 0, 256); |
403 | e80cfcfc | bellard | memset(s->g, 0, 256); |
404 | e80cfcfc | bellard | memset(s->b, 0, 256); |
405 | e80cfcfc | bellard | s->r[255] = s->g[255] = s->b[255] = 255; |
406 | 21206a10 | bellard | update_palette_entries(s, 0, 256); |
407 | e80cfcfc | bellard | memset(s->vram, 0, MAXX*MAXY);
|
408 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + |
409 | eee0b836 | blueswir1 | MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG); |
410 | 6f7e9aec | bellard | s->dac_index = 0;
|
411 | 6f7e9aec | bellard | s->dac_state = 0;
|
412 | 6f7e9aec | bellard | } |
413 | 6f7e9aec | bellard | |
414 | 6f7e9aec | bellard | static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr) |
415 | 6f7e9aec | bellard | { |
416 | 6f7e9aec | bellard | return 0; |
417 | 6f7e9aec | bellard | } |
418 | 6f7e9aec | bellard | |
419 | 6f7e9aec | bellard | static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
420 | 6f7e9aec | bellard | { |
421 | 6f7e9aec | bellard | TCXState *s = opaque; |
422 | 6f7e9aec | bellard | uint32_t saddr; |
423 | 6f7e9aec | bellard | |
424 | 6f7e9aec | bellard | saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2; |
425 | 6f7e9aec | bellard | switch (saddr) {
|
426 | 6f7e9aec | bellard | case 0: |
427 | 6f7e9aec | bellard | s->dac_index = val >> 24;
|
428 | 6f7e9aec | bellard | s->dac_state = 0;
|
429 | 6f7e9aec | bellard | break;
|
430 | 6f7e9aec | bellard | case 1: |
431 | 6f7e9aec | bellard | switch (s->dac_state) {
|
432 | 6f7e9aec | bellard | case 0: |
433 | 6f7e9aec | bellard | s->r[s->dac_index] = val >> 24;
|
434 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
435 | 6f7e9aec | bellard | s->dac_state++; |
436 | 6f7e9aec | bellard | break;
|
437 | 6f7e9aec | bellard | case 1: |
438 | 6f7e9aec | bellard | s->g[s->dac_index] = val >> 24;
|
439 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
440 | 6f7e9aec | bellard | s->dac_state++; |
441 | 6f7e9aec | bellard | break;
|
442 | 6f7e9aec | bellard | case 2: |
443 | 6f7e9aec | bellard | s->b[s->dac_index] = val >> 24;
|
444 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
445 | 5c8cdbf8 | blueswir1 | s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement |
446 | 6f7e9aec | bellard | default:
|
447 | 6f7e9aec | bellard | s->dac_state = 0;
|
448 | 6f7e9aec | bellard | break;
|
449 | 6f7e9aec | bellard | } |
450 | 6f7e9aec | bellard | break;
|
451 | 6f7e9aec | bellard | default:
|
452 | 6f7e9aec | bellard | break;
|
453 | 6f7e9aec | bellard | } |
454 | 6f7e9aec | bellard | return;
|
455 | 420557e8 | bellard | } |
456 | 420557e8 | bellard | |
457 | 6f7e9aec | bellard | static CPUReadMemoryFunc *tcx_dac_read[3] = { |
458 | 6f7e9aec | bellard | tcx_dac_readl, |
459 | 6f7e9aec | bellard | tcx_dac_readl, |
460 | 6f7e9aec | bellard | tcx_dac_readl, |
461 | 6f7e9aec | bellard | }; |
462 | 6f7e9aec | bellard | |
463 | 6f7e9aec | bellard | static CPUWriteMemoryFunc *tcx_dac_write[3] = { |
464 | 6f7e9aec | bellard | tcx_dac_writel, |
465 | 6f7e9aec | bellard | tcx_dac_writel, |
466 | 6f7e9aec | bellard | tcx_dac_writel, |
467 | 6f7e9aec | bellard | }; |
468 | 6f7e9aec | bellard | |
469 | 8508b89e | blueswir1 | static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr) |
470 | 8508b89e | blueswir1 | { |
471 | 8508b89e | blueswir1 | return 0; |
472 | 8508b89e | blueswir1 | } |
473 | 8508b89e | blueswir1 | |
474 | 8508b89e | blueswir1 | static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr, |
475 | 8508b89e | blueswir1 | uint32_t val) |
476 | 8508b89e | blueswir1 | { |
477 | 8508b89e | blueswir1 | } |
478 | 8508b89e | blueswir1 | |
479 | 8508b89e | blueswir1 | static CPUReadMemoryFunc *tcx_dummy_read[3] = { |
480 | 8508b89e | blueswir1 | tcx_dummy_readl, |
481 | 8508b89e | blueswir1 | tcx_dummy_readl, |
482 | 8508b89e | blueswir1 | tcx_dummy_readl, |
483 | 8508b89e | blueswir1 | }; |
484 | 8508b89e | blueswir1 | |
485 | 8508b89e | blueswir1 | static CPUWriteMemoryFunc *tcx_dummy_write[3] = { |
486 | 8508b89e | blueswir1 | tcx_dummy_writel, |
487 | 8508b89e | blueswir1 | tcx_dummy_writel, |
488 | 8508b89e | blueswir1 | tcx_dummy_writel, |
489 | 8508b89e | blueswir1 | }; |
490 | 8508b89e | blueswir1 | |
491 | 5dcb6b91 | blueswir1 | void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
|
492 | eee0b836 | blueswir1 | unsigned long vram_offset, int vram_size, int width, int height, |
493 | eee0b836 | blueswir1 | int depth)
|
494 | 420557e8 | bellard | { |
495 | 420557e8 | bellard | TCXState *s; |
496 | 8508b89e | blueswir1 | int io_memory, dummy_memory;
|
497 | eee0b836 | blueswir1 | int size;
|
498 | 420557e8 | bellard | |
499 | 420557e8 | bellard | s = qemu_mallocz(sizeof(TCXState));
|
500 | 420557e8 | bellard | if (!s)
|
501 | 95219897 | pbrook | return;
|
502 | 420557e8 | bellard | s->ds = ds; |
503 | 8d5f07fa | bellard | s->addr = addr; |
504 | e80cfcfc | bellard | s->vram_offset = vram_offset; |
505 | 6f7e9aec | bellard | s->width = width; |
506 | 6f7e9aec | bellard | s->height = height; |
507 | eee0b836 | blueswir1 | s->depth = depth; |
508 | eee0b836 | blueswir1 | |
509 | eee0b836 | blueswir1 | // 8-bit plane
|
510 | eee0b836 | blueswir1 | s->vram = vram_base; |
511 | eee0b836 | blueswir1 | size = vram_size; |
512 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
|
513 | eee0b836 | blueswir1 | vram_offset += size; |
514 | eee0b836 | blueswir1 | vram_base += size; |
515 | e80cfcfc | bellard | |
516 | 6f7e9aec | bellard | io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
|
517 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS, io_memory);
|
518 | eee0b836 | blueswir1 | |
519 | 8508b89e | blueswir1 | dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
|
520 | 8508b89e | blueswir1 | s); |
521 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
|
522 | 8508b89e | blueswir1 | dummy_memory); |
523 | eee0b836 | blueswir1 | if (depth == 24) { |
524 | eee0b836 | blueswir1 | // 24-bit plane
|
525 | eee0b836 | blueswir1 | size = vram_size * 4;
|
526 | eee0b836 | blueswir1 | s->vram24 = (uint32_t *)vram_base; |
527 | eee0b836 | blueswir1 | s->vram24_offset = vram_offset; |
528 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
|
529 | eee0b836 | blueswir1 | vram_offset += size; |
530 | eee0b836 | blueswir1 | vram_base += size; |
531 | eee0b836 | blueswir1 | |
532 | eee0b836 | blueswir1 | // Control plane
|
533 | eee0b836 | blueswir1 | size = vram_size * 4;
|
534 | eee0b836 | blueswir1 | s->cplane = (uint32_t *)vram_base; |
535 | eee0b836 | blueswir1 | s->cplane_offset = vram_offset; |
536 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
|
537 | 8508b89e | blueswir1 | graphic_console_init(s->ds, tcx24_update_display, |
538 | 8508b89e | blueswir1 | tcx24_invalidate_display, tcx24_screen_dump, s); |
539 | eee0b836 | blueswir1 | } else {
|
540 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
|
541 | 8508b89e | blueswir1 | dummy_memory); |
542 | eee0b836 | blueswir1 | graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display, |
543 | eee0b836 | blueswir1 | tcx_screen_dump, s); |
544 | eee0b836 | blueswir1 | } |
545 | f96f4c9d | blueswir1 | // NetBSD writes here even with 8-bit display
|
546 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
|
547 | f96f4c9d | blueswir1 | dummy_memory); |
548 | e80cfcfc | bellard | |
549 | fda77c2d | blueswir1 | register_savevm("tcx", addr, 4, tcx_save, tcx_load, s); |
550 | e80cfcfc | bellard | qemu_register_reset(tcx_reset, s); |
551 | e80cfcfc | bellard | tcx_reset(s); |
552 | 6f7e9aec | bellard | dpy_resize(s->ds, width, height); |
553 | 420557e8 | bellard | } |
554 | 420557e8 | bellard | |
555 | 95219897 | pbrook | static void tcx_screen_dump(void *opaque, const char *filename) |
556 | 8d5f07fa | bellard | { |
557 | e80cfcfc | bellard | TCXState *s = opaque; |
558 | 8d5f07fa | bellard | FILE *f; |
559 | e80cfcfc | bellard | uint8_t *d, *d1, v; |
560 | 8d5f07fa | bellard | int y, x;
|
561 | 8d5f07fa | bellard | |
562 | 8d5f07fa | bellard | f = fopen(filename, "wb");
|
563 | 8d5f07fa | bellard | if (!f)
|
564 | e80cfcfc | bellard | return;
|
565 | 6f7e9aec | bellard | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
566 | 6f7e9aec | bellard | d1 = s->vram; |
567 | 6f7e9aec | bellard | for(y = 0; y < s->height; y++) { |
568 | 8d5f07fa | bellard | d = d1; |
569 | 6f7e9aec | bellard | for(x = 0; x < s->width; x++) { |
570 | 8d5f07fa | bellard | v = *d; |
571 | e80cfcfc | bellard | fputc(s->r[v], f); |
572 | e80cfcfc | bellard | fputc(s->g[v], f); |
573 | e80cfcfc | bellard | fputc(s->b[v], f); |
574 | 8d5f07fa | bellard | d++; |
575 | 8d5f07fa | bellard | } |
576 | e80cfcfc | bellard | d1 += MAXX; |
577 | 8d5f07fa | bellard | } |
578 | 8d5f07fa | bellard | fclose(f); |
579 | 8d5f07fa | bellard | return;
|
580 | 8d5f07fa | bellard | } |
581 | 8d5f07fa | bellard | |
582 | eee0b836 | blueswir1 | static void tcx24_screen_dump(void *opaque, const char *filename) |
583 | eee0b836 | blueswir1 | { |
584 | eee0b836 | blueswir1 | TCXState *s = opaque; |
585 | eee0b836 | blueswir1 | FILE *f; |
586 | eee0b836 | blueswir1 | uint8_t *d, *d1, v; |
587 | eee0b836 | blueswir1 | uint32_t *s24, *cptr, dval; |
588 | eee0b836 | blueswir1 | int y, x;
|
589 | 8d5f07fa | bellard | |
590 | eee0b836 | blueswir1 | f = fopen(filename, "wb");
|
591 | eee0b836 | blueswir1 | if (!f)
|
592 | eee0b836 | blueswir1 | return;
|
593 | eee0b836 | blueswir1 | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
594 | eee0b836 | blueswir1 | d1 = s->vram; |
595 | eee0b836 | blueswir1 | s24 = s->vram24; |
596 | eee0b836 | blueswir1 | cptr = s->cplane; |
597 | eee0b836 | blueswir1 | for(y = 0; y < s->height; y++) { |
598 | eee0b836 | blueswir1 | d = d1; |
599 | eee0b836 | blueswir1 | for(x = 0; x < s->width; x++, d++, s24++) { |
600 | eee0b836 | blueswir1 | if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct |
601 | eee0b836 | blueswir1 | dval = *s24 & 0x00ffffff;
|
602 | eee0b836 | blueswir1 | fputc((dval >> 16) & 0xff, f); |
603 | eee0b836 | blueswir1 | fputc((dval >> 8) & 0xff, f); |
604 | eee0b836 | blueswir1 | fputc(dval & 0xff, f);
|
605 | eee0b836 | blueswir1 | } else {
|
606 | eee0b836 | blueswir1 | v = *d; |
607 | eee0b836 | blueswir1 | fputc(s->r[v], f); |
608 | eee0b836 | blueswir1 | fputc(s->g[v], f); |
609 | eee0b836 | blueswir1 | fputc(s->b[v], f); |
610 | eee0b836 | blueswir1 | } |
611 | eee0b836 | blueswir1 | } |
612 | eee0b836 | blueswir1 | d1 += MAXX; |
613 | eee0b836 | blueswir1 | } |
614 | eee0b836 | blueswir1 | fclose(f); |
615 | eee0b836 | blueswir1 | return;
|
616 | eee0b836 | blueswir1 | } |