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/*
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* QEMU PowerPC 405 embedded processors emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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#include "ppc405.h" |
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extern int loglevel; |
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extern FILE *logfile;
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//#define DEBUG_MMIO
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#define DEBUG_OPBA
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#define DEBUG_SDRAM
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#define DEBUG_GPIO
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#define DEBUG_SERIAL
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#define DEBUG_OCM
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//#define DEBUG_I2C
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#define DEBUG_GPT
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#define DEBUG_MAL
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#define DEBUG_UIC
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#define DEBUG_CLOCKS
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//#define DEBUG_UNASSIGNED
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/*****************************************************************************/
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/* Generic PowerPC 405 processor instanciation */
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CPUState *ppc405_init (const unsigned char *cpu_model, |
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clk_setup_t *cpu_clk, clk_setup_t *tb_clk, |
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uint32_t sysclk) |
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{ |
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CPUState *env; |
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ppc_def_t *def; |
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/* init CPUs */
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env = cpu_init(); |
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qemu_register_reset(&cpu_ppc_reset, env); |
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
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ppc_find_by_name(cpu_model, &def); |
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if (def == NULL) { |
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cpu_abort(env, "Unable to find PowerPC %s CPU definition\n",
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cpu_model); |
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} |
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cpu_ppc_register(env, def); |
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cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ |
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cpu_clk->opaque = env; |
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/* Set time-base frequency to sysclk */
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tb_clk->cb = ppc_emb_timers_init(env, sysclk); |
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tb_clk->opaque = env; |
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ppc_dcr_init(env, NULL, NULL); |
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return env;
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} |
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ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, |
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uint32_t flags) |
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{ |
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ram_addr_t bdloc; |
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int i, n;
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/* We put the bd structure at the top of memory */
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if (bd->bi_memsize >= 0x01000000UL) |
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bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); |
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else
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bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); |
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stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);
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stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);
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stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);
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stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);
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stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);
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stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);
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stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);
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stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);
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stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);
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for (i = 0; i < 6; i++) |
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stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);
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stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);
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stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);
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stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);
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stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);
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for (i = 0; i < 4; i++) |
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stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);
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for (i = 0; i < 32; i++) |
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stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);
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stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);
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stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);
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for (i = 0; i < 6; i++) |
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stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
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n = 0x6A;
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if (flags & 0x00000001) { |
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for (i = 0; i < 6; i++) |
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stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]); |
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} |
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stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq); |
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n += 4;
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for (i = 0; i < 2; i++) { |
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stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]); |
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n += 4;
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} |
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return bdloc;
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} |
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/*****************************************************************************/
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/* Shared peripherals */
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/*****************************************************************************/
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/* Fake device used to map multiple devices in a single memory page */
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#define MMIO_AREA_BITS 8 |
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#define MMIO_AREA_LEN (1 << MMIO_AREA_BITS) |
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#define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS)) |
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#define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1)) |
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struct ppc4xx_mmio_t {
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target_phys_addr_t base; |
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CPUReadMemoryFunc **mem_read[MMIO_AREA_NB]; |
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CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB]; |
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void *opaque[MMIO_AREA_NB];
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}; |
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static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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#ifdef DEBUG_UNASSIGNED
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ppc4xx_mmio_t *mmio; |
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mmio = opaque; |
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printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n", |
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addr, mmio->base); |
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#endif
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return 0; |
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} |
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static void unassigned_mmio_writeb (void *opaque, |
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target_phys_addr_t addr, uint32_t val) |
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{ |
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#ifdef DEBUG_UNASSIGNED
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ppc4xx_mmio_t *mmio; |
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mmio = opaque; |
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printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n", |
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addr, val, mmio->base); |
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#endif
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} |
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static CPUReadMemoryFunc *unassigned_mmio_read[3] = { |
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unassigned_mmio_readb, |
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unassigned_mmio_readb, |
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unassigned_mmio_readb, |
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}; |
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static CPUWriteMemoryFunc *unassigned_mmio_write[3] = { |
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unassigned_mmio_writeb, |
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unassigned_mmio_writeb, |
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unassigned_mmio_writeb, |
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}; |
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static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
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target_phys_addr_t addr, int len)
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{ |
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CPUReadMemoryFunc **mem_read; |
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uint32_t ret; |
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int idx;
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idx = MMIO_IDX(addr - mmio->base); |
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#if defined(DEBUG_MMIO)
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printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__, |
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mmio, len, addr, idx); |
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#endif
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mem_read = mmio->mem_read[idx]; |
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ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base); |
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return ret;
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} |
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static void mmio_writelen (ppc4xx_mmio_t *mmio, |
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target_phys_addr_t addr, uint32_t value, int len)
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{ |
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CPUWriteMemoryFunc **mem_write; |
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int idx;
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idx = MMIO_IDX(addr - mmio->base); |
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#if defined(DEBUG_MMIO)
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printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08x\n", __func__, |
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mmio, len, addr, idx, value); |
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#endif
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mem_write = mmio->mem_write[idx]; |
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(*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value); |
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} |
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static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX "\n", __func__, addr); |
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#endif
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return mmio_readlen(opaque, addr, 0); |
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} |
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static void mmio_writeb (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
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#endif
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mmio_writelen(opaque, addr, value, 0);
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} |
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static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr) |
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{ |
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX "\n", __func__, addr); |
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#endif
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return mmio_readlen(opaque, addr, 1); |
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} |
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static void mmio_writew (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
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#endif
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mmio_writelen(opaque, addr, value, 1);
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} |
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static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr) |
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{ |
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX "\n", __func__, addr); |
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#endif
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return mmio_readlen(opaque, addr, 2); |
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} |
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static void mmio_writel (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
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#endif
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mmio_writelen(opaque, addr, value, 2);
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} |
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static CPUReadMemoryFunc *mmio_read[] = {
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&mmio_readb, |
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&mmio_readw, |
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&mmio_readl, |
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}; |
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static CPUWriteMemoryFunc *mmio_write[] = {
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&mmio_writeb, |
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&mmio_writew, |
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&mmio_writel, |
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}; |
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int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
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target_phys_addr_t offset, uint32_t len, |
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CPUReadMemoryFunc **mem_read, |
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CPUWriteMemoryFunc **mem_write, void *opaque)
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{ |
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uint32_t end; |
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int idx, eidx;
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if ((offset + len) > TARGET_PAGE_SIZE)
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return -1; |
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idx = MMIO_IDX(offset); |
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end = offset + len - 1;
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eidx = MMIO_IDX(end); |
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#if defined(DEBUG_MMIO)
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printf("%s: offset %08x len %08x %08x %d %d\n", __func__, offset, len,
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end, idx, eidx); |
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#endif
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for (; idx <= eidx; idx++) {
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mmio->mem_read[idx] = mem_read; |
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mmio->mem_write[idx] = mem_write; |
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mmio->opaque[idx] = opaque; |
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} |
295 |
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return 0; |
297 |
} |
298 |
|
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ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base) |
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{ |
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ppc4xx_mmio_t *mmio; |
302 |
int mmio_memory;
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mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
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if (mmio != NULL) { |
306 |
mmio->base = base; |
307 |
mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
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#if defined(DEBUG_MMIO)
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printf("%s: %p base %08x len %08x %d\n", __func__,
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mmio, base, TARGET_PAGE_SIZE, mmio_memory); |
311 |
#endif
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cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory); |
313 |
ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
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unassigned_mmio_read, unassigned_mmio_write, |
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mmio); |
316 |
} |
317 |
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return mmio;
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} |
320 |
|
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/*****************************************************************************/
|
322 |
/* Peripheral local bus arbitrer */
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enum {
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324 |
PLB0_BESR = 0x084,
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PLB0_BEAR = 0x086,
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PLB0_ACR = 0x087,
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327 |
}; |
328 |
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typedef struct ppc4xx_plb_t ppc4xx_plb_t; |
330 |
struct ppc4xx_plb_t {
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uint32_t acr; |
332 |
uint32_t bear; |
333 |
uint32_t besr; |
334 |
}; |
335 |
|
336 |
static target_ulong dcr_read_plb (void *opaque, int dcrn) |
337 |
{ |
338 |
ppc4xx_plb_t *plb; |
339 |
target_ulong ret; |
340 |
|
341 |
plb = opaque; |
342 |
switch (dcrn) {
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343 |
case PLB0_ACR:
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344 |
ret = plb->acr; |
345 |
break;
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346 |
case PLB0_BEAR:
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347 |
ret = plb->bear; |
348 |
break;
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349 |
case PLB0_BESR:
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350 |
ret = plb->besr; |
351 |
break;
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352 |
default:
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353 |
/* Avoid gcc warning */
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354 |
ret = 0;
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355 |
break;
|
356 |
} |
357 |
|
358 |
return ret;
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359 |
} |
360 |
|
361 |
static void dcr_write_plb (void *opaque, int dcrn, target_ulong val) |
362 |
{ |
363 |
ppc4xx_plb_t *plb; |
364 |
|
365 |
plb = opaque; |
366 |
switch (dcrn) {
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367 |
case PLB0_ACR:
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368 |
/* We don't care about the actual parameters written as
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369 |
* we don't manage any priorities on the bus
|
370 |
*/
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371 |
plb->acr = val & 0xF8000000;
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372 |
break;
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373 |
case PLB0_BEAR:
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374 |
/* Read only */
|
375 |
break;
|
376 |
case PLB0_BESR:
|
377 |
/* Write-clear */
|
378 |
plb->besr &= ~val; |
379 |
break;
|
380 |
} |
381 |
} |
382 |
|
383 |
static void ppc4xx_plb_reset (void *opaque) |
384 |
{ |
385 |
ppc4xx_plb_t *plb; |
386 |
|
387 |
plb = opaque; |
388 |
plb->acr = 0x00000000;
|
389 |
plb->bear = 0x00000000;
|
390 |
plb->besr = 0x00000000;
|
391 |
} |
392 |
|
393 |
void ppc4xx_plb_init (CPUState *env)
|
394 |
{ |
395 |
ppc4xx_plb_t *plb; |
396 |
|
397 |
plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
|
398 |
if (plb != NULL) { |
399 |
ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); |
400 |
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); |
401 |
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); |
402 |
ppc4xx_plb_reset(plb); |
403 |
qemu_register_reset(ppc4xx_plb_reset, plb); |
404 |
} |
405 |
} |
406 |
|
407 |
/*****************************************************************************/
|
408 |
/* PLB to OPB bridge */
|
409 |
enum {
|
410 |
POB0_BESR0 = 0x0A0,
|
411 |
POB0_BESR1 = 0x0A2,
|
412 |
POB0_BEAR = 0x0A4,
|
413 |
}; |
414 |
|
415 |
typedef struct ppc4xx_pob_t ppc4xx_pob_t; |
416 |
struct ppc4xx_pob_t {
|
417 |
uint32_t bear; |
418 |
uint32_t besr[2];
|
419 |
}; |
420 |
|
421 |
static target_ulong dcr_read_pob (void *opaque, int dcrn) |
422 |
{ |
423 |
ppc4xx_pob_t *pob; |
424 |
target_ulong ret; |
425 |
|
426 |
pob = opaque; |
427 |
switch (dcrn) {
|
428 |
case POB0_BEAR:
|
429 |
ret = pob->bear; |
430 |
break;
|
431 |
case POB0_BESR0:
|
432 |
case POB0_BESR1:
|
433 |
ret = pob->besr[dcrn - POB0_BESR0]; |
434 |
break;
|
435 |
default:
|
436 |
/* Avoid gcc warning */
|
437 |
ret = 0;
|
438 |
break;
|
439 |
} |
440 |
|
441 |
return ret;
|
442 |
} |
443 |
|
444 |
static void dcr_write_pob (void *opaque, int dcrn, target_ulong val) |
445 |
{ |
446 |
ppc4xx_pob_t *pob; |
447 |
|
448 |
pob = opaque; |
449 |
switch (dcrn) {
|
450 |
case POB0_BEAR:
|
451 |
/* Read only */
|
452 |
break;
|
453 |
case POB0_BESR0:
|
454 |
case POB0_BESR1:
|
455 |
/* Write-clear */
|
456 |
pob->besr[dcrn - POB0_BESR0] &= ~val; |
457 |
break;
|
458 |
} |
459 |
} |
460 |
|
461 |
static void ppc4xx_pob_reset (void *opaque) |
462 |
{ |
463 |
ppc4xx_pob_t *pob; |
464 |
|
465 |
pob = opaque; |
466 |
/* No error */
|
467 |
pob->bear = 0x00000000;
|
468 |
pob->besr[0] = 0x0000000; |
469 |
pob->besr[1] = 0x0000000; |
470 |
} |
471 |
|
472 |
void ppc4xx_pob_init (CPUState *env)
|
473 |
{ |
474 |
ppc4xx_pob_t *pob; |
475 |
|
476 |
pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
|
477 |
if (pob != NULL) { |
478 |
ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); |
479 |
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); |
480 |
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); |
481 |
qemu_register_reset(ppc4xx_pob_reset, pob); |
482 |
ppc4xx_pob_reset(env); |
483 |
} |
484 |
} |
485 |
|
486 |
/*****************************************************************************/
|
487 |
/* OPB arbitrer */
|
488 |
typedef struct ppc4xx_opba_t ppc4xx_opba_t; |
489 |
struct ppc4xx_opba_t {
|
490 |
target_phys_addr_t base; |
491 |
uint8_t cr; |
492 |
uint8_t pr; |
493 |
}; |
494 |
|
495 |
static uint32_t opba_readb (void *opaque, target_phys_addr_t addr) |
496 |
{ |
497 |
ppc4xx_opba_t *opba; |
498 |
uint32_t ret; |
499 |
|
500 |
#ifdef DEBUG_OPBA
|
501 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
502 |
#endif
|
503 |
opba = opaque; |
504 |
switch (addr - opba->base) {
|
505 |
case 0x00: |
506 |
ret = opba->cr; |
507 |
break;
|
508 |
case 0x01: |
509 |
ret = opba->pr; |
510 |
break;
|
511 |
default:
|
512 |
ret = 0x00;
|
513 |
break;
|
514 |
} |
515 |
|
516 |
return ret;
|
517 |
} |
518 |
|
519 |
static void opba_writeb (void *opaque, |
520 |
target_phys_addr_t addr, uint32_t value) |
521 |
{ |
522 |
ppc4xx_opba_t *opba; |
523 |
|
524 |
#ifdef DEBUG_OPBA
|
525 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
526 |
#endif
|
527 |
opba = opaque; |
528 |
switch (addr - opba->base) {
|
529 |
case 0x00: |
530 |
opba->cr = value & 0xF8;
|
531 |
break;
|
532 |
case 0x01: |
533 |
opba->pr = value & 0xFF;
|
534 |
break;
|
535 |
default:
|
536 |
break;
|
537 |
} |
538 |
} |
539 |
|
540 |
static uint32_t opba_readw (void *opaque, target_phys_addr_t addr) |
541 |
{ |
542 |
uint32_t ret; |
543 |
|
544 |
#ifdef DEBUG_OPBA
|
545 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
546 |
#endif
|
547 |
ret = opba_readb(opaque, addr) << 8;
|
548 |
ret |= opba_readb(opaque, addr + 1);
|
549 |
|
550 |
return ret;
|
551 |
} |
552 |
|
553 |
static void opba_writew (void *opaque, |
554 |
target_phys_addr_t addr, uint32_t value) |
555 |
{ |
556 |
#ifdef DEBUG_OPBA
|
557 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
558 |
#endif
|
559 |
opba_writeb(opaque, addr, value >> 8);
|
560 |
opba_writeb(opaque, addr + 1, value);
|
561 |
} |
562 |
|
563 |
static uint32_t opba_readl (void *opaque, target_phys_addr_t addr) |
564 |
{ |
565 |
uint32_t ret; |
566 |
|
567 |
#ifdef DEBUG_OPBA
|
568 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
569 |
#endif
|
570 |
ret = opba_readb(opaque, addr) << 24;
|
571 |
ret |= opba_readb(opaque, addr + 1) << 16; |
572 |
|
573 |
return ret;
|
574 |
} |
575 |
|
576 |
static void opba_writel (void *opaque, |
577 |
target_phys_addr_t addr, uint32_t value) |
578 |
{ |
579 |
#ifdef DEBUG_OPBA
|
580 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
581 |
#endif
|
582 |
opba_writeb(opaque, addr, value >> 24);
|
583 |
opba_writeb(opaque, addr + 1, value >> 16); |
584 |
} |
585 |
|
586 |
static CPUReadMemoryFunc *opba_read[] = {
|
587 |
&opba_readb, |
588 |
&opba_readw, |
589 |
&opba_readl, |
590 |
}; |
591 |
|
592 |
static CPUWriteMemoryFunc *opba_write[] = {
|
593 |
&opba_writeb, |
594 |
&opba_writew, |
595 |
&opba_writel, |
596 |
}; |
597 |
|
598 |
static void ppc4xx_opba_reset (void *opaque) |
599 |
{ |
600 |
ppc4xx_opba_t *opba; |
601 |
|
602 |
opba = opaque; |
603 |
opba->cr = 0x00; /* No dynamic priorities - park disabled */ |
604 |
opba->pr = 0x11;
|
605 |
} |
606 |
|
607 |
void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
608 |
target_phys_addr_t offset) |
609 |
{ |
610 |
ppc4xx_opba_t *opba; |
611 |
|
612 |
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
|
613 |
if (opba != NULL) { |
614 |
opba->base = offset; |
615 |
#ifdef DEBUG_OPBA
|
616 |
printf("%s: offset=" PADDRX "\n", __func__, offset); |
617 |
#endif
|
618 |
ppc4xx_mmio_register(env, mmio, offset, 0x002,
|
619 |
opba_read, opba_write, opba); |
620 |
qemu_register_reset(ppc4xx_opba_reset, opba); |
621 |
ppc4xx_opba_reset(opba); |
622 |
} |
623 |
} |
624 |
|
625 |
/*****************************************************************************/
|
626 |
/* "Universal" Interrupt controller */
|
627 |
enum {
|
628 |
DCR_UICSR = 0x000,
|
629 |
DCR_UICSRS = 0x001,
|
630 |
DCR_UICER = 0x002,
|
631 |
DCR_UICCR = 0x003,
|
632 |
DCR_UICPR = 0x004,
|
633 |
DCR_UICTR = 0x005,
|
634 |
DCR_UICMSR = 0x006,
|
635 |
DCR_UICVR = 0x007,
|
636 |
DCR_UICVCR = 0x008,
|
637 |
DCR_UICMAX = 0x009,
|
638 |
}; |
639 |
|
640 |
#define UIC_MAX_IRQ 32 |
641 |
typedef struct ppcuic_t ppcuic_t; |
642 |
struct ppcuic_t {
|
643 |
uint32_t dcr_base; |
644 |
int use_vectors;
|
645 |
uint32_t uicsr; /* Status register */
|
646 |
uint32_t uicer; /* Enable register */
|
647 |
uint32_t uiccr; /* Critical register */
|
648 |
uint32_t uicpr; /* Polarity register */
|
649 |
uint32_t uictr; /* Triggering register */
|
650 |
uint32_t uicvcr; /* Vector configuration register */
|
651 |
uint32_t uicvr; |
652 |
qemu_irq *irqs; |
653 |
}; |
654 |
|
655 |
static void ppcuic_trigger_irq (ppcuic_t *uic) |
656 |
{ |
657 |
uint32_t ir, cr; |
658 |
int start, end, inc, i;
|
659 |
|
660 |
/* Trigger interrupt if any is pending */
|
661 |
ir = uic->uicsr & uic->uicer & (~uic->uiccr); |
662 |
cr = uic->uicsr & uic->uicer & uic->uiccr; |
663 |
#ifdef DEBUG_UIC
|
664 |
if (loglevel & CPU_LOG_INT) {
|
665 |
fprintf(logfile, "%s: uicsr %08x uicer %08x uiccr %08x\n"
|
666 |
" %08x ir %08x cr %08x\n", __func__,
|
667 |
uic->uicsr, uic->uicer, uic->uiccr, |
668 |
uic->uicsr & uic->uicer, ir, cr); |
669 |
} |
670 |
#endif
|
671 |
if (ir != 0x0000000) { |
672 |
#ifdef DEBUG_UIC
|
673 |
if (loglevel & CPU_LOG_INT) {
|
674 |
fprintf(logfile, "Raise UIC interrupt\n");
|
675 |
} |
676 |
#endif
|
677 |
qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); |
678 |
} else {
|
679 |
#ifdef DEBUG_UIC
|
680 |
if (loglevel & CPU_LOG_INT) {
|
681 |
fprintf(logfile, "Lower UIC interrupt\n");
|
682 |
} |
683 |
#endif
|
684 |
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); |
685 |
} |
686 |
/* Trigger critical interrupt if any is pending and update vector */
|
687 |
if (cr != 0x0000000) { |
688 |
qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]); |
689 |
if (uic->use_vectors) {
|
690 |
/* Compute critical IRQ vector */
|
691 |
if (uic->uicvcr & 1) { |
692 |
start = 31;
|
693 |
end = 0;
|
694 |
inc = -1;
|
695 |
} else {
|
696 |
start = 0;
|
697 |
end = 31;
|
698 |
inc = 1;
|
699 |
} |
700 |
uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
|
701 |
for (i = start; i <= end; i += inc) {
|
702 |
if (cr & (1 << i)) { |
703 |
uic->uicvr += (i - start) * 512 * inc;
|
704 |
break;
|
705 |
} |
706 |
} |
707 |
} |
708 |
#ifdef DEBUG_UIC
|
709 |
if (loglevel & CPU_LOG_INT) {
|
710 |
fprintf(logfile, "Raise UIC critical interrupt - vector %08x\n",
|
711 |
uic->uicvr); |
712 |
} |
713 |
#endif
|
714 |
} else {
|
715 |
#ifdef DEBUG_UIC
|
716 |
if (loglevel & CPU_LOG_INT) {
|
717 |
fprintf(logfile, "Lower UIC critical interrupt\n");
|
718 |
} |
719 |
#endif
|
720 |
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); |
721 |
uic->uicvr = 0x00000000;
|
722 |
} |
723 |
} |
724 |
|
725 |
static void ppcuic_set_irq (void *opaque, int irq_num, int level) |
726 |
{ |
727 |
ppcuic_t *uic; |
728 |
uint32_t mask, sr; |
729 |
|
730 |
uic = opaque; |
731 |
mask = 1 << irq_num;
|
732 |
#ifdef DEBUG_UIC
|
733 |
if (loglevel & CPU_LOG_INT) {
|
734 |
fprintf(logfile, "%s: irq %d level %d uicsr %08x mask %08x => %08x "
|
735 |
"%08x\n", __func__, irq_num, level,
|
736 |
uic->uicsr, mask, uic->uicsr & mask, level << irq_num); |
737 |
} |
738 |
#endif
|
739 |
if (irq_num < 0 || irq_num > 31) |
740 |
return;
|
741 |
sr = uic->uicsr; |
742 |
if (!(uic->uicpr & mask)) {
|
743 |
/* Negatively asserted IRQ */
|
744 |
level = level == 0 ? 1 : 0; |
745 |
} |
746 |
/* Update status register */
|
747 |
if (uic->uictr & mask) {
|
748 |
/* Edge sensitive interrupt */
|
749 |
if (level == 1) |
750 |
uic->uicsr |= mask; |
751 |
} else {
|
752 |
/* Level sensitive interrupt */
|
753 |
if (level == 1) |
754 |
uic->uicsr |= mask; |
755 |
else
|
756 |
uic->uicsr &= ~mask; |
757 |
} |
758 |
#ifdef DEBUG_UIC
|
759 |
if (loglevel & CPU_LOG_INT) {
|
760 |
fprintf(logfile, "%s: irq %d level %d sr %08x => %08x\n", __func__,
|
761 |
irq_num, level, uic->uicsr, sr); |
762 |
} |
763 |
#endif
|
764 |
if (sr != uic->uicsr)
|
765 |
ppcuic_trigger_irq(uic); |
766 |
} |
767 |
|
768 |
static target_ulong dcr_read_uic (void *opaque, int dcrn) |
769 |
{ |
770 |
ppcuic_t *uic; |
771 |
target_ulong ret; |
772 |
|
773 |
uic = opaque; |
774 |
dcrn -= uic->dcr_base; |
775 |
switch (dcrn) {
|
776 |
case DCR_UICSR:
|
777 |
case DCR_UICSRS:
|
778 |
ret = uic->uicsr; |
779 |
break;
|
780 |
case DCR_UICER:
|
781 |
ret = uic->uicer; |
782 |
break;
|
783 |
case DCR_UICCR:
|
784 |
ret = uic->uiccr; |
785 |
break;
|
786 |
case DCR_UICPR:
|
787 |
ret = uic->uicpr; |
788 |
break;
|
789 |
case DCR_UICTR:
|
790 |
ret = uic->uictr; |
791 |
break;
|
792 |
case DCR_UICMSR:
|
793 |
ret = uic->uicsr & uic->uicer; |
794 |
break;
|
795 |
case DCR_UICVR:
|
796 |
if (!uic->use_vectors)
|
797 |
goto no_read;
|
798 |
ret = uic->uicvr; |
799 |
break;
|
800 |
case DCR_UICVCR:
|
801 |
if (!uic->use_vectors)
|
802 |
goto no_read;
|
803 |
ret = uic->uicvcr; |
804 |
break;
|
805 |
default:
|
806 |
no_read:
|
807 |
ret = 0x00000000;
|
808 |
break;
|
809 |
} |
810 |
|
811 |
return ret;
|
812 |
} |
813 |
|
814 |
static void dcr_write_uic (void *opaque, int dcrn, target_ulong val) |
815 |
{ |
816 |
ppcuic_t *uic; |
817 |
|
818 |
uic = opaque; |
819 |
dcrn -= uic->dcr_base; |
820 |
#ifdef DEBUG_UIC
|
821 |
if (loglevel & CPU_LOG_INT) {
|
822 |
fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val); |
823 |
} |
824 |
#endif
|
825 |
switch (dcrn) {
|
826 |
case DCR_UICSR:
|
827 |
uic->uicsr &= ~val; |
828 |
ppcuic_trigger_irq(uic); |
829 |
break;
|
830 |
case DCR_UICSRS:
|
831 |
uic->uicsr |= val; |
832 |
ppcuic_trigger_irq(uic); |
833 |
break;
|
834 |
case DCR_UICER:
|
835 |
uic->uicer = val; |
836 |
ppcuic_trigger_irq(uic); |
837 |
break;
|
838 |
case DCR_UICCR:
|
839 |
uic->uiccr = val; |
840 |
ppcuic_trigger_irq(uic); |
841 |
break;
|
842 |
case DCR_UICPR:
|
843 |
uic->uicpr = val; |
844 |
ppcuic_trigger_irq(uic); |
845 |
break;
|
846 |
case DCR_UICTR:
|
847 |
uic->uictr = val; |
848 |
ppcuic_trigger_irq(uic); |
849 |
break;
|
850 |
case DCR_UICMSR:
|
851 |
break;
|
852 |
case DCR_UICVR:
|
853 |
break;
|
854 |
case DCR_UICVCR:
|
855 |
uic->uicvcr = val & 0xFFFFFFFD;
|
856 |
ppcuic_trigger_irq(uic); |
857 |
break;
|
858 |
} |
859 |
} |
860 |
|
861 |
static void ppcuic_reset (void *opaque) |
862 |
{ |
863 |
ppcuic_t *uic; |
864 |
|
865 |
uic = opaque; |
866 |
uic->uiccr = 0x00000000;
|
867 |
uic->uicer = 0x00000000;
|
868 |
uic->uicpr = 0x00000000;
|
869 |
uic->uicsr = 0x00000000;
|
870 |
uic->uictr = 0x00000000;
|
871 |
if (uic->use_vectors) {
|
872 |
uic->uicvcr = 0x00000000;
|
873 |
uic->uicvr = 0x0000000;
|
874 |
} |
875 |
} |
876 |
|
877 |
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, |
878 |
uint32_t dcr_base, int has_ssr, int has_vr) |
879 |
{ |
880 |
ppcuic_t *uic; |
881 |
int i;
|
882 |
|
883 |
uic = qemu_mallocz(sizeof(ppcuic_t));
|
884 |
if (uic != NULL) { |
885 |
uic->dcr_base = dcr_base; |
886 |
uic->irqs = irqs; |
887 |
if (has_vr)
|
888 |
uic->use_vectors = 1;
|
889 |
for (i = 0; i < DCR_UICMAX; i++) { |
890 |
ppc_dcr_register(env, dcr_base + i, uic, |
891 |
&dcr_read_uic, &dcr_write_uic); |
892 |
} |
893 |
qemu_register_reset(ppcuic_reset, uic); |
894 |
ppcuic_reset(uic); |
895 |
} |
896 |
|
897 |
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
|
898 |
} |
899 |
|
900 |
/*****************************************************************************/
|
901 |
/* Code decompression controller */
|
902 |
/* XXX: TODO */
|
903 |
|
904 |
/*****************************************************************************/
|
905 |
/* SDRAM controller */
|
906 |
typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; |
907 |
struct ppc4xx_sdram_t {
|
908 |
uint32_t addr; |
909 |
int nbanks;
|
910 |
target_phys_addr_t ram_bases[4];
|
911 |
target_phys_addr_t ram_sizes[4];
|
912 |
uint32_t besr0; |
913 |
uint32_t besr1; |
914 |
uint32_t bear; |
915 |
uint32_t cfg; |
916 |
uint32_t status; |
917 |
uint32_t rtr; |
918 |
uint32_t pmit; |
919 |
uint32_t bcr[4];
|
920 |
uint32_t tr; |
921 |
uint32_t ecccfg; |
922 |
uint32_t eccesr; |
923 |
qemu_irq irq; |
924 |
}; |
925 |
|
926 |
enum {
|
927 |
SDRAM0_CFGADDR = 0x010,
|
928 |
SDRAM0_CFGDATA = 0x011,
|
929 |
}; |
930 |
|
931 |
static uint32_t sdram_bcr (target_phys_addr_t ram_base,
|
932 |
target_phys_addr_t ram_size) |
933 |
{ |
934 |
uint32_t bcr; |
935 |
|
936 |
switch (ram_size) {
|
937 |
case (4 * 1024 * 1024): |
938 |
bcr = 0x00000000;
|
939 |
break;
|
940 |
case (8 * 1024 * 1024): |
941 |
bcr = 0x00020000;
|
942 |
break;
|
943 |
case (16 * 1024 * 1024): |
944 |
bcr = 0x00040000;
|
945 |
break;
|
946 |
case (32 * 1024 * 1024): |
947 |
bcr = 0x00060000;
|
948 |
break;
|
949 |
case (64 * 1024 * 1024): |
950 |
bcr = 0x00080000;
|
951 |
break;
|
952 |
case (128 * 1024 * 1024): |
953 |
bcr = 0x000A0000;
|
954 |
break;
|
955 |
case (256 * 1024 * 1024): |
956 |
bcr = 0x000C0000;
|
957 |
break;
|
958 |
default:
|
959 |
printf("%s: invalid RAM size " TARGET_FMT_plx "\n", |
960 |
__func__, ram_size); |
961 |
return 0x00000000; |
962 |
} |
963 |
bcr |= ram_base & 0xFF800000;
|
964 |
bcr |= 1;
|
965 |
|
966 |
return bcr;
|
967 |
} |
968 |
|
969 |
static inline target_phys_addr_t sdram_base (uint32_t bcr) |
970 |
{ |
971 |
return bcr & 0xFF800000; |
972 |
} |
973 |
|
974 |
static target_ulong sdram_size (uint32_t bcr)
|
975 |
{ |
976 |
target_ulong size; |
977 |
int sh;
|
978 |
|
979 |
sh = (bcr >> 17) & 0x7; |
980 |
if (sh == 7) |
981 |
size = -1;
|
982 |
else
|
983 |
size = (4 * 1024 * 1024) << sh; |
984 |
|
985 |
return size;
|
986 |
} |
987 |
|
988 |
static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled) |
989 |
{ |
990 |
if (*bcrp & 0x00000001) { |
991 |
/* Unmap RAM */
|
992 |
#ifdef DEBUG_SDRAM
|
993 |
printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
994 |
__func__, sdram_base(*bcrp), sdram_size(*bcrp)); |
995 |
#endif
|
996 |
cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp), |
997 |
IO_MEM_UNASSIGNED); |
998 |
} |
999 |
*bcrp = bcr & 0xFFDEE001;
|
1000 |
if (enabled && (bcr & 0x00000001)) { |
1001 |
#ifdef DEBUG_SDRAM
|
1002 |
printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
1003 |
__func__, sdram_base(bcr), sdram_size(bcr)); |
1004 |
#endif
|
1005 |
cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr), |
1006 |
sdram_base(bcr) | IO_MEM_RAM); |
1007 |
} |
1008 |
} |
1009 |
|
1010 |
static void sdram_map_bcr (ppc4xx_sdram_t *sdram) |
1011 |
{ |
1012 |
int i;
|
1013 |
|
1014 |
for (i = 0; i < sdram->nbanks; i++) { |
1015 |
if (sdram->ram_sizes[i] != 0) { |
1016 |
sdram_set_bcr(&sdram->bcr[i], |
1017 |
sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), |
1018 |
1);
|
1019 |
} else {
|
1020 |
sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0); |
1021 |
} |
1022 |
} |
1023 |
} |
1024 |
|
1025 |
static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) |
1026 |
{ |
1027 |
int i;
|
1028 |
|
1029 |
for (i = 0; i < sdram->nbanks; i++) { |
1030 |
#ifdef DEBUG_SDRAM
|
1031 |
printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
1032 |
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); |
1033 |
#endif
|
1034 |
cpu_register_physical_memory(sdram_base(sdram->bcr[i]), |
1035 |
sdram_size(sdram->bcr[i]), |
1036 |
IO_MEM_UNASSIGNED); |
1037 |
} |
1038 |
} |
1039 |
|
1040 |
static target_ulong dcr_read_sdram (void *opaque, int dcrn) |
1041 |
{ |
1042 |
ppc4xx_sdram_t *sdram; |
1043 |
target_ulong ret; |
1044 |
|
1045 |
sdram = opaque; |
1046 |
switch (dcrn) {
|
1047 |
case SDRAM0_CFGADDR:
|
1048 |
ret = sdram->addr; |
1049 |
break;
|
1050 |
case SDRAM0_CFGDATA:
|
1051 |
switch (sdram->addr) {
|
1052 |
case 0x00: /* SDRAM_BESR0 */ |
1053 |
ret = sdram->besr0; |
1054 |
break;
|
1055 |
case 0x08: /* SDRAM_BESR1 */ |
1056 |
ret = sdram->besr1; |
1057 |
break;
|
1058 |
case 0x10: /* SDRAM_BEAR */ |
1059 |
ret = sdram->bear; |
1060 |
break;
|
1061 |
case 0x20: /* SDRAM_CFG */ |
1062 |
ret = sdram->cfg; |
1063 |
break;
|
1064 |
case 0x24: /* SDRAM_STATUS */ |
1065 |
ret = sdram->status; |
1066 |
break;
|
1067 |
case 0x30: /* SDRAM_RTR */ |
1068 |
ret = sdram->rtr; |
1069 |
break;
|
1070 |
case 0x34: /* SDRAM_PMIT */ |
1071 |
ret = sdram->pmit; |
1072 |
break;
|
1073 |
case 0x40: /* SDRAM_B0CR */ |
1074 |
ret = sdram->bcr[0];
|
1075 |
break;
|
1076 |
case 0x44: /* SDRAM_B1CR */ |
1077 |
ret = sdram->bcr[1];
|
1078 |
break;
|
1079 |
case 0x48: /* SDRAM_B2CR */ |
1080 |
ret = sdram->bcr[2];
|
1081 |
break;
|
1082 |
case 0x4C: /* SDRAM_B3CR */ |
1083 |
ret = sdram->bcr[3];
|
1084 |
break;
|
1085 |
case 0x80: /* SDRAM_TR */ |
1086 |
ret = -1; /* ? */ |
1087 |
break;
|
1088 |
case 0x94: /* SDRAM_ECCCFG */ |
1089 |
ret = sdram->ecccfg; |
1090 |
break;
|
1091 |
case 0x98: /* SDRAM_ECCESR */ |
1092 |
ret = sdram->eccesr; |
1093 |
break;
|
1094 |
default: /* Error */ |
1095 |
ret = -1;
|
1096 |
break;
|
1097 |
} |
1098 |
break;
|
1099 |
default:
|
1100 |
/* Avoid gcc warning */
|
1101 |
ret = 0x00000000;
|
1102 |
break;
|
1103 |
} |
1104 |
|
1105 |
return ret;
|
1106 |
} |
1107 |
|
1108 |
static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val) |
1109 |
{ |
1110 |
ppc4xx_sdram_t *sdram; |
1111 |
|
1112 |
sdram = opaque; |
1113 |
switch (dcrn) {
|
1114 |
case SDRAM0_CFGADDR:
|
1115 |
sdram->addr = val; |
1116 |
break;
|
1117 |
case SDRAM0_CFGDATA:
|
1118 |
switch (sdram->addr) {
|
1119 |
case 0x00: /* SDRAM_BESR0 */ |
1120 |
sdram->besr0 &= ~val; |
1121 |
break;
|
1122 |
case 0x08: /* SDRAM_BESR1 */ |
1123 |
sdram->besr1 &= ~val; |
1124 |
break;
|
1125 |
case 0x10: /* SDRAM_BEAR */ |
1126 |
sdram->bear = val; |
1127 |
break;
|
1128 |
case 0x20: /* SDRAM_CFG */ |
1129 |
val &= 0xFFE00000;
|
1130 |
if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { |
1131 |
#ifdef DEBUG_SDRAM
|
1132 |
printf("%s: enable SDRAM controller\n", __func__);
|
1133 |
#endif
|
1134 |
/* validate all RAM mappings */
|
1135 |
sdram_map_bcr(sdram); |
1136 |
sdram->status &= ~0x80000000;
|
1137 |
} else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { |
1138 |
#ifdef DEBUG_SDRAM
|
1139 |
printf("%s: disable SDRAM controller\n", __func__);
|
1140 |
#endif
|
1141 |
/* invalidate all RAM mappings */
|
1142 |
sdram_unmap_bcr(sdram); |
1143 |
sdram->status |= 0x80000000;
|
1144 |
} |
1145 |
if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) |
1146 |
sdram->status |= 0x40000000;
|
1147 |
else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) |
1148 |
sdram->status &= ~0x40000000;
|
1149 |
sdram->cfg = val; |
1150 |
break;
|
1151 |
case 0x24: /* SDRAM_STATUS */ |
1152 |
/* Read-only register */
|
1153 |
break;
|
1154 |
case 0x30: /* SDRAM_RTR */ |
1155 |
sdram->rtr = val & 0x3FF80000;
|
1156 |
break;
|
1157 |
case 0x34: /* SDRAM_PMIT */ |
1158 |
sdram->pmit = (val & 0xF8000000) | 0x07C00000; |
1159 |
break;
|
1160 |
case 0x40: /* SDRAM_B0CR */ |
1161 |
sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000); |
1162 |
break;
|
1163 |
case 0x44: /* SDRAM_B1CR */ |
1164 |
sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000); |
1165 |
break;
|
1166 |
case 0x48: /* SDRAM_B2CR */ |
1167 |
sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000); |
1168 |
break;
|
1169 |
case 0x4C: /* SDRAM_B3CR */ |
1170 |
sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000); |
1171 |
break;
|
1172 |
case 0x80: /* SDRAM_TR */ |
1173 |
sdram->tr = val & 0x018FC01F;
|
1174 |
break;
|
1175 |
case 0x94: /* SDRAM_ECCCFG */ |
1176 |
sdram->ecccfg = val & 0x00F00000;
|
1177 |
break;
|
1178 |
case 0x98: /* SDRAM_ECCESR */ |
1179 |
val &= 0xFFF0F000;
|
1180 |
if (sdram->eccesr == 0 && val != 0) |
1181 |
qemu_irq_raise(sdram->irq); |
1182 |
else if (sdram->eccesr != 0 && val == 0) |
1183 |
qemu_irq_lower(sdram->irq); |
1184 |
sdram->eccesr = val; |
1185 |
break;
|
1186 |
default: /* Error */ |
1187 |
break;
|
1188 |
} |
1189 |
break;
|
1190 |
} |
1191 |
} |
1192 |
|
1193 |
static void sdram_reset (void *opaque) |
1194 |
{ |
1195 |
ppc4xx_sdram_t *sdram; |
1196 |
|
1197 |
sdram = opaque; |
1198 |
sdram->addr = 0x00000000;
|
1199 |
sdram->bear = 0x00000000;
|
1200 |
sdram->besr0 = 0x00000000; /* No error */ |
1201 |
sdram->besr1 = 0x00000000; /* No error */ |
1202 |
sdram->cfg = 0x00000000;
|
1203 |
sdram->ecccfg = 0x00000000; /* No ECC */ |
1204 |
sdram->eccesr = 0x00000000; /* No error */ |
1205 |
sdram->pmit = 0x07C00000;
|
1206 |
sdram->rtr = 0x05F00000;
|
1207 |
sdram->tr = 0x00854009;
|
1208 |
/* We pre-initialize RAM banks */
|
1209 |
sdram->status = 0x00000000;
|
1210 |
sdram->cfg = 0x00800000;
|
1211 |
sdram_unmap_bcr(sdram); |
1212 |
} |
1213 |
|
1214 |
void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, |
1215 |
target_phys_addr_t *ram_bases, |
1216 |
target_phys_addr_t *ram_sizes, |
1217 |
int do_init)
|
1218 |
{ |
1219 |
ppc4xx_sdram_t *sdram; |
1220 |
|
1221 |
sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
|
1222 |
if (sdram != NULL) { |
1223 |
sdram->irq = irq; |
1224 |
sdram->nbanks = nbanks; |
1225 |
memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); |
1226 |
memcpy(sdram->ram_bases, ram_bases, |
1227 |
nbanks * sizeof(target_phys_addr_t));
|
1228 |
memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t)); |
1229 |
memcpy(sdram->ram_sizes, ram_sizes, |
1230 |
nbanks * sizeof(target_phys_addr_t));
|
1231 |
sdram_reset(sdram); |
1232 |
qemu_register_reset(&sdram_reset, sdram); |
1233 |
ppc_dcr_register(env, SDRAM0_CFGADDR, |
1234 |
sdram, &dcr_read_sdram, &dcr_write_sdram); |
1235 |
ppc_dcr_register(env, SDRAM0_CFGDATA, |
1236 |
sdram, &dcr_read_sdram, &dcr_write_sdram); |
1237 |
if (do_init)
|
1238 |
sdram_map_bcr(sdram); |
1239 |
} |
1240 |
} |
1241 |
|
1242 |
/*****************************************************************************/
|
1243 |
/* Peripheral controller */
|
1244 |
typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; |
1245 |
struct ppc4xx_ebc_t {
|
1246 |
uint32_t addr; |
1247 |
uint32_t bcr[8];
|
1248 |
uint32_t bap[8];
|
1249 |
uint32_t bear; |
1250 |
uint32_t besr0; |
1251 |
uint32_t besr1; |
1252 |
uint32_t cfg; |
1253 |
}; |
1254 |
|
1255 |
enum {
|
1256 |
EBC0_CFGADDR = 0x012,
|
1257 |
EBC0_CFGDATA = 0x013,
|
1258 |
}; |
1259 |
|
1260 |
static target_ulong dcr_read_ebc (void *opaque, int dcrn) |
1261 |
{ |
1262 |
ppc4xx_ebc_t *ebc; |
1263 |
target_ulong ret; |
1264 |
|
1265 |
ebc = opaque; |
1266 |
switch (dcrn) {
|
1267 |
case EBC0_CFGADDR:
|
1268 |
ret = ebc->addr; |
1269 |
break;
|
1270 |
case EBC0_CFGDATA:
|
1271 |
switch (ebc->addr) {
|
1272 |
case 0x00: /* B0CR */ |
1273 |
ret = ebc->bcr[0];
|
1274 |
break;
|
1275 |
case 0x01: /* B1CR */ |
1276 |
ret = ebc->bcr[1];
|
1277 |
break;
|
1278 |
case 0x02: /* B2CR */ |
1279 |
ret = ebc->bcr[2];
|
1280 |
break;
|
1281 |
case 0x03: /* B3CR */ |
1282 |
ret = ebc->bcr[3];
|
1283 |
break;
|
1284 |
case 0x04: /* B4CR */ |
1285 |
ret = ebc->bcr[4];
|
1286 |
break;
|
1287 |
case 0x05: /* B5CR */ |
1288 |
ret = ebc->bcr[5];
|
1289 |
break;
|
1290 |
case 0x06: /* B6CR */ |
1291 |
ret = ebc->bcr[6];
|
1292 |
break;
|
1293 |
case 0x07: /* B7CR */ |
1294 |
ret = ebc->bcr[7];
|
1295 |
break;
|
1296 |
case 0x10: /* B0AP */ |
1297 |
ret = ebc->bap[0];
|
1298 |
break;
|
1299 |
case 0x11: /* B1AP */ |
1300 |
ret = ebc->bap[1];
|
1301 |
break;
|
1302 |
case 0x12: /* B2AP */ |
1303 |
ret = ebc->bap[2];
|
1304 |
break;
|
1305 |
case 0x13: /* B3AP */ |
1306 |
ret = ebc->bap[3];
|
1307 |
break;
|
1308 |
case 0x14: /* B4AP */ |
1309 |
ret = ebc->bap[4];
|
1310 |
break;
|
1311 |
case 0x15: /* B5AP */ |
1312 |
ret = ebc->bap[5];
|
1313 |
break;
|
1314 |
case 0x16: /* B6AP */ |
1315 |
ret = ebc->bap[6];
|
1316 |
break;
|
1317 |
case 0x17: /* B7AP */ |
1318 |
ret = ebc->bap[7];
|
1319 |
break;
|
1320 |
case 0x20: /* BEAR */ |
1321 |
ret = ebc->bear; |
1322 |
break;
|
1323 |
case 0x21: /* BESR0 */ |
1324 |
ret = ebc->besr0; |
1325 |
break;
|
1326 |
case 0x22: /* BESR1 */ |
1327 |
ret = ebc->besr1; |
1328 |
break;
|
1329 |
case 0x23: /* CFG */ |
1330 |
ret = ebc->cfg; |
1331 |
break;
|
1332 |
default:
|
1333 |
ret = 0x00000000;
|
1334 |
break;
|
1335 |
} |
1336 |
default:
|
1337 |
ret = 0x00000000;
|
1338 |
break;
|
1339 |
} |
1340 |
|
1341 |
return ret;
|
1342 |
} |
1343 |
|
1344 |
static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val) |
1345 |
{ |
1346 |
ppc4xx_ebc_t *ebc; |
1347 |
|
1348 |
ebc = opaque; |
1349 |
switch (dcrn) {
|
1350 |
case EBC0_CFGADDR:
|
1351 |
ebc->addr = val; |
1352 |
break;
|
1353 |
case EBC0_CFGDATA:
|
1354 |
switch (ebc->addr) {
|
1355 |
case 0x00: /* B0CR */ |
1356 |
break;
|
1357 |
case 0x01: /* B1CR */ |
1358 |
break;
|
1359 |
case 0x02: /* B2CR */ |
1360 |
break;
|
1361 |
case 0x03: /* B3CR */ |
1362 |
break;
|
1363 |
case 0x04: /* B4CR */ |
1364 |
break;
|
1365 |
case 0x05: /* B5CR */ |
1366 |
break;
|
1367 |
case 0x06: /* B6CR */ |
1368 |
break;
|
1369 |
case 0x07: /* B7CR */ |
1370 |
break;
|
1371 |
case 0x10: /* B0AP */ |
1372 |
break;
|
1373 |
case 0x11: /* B1AP */ |
1374 |
break;
|
1375 |
case 0x12: /* B2AP */ |
1376 |
break;
|
1377 |
case 0x13: /* B3AP */ |
1378 |
break;
|
1379 |
case 0x14: /* B4AP */ |
1380 |
break;
|
1381 |
case 0x15: /* B5AP */ |
1382 |
break;
|
1383 |
case 0x16: /* B6AP */ |
1384 |
break;
|
1385 |
case 0x17: /* B7AP */ |
1386 |
break;
|
1387 |
case 0x20: /* BEAR */ |
1388 |
break;
|
1389 |
case 0x21: /* BESR0 */ |
1390 |
break;
|
1391 |
case 0x22: /* BESR1 */ |
1392 |
break;
|
1393 |
case 0x23: /* CFG */ |
1394 |
break;
|
1395 |
default:
|
1396 |
break;
|
1397 |
} |
1398 |
break;
|
1399 |
default:
|
1400 |
break;
|
1401 |
} |
1402 |
} |
1403 |
|
1404 |
static void ebc_reset (void *opaque) |
1405 |
{ |
1406 |
ppc4xx_ebc_t *ebc; |
1407 |
int i;
|
1408 |
|
1409 |
ebc = opaque; |
1410 |
ebc->addr = 0x00000000;
|
1411 |
ebc->bap[0] = 0x7F8FFE80; |
1412 |
ebc->bcr[0] = 0xFFE28000; |
1413 |
for (i = 0; i < 8; i++) { |
1414 |
ebc->bap[i] = 0x00000000;
|
1415 |
ebc->bcr[i] = 0x00000000;
|
1416 |
} |
1417 |
ebc->besr0 = 0x00000000;
|
1418 |
ebc->besr1 = 0x00000000;
|
1419 |
ebc->cfg = 0x80400000;
|
1420 |
} |
1421 |
|
1422 |
void ppc405_ebc_init (CPUState *env)
|
1423 |
{ |
1424 |
ppc4xx_ebc_t *ebc; |
1425 |
|
1426 |
ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
|
1427 |
if (ebc != NULL) { |
1428 |
ebc_reset(ebc); |
1429 |
qemu_register_reset(&ebc_reset, ebc); |
1430 |
ppc_dcr_register(env, EBC0_CFGADDR, |
1431 |
ebc, &dcr_read_ebc, &dcr_write_ebc); |
1432 |
ppc_dcr_register(env, EBC0_CFGDATA, |
1433 |
ebc, &dcr_read_ebc, &dcr_write_ebc); |
1434 |
} |
1435 |
} |
1436 |
|
1437 |
/*****************************************************************************/
|
1438 |
/* DMA controller */
|
1439 |
enum {
|
1440 |
DMA0_CR0 = 0x100,
|
1441 |
DMA0_CT0 = 0x101,
|
1442 |
DMA0_DA0 = 0x102,
|
1443 |
DMA0_SA0 = 0x103,
|
1444 |
DMA0_SG0 = 0x104,
|
1445 |
DMA0_CR1 = 0x108,
|
1446 |
DMA0_CT1 = 0x109,
|
1447 |
DMA0_DA1 = 0x10A,
|
1448 |
DMA0_SA1 = 0x10B,
|
1449 |
DMA0_SG1 = 0x10C,
|
1450 |
DMA0_CR2 = 0x110,
|
1451 |
DMA0_CT2 = 0x111,
|
1452 |
DMA0_DA2 = 0x112,
|
1453 |
DMA0_SA2 = 0x113,
|
1454 |
DMA0_SG2 = 0x114,
|
1455 |
DMA0_CR3 = 0x118,
|
1456 |
DMA0_CT3 = 0x119,
|
1457 |
DMA0_DA3 = 0x11A,
|
1458 |
DMA0_SA3 = 0x11B,
|
1459 |
DMA0_SG3 = 0x11C,
|
1460 |
DMA0_SR = 0x120,
|
1461 |
DMA0_SGC = 0x123,
|
1462 |
DMA0_SLP = 0x125,
|
1463 |
DMA0_POL = 0x126,
|
1464 |
}; |
1465 |
|
1466 |
typedef struct ppc405_dma_t ppc405_dma_t; |
1467 |
struct ppc405_dma_t {
|
1468 |
qemu_irq irqs[4];
|
1469 |
uint32_t cr[4];
|
1470 |
uint32_t ct[4];
|
1471 |
uint32_t da[4];
|
1472 |
uint32_t sa[4];
|
1473 |
uint32_t sg[4];
|
1474 |
uint32_t sr; |
1475 |
uint32_t sgc; |
1476 |
uint32_t slp; |
1477 |
uint32_t pol; |
1478 |
}; |
1479 |
|
1480 |
static target_ulong dcr_read_dma (void *opaque, int dcrn) |
1481 |
{ |
1482 |
ppc405_dma_t *dma; |
1483 |
|
1484 |
dma = opaque; |
1485 |
|
1486 |
return 0; |
1487 |
} |
1488 |
|
1489 |
static void dcr_write_dma (void *opaque, int dcrn, target_ulong val) |
1490 |
{ |
1491 |
ppc405_dma_t *dma; |
1492 |
|
1493 |
dma = opaque; |
1494 |
} |
1495 |
|
1496 |
static void ppc405_dma_reset (void *opaque) |
1497 |
{ |
1498 |
ppc405_dma_t *dma; |
1499 |
int i;
|
1500 |
|
1501 |
dma = opaque; |
1502 |
for (i = 0; i < 4; i++) { |
1503 |
dma->cr[i] = 0x00000000;
|
1504 |
dma->ct[i] = 0x00000000;
|
1505 |
dma->da[i] = 0x00000000;
|
1506 |
dma->sa[i] = 0x00000000;
|
1507 |
dma->sg[i] = 0x00000000;
|
1508 |
} |
1509 |
dma->sr = 0x00000000;
|
1510 |
dma->sgc = 0x00000000;
|
1511 |
dma->slp = 0x7C000000;
|
1512 |
dma->pol = 0x00000000;
|
1513 |
} |
1514 |
|
1515 |
void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]) |
1516 |
{ |
1517 |
ppc405_dma_t *dma; |
1518 |
|
1519 |
dma = qemu_mallocz(sizeof(ppc405_dma_t));
|
1520 |
if (dma != NULL) { |
1521 |
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); |
1522 |
ppc405_dma_reset(dma); |
1523 |
qemu_register_reset(&ppc405_dma_reset, dma); |
1524 |
ppc_dcr_register(env, DMA0_CR0, |
1525 |
dma, &dcr_read_dma, &dcr_write_dma); |
1526 |
ppc_dcr_register(env, DMA0_CT0, |
1527 |
dma, &dcr_read_dma, &dcr_write_dma); |
1528 |
ppc_dcr_register(env, DMA0_DA0, |
1529 |
dma, &dcr_read_dma, &dcr_write_dma); |
1530 |
ppc_dcr_register(env, DMA0_SA0, |
1531 |
dma, &dcr_read_dma, &dcr_write_dma); |
1532 |
ppc_dcr_register(env, DMA0_SG0, |
1533 |
dma, &dcr_read_dma, &dcr_write_dma); |
1534 |
ppc_dcr_register(env, DMA0_CR1, |
1535 |
dma, &dcr_read_dma, &dcr_write_dma); |
1536 |
ppc_dcr_register(env, DMA0_CT1, |
1537 |
dma, &dcr_read_dma, &dcr_write_dma); |
1538 |
ppc_dcr_register(env, DMA0_DA1, |
1539 |
dma, &dcr_read_dma, &dcr_write_dma); |
1540 |
ppc_dcr_register(env, DMA0_SA1, |
1541 |
dma, &dcr_read_dma, &dcr_write_dma); |
1542 |
ppc_dcr_register(env, DMA0_SG1, |
1543 |
dma, &dcr_read_dma, &dcr_write_dma); |
1544 |
ppc_dcr_register(env, DMA0_CR2, |
1545 |
dma, &dcr_read_dma, &dcr_write_dma); |
1546 |
ppc_dcr_register(env, DMA0_CT2, |
1547 |
dma, &dcr_read_dma, &dcr_write_dma); |
1548 |
ppc_dcr_register(env, DMA0_DA2, |
1549 |
dma, &dcr_read_dma, &dcr_write_dma); |
1550 |
ppc_dcr_register(env, DMA0_SA2, |
1551 |
dma, &dcr_read_dma, &dcr_write_dma); |
1552 |
ppc_dcr_register(env, DMA0_SG2, |
1553 |
dma, &dcr_read_dma, &dcr_write_dma); |
1554 |
ppc_dcr_register(env, DMA0_CR3, |
1555 |
dma, &dcr_read_dma, &dcr_write_dma); |
1556 |
ppc_dcr_register(env, DMA0_CT3, |
1557 |
dma, &dcr_read_dma, &dcr_write_dma); |
1558 |
ppc_dcr_register(env, DMA0_DA3, |
1559 |
dma, &dcr_read_dma, &dcr_write_dma); |
1560 |
ppc_dcr_register(env, DMA0_SA3, |
1561 |
dma, &dcr_read_dma, &dcr_write_dma); |
1562 |
ppc_dcr_register(env, DMA0_SG3, |
1563 |
dma, &dcr_read_dma, &dcr_write_dma); |
1564 |
ppc_dcr_register(env, DMA0_SR, |
1565 |
dma, &dcr_read_dma, &dcr_write_dma); |
1566 |
ppc_dcr_register(env, DMA0_SGC, |
1567 |
dma, &dcr_read_dma, &dcr_write_dma); |
1568 |
ppc_dcr_register(env, DMA0_SLP, |
1569 |
dma, &dcr_read_dma, &dcr_write_dma); |
1570 |
ppc_dcr_register(env, DMA0_POL, |
1571 |
dma, &dcr_read_dma, &dcr_write_dma); |
1572 |
} |
1573 |
} |
1574 |
|
1575 |
/*****************************************************************************/
|
1576 |
/* GPIO */
|
1577 |
typedef struct ppc405_gpio_t ppc405_gpio_t; |
1578 |
struct ppc405_gpio_t {
|
1579 |
target_phys_addr_t base; |
1580 |
uint32_t or; |
1581 |
uint32_t tcr; |
1582 |
uint32_t osrh; |
1583 |
uint32_t osrl; |
1584 |
uint32_t tsrh; |
1585 |
uint32_t tsrl; |
1586 |
uint32_t odr; |
1587 |
uint32_t ir; |
1588 |
uint32_t rr1; |
1589 |
uint32_t isr1h; |
1590 |
uint32_t isr1l; |
1591 |
}; |
1592 |
|
1593 |
static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr) |
1594 |
{ |
1595 |
ppc405_gpio_t *gpio; |
1596 |
|
1597 |
gpio = opaque; |
1598 |
#ifdef DEBUG_GPIO
|
1599 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
1600 |
#endif
|
1601 |
|
1602 |
return 0; |
1603 |
} |
1604 |
|
1605 |
static void ppc405_gpio_writeb (void *opaque, |
1606 |
target_phys_addr_t addr, uint32_t value) |
1607 |
{ |
1608 |
ppc405_gpio_t *gpio; |
1609 |
|
1610 |
gpio = opaque; |
1611 |
#ifdef DEBUG_GPIO
|
1612 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
1613 |
#endif
|
1614 |
} |
1615 |
|
1616 |
static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr) |
1617 |
{ |
1618 |
ppc405_gpio_t *gpio; |
1619 |
|
1620 |
gpio = opaque; |
1621 |
#ifdef DEBUG_GPIO
|
1622 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
1623 |
#endif
|
1624 |
|
1625 |
return 0; |
1626 |
} |
1627 |
|
1628 |
static void ppc405_gpio_writew (void *opaque, |
1629 |
target_phys_addr_t addr, uint32_t value) |
1630 |
{ |
1631 |
ppc405_gpio_t *gpio; |
1632 |
|
1633 |
gpio = opaque; |
1634 |
#ifdef DEBUG_GPIO
|
1635 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
1636 |
#endif
|
1637 |
} |
1638 |
|
1639 |
static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr) |
1640 |
{ |
1641 |
ppc405_gpio_t *gpio; |
1642 |
|
1643 |
gpio = opaque; |
1644 |
#ifdef DEBUG_GPIO
|
1645 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
1646 |
#endif
|
1647 |
|
1648 |
return 0; |
1649 |
} |
1650 |
|
1651 |
static void ppc405_gpio_writel (void *opaque, |
1652 |
target_phys_addr_t addr, uint32_t value) |
1653 |
{ |
1654 |
ppc405_gpio_t *gpio; |
1655 |
|
1656 |
gpio = opaque; |
1657 |
#ifdef DEBUG_GPIO
|
1658 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
1659 |
#endif
|
1660 |
} |
1661 |
|
1662 |
static CPUReadMemoryFunc *ppc405_gpio_read[] = {
|
1663 |
&ppc405_gpio_readb, |
1664 |
&ppc405_gpio_readw, |
1665 |
&ppc405_gpio_readl, |
1666 |
}; |
1667 |
|
1668 |
static CPUWriteMemoryFunc *ppc405_gpio_write[] = {
|
1669 |
&ppc405_gpio_writeb, |
1670 |
&ppc405_gpio_writew, |
1671 |
&ppc405_gpio_writel, |
1672 |
}; |
1673 |
|
1674 |
static void ppc405_gpio_reset (void *opaque) |
1675 |
{ |
1676 |
ppc405_gpio_t *gpio; |
1677 |
|
1678 |
gpio = opaque; |
1679 |
} |
1680 |
|
1681 |
void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
1682 |
target_phys_addr_t offset) |
1683 |
{ |
1684 |
ppc405_gpio_t *gpio; |
1685 |
|
1686 |
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
|
1687 |
if (gpio != NULL) { |
1688 |
gpio->base = offset; |
1689 |
ppc405_gpio_reset(gpio); |
1690 |
qemu_register_reset(&ppc405_gpio_reset, gpio); |
1691 |
#ifdef DEBUG_GPIO
|
1692 |
printf("%s: offset=" PADDRX "\n", __func__, offset); |
1693 |
#endif
|
1694 |
ppc4xx_mmio_register(env, mmio, offset, 0x038,
|
1695 |
ppc405_gpio_read, ppc405_gpio_write, gpio); |
1696 |
} |
1697 |
} |
1698 |
|
1699 |
/*****************************************************************************/
|
1700 |
/* Serial ports */
|
1701 |
static CPUReadMemoryFunc *serial_mm_read[] = {
|
1702 |
&serial_mm_readb, |
1703 |
&serial_mm_readw, |
1704 |
&serial_mm_readl, |
1705 |
}; |
1706 |
|
1707 |
static CPUWriteMemoryFunc *serial_mm_write[] = {
|
1708 |
&serial_mm_writeb, |
1709 |
&serial_mm_writew, |
1710 |
&serial_mm_writel, |
1711 |
}; |
1712 |
|
1713 |
void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
1714 |
target_phys_addr_t offset, qemu_irq irq, |
1715 |
CharDriverState *chr) |
1716 |
{ |
1717 |
void *serial;
|
1718 |
|
1719 |
#ifdef DEBUG_SERIAL
|
1720 |
printf("%s: offset=" PADDRX "\n", __func__, offset); |
1721 |
#endif
|
1722 |
serial = serial_mm_init(offset, 0, irq, chr, 0); |
1723 |
ppc4xx_mmio_register(env, mmio, offset, 0x008,
|
1724 |
serial_mm_read, serial_mm_write, serial); |
1725 |
} |
1726 |
|
1727 |
/*****************************************************************************/
|
1728 |
/* On Chip Memory */
|
1729 |
enum {
|
1730 |
OCM0_ISARC = 0x018,
|
1731 |
OCM0_ISACNTL = 0x019,
|
1732 |
OCM0_DSARC = 0x01A,
|
1733 |
OCM0_DSACNTL = 0x01B,
|
1734 |
}; |
1735 |
|
1736 |
typedef struct ppc405_ocm_t ppc405_ocm_t; |
1737 |
struct ppc405_ocm_t {
|
1738 |
target_ulong offset; |
1739 |
uint32_t isarc; |
1740 |
uint32_t isacntl; |
1741 |
uint32_t dsarc; |
1742 |
uint32_t dsacntl; |
1743 |
}; |
1744 |
|
1745 |
static void ocm_update_mappings (ppc405_ocm_t *ocm, |
1746 |
uint32_t isarc, uint32_t isacntl, |
1747 |
uint32_t dsarc, uint32_t dsacntl) |
1748 |
{ |
1749 |
#ifdef DEBUG_OCM
|
1750 |
printf("OCM update ISA %08x %08x (%08x %08x) DSA %08x %08x (%08x %08x)\n",
|
1751 |
isarc, isacntl, dsarc, dsacntl, |
1752 |
ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); |
1753 |
#endif
|
1754 |
if (ocm->isarc != isarc ||
|
1755 |
(ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { |
1756 |
if (ocm->isacntl & 0x80000000) { |
1757 |
/* Unmap previously assigned memory region */
|
1758 |
printf("OCM unmap ISA %08x\n", ocm->isarc);
|
1759 |
cpu_register_physical_memory(ocm->isarc, 0x04000000,
|
1760 |
IO_MEM_UNASSIGNED); |
1761 |
} |
1762 |
if (isacntl & 0x80000000) { |
1763 |
/* Map new instruction memory region */
|
1764 |
#ifdef DEBUG_OCM
|
1765 |
printf("OCM map ISA %08x\n", isarc);
|
1766 |
#endif
|
1767 |
cpu_register_physical_memory(isarc, 0x04000000,
|
1768 |
ocm->offset | IO_MEM_RAM); |
1769 |
} |
1770 |
} |
1771 |
if (ocm->dsarc != dsarc ||
|
1772 |
(ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { |
1773 |
if (ocm->dsacntl & 0x80000000) { |
1774 |
/* Beware not to unmap the region we just mapped */
|
1775 |
if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { |
1776 |
/* Unmap previously assigned memory region */
|
1777 |
#ifdef DEBUG_OCM
|
1778 |
printf("OCM unmap DSA %08x\n", ocm->dsarc);
|
1779 |
#endif
|
1780 |
cpu_register_physical_memory(ocm->dsarc, 0x04000000,
|
1781 |
IO_MEM_UNASSIGNED); |
1782 |
} |
1783 |
} |
1784 |
if (dsacntl & 0x80000000) { |
1785 |
/* Beware not to remap the region we just mapped */
|
1786 |
if (!(isacntl & 0x80000000) || dsarc != isarc) { |
1787 |
/* Map new data memory region */
|
1788 |
#ifdef DEBUG_OCM
|
1789 |
printf("OCM map DSA %08x\n", dsarc);
|
1790 |
#endif
|
1791 |
cpu_register_physical_memory(dsarc, 0x04000000,
|
1792 |
ocm->offset | IO_MEM_RAM); |
1793 |
} |
1794 |
} |
1795 |
} |
1796 |
} |
1797 |
|
1798 |
static target_ulong dcr_read_ocm (void *opaque, int dcrn) |
1799 |
{ |
1800 |
ppc405_ocm_t *ocm; |
1801 |
target_ulong ret; |
1802 |
|
1803 |
ocm = opaque; |
1804 |
switch (dcrn) {
|
1805 |
case OCM0_ISARC:
|
1806 |
ret = ocm->isarc; |
1807 |
break;
|
1808 |
case OCM0_ISACNTL:
|
1809 |
ret = ocm->isacntl; |
1810 |
break;
|
1811 |
case OCM0_DSARC:
|
1812 |
ret = ocm->dsarc; |
1813 |
break;
|
1814 |
case OCM0_DSACNTL:
|
1815 |
ret = ocm->dsacntl; |
1816 |
break;
|
1817 |
default:
|
1818 |
ret = 0;
|
1819 |
break;
|
1820 |
} |
1821 |
|
1822 |
return ret;
|
1823 |
} |
1824 |
|
1825 |
static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val) |
1826 |
{ |
1827 |
ppc405_ocm_t *ocm; |
1828 |
uint32_t isarc, dsarc, isacntl, dsacntl; |
1829 |
|
1830 |
ocm = opaque; |
1831 |
isarc = ocm->isarc; |
1832 |
dsarc = ocm->dsarc; |
1833 |
isacntl = ocm->isacntl; |
1834 |
dsacntl = ocm->dsacntl; |
1835 |
switch (dcrn) {
|
1836 |
case OCM0_ISARC:
|
1837 |
isarc = val & 0xFC000000;
|
1838 |
break;
|
1839 |
case OCM0_ISACNTL:
|
1840 |
isacntl = val & 0xC0000000;
|
1841 |
break;
|
1842 |
case OCM0_DSARC:
|
1843 |
isarc = val & 0xFC000000;
|
1844 |
break;
|
1845 |
case OCM0_DSACNTL:
|
1846 |
isacntl = val & 0xC0000000;
|
1847 |
break;
|
1848 |
} |
1849 |
ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); |
1850 |
ocm->isarc = isarc; |
1851 |
ocm->dsarc = dsarc; |
1852 |
ocm->isacntl = isacntl; |
1853 |
ocm->dsacntl = dsacntl; |
1854 |
} |
1855 |
|
1856 |
static void ocm_reset (void *opaque) |
1857 |
{ |
1858 |
ppc405_ocm_t *ocm; |
1859 |
uint32_t isarc, dsarc, isacntl, dsacntl; |
1860 |
|
1861 |
ocm = opaque; |
1862 |
isarc = 0x00000000;
|
1863 |
isacntl = 0x00000000;
|
1864 |
dsarc = 0x00000000;
|
1865 |
dsacntl = 0x00000000;
|
1866 |
ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); |
1867 |
ocm->isarc = isarc; |
1868 |
ocm->dsarc = dsarc; |
1869 |
ocm->isacntl = isacntl; |
1870 |
ocm->dsacntl = dsacntl; |
1871 |
} |
1872 |
|
1873 |
void ppc405_ocm_init (CPUState *env, unsigned long offset) |
1874 |
{ |
1875 |
ppc405_ocm_t *ocm; |
1876 |
|
1877 |
ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
|
1878 |
if (ocm != NULL) { |
1879 |
ocm->offset = offset; |
1880 |
ocm_reset(ocm); |
1881 |
qemu_register_reset(&ocm_reset, ocm); |
1882 |
ppc_dcr_register(env, OCM0_ISARC, |
1883 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
1884 |
ppc_dcr_register(env, OCM0_ISACNTL, |
1885 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
1886 |
ppc_dcr_register(env, OCM0_DSARC, |
1887 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
1888 |
ppc_dcr_register(env, OCM0_DSACNTL, |
1889 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
1890 |
} |
1891 |
} |
1892 |
|
1893 |
/*****************************************************************************/
|
1894 |
/* I2C controller */
|
1895 |
typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; |
1896 |
struct ppc4xx_i2c_t {
|
1897 |
target_phys_addr_t base; |
1898 |
qemu_irq irq; |
1899 |
uint8_t mdata; |
1900 |
uint8_t lmadr; |
1901 |
uint8_t hmadr; |
1902 |
uint8_t cntl; |
1903 |
uint8_t mdcntl; |
1904 |
uint8_t sts; |
1905 |
uint8_t extsts; |
1906 |
uint8_t sdata; |
1907 |
uint8_t lsadr; |
1908 |
uint8_t hsadr; |
1909 |
uint8_t clkdiv; |
1910 |
uint8_t intrmsk; |
1911 |
uint8_t xfrcnt; |
1912 |
uint8_t xtcntlss; |
1913 |
uint8_t directcntl; |
1914 |
}; |
1915 |
|
1916 |
static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr) |
1917 |
{ |
1918 |
ppc4xx_i2c_t *i2c; |
1919 |
uint32_t ret; |
1920 |
|
1921 |
#ifdef DEBUG_I2C
|
1922 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
1923 |
#endif
|
1924 |
i2c = opaque; |
1925 |
switch (addr - i2c->base) {
|
1926 |
case 0x00: |
1927 |
// i2c_readbyte(&i2c->mdata);
|
1928 |
ret = i2c->mdata; |
1929 |
break;
|
1930 |
case 0x02: |
1931 |
ret = i2c->sdata; |
1932 |
break;
|
1933 |
case 0x04: |
1934 |
ret = i2c->lmadr; |
1935 |
break;
|
1936 |
case 0x05: |
1937 |
ret = i2c->hmadr; |
1938 |
break;
|
1939 |
case 0x06: |
1940 |
ret = i2c->cntl; |
1941 |
break;
|
1942 |
case 0x07: |
1943 |
ret = i2c->mdcntl; |
1944 |
break;
|
1945 |
case 0x08: |
1946 |
ret = i2c->sts; |
1947 |
break;
|
1948 |
case 0x09: |
1949 |
ret = i2c->extsts; |
1950 |
break;
|
1951 |
case 0x0A: |
1952 |
ret = i2c->lsadr; |
1953 |
break;
|
1954 |
case 0x0B: |
1955 |
ret = i2c->hsadr; |
1956 |
break;
|
1957 |
case 0x0C: |
1958 |
ret = i2c->clkdiv; |
1959 |
break;
|
1960 |
case 0x0D: |
1961 |
ret = i2c->intrmsk; |
1962 |
break;
|
1963 |
case 0x0E: |
1964 |
ret = i2c->xfrcnt; |
1965 |
break;
|
1966 |
case 0x0F: |
1967 |
ret = i2c->xtcntlss; |
1968 |
break;
|
1969 |
case 0x10: |
1970 |
ret = i2c->directcntl; |
1971 |
break;
|
1972 |
default:
|
1973 |
ret = 0x00;
|
1974 |
break;
|
1975 |
} |
1976 |
#ifdef DEBUG_I2C
|
1977 |
printf("%s: addr " PADDRX " %02x\n", __func__, addr, ret); |
1978 |
#endif
|
1979 |
|
1980 |
return ret;
|
1981 |
} |
1982 |
|
1983 |
static void ppc4xx_i2c_writeb (void *opaque, |
1984 |
target_phys_addr_t addr, uint32_t value) |
1985 |
{ |
1986 |
ppc4xx_i2c_t *i2c; |
1987 |
|
1988 |
#ifdef DEBUG_I2C
|
1989 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
1990 |
#endif
|
1991 |
i2c = opaque; |
1992 |
switch (addr - i2c->base) {
|
1993 |
case 0x00: |
1994 |
i2c->mdata = value; |
1995 |
// i2c_sendbyte(&i2c->mdata);
|
1996 |
break;
|
1997 |
case 0x02: |
1998 |
i2c->sdata = value; |
1999 |
break;
|
2000 |
case 0x04: |
2001 |
i2c->lmadr = value; |
2002 |
break;
|
2003 |
case 0x05: |
2004 |
i2c->hmadr = value; |
2005 |
break;
|
2006 |
case 0x06: |
2007 |
i2c->cntl = value; |
2008 |
break;
|
2009 |
case 0x07: |
2010 |
i2c->mdcntl = value & 0xDF;
|
2011 |
break;
|
2012 |
case 0x08: |
2013 |
i2c->sts &= ~(value & 0x0A);
|
2014 |
break;
|
2015 |
case 0x09: |
2016 |
i2c->extsts &= ~(value & 0x8F);
|
2017 |
break;
|
2018 |
case 0x0A: |
2019 |
i2c->lsadr = value; |
2020 |
break;
|
2021 |
case 0x0B: |
2022 |
i2c->hsadr = value; |
2023 |
break;
|
2024 |
case 0x0C: |
2025 |
i2c->clkdiv = value; |
2026 |
break;
|
2027 |
case 0x0D: |
2028 |
i2c->intrmsk = value; |
2029 |
break;
|
2030 |
case 0x0E: |
2031 |
i2c->xfrcnt = value & 0x77;
|
2032 |
break;
|
2033 |
case 0x0F: |
2034 |
i2c->xtcntlss = value; |
2035 |
break;
|
2036 |
case 0x10: |
2037 |
i2c->directcntl = value & 0x7;
|
2038 |
break;
|
2039 |
} |
2040 |
} |
2041 |
|
2042 |
static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr) |
2043 |
{ |
2044 |
uint32_t ret; |
2045 |
|
2046 |
#ifdef DEBUG_I2C
|
2047 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
2048 |
#endif
|
2049 |
ret = ppc4xx_i2c_readb(opaque, addr) << 8;
|
2050 |
ret |= ppc4xx_i2c_readb(opaque, addr + 1);
|
2051 |
|
2052 |
return ret;
|
2053 |
} |
2054 |
|
2055 |
static void ppc4xx_i2c_writew (void *opaque, |
2056 |
target_phys_addr_t addr, uint32_t value) |
2057 |
{ |
2058 |
#ifdef DEBUG_I2C
|
2059 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
2060 |
#endif
|
2061 |
ppc4xx_i2c_writeb(opaque, addr, value >> 8);
|
2062 |
ppc4xx_i2c_writeb(opaque, addr + 1, value);
|
2063 |
} |
2064 |
|
2065 |
static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr) |
2066 |
{ |
2067 |
uint32_t ret; |
2068 |
|
2069 |
#ifdef DEBUG_I2C
|
2070 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
2071 |
#endif
|
2072 |
ret = ppc4xx_i2c_readb(opaque, addr) << 24;
|
2073 |
ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16; |
2074 |
ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8; |
2075 |
ret |= ppc4xx_i2c_readb(opaque, addr + 3);
|
2076 |
|
2077 |
return ret;
|
2078 |
} |
2079 |
|
2080 |
static void ppc4xx_i2c_writel (void *opaque, |
2081 |
target_phys_addr_t addr, uint32_t value) |
2082 |
{ |
2083 |
#ifdef DEBUG_I2C
|
2084 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
2085 |
#endif
|
2086 |
ppc4xx_i2c_writeb(opaque, addr, value >> 24);
|
2087 |
ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16); |
2088 |
ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8); |
2089 |
ppc4xx_i2c_writeb(opaque, addr + 3, value);
|
2090 |
} |
2091 |
|
2092 |
static CPUReadMemoryFunc *i2c_read[] = {
|
2093 |
&ppc4xx_i2c_readb, |
2094 |
&ppc4xx_i2c_readw, |
2095 |
&ppc4xx_i2c_readl, |
2096 |
}; |
2097 |
|
2098 |
static CPUWriteMemoryFunc *i2c_write[] = {
|
2099 |
&ppc4xx_i2c_writeb, |
2100 |
&ppc4xx_i2c_writew, |
2101 |
&ppc4xx_i2c_writel, |
2102 |
}; |
2103 |
|
2104 |
static void ppc4xx_i2c_reset (void *opaque) |
2105 |
{ |
2106 |
ppc4xx_i2c_t *i2c; |
2107 |
|
2108 |
i2c = opaque; |
2109 |
i2c->mdata = 0x00;
|
2110 |
i2c->sdata = 0x00;
|
2111 |
i2c->cntl = 0x00;
|
2112 |
i2c->mdcntl = 0x00;
|
2113 |
i2c->sts = 0x00;
|
2114 |
i2c->extsts = 0x00;
|
2115 |
i2c->clkdiv = 0x00;
|
2116 |
i2c->xfrcnt = 0x00;
|
2117 |
i2c->directcntl = 0x0F;
|
2118 |
} |
2119 |
|
2120 |
void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
2121 |
target_phys_addr_t offset, qemu_irq irq) |
2122 |
{ |
2123 |
ppc4xx_i2c_t *i2c; |
2124 |
|
2125 |
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
|
2126 |
if (i2c != NULL) { |
2127 |
i2c->base = offset; |
2128 |
i2c->irq = irq; |
2129 |
ppc4xx_i2c_reset(i2c); |
2130 |
#ifdef DEBUG_I2C
|
2131 |
printf("%s: offset=" PADDRX "\n", __func__, offset); |
2132 |
#endif
|
2133 |
ppc4xx_mmio_register(env, mmio, offset, 0x011,
|
2134 |
i2c_read, i2c_write, i2c); |
2135 |
qemu_register_reset(ppc4xx_i2c_reset, i2c); |
2136 |
} |
2137 |
} |
2138 |
|
2139 |
/*****************************************************************************/
|
2140 |
/* General purpose timers */
|
2141 |
typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; |
2142 |
struct ppc4xx_gpt_t {
|
2143 |
target_phys_addr_t base; |
2144 |
int64_t tb_offset; |
2145 |
uint32_t tb_freq; |
2146 |
struct QEMUTimer *timer;
|
2147 |
qemu_irq irqs[5];
|
2148 |
uint32_t oe; |
2149 |
uint32_t ol; |
2150 |
uint32_t im; |
2151 |
uint32_t is; |
2152 |
uint32_t ie; |
2153 |
uint32_t comp[5];
|
2154 |
uint32_t mask[5];
|
2155 |
}; |
2156 |
|
2157 |
static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr) |
2158 |
{ |
2159 |
#ifdef DEBUG_GPT
|
2160 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
2161 |
#endif
|
2162 |
/* XXX: generate a bus fault */
|
2163 |
return -1; |
2164 |
} |
2165 |
|
2166 |
static void ppc4xx_gpt_writeb (void *opaque, |
2167 |
target_phys_addr_t addr, uint32_t value) |
2168 |
{ |
2169 |
#ifdef DEBUG_I2C
|
2170 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
2171 |
#endif
|
2172 |
/* XXX: generate a bus fault */
|
2173 |
} |
2174 |
|
2175 |
static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr) |
2176 |
{ |
2177 |
#ifdef DEBUG_GPT
|
2178 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
2179 |
#endif
|
2180 |
/* XXX: generate a bus fault */
|
2181 |
return -1; |
2182 |
} |
2183 |
|
2184 |
static void ppc4xx_gpt_writew (void *opaque, |
2185 |
target_phys_addr_t addr, uint32_t value) |
2186 |
{ |
2187 |
#ifdef DEBUG_I2C
|
2188 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
2189 |
#endif
|
2190 |
/* XXX: generate a bus fault */
|
2191 |
} |
2192 |
|
2193 |
static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) |
2194 |
{ |
2195 |
/* XXX: TODO */
|
2196 |
return 0; |
2197 |
} |
2198 |
|
2199 |
static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) |
2200 |
{ |
2201 |
/* XXX: TODO */
|
2202 |
} |
2203 |
|
2204 |
static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) |
2205 |
{ |
2206 |
uint32_t mask; |
2207 |
int i;
|
2208 |
|
2209 |
mask = 0x80000000;
|
2210 |
for (i = 0; i < 5; i++) { |
2211 |
if (gpt->oe & mask) {
|
2212 |
/* Output is enabled */
|
2213 |
if (ppc4xx_gpt_compare(gpt, i)) {
|
2214 |
/* Comparison is OK */
|
2215 |
ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); |
2216 |
} else {
|
2217 |
/* Comparison is KO */
|
2218 |
ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); |
2219 |
} |
2220 |
} |
2221 |
mask = mask >> 1;
|
2222 |
} |
2223 |
} |
2224 |
|
2225 |
static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) |
2226 |
{ |
2227 |
uint32_t mask; |
2228 |
int i;
|
2229 |
|
2230 |
mask = 0x00008000;
|
2231 |
for (i = 0; i < 5; i++) { |
2232 |
if (gpt->is & gpt->im & mask)
|
2233 |
qemu_irq_raise(gpt->irqs[i]); |
2234 |
else
|
2235 |
qemu_irq_lower(gpt->irqs[i]); |
2236 |
mask = mask >> 1;
|
2237 |
} |
2238 |
} |
2239 |
|
2240 |
static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) |
2241 |
{ |
2242 |
/* XXX: TODO */
|
2243 |
} |
2244 |
|
2245 |
static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) |
2246 |
{ |
2247 |
ppc4xx_gpt_t *gpt; |
2248 |
uint32_t ret; |
2249 |
int idx;
|
2250 |
|
2251 |
#ifdef DEBUG_GPT
|
2252 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
2253 |
#endif
|
2254 |
gpt = opaque; |
2255 |
switch (addr - gpt->base) {
|
2256 |
case 0x00: |
2257 |
/* Time base counter */
|
2258 |
ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset, |
2259 |
gpt->tb_freq, ticks_per_sec); |
2260 |
break;
|
2261 |
case 0x10: |
2262 |
/* Output enable */
|
2263 |
ret = gpt->oe; |
2264 |
break;
|
2265 |
case 0x14: |
2266 |
/* Output level */
|
2267 |
ret = gpt->ol; |
2268 |
break;
|
2269 |
case 0x18: |
2270 |
/* Interrupt mask */
|
2271 |
ret = gpt->im; |
2272 |
break;
|
2273 |
case 0x1C: |
2274 |
case 0x20: |
2275 |
/* Interrupt status */
|
2276 |
ret = gpt->is; |
2277 |
break;
|
2278 |
case 0x24: |
2279 |
/* Interrupt enable */
|
2280 |
ret = gpt->ie; |
2281 |
break;
|
2282 |
case 0x80 ... 0x90: |
2283 |
/* Compare timer */
|
2284 |
idx = ((addr - gpt->base) - 0x80) >> 2; |
2285 |
ret = gpt->comp[idx]; |
2286 |
break;
|
2287 |
case 0xC0 ... 0xD0: |
2288 |
/* Compare mask */
|
2289 |
idx = ((addr - gpt->base) - 0xC0) >> 2; |
2290 |
ret = gpt->mask[idx]; |
2291 |
break;
|
2292 |
default:
|
2293 |
ret = -1;
|
2294 |
break;
|
2295 |
} |
2296 |
|
2297 |
return ret;
|
2298 |
} |
2299 |
|
2300 |
static void ppc4xx_gpt_writel (void *opaque, |
2301 |
target_phys_addr_t addr, uint32_t value) |
2302 |
{ |
2303 |
ppc4xx_gpt_t *gpt; |
2304 |
int idx;
|
2305 |
|
2306 |
#ifdef DEBUG_I2C
|
2307 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
2308 |
#endif
|
2309 |
gpt = opaque; |
2310 |
switch (addr - gpt->base) {
|
2311 |
case 0x00: |
2312 |
/* Time base counter */
|
2313 |
gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq) |
2314 |
- qemu_get_clock(vm_clock); |
2315 |
ppc4xx_gpt_compute_timer(gpt); |
2316 |
break;
|
2317 |
case 0x10: |
2318 |
/* Output enable */
|
2319 |
gpt->oe = value & 0xF8000000;
|
2320 |
ppc4xx_gpt_set_outputs(gpt); |
2321 |
break;
|
2322 |
case 0x14: |
2323 |
/* Output level */
|
2324 |
gpt->ol = value & 0xF8000000;
|
2325 |
ppc4xx_gpt_set_outputs(gpt); |
2326 |
break;
|
2327 |
case 0x18: |
2328 |
/* Interrupt mask */
|
2329 |
gpt->im = value & 0x0000F800;
|
2330 |
break;
|
2331 |
case 0x1C: |
2332 |
/* Interrupt status set */
|
2333 |
gpt->is |= value & 0x0000F800;
|
2334 |
ppc4xx_gpt_set_irqs(gpt); |
2335 |
break;
|
2336 |
case 0x20: |
2337 |
/* Interrupt status clear */
|
2338 |
gpt->is &= ~(value & 0x0000F800);
|
2339 |
ppc4xx_gpt_set_irqs(gpt); |
2340 |
break;
|
2341 |
case 0x24: |
2342 |
/* Interrupt enable */
|
2343 |
gpt->ie = value & 0x0000F800;
|
2344 |
ppc4xx_gpt_set_irqs(gpt); |
2345 |
break;
|
2346 |
case 0x80 ... 0x90: |
2347 |
/* Compare timer */
|
2348 |
idx = ((addr - gpt->base) - 0x80) >> 2; |
2349 |
gpt->comp[idx] = value & 0xF8000000;
|
2350 |
ppc4xx_gpt_compute_timer(gpt); |
2351 |
break;
|
2352 |
case 0xC0 ... 0xD0: |
2353 |
/* Compare mask */
|
2354 |
idx = ((addr - gpt->base) - 0xC0) >> 2; |
2355 |
gpt->mask[idx] = value & 0xF8000000;
|
2356 |
ppc4xx_gpt_compute_timer(gpt); |
2357 |
break;
|
2358 |
} |
2359 |
} |
2360 |
|
2361 |
static CPUReadMemoryFunc *gpt_read[] = {
|
2362 |
&ppc4xx_gpt_readb, |
2363 |
&ppc4xx_gpt_readw, |
2364 |
&ppc4xx_gpt_readl, |
2365 |
}; |
2366 |
|
2367 |
static CPUWriteMemoryFunc *gpt_write[] = {
|
2368 |
&ppc4xx_gpt_writeb, |
2369 |
&ppc4xx_gpt_writew, |
2370 |
&ppc4xx_gpt_writel, |
2371 |
}; |
2372 |
|
2373 |
static void ppc4xx_gpt_cb (void *opaque) |
2374 |
{ |
2375 |
ppc4xx_gpt_t *gpt; |
2376 |
|
2377 |
gpt = opaque; |
2378 |
ppc4xx_gpt_set_irqs(gpt); |
2379 |
ppc4xx_gpt_set_outputs(gpt); |
2380 |
ppc4xx_gpt_compute_timer(gpt); |
2381 |
} |
2382 |
|
2383 |
static void ppc4xx_gpt_reset (void *opaque) |
2384 |
{ |
2385 |
ppc4xx_gpt_t *gpt; |
2386 |
int i;
|
2387 |
|
2388 |
gpt = opaque; |
2389 |
qemu_del_timer(gpt->timer); |
2390 |
gpt->oe = 0x00000000;
|
2391 |
gpt->ol = 0x00000000;
|
2392 |
gpt->im = 0x00000000;
|
2393 |
gpt->is = 0x00000000;
|
2394 |
gpt->ie = 0x00000000;
|
2395 |
for (i = 0; i < 5; i++) { |
2396 |
gpt->comp[i] = 0x00000000;
|
2397 |
gpt->mask[i] = 0x00000000;
|
2398 |
} |
2399 |
} |
2400 |
|
2401 |
void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
2402 |
target_phys_addr_t offset, qemu_irq irqs[5])
|
2403 |
{ |
2404 |
ppc4xx_gpt_t *gpt; |
2405 |
int i;
|
2406 |
|
2407 |
gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
|
2408 |
if (gpt != NULL) { |
2409 |
gpt->base = offset; |
2410 |
for (i = 0; i < 5; i++) |
2411 |
gpt->irqs[i] = irqs[i]; |
2412 |
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); |
2413 |
ppc4xx_gpt_reset(gpt); |
2414 |
#ifdef DEBUG_GPT
|
2415 |
printf("%s: offset=" PADDRX "\n", __func__, offset); |
2416 |
#endif
|
2417 |
ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
|
2418 |
gpt_read, gpt_write, gpt); |
2419 |
qemu_register_reset(ppc4xx_gpt_reset, gpt); |
2420 |
} |
2421 |
} |
2422 |
|
2423 |
/*****************************************************************************/
|
2424 |
/* MAL */
|
2425 |
enum {
|
2426 |
MAL0_CFG = 0x180,
|
2427 |
MAL0_ESR = 0x181,
|
2428 |
MAL0_IER = 0x182,
|
2429 |
MAL0_TXCASR = 0x184,
|
2430 |
MAL0_TXCARR = 0x185,
|
2431 |
MAL0_TXEOBISR = 0x186,
|
2432 |
MAL0_TXDEIR = 0x187,
|
2433 |
MAL0_RXCASR = 0x190,
|
2434 |
MAL0_RXCARR = 0x191,
|
2435 |
MAL0_RXEOBISR = 0x192,
|
2436 |
MAL0_RXDEIR = 0x193,
|
2437 |
MAL0_TXCTP0R = 0x1A0,
|
2438 |
MAL0_TXCTP1R = 0x1A1,
|
2439 |
MAL0_TXCTP2R = 0x1A2,
|
2440 |
MAL0_TXCTP3R = 0x1A3,
|
2441 |
MAL0_RXCTP0R = 0x1C0,
|
2442 |
MAL0_RXCTP1R = 0x1C1,
|
2443 |
MAL0_RCBS0 = 0x1E0,
|
2444 |
MAL0_RCBS1 = 0x1E1,
|
2445 |
}; |
2446 |
|
2447 |
typedef struct ppc40x_mal_t ppc40x_mal_t; |
2448 |
struct ppc40x_mal_t {
|
2449 |
qemu_irq irqs[4];
|
2450 |
uint32_t cfg; |
2451 |
uint32_t esr; |
2452 |
uint32_t ier; |
2453 |
uint32_t txcasr; |
2454 |
uint32_t txcarr; |
2455 |
uint32_t txeobisr; |
2456 |
uint32_t txdeir; |
2457 |
uint32_t rxcasr; |
2458 |
uint32_t rxcarr; |
2459 |
uint32_t rxeobisr; |
2460 |
uint32_t rxdeir; |
2461 |
uint32_t txctpr[4];
|
2462 |
uint32_t rxctpr[2];
|
2463 |
uint32_t rcbs[2];
|
2464 |
}; |
2465 |
|
2466 |
static void ppc40x_mal_reset (void *opaque); |
2467 |
|
2468 |
static target_ulong dcr_read_mal (void *opaque, int dcrn) |
2469 |
{ |
2470 |
ppc40x_mal_t *mal; |
2471 |
target_ulong ret; |
2472 |
|
2473 |
mal = opaque; |
2474 |
switch (dcrn) {
|
2475 |
case MAL0_CFG:
|
2476 |
ret = mal->cfg; |
2477 |
break;
|
2478 |
case MAL0_ESR:
|
2479 |
ret = mal->esr; |
2480 |
break;
|
2481 |
case MAL0_IER:
|
2482 |
ret = mal->ier; |
2483 |
break;
|
2484 |
case MAL0_TXCASR:
|
2485 |
ret = mal->txcasr; |
2486 |
break;
|
2487 |
case MAL0_TXCARR:
|
2488 |
ret = mal->txcarr; |
2489 |
break;
|
2490 |
case MAL0_TXEOBISR:
|
2491 |
ret = mal->txeobisr; |
2492 |
break;
|
2493 |
case MAL0_TXDEIR:
|
2494 |
ret = mal->txdeir; |
2495 |
break;
|
2496 |
case MAL0_RXCASR:
|
2497 |
ret = mal->rxcasr; |
2498 |
break;
|
2499 |
case MAL0_RXCARR:
|
2500 |
ret = mal->rxcarr; |
2501 |
break;
|
2502 |
case MAL0_RXEOBISR:
|
2503 |
ret = mal->rxeobisr; |
2504 |
break;
|
2505 |
case MAL0_RXDEIR:
|
2506 |
ret = mal->rxdeir; |
2507 |
break;
|
2508 |
case MAL0_TXCTP0R:
|
2509 |
ret = mal->txctpr[0];
|
2510 |
break;
|
2511 |
case MAL0_TXCTP1R:
|
2512 |
ret = mal->txctpr[1];
|
2513 |
break;
|
2514 |
case MAL0_TXCTP2R:
|
2515 |
ret = mal->txctpr[2];
|
2516 |
break;
|
2517 |
case MAL0_TXCTP3R:
|
2518 |
ret = mal->txctpr[3];
|
2519 |
break;
|
2520 |
case MAL0_RXCTP0R:
|
2521 |
ret = mal->rxctpr[0];
|
2522 |
break;
|
2523 |
case MAL0_RXCTP1R:
|
2524 |
ret = mal->rxctpr[1];
|
2525 |
break;
|
2526 |
case MAL0_RCBS0:
|
2527 |
ret = mal->rcbs[0];
|
2528 |
break;
|
2529 |
case MAL0_RCBS1:
|
2530 |
ret = mal->rcbs[1];
|
2531 |
break;
|
2532 |
default:
|
2533 |
ret = 0;
|
2534 |
break;
|
2535 |
} |
2536 |
|
2537 |
return ret;
|
2538 |
} |
2539 |
|
2540 |
static void dcr_write_mal (void *opaque, int dcrn, target_ulong val) |
2541 |
{ |
2542 |
ppc40x_mal_t *mal; |
2543 |
int idx;
|
2544 |
|
2545 |
mal = opaque; |
2546 |
switch (dcrn) {
|
2547 |
case MAL0_CFG:
|
2548 |
if (val & 0x80000000) |
2549 |
ppc40x_mal_reset(mal); |
2550 |
mal->cfg = val & 0x00FFC087;
|
2551 |
break;
|
2552 |
case MAL0_ESR:
|
2553 |
/* Read/clear */
|
2554 |
mal->esr &= ~val; |
2555 |
break;
|
2556 |
case MAL0_IER:
|
2557 |
mal->ier = val & 0x0000001F;
|
2558 |
break;
|
2559 |
case MAL0_TXCASR:
|
2560 |
mal->txcasr = val & 0xF0000000;
|
2561 |
break;
|
2562 |
case MAL0_TXCARR:
|
2563 |
mal->txcarr = val & 0xF0000000;
|
2564 |
break;
|
2565 |
case MAL0_TXEOBISR:
|
2566 |
/* Read/clear */
|
2567 |
mal->txeobisr &= ~val; |
2568 |
break;
|
2569 |
case MAL0_TXDEIR:
|
2570 |
/* Read/clear */
|
2571 |
mal->txdeir &= ~val; |
2572 |
break;
|
2573 |
case MAL0_RXCASR:
|
2574 |
mal->rxcasr = val & 0xC0000000;
|
2575 |
break;
|
2576 |
case MAL0_RXCARR:
|
2577 |
mal->rxcarr = val & 0xC0000000;
|
2578 |
break;
|
2579 |
case MAL0_RXEOBISR:
|
2580 |
/* Read/clear */
|
2581 |
mal->rxeobisr &= ~val; |
2582 |
break;
|
2583 |
case MAL0_RXDEIR:
|
2584 |
/* Read/clear */
|
2585 |
mal->rxdeir &= ~val; |
2586 |
break;
|
2587 |
case MAL0_TXCTP0R:
|
2588 |
idx = 0;
|
2589 |
goto update_tx_ptr;
|
2590 |
case MAL0_TXCTP1R:
|
2591 |
idx = 1;
|
2592 |
goto update_tx_ptr;
|
2593 |
case MAL0_TXCTP2R:
|
2594 |
idx = 2;
|
2595 |
goto update_tx_ptr;
|
2596 |
case MAL0_TXCTP3R:
|
2597 |
idx = 3;
|
2598 |
update_tx_ptr:
|
2599 |
mal->txctpr[idx] = val; |
2600 |
break;
|
2601 |
case MAL0_RXCTP0R:
|
2602 |
idx = 0;
|
2603 |
goto update_rx_ptr;
|
2604 |
case MAL0_RXCTP1R:
|
2605 |
idx = 1;
|
2606 |
update_rx_ptr:
|
2607 |
mal->rxctpr[idx] = val; |
2608 |
break;
|
2609 |
case MAL0_RCBS0:
|
2610 |
idx = 0;
|
2611 |
goto update_rx_size;
|
2612 |
case MAL0_RCBS1:
|
2613 |
idx = 1;
|
2614 |
update_rx_size:
|
2615 |
mal->rcbs[idx] = val & 0x000000FF;
|
2616 |
break;
|
2617 |
} |
2618 |
} |
2619 |
|
2620 |
static void ppc40x_mal_reset (void *opaque) |
2621 |
{ |
2622 |
ppc40x_mal_t *mal; |
2623 |
|
2624 |
mal = opaque; |
2625 |
mal->cfg = 0x0007C000;
|
2626 |
mal->esr = 0x00000000;
|
2627 |
mal->ier = 0x00000000;
|
2628 |
mal->rxcasr = 0x00000000;
|
2629 |
mal->rxdeir = 0x00000000;
|
2630 |
mal->rxeobisr = 0x00000000;
|
2631 |
mal->txcasr = 0x00000000;
|
2632 |
mal->txdeir = 0x00000000;
|
2633 |
mal->txeobisr = 0x00000000;
|
2634 |
} |
2635 |
|
2636 |
void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]) |
2637 |
{ |
2638 |
ppc40x_mal_t *mal; |
2639 |
int i;
|
2640 |
|
2641 |
mal = qemu_mallocz(sizeof(ppc40x_mal_t));
|
2642 |
if (mal != NULL) { |
2643 |
for (i = 0; i < 4; i++) |
2644 |
mal->irqs[i] = irqs[i]; |
2645 |
ppc40x_mal_reset(mal); |
2646 |
qemu_register_reset(&ppc40x_mal_reset, mal); |
2647 |
ppc_dcr_register(env, MAL0_CFG, |
2648 |
mal, &dcr_read_mal, &dcr_write_mal); |
2649 |
ppc_dcr_register(env, MAL0_ESR, |
2650 |
mal, &dcr_read_mal, &dcr_write_mal); |
2651 |
ppc_dcr_register(env, MAL0_IER, |
2652 |
mal, &dcr_read_mal, &dcr_write_mal); |
2653 |
ppc_dcr_register(env, MAL0_TXCASR, |
2654 |
mal, &dcr_read_mal, &dcr_write_mal); |
2655 |
ppc_dcr_register(env, MAL0_TXCARR, |
2656 |
mal, &dcr_read_mal, &dcr_write_mal); |
2657 |
ppc_dcr_register(env, MAL0_TXEOBISR, |
2658 |
mal, &dcr_read_mal, &dcr_write_mal); |
2659 |
ppc_dcr_register(env, MAL0_TXDEIR, |
2660 |
mal, &dcr_read_mal, &dcr_write_mal); |
2661 |
ppc_dcr_register(env, MAL0_RXCASR, |
2662 |
mal, &dcr_read_mal, &dcr_write_mal); |
2663 |
ppc_dcr_register(env, MAL0_RXCARR, |
2664 |
mal, &dcr_read_mal, &dcr_write_mal); |
2665 |
ppc_dcr_register(env, MAL0_RXEOBISR, |
2666 |
mal, &dcr_read_mal, &dcr_write_mal); |
2667 |
ppc_dcr_register(env, MAL0_RXDEIR, |
2668 |
mal, &dcr_read_mal, &dcr_write_mal); |
2669 |
ppc_dcr_register(env, MAL0_TXCTP0R, |
2670 |
mal, &dcr_read_mal, &dcr_write_mal); |
2671 |
ppc_dcr_register(env, MAL0_TXCTP1R, |
2672 |
mal, &dcr_read_mal, &dcr_write_mal); |
2673 |
ppc_dcr_register(env, MAL0_TXCTP2R, |
2674 |
mal, &dcr_read_mal, &dcr_write_mal); |
2675 |
ppc_dcr_register(env, MAL0_TXCTP3R, |
2676 |
mal, &dcr_read_mal, &dcr_write_mal); |
2677 |
ppc_dcr_register(env, MAL0_RXCTP0R, |
2678 |
mal, &dcr_read_mal, &dcr_write_mal); |
2679 |
ppc_dcr_register(env, MAL0_RXCTP1R, |
2680 |
mal, &dcr_read_mal, &dcr_write_mal); |
2681 |
ppc_dcr_register(env, MAL0_RCBS0, |
2682 |
mal, &dcr_read_mal, &dcr_write_mal); |
2683 |
ppc_dcr_register(env, MAL0_RCBS1, |
2684 |
mal, &dcr_read_mal, &dcr_write_mal); |
2685 |
} |
2686 |
} |
2687 |
|
2688 |
/*****************************************************************************/
|
2689 |
/* SPR */
|
2690 |
void ppc40x_core_reset (CPUState *env)
|
2691 |
{ |
2692 |
target_ulong dbsr; |
2693 |
|
2694 |
printf("Reset PowerPC core\n");
|
2695 |
cpu_ppc_reset(env); |
2696 |
dbsr = env->spr[SPR_40x_DBSR]; |
2697 |
dbsr &= ~0x00000300;
|
2698 |
dbsr |= 0x00000100;
|
2699 |
env->spr[SPR_40x_DBSR] = dbsr; |
2700 |
cpu_loop_exit(); |
2701 |
} |
2702 |
|
2703 |
void ppc40x_chip_reset (CPUState *env)
|
2704 |
{ |
2705 |
target_ulong dbsr; |
2706 |
|
2707 |
printf("Reset PowerPC chip\n");
|
2708 |
cpu_ppc_reset(env); |
2709 |
/* XXX: TODO reset all internal peripherals */
|
2710 |
dbsr = env->spr[SPR_40x_DBSR]; |
2711 |
dbsr &= ~0x00000300;
|
2712 |
dbsr |= 0x00000200;
|
2713 |
env->spr[SPR_40x_DBSR] = dbsr; |
2714 |
cpu_loop_exit(); |
2715 |
} |
2716 |
|
2717 |
void ppc40x_system_reset (CPUState *env)
|
2718 |
{ |
2719 |
printf("Reset PowerPC system\n");
|
2720 |
qemu_system_reset_request(); |
2721 |
} |
2722 |
|
2723 |
void store_40x_dbcr0 (CPUState *env, uint32_t val)
|
2724 |
{ |
2725 |
switch ((val >> 28) & 0x3) { |
2726 |
case 0x0: |
2727 |
/* No action */
|
2728 |
break;
|
2729 |
case 0x1: |
2730 |
/* Core reset */
|
2731 |
ppc40x_core_reset(env); |
2732 |
break;
|
2733 |
case 0x2: |
2734 |
/* Chip reset */
|
2735 |
ppc40x_chip_reset(env); |
2736 |
break;
|
2737 |
case 0x3: |
2738 |
/* System reset */
|
2739 |
ppc40x_system_reset(env); |
2740 |
break;
|
2741 |
} |
2742 |
} |
2743 |
|
2744 |
/*****************************************************************************/
|
2745 |
/* PowerPC 405CR */
|
2746 |
enum {
|
2747 |
PPC405CR_CPC0_PLLMR = 0x0B0,
|
2748 |
PPC405CR_CPC0_CR0 = 0x0B1,
|
2749 |
PPC405CR_CPC0_CR1 = 0x0B2,
|
2750 |
PPC405CR_CPC0_PSR = 0x0B4,
|
2751 |
PPC405CR_CPC0_JTAGID = 0x0B5,
|
2752 |
PPC405CR_CPC0_ER = 0x0B9,
|
2753 |
PPC405CR_CPC0_FR = 0x0BA,
|
2754 |
PPC405CR_CPC0_SR = 0x0BB,
|
2755 |
}; |
2756 |
|
2757 |
enum {
|
2758 |
PPC405CR_CPU_CLK = 0,
|
2759 |
PPC405CR_TMR_CLK = 1,
|
2760 |
PPC405CR_PLB_CLK = 2,
|
2761 |
PPC405CR_SDRAM_CLK = 3,
|
2762 |
PPC405CR_OPB_CLK = 4,
|
2763 |
PPC405CR_EXT_CLK = 5,
|
2764 |
PPC405CR_UART_CLK = 6,
|
2765 |
PPC405CR_CLK_NB = 7,
|
2766 |
}; |
2767 |
|
2768 |
typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; |
2769 |
struct ppc405cr_cpc_t {
|
2770 |
clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
2771 |
uint32_t sysclk; |
2772 |
uint32_t psr; |
2773 |
uint32_t cr0; |
2774 |
uint32_t cr1; |
2775 |
uint32_t jtagid; |
2776 |
uint32_t pllmr; |
2777 |
uint32_t er; |
2778 |
uint32_t fr; |
2779 |
}; |
2780 |
|
2781 |
static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) |
2782 |
{ |
2783 |
uint64_t VCO_out, PLL_out; |
2784 |
uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; |
2785 |
int M, D0, D1, D2;
|
2786 |
|
2787 |
D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ |
2788 |
if (cpc->pllmr & 0x80000000) { |
2789 |
D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ |
2790 |
D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ |
2791 |
M = D0 * D1 * D2; |
2792 |
VCO_out = cpc->sysclk * M; |
2793 |
if (VCO_out < 400000000 || VCO_out > 800000000) { |
2794 |
/* PLL cannot lock */
|
2795 |
cpc->pllmr &= ~0x80000000;
|
2796 |
goto bypass_pll;
|
2797 |
} |
2798 |
PLL_out = VCO_out / D2; |
2799 |
} else {
|
2800 |
/* Bypass PLL */
|
2801 |
bypass_pll:
|
2802 |
M = D0; |
2803 |
PLL_out = cpc->sysclk * M; |
2804 |
} |
2805 |
CPU_clk = PLL_out; |
2806 |
if (cpc->cr1 & 0x00800000) |
2807 |
TMR_clk = cpc->sysclk; /* Should have a separate clock */
|
2808 |
else
|
2809 |
TMR_clk = CPU_clk; |
2810 |
PLB_clk = CPU_clk / D0; |
2811 |
SDRAM_clk = PLB_clk; |
2812 |
D0 = ((cpc->pllmr >> 10) & 0x3) + 1; |
2813 |
OPB_clk = PLB_clk / D0; |
2814 |
D0 = ((cpc->pllmr >> 24) & 0x3) + 2; |
2815 |
EXT_clk = PLB_clk / D0; |
2816 |
D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; |
2817 |
UART_clk = CPU_clk / D0; |
2818 |
/* Setup CPU clocks */
|
2819 |
clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); |
2820 |
/* Setup time-base clock */
|
2821 |
clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); |
2822 |
/* Setup PLB clock */
|
2823 |
clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); |
2824 |
/* Setup SDRAM clock */
|
2825 |
clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); |
2826 |
/* Setup OPB clock */
|
2827 |
clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); |
2828 |
/* Setup external clock */
|
2829 |
clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); |
2830 |
/* Setup UART clock */
|
2831 |
clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); |
2832 |
} |
2833 |
|
2834 |
static target_ulong dcr_read_crcpc (void *opaque, int dcrn) |
2835 |
{ |
2836 |
ppc405cr_cpc_t *cpc; |
2837 |
target_ulong ret; |
2838 |
|
2839 |
cpc = opaque; |
2840 |
switch (dcrn) {
|
2841 |
case PPC405CR_CPC0_PLLMR:
|
2842 |
ret = cpc->pllmr; |
2843 |
break;
|
2844 |
case PPC405CR_CPC0_CR0:
|
2845 |
ret = cpc->cr0; |
2846 |
break;
|
2847 |
case PPC405CR_CPC0_CR1:
|
2848 |
ret = cpc->cr1; |
2849 |
break;
|
2850 |
case PPC405CR_CPC0_PSR:
|
2851 |
ret = cpc->psr; |
2852 |
break;
|
2853 |
case PPC405CR_CPC0_JTAGID:
|
2854 |
ret = cpc->jtagid; |
2855 |
break;
|
2856 |
case PPC405CR_CPC0_ER:
|
2857 |
ret = cpc->er; |
2858 |
break;
|
2859 |
case PPC405CR_CPC0_FR:
|
2860 |
ret = cpc->fr; |
2861 |
break;
|
2862 |
case PPC405CR_CPC0_SR:
|
2863 |
ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
|
2864 |
break;
|
2865 |
default:
|
2866 |
/* Avoid gcc warning */
|
2867 |
ret = 0;
|
2868 |
break;
|
2869 |
} |
2870 |
|
2871 |
return ret;
|
2872 |
} |
2873 |
|
2874 |
static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val) |
2875 |
{ |
2876 |
ppc405cr_cpc_t *cpc; |
2877 |
|
2878 |
cpc = opaque; |
2879 |
switch (dcrn) {
|
2880 |
case PPC405CR_CPC0_PLLMR:
|
2881 |
cpc->pllmr = val & 0xFFF77C3F;
|
2882 |
break;
|
2883 |
case PPC405CR_CPC0_CR0:
|
2884 |
cpc->cr0 = val & 0x0FFFFFFE;
|
2885 |
break;
|
2886 |
case PPC405CR_CPC0_CR1:
|
2887 |
cpc->cr1 = val & 0x00800000;
|
2888 |
break;
|
2889 |
case PPC405CR_CPC0_PSR:
|
2890 |
/* Read-only */
|
2891 |
break;
|
2892 |
case PPC405CR_CPC0_JTAGID:
|
2893 |
/* Read-only */
|
2894 |
break;
|
2895 |
case PPC405CR_CPC0_ER:
|
2896 |
cpc->er = val & 0xBFFC0000;
|
2897 |
break;
|
2898 |
case PPC405CR_CPC0_FR:
|
2899 |
cpc->fr = val & 0xBFFC0000;
|
2900 |
break;
|
2901 |
case PPC405CR_CPC0_SR:
|
2902 |
/* Read-only */
|
2903 |
break;
|
2904 |
} |
2905 |
} |
2906 |
|
2907 |
static void ppc405cr_cpc_reset (void *opaque) |
2908 |
{ |
2909 |
ppc405cr_cpc_t *cpc; |
2910 |
int D;
|
2911 |
|
2912 |
cpc = opaque; |
2913 |
/* Compute PLLMR value from PSR settings */
|
2914 |
cpc->pllmr = 0x80000000;
|
2915 |
/* PFWD */
|
2916 |
switch ((cpc->psr >> 30) & 3) { |
2917 |
case 0: |
2918 |
/* Bypass */
|
2919 |
cpc->pllmr &= ~0x80000000;
|
2920 |
break;
|
2921 |
case 1: |
2922 |
/* Divide by 3 */
|
2923 |
cpc->pllmr |= 5 << 16; |
2924 |
break;
|
2925 |
case 2: |
2926 |
/* Divide by 4 */
|
2927 |
cpc->pllmr |= 4 << 16; |
2928 |
break;
|
2929 |
case 3: |
2930 |
/* Divide by 6 */
|
2931 |
cpc->pllmr |= 2 << 16; |
2932 |
break;
|
2933 |
} |
2934 |
/* PFBD */
|
2935 |
D = (cpc->psr >> 28) & 3; |
2936 |
cpc->pllmr |= (D + 1) << 20; |
2937 |
/* PT */
|
2938 |
D = (cpc->psr >> 25) & 7; |
2939 |
switch (D) {
|
2940 |
case 0x2: |
2941 |
cpc->pllmr |= 0x13;
|
2942 |
break;
|
2943 |
case 0x4: |
2944 |
cpc->pllmr |= 0x15;
|
2945 |
break;
|
2946 |
case 0x5: |
2947 |
cpc->pllmr |= 0x16;
|
2948 |
break;
|
2949 |
default:
|
2950 |
break;
|
2951 |
} |
2952 |
/* PDC */
|
2953 |
D = (cpc->psr >> 23) & 3; |
2954 |
cpc->pllmr |= D << 26;
|
2955 |
/* ODP */
|
2956 |
D = (cpc->psr >> 21) & 3; |
2957 |
cpc->pllmr |= D << 10;
|
2958 |
/* EBPD */
|
2959 |
D = (cpc->psr >> 17) & 3; |
2960 |
cpc->pllmr |= D << 24;
|
2961 |
cpc->cr0 = 0x0000003C;
|
2962 |
cpc->cr1 = 0x2B0D8800;
|
2963 |
cpc->er = 0x00000000;
|
2964 |
cpc->fr = 0x00000000;
|
2965 |
ppc405cr_clk_setup(cpc); |
2966 |
} |
2967 |
|
2968 |
static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) |
2969 |
{ |
2970 |
int D;
|
2971 |
|
2972 |
/* XXX: this should be read from IO pins */
|
2973 |
cpc->psr = 0x00000000; /* 8 bits ROM */ |
2974 |
/* PFWD */
|
2975 |
D = 0x2; /* Divide by 4 */ |
2976 |
cpc->psr |= D << 30;
|
2977 |
/* PFBD */
|
2978 |
D = 0x1; /* Divide by 2 */ |
2979 |
cpc->psr |= D << 28;
|
2980 |
/* PDC */
|
2981 |
D = 0x1; /* Divide by 2 */ |
2982 |
cpc->psr |= D << 23;
|
2983 |
/* PT */
|
2984 |
D = 0x5; /* M = 16 */ |
2985 |
cpc->psr |= D << 25;
|
2986 |
/* ODP */
|
2987 |
D = 0x1; /* Divide by 2 */ |
2988 |
cpc->psr |= D << 21;
|
2989 |
/* EBDP */
|
2990 |
D = 0x2; /* Divide by 4 */ |
2991 |
cpc->psr |= D << 17;
|
2992 |
} |
2993 |
|
2994 |
static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], |
2995 |
uint32_t sysclk) |
2996 |
{ |
2997 |
ppc405cr_cpc_t *cpc; |
2998 |
|
2999 |
cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
|
3000 |
if (cpc != NULL) { |
3001 |
memcpy(cpc->clk_setup, clk_setup, |
3002 |
PPC405CR_CLK_NB * sizeof(clk_setup_t));
|
3003 |
cpc->sysclk = sysclk; |
3004 |
cpc->jtagid = 0x42051049;
|
3005 |
ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, |
3006 |
&dcr_read_crcpc, &dcr_write_crcpc); |
3007 |
ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, |
3008 |
&dcr_read_crcpc, &dcr_write_crcpc); |
3009 |
ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, |
3010 |
&dcr_read_crcpc, &dcr_write_crcpc); |
3011 |
ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, |
3012 |
&dcr_read_crcpc, &dcr_write_crcpc); |
3013 |
ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, |
3014 |
&dcr_read_crcpc, &dcr_write_crcpc); |
3015 |
ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, |
3016 |
&dcr_read_crcpc, &dcr_write_crcpc); |
3017 |
ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, |
3018 |
&dcr_read_crcpc, &dcr_write_crcpc); |
3019 |
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, |
3020 |
&dcr_read_crcpc, &dcr_write_crcpc); |
3021 |
ppc405cr_clk_init(cpc); |
3022 |
qemu_register_reset(ppc405cr_cpc_reset, cpc); |
3023 |
ppc405cr_cpc_reset(cpc); |
3024 |
} |
3025 |
} |
3026 |
|
3027 |
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
|
3028 |
target_phys_addr_t ram_sizes[4],
|
3029 |
uint32_t sysclk, qemu_irq **picp, |
3030 |
ram_addr_t *offsetp, int do_init)
|
3031 |
{ |
3032 |
clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
3033 |
qemu_irq dma_irqs[4];
|
3034 |
CPUState *env; |
3035 |
ppc4xx_mmio_t *mmio; |
3036 |
qemu_irq *pic, *irqs; |
3037 |
ram_addr_t offset; |
3038 |
int i;
|
3039 |
|
3040 |
memset(clk_setup, 0, sizeof(clk_setup)); |
3041 |
env = ppc405_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
|
3042 |
&clk_setup[PPC405CR_TMR_CLK], sysclk); |
3043 |
/* Memory mapped devices registers */
|
3044 |
mmio = ppc4xx_mmio_init(env, 0xEF600000);
|
3045 |
/* PLB arbitrer */
|
3046 |
ppc4xx_plb_init(env); |
3047 |
/* PLB to OPB bridge */
|
3048 |
ppc4xx_pob_init(env); |
3049 |
/* OBP arbitrer */
|
3050 |
ppc4xx_opba_init(env, mmio, 0x600);
|
3051 |
/* Universal interrupt controller */
|
3052 |
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
3053 |
irqs[PPCUIC_OUTPUT_INT] = |
3054 |
((qemu_irq *)env->irq_inputs)[PPC405_INPUT_INT]; |
3055 |
irqs[PPCUIC_OUTPUT_CINT] = |
3056 |
((qemu_irq *)env->irq_inputs)[PPC405_INPUT_CINT]; |
3057 |
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
3058 |
*picp = pic; |
3059 |
/* SDRAM controller */
|
3060 |
ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); |
3061 |
offset = 0;
|
3062 |
for (i = 0; i < 4; i++) |
3063 |
offset += ram_sizes[i]; |
3064 |
/* External bus controller */
|
3065 |
ppc405_ebc_init(env); |
3066 |
/* DMA controller */
|
3067 |
dma_irqs[0] = pic[26]; |
3068 |
dma_irqs[1] = pic[25]; |
3069 |
dma_irqs[2] = pic[24]; |
3070 |
dma_irqs[3] = pic[23]; |
3071 |
ppc405_dma_init(env, dma_irqs); |
3072 |
/* Serial ports */
|
3073 |
if (serial_hds[0] != NULL) { |
3074 |
ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]); |
3075 |
} |
3076 |
if (serial_hds[1] != NULL) { |
3077 |
ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]); |
3078 |
} |
3079 |
/* IIC controller */
|
3080 |
ppc405_i2c_init(env, mmio, 0x500, pic[29]); |
3081 |
/* GPIO */
|
3082 |
ppc405_gpio_init(env, mmio, 0x700);
|
3083 |
/* CPU control */
|
3084 |
ppc405cr_cpc_init(env, clk_setup, sysclk); |
3085 |
*offsetp = offset; |
3086 |
|
3087 |
return env;
|
3088 |
} |
3089 |
|
3090 |
/*****************************************************************************/
|
3091 |
/* PowerPC 405EP */
|
3092 |
/* CPU control */
|
3093 |
enum {
|
3094 |
PPC405EP_CPC0_PLLMR0 = 0x0F0,
|
3095 |
PPC405EP_CPC0_BOOT = 0x0F1,
|
3096 |
PPC405EP_CPC0_EPCTL = 0x0F3,
|
3097 |
PPC405EP_CPC0_PLLMR1 = 0x0F4,
|
3098 |
PPC405EP_CPC0_UCR = 0x0F5,
|
3099 |
PPC405EP_CPC0_SRR = 0x0F6,
|
3100 |
PPC405EP_CPC0_JTAGID = 0x0F7,
|
3101 |
PPC405EP_CPC0_PCI = 0x0F9,
|
3102 |
#if 0
|
3103 |
PPC405EP_CPC0_ER = xxx,
|
3104 |
PPC405EP_CPC0_FR = xxx,
|
3105 |
PPC405EP_CPC0_SR = xxx,
|
3106 |
#endif
|
3107 |
}; |
3108 |
|
3109 |
enum {
|
3110 |
PPC405EP_CPU_CLK = 0,
|
3111 |
PPC405EP_PLB_CLK = 1,
|
3112 |
PPC405EP_OPB_CLK = 2,
|
3113 |
PPC405EP_EBC_CLK = 3,
|
3114 |
PPC405EP_MAL_CLK = 4,
|
3115 |
PPC405EP_PCI_CLK = 5,
|
3116 |
PPC405EP_UART0_CLK = 6,
|
3117 |
PPC405EP_UART1_CLK = 7,
|
3118 |
PPC405EP_CLK_NB = 8,
|
3119 |
}; |
3120 |
|
3121 |
typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; |
3122 |
struct ppc405ep_cpc_t {
|
3123 |
uint32_t sysclk; |
3124 |
clk_setup_t clk_setup[PPC405EP_CLK_NB]; |
3125 |
uint32_t boot; |
3126 |
uint32_t epctl; |
3127 |
uint32_t pllmr[2];
|
3128 |
uint32_t ucr; |
3129 |
uint32_t srr; |
3130 |
uint32_t jtagid; |
3131 |
uint32_t pci; |
3132 |
/* Clock and power management */
|
3133 |
uint32_t er; |
3134 |
uint32_t fr; |
3135 |
uint32_t sr; |
3136 |
}; |
3137 |
|
3138 |
static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) |
3139 |
{ |
3140 |
uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; |
3141 |
uint32_t UART0_clk, UART1_clk; |
3142 |
uint64_t VCO_out, PLL_out; |
3143 |
int M, D;
|
3144 |
|
3145 |
VCO_out = 0;
|
3146 |
if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { |
3147 |
M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ |
3148 |
// printf("FBMUL %01x %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
|
3149 |
D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ |
3150 |
// printf("FWDA %01x %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
|
3151 |
VCO_out = cpc->sysclk * M * D; |
3152 |
if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { |
3153 |
/* Error - unlock the PLL */
|
3154 |
printf("VCO out of range %" PRIu64 "\n", VCO_out); |
3155 |
#if 0
|
3156 |
cpc->pllmr[1] &= ~0x80000000;
|
3157 |
goto pll_bypass;
|
3158 |
#endif
|
3159 |
} |
3160 |
PLL_out = VCO_out / D; |
3161 |
/* Pretend the PLL is locked */
|
3162 |
cpc->boot |= 0x00000001;
|
3163 |
} else {
|
3164 |
#if 0
|
3165 |
pll_bypass:
|
3166 |
#endif
|
3167 |
PLL_out = cpc->sysclk; |
3168 |
if (cpc->pllmr[1] & 0x40000000) { |
3169 |
/* Pretend the PLL is not locked */
|
3170 |
cpc->boot &= ~0x00000001;
|
3171 |
} |
3172 |
} |
3173 |
/* Now, compute all other clocks */
|
3174 |
D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ |
3175 |
#ifdef DEBUG_CLOCKS
|
3176 |
// printf("CCDV %01x %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
|
3177 |
#endif
|
3178 |
CPU_clk = PLL_out / D; |
3179 |
D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ |
3180 |
#ifdef DEBUG_CLOCKS
|
3181 |
// printf("CBDV %01x %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
|
3182 |
#endif
|
3183 |
PLB_clk = CPU_clk / D; |
3184 |
D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ |
3185 |
#ifdef DEBUG_CLOCKS
|
3186 |
// printf("OPDV %01x %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
|
3187 |
#endif
|
3188 |
OPB_clk = PLB_clk / D; |
3189 |
D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ |
3190 |
#ifdef DEBUG_CLOCKS
|
3191 |
// printf("EPDV %01x %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
|
3192 |
#endif
|
3193 |
EBC_clk = PLB_clk / D; |
3194 |
D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ |
3195 |
#ifdef DEBUG_CLOCKS
|
3196 |
// printf("MPDV %01x %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
|
3197 |
#endif
|
3198 |
MAL_clk = PLB_clk / D; |
3199 |
D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ |
3200 |
#ifdef DEBUG_CLOCKS
|
3201 |
// printf("PPDV %01x %d\n", cpc->pllmr[0] & 0x3, D);
|
3202 |
#endif
|
3203 |
PCI_clk = PLB_clk / D; |
3204 |
D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ |
3205 |
#ifdef DEBUG_CLOCKS
|
3206 |
// printf("U0DIV %01x %d\n", cpc->ucr & 0x7F, D);
|
3207 |
#endif
|
3208 |
UART0_clk = PLL_out / D; |
3209 |
D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ |
3210 |
#ifdef DEBUG_CLOCKS
|
3211 |
// printf("U1DIV %01x %d\n", (cpc->ucr >> 8) & 0x7F, D);
|
3212 |
#endif
|
3213 |
UART1_clk = PLL_out / D; |
3214 |
#ifdef DEBUG_CLOCKS
|
3215 |
printf("Setup PPC405EP clocks - sysclk %d VCO %" PRIu64
|
3216 |
" PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); |
3217 |
printf("CPU %d PLB %d OPB %d EBC %d MAL %d PCI %d UART0 %d UART1 %d\n",
|
3218 |
CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, |
3219 |
UART0_clk, UART1_clk); |
3220 |
printf("CB %p opaque %p\n", cpc->clk_setup[PPC405EP_CPU_CLK].cb,
|
3221 |
cpc->clk_setup[PPC405EP_CPU_CLK].opaque); |
3222 |
#endif
|
3223 |
/* Setup CPU clocks */
|
3224 |
clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); |
3225 |
/* Setup PLB clock */
|
3226 |
clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); |
3227 |
/* Setup OPB clock */
|
3228 |
clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); |
3229 |
/* Setup external clock */
|
3230 |
clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); |
3231 |
/* Setup MAL clock */
|
3232 |
clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); |
3233 |
/* Setup PCI clock */
|
3234 |
clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); |
3235 |
/* Setup UART0 clock */
|
3236 |
clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); |
3237 |
/* Setup UART1 clock */
|
3238 |
clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); |
3239 |
} |
3240 |
|
3241 |
static target_ulong dcr_read_epcpc (void *opaque, int dcrn) |
3242 |
{ |
3243 |
ppc405ep_cpc_t *cpc; |
3244 |
target_ulong ret; |
3245 |
|
3246 |
cpc = opaque; |
3247 |
switch (dcrn) {
|
3248 |
case PPC405EP_CPC0_BOOT:
|
3249 |
ret = cpc->boot; |
3250 |
break;
|
3251 |
case PPC405EP_CPC0_EPCTL:
|
3252 |
ret = cpc->epctl; |
3253 |
break;
|
3254 |
case PPC405EP_CPC0_PLLMR0:
|
3255 |
ret = cpc->pllmr[0];
|
3256 |
break;
|
3257 |
case PPC405EP_CPC0_PLLMR1:
|
3258 |
ret = cpc->pllmr[1];
|
3259 |
break;
|
3260 |
case PPC405EP_CPC0_UCR:
|
3261 |
ret = cpc->ucr; |
3262 |
break;
|
3263 |
case PPC405EP_CPC0_SRR:
|
3264 |
ret = cpc->srr; |
3265 |
break;
|
3266 |
case PPC405EP_CPC0_JTAGID:
|
3267 |
ret = cpc->jtagid; |
3268 |
break;
|
3269 |
case PPC405EP_CPC0_PCI:
|
3270 |
ret = cpc->pci; |
3271 |
break;
|
3272 |
default:
|
3273 |
/* Avoid gcc warning */
|
3274 |
ret = 0;
|
3275 |
break;
|
3276 |
} |
3277 |
|
3278 |
return ret;
|
3279 |
} |
3280 |
|
3281 |
static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val) |
3282 |
{ |
3283 |
ppc405ep_cpc_t *cpc; |
3284 |
|
3285 |
cpc = opaque; |
3286 |
switch (dcrn) {
|
3287 |
case PPC405EP_CPC0_BOOT:
|
3288 |
/* Read-only register */
|
3289 |
break;
|
3290 |
case PPC405EP_CPC0_EPCTL:
|
3291 |
/* Don't care for now */
|
3292 |
cpc->epctl = val & 0xC00000F3;
|
3293 |
break;
|
3294 |
case PPC405EP_CPC0_PLLMR0:
|
3295 |
cpc->pllmr[0] = val & 0x00633333; |
3296 |
ppc405ep_compute_clocks(cpc); |
3297 |
break;
|
3298 |
case PPC405EP_CPC0_PLLMR1:
|
3299 |
cpc->pllmr[1] = val & 0xC0F73FFF; |
3300 |
ppc405ep_compute_clocks(cpc); |
3301 |
break;
|
3302 |
case PPC405EP_CPC0_UCR:
|
3303 |
/* UART control - don't care for now */
|
3304 |
cpc->ucr = val & 0x003F7F7F;
|
3305 |
break;
|
3306 |
case PPC405EP_CPC0_SRR:
|
3307 |
cpc->srr = val; |
3308 |
break;
|
3309 |
case PPC405EP_CPC0_JTAGID:
|
3310 |
/* Read-only */
|
3311 |
break;
|
3312 |
case PPC405EP_CPC0_PCI:
|
3313 |
cpc->pci = val; |
3314 |
break;
|
3315 |
} |
3316 |
} |
3317 |
|
3318 |
static void ppc405ep_cpc_reset (void *opaque) |
3319 |
{ |
3320 |
ppc405ep_cpc_t *cpc = opaque; |
3321 |
|
3322 |
cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ |
3323 |
cpc->epctl = 0x00000000;
|
3324 |
cpc->pllmr[0] = 0x00011010; |
3325 |
cpc->pllmr[1] = 0x40000000; |
3326 |
cpc->ucr = 0x00000000;
|
3327 |
cpc->srr = 0x00040000;
|
3328 |
cpc->pci = 0x00000000;
|
3329 |
cpc->er = 0x00000000;
|
3330 |
cpc->fr = 0x00000000;
|
3331 |
cpc->sr = 0x00000000;
|
3332 |
ppc405ep_compute_clocks(cpc); |
3333 |
} |
3334 |
|
3335 |
/* XXX: sysclk should be between 25 and 100 MHz */
|
3336 |
static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], |
3337 |
uint32_t sysclk) |
3338 |
{ |
3339 |
ppc405ep_cpc_t *cpc; |
3340 |
|
3341 |
cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
|
3342 |
if (cpc != NULL) { |
3343 |
memcpy(cpc->clk_setup, clk_setup, |
3344 |
PPC405EP_CLK_NB * sizeof(clk_setup_t));
|
3345 |
cpc->jtagid = 0x20267049;
|
3346 |
cpc->sysclk = sysclk; |
3347 |
ppc405ep_cpc_reset(cpc); |
3348 |
qemu_register_reset(&ppc405ep_cpc_reset, cpc); |
3349 |
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, |
3350 |
&dcr_read_epcpc, &dcr_write_epcpc); |
3351 |
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, |
3352 |
&dcr_read_epcpc, &dcr_write_epcpc); |
3353 |
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, |
3354 |
&dcr_read_epcpc, &dcr_write_epcpc); |
3355 |
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, |
3356 |
&dcr_read_epcpc, &dcr_write_epcpc); |
3357 |
ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, |
3358 |
&dcr_read_epcpc, &dcr_write_epcpc); |
3359 |
ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, |
3360 |
&dcr_read_epcpc, &dcr_write_epcpc); |
3361 |
ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, |
3362 |
&dcr_read_epcpc, &dcr_write_epcpc); |
3363 |
ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, |
3364 |
&dcr_read_epcpc, &dcr_write_epcpc); |
3365 |
#if 0
|
3366 |
ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
|
3367 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
3368 |
ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
|
3369 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
3370 |
ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
|
3371 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
3372 |
#endif
|
3373 |
} |
3374 |
} |
3375 |
|
3376 |
CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
|
3377 |
target_phys_addr_t ram_sizes[2],
|
3378 |
uint32_t sysclk, qemu_irq **picp, |
3379 |
ram_addr_t *offsetp, int do_init)
|
3380 |
{ |
3381 |
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; |
3382 |
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; |
3383 |
CPUState *env; |
3384 |
ppc4xx_mmio_t *mmio; |
3385 |
qemu_irq *pic, *irqs; |
3386 |
ram_addr_t offset; |
3387 |
int i;
|
3388 |
|
3389 |
memset(clk_setup, 0, sizeof(clk_setup)); |
3390 |
/* init CPUs */
|
3391 |
env = ppc405_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
|
3392 |
&tlb_clk_setup, sysclk); |
3393 |
clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; |
3394 |
clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; |
3395 |
/* Internal devices init */
|
3396 |
/* Memory mapped devices registers */
|
3397 |
mmio = ppc4xx_mmio_init(env, 0xEF600000);
|
3398 |
/* PLB arbitrer */
|
3399 |
ppc4xx_plb_init(env); |
3400 |
/* PLB to OPB bridge */
|
3401 |
ppc4xx_pob_init(env); |
3402 |
/* OBP arbitrer */
|
3403 |
ppc4xx_opba_init(env, mmio, 0x600);
|
3404 |
/* Universal interrupt controller */
|
3405 |
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
3406 |
irqs[PPCUIC_OUTPUT_INT] = |
3407 |
((qemu_irq *)env->irq_inputs)[PPC405_INPUT_INT]; |
3408 |
irqs[PPCUIC_OUTPUT_CINT] = |
3409 |
((qemu_irq *)env->irq_inputs)[PPC405_INPUT_CINT]; |
3410 |
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
3411 |
*picp = pic; |
3412 |
/* SDRAM controller */
|
3413 |
ppc405_sdram_init(env, pic[14], 2, ram_bases, ram_sizes, do_init); |
3414 |
offset = 0;
|
3415 |
for (i = 0; i < 2; i++) |
3416 |
offset += ram_sizes[i]; |
3417 |
/* External bus controller */
|
3418 |
ppc405_ebc_init(env); |
3419 |
/* DMA controller */
|
3420 |
dma_irqs[0] = pic[26]; |
3421 |
dma_irqs[1] = pic[25]; |
3422 |
dma_irqs[2] = pic[24]; |
3423 |
dma_irqs[3] = pic[23]; |
3424 |
ppc405_dma_init(env, dma_irqs); |
3425 |
/* IIC controller */
|
3426 |
ppc405_i2c_init(env, mmio, 0x500, pic[29]); |
3427 |
/* GPIO */
|
3428 |
ppc405_gpio_init(env, mmio, 0x700);
|
3429 |
/* Serial ports */
|
3430 |
if (serial_hds[0] != NULL) { |
3431 |
ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]); |
3432 |
} |
3433 |
if (serial_hds[1] != NULL) { |
3434 |
ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]); |
3435 |
} |
3436 |
/* OCM */
|
3437 |
ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]); |
3438 |
offset += 4096;
|
3439 |
/* GPT */
|
3440 |
gpt_irqs[0] = pic[12]; |
3441 |
gpt_irqs[1] = pic[11]; |
3442 |
gpt_irqs[2] = pic[10]; |
3443 |
gpt_irqs[3] = pic[9]; |
3444 |
gpt_irqs[4] = pic[8]; |
3445 |
ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
|
3446 |
/* PCI */
|
3447 |
/* Uses pic[28], pic[15], pic[13] */
|
3448 |
/* MAL */
|
3449 |
mal_irqs[0] = pic[20]; |
3450 |
mal_irqs[1] = pic[19]; |
3451 |
mal_irqs[2] = pic[18]; |
3452 |
mal_irqs[3] = pic[17]; |
3453 |
ppc405_mal_init(env, mal_irqs); |
3454 |
/* Ethernet */
|
3455 |
/* Uses pic[22], pic[16], pic[14] */
|
3456 |
/* CPU control */
|
3457 |
ppc405ep_cpc_init(env, clk_setup, sysclk); |
3458 |
*offsetp = offset; |
3459 |
|
3460 |
return env;
|
3461 |
} |