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/*
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* PowerPC emulation helpers for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <signal.h> |
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#include <assert.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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//#define DEBUG_MMU
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//#define DEBUG_BATS
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//#define DEBUG_SOFTWARE_TLB
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//#define DEBUG_EXCEPTIONS
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//#define FLUSH_ALL_TLBS
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/*****************************************************************************/
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/* PowerPC MMU emulation */
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#if defined(CONFIG_USER_ONLY)
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int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int is_user, int is_softmmu) |
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{ |
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int exception, error_code;
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if (rw == 2) { |
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exception = EXCP_ISI; |
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error_code = 0;
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} else {
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exception = EXCP_DSI; |
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error_code = 0;
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if (rw)
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error_code |= 0x02000000;
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env->spr[SPR_DAR] = address; |
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env->spr[SPR_DSISR] = error_code; |
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} |
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env->exception_index = exception; |
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env->error_code = error_code; |
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return 1; |
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} |
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target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
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{ |
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return addr;
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} |
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#else
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/* Common routines used by software and hardware TLBs emulation */
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static inline int pte_is_valid (target_ulong pte0) |
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{ |
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return pte0 & 0x80000000 ? 1 : 0; |
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} |
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static inline void pte_invalidate (target_ulong *pte0) |
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{ |
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*pte0 &= ~0x80000000;
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} |
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#if defined(TARGET_PPC64)
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static inline int pte64_is_valid (target_ulong pte0) |
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{ |
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return pte0 & 0x0000000000000001ULL ? 1 : 0; |
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} |
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static inline void pte64_invalidate (target_ulong *pte0) |
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{ |
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*pte0 &= ~0x0000000000000001ULL;
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} |
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#endif
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#define PTE_PTEM_MASK 0x7FFFFFBF |
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#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) |
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#if defined(TARGET_PPC64)
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#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL |
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#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F) |
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#endif
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static inline int _pte_check (mmu_ctx_t *ctx, int is_64b, |
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target_ulong pte0, target_ulong pte1, |
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int h, int rw) |
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{ |
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target_ulong ptem, mmask; |
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int access, ret, pteh, ptev;
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access = 0;
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ret = -1;
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/* Check validity and table match */
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#if defined(TARGET_PPC64)
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if (is_64b) {
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ptev = pte64_is_valid(pte0); |
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pteh = (pte0 >> 1) & 1; |
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} else
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#endif
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{ |
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ptev = pte_is_valid(pte0); |
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pteh = (pte0 >> 6) & 1; |
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} |
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if (ptev && h == pteh) {
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/* Check vsid & api */
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#if defined(TARGET_PPC64)
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if (is_64b) {
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ptem = pte0 & PTE64_PTEM_MASK; |
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mmask = PTE64_CHECK_MASK; |
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} else
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#endif
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{ |
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ptem = pte0 & PTE_PTEM_MASK; |
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mmask = PTE_CHECK_MASK; |
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} |
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if (ptem == ctx->ptem) {
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if (ctx->raddr != (target_ulong)-1) { |
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/* all matches should have equal RPN, WIMG & PP */
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if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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if (loglevel != 0) |
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fprintf(logfile, "Bad RPN/WIMG/PP\n");
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return -3; |
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} |
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} |
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/* Compute access rights */
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if (ctx->key == 0) { |
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access = PAGE_READ; |
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if ((pte1 & 0x00000003) != 0x3) |
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access |= PAGE_WRITE; |
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} else {
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switch (pte1 & 0x00000003) { |
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case 0x0: |
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access = 0;
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break;
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case 0x1: |
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case 0x3: |
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access = PAGE_READ; |
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break;
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case 0x2: |
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access = PAGE_READ | PAGE_WRITE; |
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break;
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} |
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} |
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/* Keep the matching PTE informations */
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ctx->raddr = pte1; |
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ctx->prot = access; |
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if ((rw == 0 && (access & PAGE_READ)) || |
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(rw == 1 && (access & PAGE_WRITE))) {
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/* Access granted */
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#if defined (DEBUG_MMU)
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if (loglevel != 0) |
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fprintf(logfile, "PTE access granted !\n");
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#endif
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ret = 0;
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} else {
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/* Access right violation */
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#if defined (DEBUG_MMU)
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if (loglevel != 0) |
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fprintf(logfile, "PTE access rejected\n");
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#endif
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ret = -2;
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} |
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} |
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} |
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return ret;
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} |
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static int pte32_check (mmu_ctx_t *ctx, |
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target_ulong pte0, target_ulong pte1, int h, int rw) |
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{ |
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return _pte_check(ctx, 0, pte0, pte1, h, rw); |
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} |
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#if defined(TARGET_PPC64)
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static int pte64_check (mmu_ctx_t *ctx, |
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target_ulong pte0, target_ulong pte1, int h, int rw) |
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{ |
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return _pte_check(ctx, 1, pte0, pte1, h, rw); |
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} |
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#endif
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static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p, |
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int ret, int rw) |
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{ |
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int store = 0; |
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/* Update page flags */
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if (!(*pte1p & 0x00000100)) { |
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/* Update accessed flag */
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*pte1p |= 0x00000100;
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store = 1;
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} |
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if (!(*pte1p & 0x00000080)) { |
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if (rw == 1 && ret == 0) { |
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/* Update changed flag */
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*pte1p |= 0x00000080;
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store = 1;
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} else {
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/* Force page fault for first write access */
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ctx->prot &= ~PAGE_WRITE; |
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} |
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} |
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return store;
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} |
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/* Software driven TLB helpers */
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static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr, |
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int way, int is_code) |
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{ |
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int nr;
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/* Select TLB num in a way from address */
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nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
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/* Select TLB way */
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nr += env->tlb_per_way * way; |
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/* 6xx have separate TLBs for instructions and data */
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if (is_code && env->id_tlbs == 1) |
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nr += env->nb_tlb; |
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return nr;
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} |
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void ppc6xx_tlb_invalidate_all (CPUState *env)
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{ |
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ppc6xx_tlb_t *tlb; |
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int nr, max;
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#if defined (DEBUG_SOFTWARE_TLB) && 0 |
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if (loglevel != 0) { |
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fprintf(logfile, "Invalidate all TLBs\n");
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} |
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#endif
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/* Invalidate all defined software TLB */
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max = env->nb_tlb; |
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if (env->id_tlbs == 1) |
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max *= 2;
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for (nr = 0; nr < max; nr++) { |
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tlb = &env->tlb[nr].tlb6; |
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#if !defined(FLUSH_ALL_TLBS)
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tlb_flush_page(env, tlb->EPN); |
258 |
#endif
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pte_invalidate(&tlb->pte0); |
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} |
261 |
#if defined(FLUSH_ALL_TLBS)
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tlb_flush(env, 1);
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#endif
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} |
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static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, |
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target_ulong eaddr, |
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int is_code, int match_epn) |
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{ |
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#if !defined(FLUSH_ALL_TLBS)
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ppc6xx_tlb_t *tlb; |
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int way, nr;
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/* Invalidate ITLB + DTLB, all ways */
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for (way = 0; way < env->nb_ways; way++) { |
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nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); |
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tlb = &env->tlb[nr].tlb6; |
278 |
if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
279 |
#if defined (DEBUG_SOFTWARE_TLB)
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if (loglevel != 0) { |
281 |
fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n", |
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nr, env->nb_tlb, eaddr); |
283 |
} |
284 |
#endif
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pte_invalidate(&tlb->pte0); |
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tlb_flush_page(env, tlb->EPN); |
287 |
} |
288 |
} |
289 |
#else
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/* XXX: PowerPC specification say this is valid as well */
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ppc6xx_tlb_invalidate_all(env); |
292 |
#endif
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} |
294 |
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void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
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int is_code)
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{ |
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__ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
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} |
300 |
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void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, |
302 |
target_ulong pte0, target_ulong pte1) |
303 |
{ |
304 |
ppc6xx_tlb_t *tlb; |
305 |
int nr;
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306 |
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nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); |
308 |
tlb = &env->tlb[nr].tlb6; |
309 |
#if defined (DEBUG_SOFTWARE_TLB)
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if (loglevel != 0) { |
311 |
fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX |
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" PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1); |
313 |
} |
314 |
#endif
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/* Invalidate any pending reference in Qemu for this virtual address */
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__ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
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tlb->pte0 = pte0; |
318 |
tlb->pte1 = pte1; |
319 |
tlb->EPN = EPN; |
320 |
/* Store last way for LRU mechanism */
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env->last_way = way; |
322 |
} |
323 |
|
324 |
static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, |
325 |
target_ulong eaddr, int rw, int access_type) |
326 |
{ |
327 |
ppc6xx_tlb_t *tlb; |
328 |
int nr, best, way;
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int ret;
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330 |
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331 |
best = -1;
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ret = -1; /* No TLB found */ |
333 |
for (way = 0; way < env->nb_ways; way++) { |
334 |
nr = ppc6xx_tlb_getnum(env, eaddr, way, |
335 |
access_type == ACCESS_CODE ? 1 : 0); |
336 |
tlb = &env->tlb[nr].tlb6; |
337 |
/* This test "emulates" the PTE index match for hardware TLBs */
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338 |
if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
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339 |
#if defined (DEBUG_SOFTWARE_TLB)
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340 |
if (loglevel != 0) { |
341 |
fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX |
342 |
"] <> " ADDRX "\n", |
343 |
nr, env->nb_tlb, |
344 |
pte_is_valid(tlb->pte0) ? "valid" : "inval", |
345 |
tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); |
346 |
} |
347 |
#endif
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348 |
continue;
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349 |
} |
350 |
#if defined (DEBUG_SOFTWARE_TLB)
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351 |
if (loglevel != 0) { |
352 |
fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX |
353 |
" %c %c\n",
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nr, env->nb_tlb, |
355 |
pte_is_valid(tlb->pte0) ? "valid" : "inval", |
356 |
tlb->EPN, eaddr, tlb->pte1, |
357 |
rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); |
358 |
} |
359 |
#endif
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360 |
switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) { |
361 |
case -3: |
362 |
/* TLB inconsistency */
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363 |
return -1; |
364 |
case -2: |
365 |
/* Access violation */
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366 |
ret = -2;
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367 |
best = nr; |
368 |
break;
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369 |
case -1: |
370 |
default:
|
371 |
/* No match */
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372 |
break;
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373 |
case 0: |
374 |
/* access granted */
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375 |
/* XXX: we should go on looping to check all TLBs consistency
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376 |
* but we can speed-up the whole thing as the
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377 |
* result would be undefined if TLBs are not consistent.
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378 |
*/
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379 |
ret = 0;
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380 |
best = nr; |
381 |
goto done;
|
382 |
} |
383 |
} |
384 |
if (best != -1) { |
385 |
done:
|
386 |
#if defined (DEBUG_SOFTWARE_TLB)
|
387 |
if (loglevel != 0) { |
388 |
fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
|
389 |
ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); |
390 |
} |
391 |
#endif
|
392 |
/* Update page flags */
|
393 |
pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); |
394 |
} |
395 |
|
396 |
return ret;
|
397 |
} |
398 |
|
399 |
/* Perform BAT hit & translation */
|
400 |
static int get_bat (CPUState *env, mmu_ctx_t *ctx, |
401 |
target_ulong virtual, int rw, int type) |
402 |
{ |
403 |
target_ulong *BATlt, *BATut, *BATu, *BATl; |
404 |
target_ulong base, BEPIl, BEPIu, bl; |
405 |
int i;
|
406 |
int ret = -1; |
407 |
|
408 |
#if defined (DEBUG_BATS)
|
409 |
if (loglevel != 0) { |
410 |
fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__, |
411 |
type == ACCESS_CODE ? 'I' : 'D', virtual); |
412 |
} |
413 |
#endif
|
414 |
switch (type) {
|
415 |
case ACCESS_CODE:
|
416 |
BATlt = env->IBAT[1];
|
417 |
BATut = env->IBAT[0];
|
418 |
break;
|
419 |
default:
|
420 |
BATlt = env->DBAT[1];
|
421 |
BATut = env->DBAT[0];
|
422 |
break;
|
423 |
} |
424 |
#if defined (DEBUG_BATS)
|
425 |
if (loglevel != 0) { |
426 |
fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__, |
427 |
type == ACCESS_CODE ? 'I' : 'D', virtual); |
428 |
} |
429 |
#endif
|
430 |
base = virtual & 0xFFFC0000;
|
431 |
for (i = 0; i < 4; i++) { |
432 |
BATu = &BATut[i]; |
433 |
BATl = &BATlt[i]; |
434 |
BEPIu = *BATu & 0xF0000000;
|
435 |
BEPIl = *BATu & 0x0FFE0000;
|
436 |
bl = (*BATu & 0x00001FFC) << 15; |
437 |
#if defined (DEBUG_BATS)
|
438 |
if (loglevel != 0) { |
439 |
fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
440 |
" BATl 0x" ADDRX "\n", |
441 |
__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
442 |
*BATu, *BATl); |
443 |
} |
444 |
#endif
|
445 |
if ((virtual & 0xF0000000) == BEPIu && |
446 |
((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
|
447 |
/* BAT matches */
|
448 |
if ((msr_pr == 0 && (*BATu & 0x00000002)) || |
449 |
(msr_pr == 1 && (*BATu & 0x00000001))) { |
450 |
/* Get physical address */
|
451 |
ctx->raddr = (*BATl & 0xF0000000) |
|
452 |
((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
453 |
(virtual & 0x0001F000);
|
454 |
if (*BATl & 0x00000001) |
455 |
ctx->prot = PAGE_READ; |
456 |
if (*BATl & 0x00000002) |
457 |
ctx->prot = PAGE_WRITE | PAGE_READ; |
458 |
#if defined (DEBUG_BATS)
|
459 |
if (loglevel != 0) { |
460 |
fprintf(logfile, "BAT %d match: r 0x" PADDRX
|
461 |
" prot=%c%c\n",
|
462 |
i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
463 |
ctx->prot & PAGE_WRITE ? 'W' : '-'); |
464 |
} |
465 |
#endif
|
466 |
ret = 0;
|
467 |
break;
|
468 |
} |
469 |
} |
470 |
} |
471 |
if (ret < 0) { |
472 |
#if defined (DEBUG_BATS)
|
473 |
if (loglevel != 0) { |
474 |
fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual); |
475 |
for (i = 0; i < 4; i++) { |
476 |
BATu = &BATut[i]; |
477 |
BATl = &BATlt[i]; |
478 |
BEPIu = *BATu & 0xF0000000;
|
479 |
BEPIl = *BATu & 0x0FFE0000;
|
480 |
bl = (*BATu & 0x00001FFC) << 15; |
481 |
fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
482 |
" BATl 0x" ADDRX " \n\t" |
483 |
"0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n", |
484 |
__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
485 |
*BATu, *BATl, BEPIu, BEPIl, bl); |
486 |
} |
487 |
} |
488 |
#endif
|
489 |
} |
490 |
/* No hit */
|
491 |
return ret;
|
492 |
} |
493 |
|
494 |
/* PTE table lookup */
|
495 |
static inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw) |
496 |
{ |
497 |
target_ulong base, pte0, pte1; |
498 |
int i, good = -1; |
499 |
int ret, r;
|
500 |
|
501 |
ret = -1; /* No entry found */ |
502 |
base = ctx->pg_addr[h]; |
503 |
for (i = 0; i < 8; i++) { |
504 |
#if defined(TARGET_PPC64)
|
505 |
if (is_64b) {
|
506 |
pte0 = ldq_phys(base + (i * 16));
|
507 |
pte1 = ldq_phys(base + (i * 16) + 8); |
508 |
r = pte64_check(ctx, pte0, pte1, h, rw); |
509 |
} else
|
510 |
#endif
|
511 |
{ |
512 |
pte0 = ldl_phys(base + (i * 8));
|
513 |
pte1 = ldl_phys(base + (i * 8) + 4); |
514 |
r = pte32_check(ctx, pte0, pte1, h, rw); |
515 |
} |
516 |
#if defined (DEBUG_MMU)
|
517 |
if (loglevel != 0) { |
518 |
fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX |
519 |
" 0x" ADDRX " %d %d %d 0x" ADDRX "\n", |
520 |
base + (i * 8), pte0, pte1,
|
521 |
(int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), ctx->ptem); |
522 |
} |
523 |
#endif
|
524 |
switch (r) {
|
525 |
case -3: |
526 |
/* PTE inconsistency */
|
527 |
return -1; |
528 |
case -2: |
529 |
/* Access violation */
|
530 |
ret = -2;
|
531 |
good = i; |
532 |
break;
|
533 |
case -1: |
534 |
default:
|
535 |
/* No PTE match */
|
536 |
break;
|
537 |
case 0: |
538 |
/* access granted */
|
539 |
/* XXX: we should go on looping to check all PTEs consistency
|
540 |
* but if we can speed-up the whole thing as the
|
541 |
* result would be undefined if PTEs are not consistent.
|
542 |
*/
|
543 |
ret = 0;
|
544 |
good = i; |
545 |
goto done;
|
546 |
} |
547 |
} |
548 |
if (good != -1) { |
549 |
done:
|
550 |
#if defined (DEBUG_MMU)
|
551 |
if (loglevel != 0) { |
552 |
fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x " |
553 |
"ret=%d\n",
|
554 |
ctx->raddr, ctx->prot, ret); |
555 |
} |
556 |
#endif
|
557 |
/* Update page flags */
|
558 |
pte1 = ctx->raddr; |
559 |
if (pte_update_flags(ctx, &pte1, ret, rw) == 1) { |
560 |
#if defined(TARGET_PPC64)
|
561 |
if (is_64b) {
|
562 |
stq_phys_notdirty(base + (good * 16) + 8, pte1); |
563 |
} else
|
564 |
#endif
|
565 |
{ |
566 |
stl_phys_notdirty(base + (good * 8) + 4, pte1); |
567 |
} |
568 |
} |
569 |
} |
570 |
|
571 |
return ret;
|
572 |
} |
573 |
|
574 |
static int find_pte32 (mmu_ctx_t *ctx, int h, int rw) |
575 |
{ |
576 |
return _find_pte(ctx, 0, h, rw); |
577 |
} |
578 |
|
579 |
#if defined(TARGET_PPC64)
|
580 |
static int find_pte64 (mmu_ctx_t *ctx, int h, int rw) |
581 |
{ |
582 |
return _find_pte(ctx, 1, h, rw); |
583 |
} |
584 |
#endif
|
585 |
|
586 |
static inline int find_pte (CPUState *env, mmu_ctx_t *ctx, int h, int rw) |
587 |
{ |
588 |
#if defined(TARGET_PPC64)
|
589 |
if (env->mmu_model == POWERPC_MMU_64B ||
|
590 |
env->mmu_model == POWERPC_MMU_64BRIDGE) |
591 |
return find_pte64(ctx, h, rw);
|
592 |
#endif
|
593 |
|
594 |
return find_pte32(ctx, h, rw);
|
595 |
} |
596 |
|
597 |
static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1, |
598 |
int sdr_sh,
|
599 |
target_phys_addr_t hash, |
600 |
target_phys_addr_t mask) |
601 |
{ |
602 |
return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask); |
603 |
} |
604 |
|
605 |
#if defined(TARGET_PPC64)
|
606 |
static int slb_lookup (CPUState *env, target_ulong eaddr, |
607 |
target_ulong *vsid, target_ulong *page_mask, int *attr)
|
608 |
{ |
609 |
target_phys_addr_t sr_base; |
610 |
target_ulong mask; |
611 |
uint64_t tmp64; |
612 |
uint32_t tmp; |
613 |
int n, ret;
|
614 |
int slb_nr;
|
615 |
|
616 |
ret = -5;
|
617 |
sr_base = env->spr[SPR_ASR]; |
618 |
mask = 0x0000000000000000ULL; /* Avoid gcc warning */ |
619 |
#if 0 /* XXX: Fix this */
|
620 |
slb_nr = env->slb_nr;
|
621 |
#else
|
622 |
slb_nr = 32;
|
623 |
#endif
|
624 |
for (n = 0; n < slb_nr; n++) { |
625 |
tmp64 = ldq_phys(sr_base); |
626 |
if (tmp64 & 0x0000000008000000ULL) { |
627 |
/* SLB entry is valid */
|
628 |
switch (tmp64 & 0x0000000006000000ULL) { |
629 |
case 0x0000000000000000ULL: |
630 |
/* 256 MB segment */
|
631 |
mask = 0xFFFFFFFFF0000000ULL;
|
632 |
break;
|
633 |
case 0x0000000002000000ULL: |
634 |
/* 1 TB segment */
|
635 |
mask = 0xFFFF000000000000ULL;
|
636 |
break;
|
637 |
case 0x0000000004000000ULL: |
638 |
case 0x0000000006000000ULL: |
639 |
/* Reserved => segment is invalid */
|
640 |
continue;
|
641 |
} |
642 |
if ((eaddr & mask) == (tmp64 & mask)) {
|
643 |
/* SLB match */
|
644 |
tmp = ldl_phys(sr_base + 8);
|
645 |
*vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL; |
646 |
*page_mask = ~mask; |
647 |
*attr = tmp & 0xFF;
|
648 |
ret = 0;
|
649 |
break;
|
650 |
} |
651 |
} |
652 |
sr_base += 12;
|
653 |
} |
654 |
|
655 |
return ret;
|
656 |
} |
657 |
#endif /* defined(TARGET_PPC64) */ |
658 |
|
659 |
/* Perform segment based translation */
|
660 |
static int get_segment (CPUState *env, mmu_ctx_t *ctx, |
661 |
target_ulong eaddr, int rw, int type) |
662 |
{ |
663 |
target_phys_addr_t sdr, hash, mask, sdr_mask; |
664 |
target_ulong sr, vsid, vsid_mask, pgidx, page_mask; |
665 |
#if defined(TARGET_PPC64)
|
666 |
int attr;
|
667 |
#endif
|
668 |
int ds, nx, vsid_sh, sdr_sh;
|
669 |
int ret, ret2;
|
670 |
|
671 |
#if defined(TARGET_PPC64)
|
672 |
if (env->mmu_model == POWERPC_MMU_64B) {
|
673 |
ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr); |
674 |
if (ret < 0) |
675 |
return ret;
|
676 |
ctx->key = ((attr & 0x40) && msr_pr == 1) || |
677 |
((attr & 0x80) && msr_pr == 0) ? 1 : 0; |
678 |
ds = 0;
|
679 |
nx = attr & 0x20 ? 1 : 0; |
680 |
vsid_mask = 0x00003FFFFFFFFF80ULL;
|
681 |
vsid_sh = 7;
|
682 |
sdr_sh = 18;
|
683 |
sdr_mask = 0x3FF80;
|
684 |
} else
|
685 |
#endif /* defined(TARGET_PPC64) */ |
686 |
{ |
687 |
sr = env->sr[eaddr >> 28];
|
688 |
page_mask = 0x0FFFFFFF;
|
689 |
ctx->key = (((sr & 0x20000000) && msr_pr == 1) || |
690 |
((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0; |
691 |
ds = sr & 0x80000000 ? 1 : 0; |
692 |
nx = sr & 0x10000000 ? 1 : 0; |
693 |
vsid = sr & 0x00FFFFFF;
|
694 |
vsid_mask = 0x01FFFFC0;
|
695 |
vsid_sh = 6;
|
696 |
sdr_sh = 16;
|
697 |
sdr_mask = 0xFFC0;
|
698 |
#if defined (DEBUG_MMU)
|
699 |
if (loglevel != 0) { |
700 |
fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX |
701 |
" nip=0x" ADDRX " lr=0x" ADDRX |
702 |
" ir=%d dr=%d pr=%d %d t=%d\n",
|
703 |
eaddr, (int)(eaddr >> 28), sr, env->nip, |
704 |
env->lr, msr_ir, msr_dr, msr_pr, rw, type); |
705 |
} |
706 |
if (!ds && loglevel != 0) { |
707 |
fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n", |
708 |
ctx->key, sr & 0x10000000);
|
709 |
} |
710 |
#endif
|
711 |
} |
712 |
ret = -1;
|
713 |
if (!ds) {
|
714 |
/* Check if instruction fetch is allowed, if needed */
|
715 |
if (type != ACCESS_CODE || nx == 0) { |
716 |
/* Page address translation */
|
717 |
pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS; |
718 |
hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
719 |
/* Primary table address */
|
720 |
sdr = env->sdr1; |
721 |
mask = ((sdr & 0x000001FF) << sdr_sh) | sdr_mask;
|
722 |
ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
723 |
/* Secondary table address */
|
724 |
hash = (~hash) & vsid_mask; |
725 |
ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
726 |
#if defined(TARGET_PPC64)
|
727 |
if (env->mmu_model == POWERPC_MMU_64B ||
|
728 |
env->mmu_model == POWERPC_MMU_64BRIDGE) { |
729 |
/* Only 5 bits of the page index are used in the AVPN */
|
730 |
ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80); |
731 |
} else
|
732 |
#endif
|
733 |
{ |
734 |
ctx->ptem = (vsid << 7) | (pgidx >> 10); |
735 |
} |
736 |
/* Initialize real address with an invalid value */
|
737 |
ctx->raddr = (target_ulong)-1;
|
738 |
if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
|
739 |
/* Software TLB search */
|
740 |
ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); |
741 |
} else {
|
742 |
#if defined (DEBUG_MMU)
|
743 |
if (loglevel != 0) { |
744 |
fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x " |
745 |
"api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n", |
746 |
sdr, (uint32_t)vsid, (uint32_t)pgidx, |
747 |
(uint32_t)hash, ctx->pg_addr[0]);
|
748 |
} |
749 |
#endif
|
750 |
/* Primary table lookup */
|
751 |
ret = find_pte(env, ctx, 0, rw);
|
752 |
if (ret < 0) { |
753 |
/* Secondary table lookup */
|
754 |
#if defined (DEBUG_MMU)
|
755 |
if (eaddr != 0xEFFFFFFF && loglevel != 0) { |
756 |
fprintf(logfile, |
757 |
"1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x " |
758 |
"hash=0x%05x pg_addr=0x" PADDRX "\n", |
759 |
sdr, (uint32_t)vsid, (uint32_t)pgidx, |
760 |
(uint32_t)hash, ctx->pg_addr[1]);
|
761 |
} |
762 |
#endif
|
763 |
ret2 = find_pte(env, ctx, 1, rw);
|
764 |
if (ret2 != -1) |
765 |
ret = ret2; |
766 |
} |
767 |
} |
768 |
} else {
|
769 |
#if defined (DEBUG_MMU)
|
770 |
if (loglevel != 0) |
771 |
fprintf(logfile, "No access allowed\n");
|
772 |
#endif
|
773 |
ret = -3;
|
774 |
} |
775 |
} else {
|
776 |
#if defined (DEBUG_MMU)
|
777 |
if (loglevel != 0) |
778 |
fprintf(logfile, "direct store...\n");
|
779 |
#endif
|
780 |
/* Direct-store segment : absolutely *BUGGY* for now */
|
781 |
switch (type) {
|
782 |
case ACCESS_INT:
|
783 |
/* Integer load/store : only access allowed */
|
784 |
break;
|
785 |
case ACCESS_CODE:
|
786 |
/* No code fetch is allowed in direct-store areas */
|
787 |
return -4; |
788 |
case ACCESS_FLOAT:
|
789 |
/* Floating point load/store */
|
790 |
return -4; |
791 |
case ACCESS_RES:
|
792 |
/* lwarx, ldarx or srwcx. */
|
793 |
return -4; |
794 |
case ACCESS_CACHE:
|
795 |
/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
|
796 |
/* Should make the instruction do no-op.
|
797 |
* As it already do no-op, it's quite easy :-)
|
798 |
*/
|
799 |
ctx->raddr = eaddr; |
800 |
return 0; |
801 |
case ACCESS_EXT:
|
802 |
/* eciwx or ecowx */
|
803 |
return -4; |
804 |
default:
|
805 |
if (logfile) {
|
806 |
fprintf(logfile, "ERROR: instruction should not need "
|
807 |
"address translation\n");
|
808 |
} |
809 |
return -4; |
810 |
} |
811 |
if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
812 |
ctx->raddr = eaddr; |
813 |
ret = 2;
|
814 |
} else {
|
815 |
ret = -2;
|
816 |
} |
817 |
} |
818 |
|
819 |
return ret;
|
820 |
} |
821 |
|
822 |
/* Generic TLB check function for embedded PowerPC implementations */
|
823 |
static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb, |
824 |
target_phys_addr_t *raddrp, |
825 |
target_ulong address, |
826 |
uint32_t pid, int ext, int i) |
827 |
{ |
828 |
target_ulong mask; |
829 |
|
830 |
/* Check valid flag */
|
831 |
if (!(tlb->prot & PAGE_VALID)) {
|
832 |
if (loglevel != 0) |
833 |
fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
|
834 |
return -1; |
835 |
} |
836 |
mask = ~(tlb->size - 1);
|
837 |
if (loglevel != 0) { |
838 |
fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> " |
839 |
ADDRX " " ADDRX " %d\n", |
840 |
__func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
|
841 |
} |
842 |
/* Check PID */
|
843 |
if (tlb->PID != 0 && tlb->PID != pid) |
844 |
return -1; |
845 |
/* Check effective address */
|
846 |
if ((address & mask) != tlb->EPN)
|
847 |
return -1; |
848 |
*raddrp = (tlb->RPN & mask) | (address & ~mask); |
849 |
#if (TARGET_PHYS_ADDR_BITS >= 36) |
850 |
if (ext) {
|
851 |
/* Extend the physical address to 36 bits */
|
852 |
*raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32; |
853 |
} |
854 |
#endif
|
855 |
|
856 |
return 0; |
857 |
} |
858 |
|
859 |
/* Generic TLB search function for PowerPC embedded implementations */
|
860 |
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
|
861 |
{ |
862 |
ppcemb_tlb_t *tlb; |
863 |
target_phys_addr_t raddr; |
864 |
int i, ret;
|
865 |
|
866 |
/* Default return value is no match */
|
867 |
ret = -1;
|
868 |
for (i = 0; i < env->nb_tlb; i++) { |
869 |
tlb = &env->tlb[i].tlbe; |
870 |
if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) { |
871 |
ret = i; |
872 |
break;
|
873 |
} |
874 |
} |
875 |
|
876 |
return ret;
|
877 |
} |
878 |
|
879 |
void ppc4xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
|
880 |
uint32_t pid) |
881 |
{ |
882 |
ppcemb_tlb_t *tlb; |
883 |
target_phys_addr_t raddr; |
884 |
target_ulong page, end; |
885 |
int i;
|
886 |
|
887 |
for (i = 0; i < env->nb_tlb; i++) { |
888 |
tlb = &env->tlb[i].tlbe; |
889 |
if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { |
890 |
end = tlb->EPN + tlb->size; |
891 |
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
892 |
tlb_flush_page(env, page); |
893 |
tlb->prot &= ~PAGE_VALID; |
894 |
break;
|
895 |
} |
896 |
} |
897 |
} |
898 |
|
899 |
/* Helpers specific to PowerPC 40x implementations */
|
900 |
void ppc4xx_tlb_invalidate_all (CPUState *env)
|
901 |
{ |
902 |
ppcemb_tlb_t *tlb; |
903 |
int i;
|
904 |
|
905 |
for (i = 0; i < env->nb_tlb; i++) { |
906 |
tlb = &env->tlb[i].tlbe; |
907 |
if (tlb->prot & PAGE_VALID) {
|
908 |
#if 0 // XXX: TLB have variable sizes then we flush all Qemu TLB.
|
909 |
end = tlb->EPN + tlb->size;
|
910 |
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
911 |
tlb_flush_page(env, page);
|
912 |
#endif
|
913 |
tlb->prot &= ~PAGE_VALID; |
914 |
} |
915 |
} |
916 |
tlb_flush(env, 1);
|
917 |
} |
918 |
|
919 |
int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
|
920 |
target_ulong address, int rw, int access_type) |
921 |
{ |
922 |
ppcemb_tlb_t *tlb; |
923 |
target_phys_addr_t raddr; |
924 |
int i, ret, zsel, zpr;
|
925 |
|
926 |
ret = -1;
|
927 |
raddr = -1;
|
928 |
for (i = 0; i < env->nb_tlb; i++) { |
929 |
tlb = &env->tlb[i].tlbe; |
930 |
if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
931 |
env->spr[SPR_40x_PID], 0, i) < 0) |
932 |
continue;
|
933 |
zsel = (tlb->attr >> 4) & 0xF; |
934 |
zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3; |
935 |
if (loglevel != 0) { |
936 |
fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
|
937 |
__func__, i, zsel, zpr, rw, tlb->attr); |
938 |
} |
939 |
if (access_type == ACCESS_CODE) {
|
940 |
/* Check execute enable bit */
|
941 |
switch (zpr) {
|
942 |
case 0x2: |
943 |
if (msr_pr)
|
944 |
goto check_exec_perm;
|
945 |
goto exec_granted;
|
946 |
case 0x0: |
947 |
if (msr_pr) {
|
948 |
ctx->prot = 0;
|
949 |
ret = -3;
|
950 |
break;
|
951 |
} |
952 |
/* No break here */
|
953 |
case 0x1: |
954 |
check_exec_perm:
|
955 |
/* Check from TLB entry */
|
956 |
if (!(tlb->prot & PAGE_EXEC)) {
|
957 |
ret = -3;
|
958 |
} else {
|
959 |
if (tlb->prot & PAGE_WRITE) {
|
960 |
ctx->prot = PAGE_READ | PAGE_WRITE; |
961 |
} else {
|
962 |
ctx->prot = PAGE_READ; |
963 |
} |
964 |
ret = 0;
|
965 |
} |
966 |
break;
|
967 |
case 0x3: |
968 |
exec_granted:
|
969 |
/* All accesses granted */
|
970 |
ctx->prot = PAGE_READ | PAGE_WRITE; |
971 |
ret = 0;
|
972 |
break;
|
973 |
} |
974 |
} else {
|
975 |
switch (zpr) {
|
976 |
case 0x2: |
977 |
if (msr_pr)
|
978 |
goto check_rw_perm;
|
979 |
goto rw_granted;
|
980 |
case 0x0: |
981 |
if (msr_pr) {
|
982 |
ctx->prot = 0;
|
983 |
ret = -2;
|
984 |
break;
|
985 |
} |
986 |
/* No break here */
|
987 |
case 0x1: |
988 |
check_rw_perm:
|
989 |
/* Check from TLB entry */
|
990 |
/* Check write protection bit */
|
991 |
if (tlb->prot & PAGE_WRITE) {
|
992 |
ctx->prot = PAGE_READ | PAGE_WRITE; |
993 |
ret = 0;
|
994 |
} else {
|
995 |
ctx->prot = PAGE_READ; |
996 |
if (rw)
|
997 |
ret = -2;
|
998 |
else
|
999 |
ret = 0;
|
1000 |
} |
1001 |
break;
|
1002 |
case 0x3: |
1003 |
rw_granted:
|
1004 |
/* All accesses granted */
|
1005 |
ctx->prot = PAGE_READ | PAGE_WRITE; |
1006 |
ret = 0;
|
1007 |
break;
|
1008 |
} |
1009 |
} |
1010 |
if (ret >= 0) { |
1011 |
ctx->raddr = raddr; |
1012 |
if (loglevel != 0) { |
1013 |
fprintf(logfile, "%s: access granted " ADDRX " => " REGX |
1014 |
" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
|
1015 |
ret); |
1016 |
} |
1017 |
return 0; |
1018 |
} |
1019 |
} |
1020 |
if (loglevel != 0) { |
1021 |
fprintf(logfile, "%s: access refused " ADDRX " => " REGX |
1022 |
" %d %d\n", __func__, address, raddr, ctx->prot,
|
1023 |
ret); |
1024 |
} |
1025 |
|
1026 |
return ret;
|
1027 |
} |
1028 |
|
1029 |
void store_40x_sler (CPUPPCState *env, uint32_t val)
|
1030 |
{ |
1031 |
/* XXX: TO BE FIXED */
|
1032 |
if (val != 0x00000000) { |
1033 |
cpu_abort(env, "Little-endian regions are not supported by now\n");
|
1034 |
} |
1035 |
env->spr[SPR_405_SLER] = val; |
1036 |
} |
1037 |
|
1038 |
int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
|
1039 |
target_ulong address, int rw,
|
1040 |
int access_type)
|
1041 |
{ |
1042 |
ppcemb_tlb_t *tlb; |
1043 |
target_phys_addr_t raddr; |
1044 |
int i, prot, ret;
|
1045 |
|
1046 |
ret = -1;
|
1047 |
raddr = -1;
|
1048 |
for (i = 0; i < env->nb_tlb; i++) { |
1049 |
tlb = &env->tlb[i].tlbe; |
1050 |
if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
1051 |
env->spr[SPR_BOOKE_PID], 1, i) < 0) |
1052 |
continue;
|
1053 |
if (msr_pr)
|
1054 |
prot = tlb->prot & 0xF;
|
1055 |
else
|
1056 |
prot = (tlb->prot >> 4) & 0xF; |
1057 |
/* Check the address space */
|
1058 |
if (access_type == ACCESS_CODE) {
|
1059 |
if (msr_is != (tlb->attr & 1)) |
1060 |
continue;
|
1061 |
ctx->prot = prot; |
1062 |
if (prot & PAGE_EXEC) {
|
1063 |
ret = 0;
|
1064 |
break;
|
1065 |
} |
1066 |
ret = -3;
|
1067 |
} else {
|
1068 |
if (msr_ds != (tlb->attr & 1)) |
1069 |
continue;
|
1070 |
ctx->prot = prot; |
1071 |
if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
|
1072 |
ret = 0;
|
1073 |
break;
|
1074 |
} |
1075 |
ret = -2;
|
1076 |
} |
1077 |
} |
1078 |
if (ret >= 0) |
1079 |
ctx->raddr = raddr; |
1080 |
|
1081 |
return ret;
|
1082 |
} |
1083 |
|
1084 |
static int check_physical (CPUState *env, mmu_ctx_t *ctx, |
1085 |
target_ulong eaddr, int rw)
|
1086 |
{ |
1087 |
int in_plb, ret;
|
1088 |
|
1089 |
ctx->raddr = eaddr; |
1090 |
ctx->prot = PAGE_READ; |
1091 |
ret = 0;
|
1092 |
switch (env->mmu_model) {
|
1093 |
case POWERPC_MMU_32B:
|
1094 |
case POWERPC_MMU_SOFT_6xx:
|
1095 |
case POWERPC_MMU_601:
|
1096 |
case POWERPC_MMU_SOFT_4xx:
|
1097 |
case POWERPC_MMU_REAL_4xx:
|
1098 |
ctx->prot |= PAGE_WRITE; |
1099 |
break;
|
1100 |
#if defined(TARGET_PPC64)
|
1101 |
case POWERPC_MMU_64B:
|
1102 |
case POWERPC_MMU_64BRIDGE:
|
1103 |
/* Real address are 60 bits long */
|
1104 |
ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
|
1105 |
ctx->prot |= PAGE_WRITE; |
1106 |
break;
|
1107 |
#endif
|
1108 |
case POWERPC_MMU_SOFT_4xx_Z:
|
1109 |
if (unlikely(msr_pe != 0)) { |
1110 |
/* 403 family add some particular protections,
|
1111 |
* using PBL/PBU registers for accesses with no translation.
|
1112 |
*/
|
1113 |
in_plb = |
1114 |
/* Check PLB validity */
|
1115 |
(env->pb[0] < env->pb[1] && |
1116 |
/* and address in plb area */
|
1117 |
eaddr >= env->pb[0] && eaddr < env->pb[1]) || |
1118 |
(env->pb[2] < env->pb[3] && |
1119 |
eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; |
1120 |
if (in_plb ^ msr_px) {
|
1121 |
/* Access in protected area */
|
1122 |
if (rw == 1) { |
1123 |
/* Access is not allowed */
|
1124 |
ret = -2;
|
1125 |
} |
1126 |
} else {
|
1127 |
/* Read-write access is allowed */
|
1128 |
ctx->prot |= PAGE_WRITE; |
1129 |
} |
1130 |
} |
1131 |
case POWERPC_MMU_BOOKE:
|
1132 |
ctx->prot |= PAGE_WRITE; |
1133 |
break;
|
1134 |
case POWERPC_MMU_BOOKE_FSL:
|
1135 |
/* XXX: TODO */
|
1136 |
cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1137 |
break;
|
1138 |
default:
|
1139 |
cpu_abort(env, "Unknown or invalid MMU model\n");
|
1140 |
return -1; |
1141 |
} |
1142 |
|
1143 |
return ret;
|
1144 |
} |
1145 |
|
1146 |
int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
|
1147 |
int rw, int access_type, int check_BATs) |
1148 |
{ |
1149 |
int ret;
|
1150 |
#if 0
|
1151 |
if (loglevel != 0) {
|
1152 |
fprintf(logfile, "%s\n", __func__);
|
1153 |
}
|
1154 |
#endif
|
1155 |
if ((access_type == ACCESS_CODE && msr_ir == 0) || |
1156 |
(access_type != ACCESS_CODE && msr_dr == 0)) {
|
1157 |
/* No address translation */
|
1158 |
ret = check_physical(env, ctx, eaddr, rw); |
1159 |
} else {
|
1160 |
ret = -1;
|
1161 |
switch (env->mmu_model) {
|
1162 |
case POWERPC_MMU_32B:
|
1163 |
case POWERPC_MMU_SOFT_6xx:
|
1164 |
/* Try to find a BAT */
|
1165 |
if (check_BATs)
|
1166 |
ret = get_bat(env, ctx, eaddr, rw, access_type); |
1167 |
/* No break here */
|
1168 |
#if defined(TARGET_PPC64)
|
1169 |
case POWERPC_MMU_64B:
|
1170 |
case POWERPC_MMU_64BRIDGE:
|
1171 |
#endif
|
1172 |
if (ret < 0) { |
1173 |
/* We didn't match any BAT entry or don't have BATs */
|
1174 |
ret = get_segment(env, ctx, eaddr, rw, access_type); |
1175 |
} |
1176 |
break;
|
1177 |
case POWERPC_MMU_SOFT_4xx:
|
1178 |
case POWERPC_MMU_SOFT_4xx_Z:
|
1179 |
ret = mmu40x_get_physical_address(env, ctx, eaddr, |
1180 |
rw, access_type); |
1181 |
break;
|
1182 |
case POWERPC_MMU_601:
|
1183 |
/* XXX: TODO */
|
1184 |
cpu_abort(env, "601 MMU model not implemented\n");
|
1185 |
return -1; |
1186 |
case POWERPC_MMU_BOOKE:
|
1187 |
ret = mmubooke_get_physical_address(env, ctx, eaddr, |
1188 |
rw, access_type); |
1189 |
break;
|
1190 |
case POWERPC_MMU_BOOKE_FSL:
|
1191 |
/* XXX: TODO */
|
1192 |
cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1193 |
return -1; |
1194 |
case POWERPC_MMU_REAL_4xx:
|
1195 |
cpu_abort(env, "PowerPC 401 does not do any translation\n");
|
1196 |
return -1; |
1197 |
default:
|
1198 |
cpu_abort(env, "Unknown or invalid MMU model\n");
|
1199 |
return -1; |
1200 |
} |
1201 |
} |
1202 |
#if 0
|
1203 |
if (loglevel != 0) {
|
1204 |
fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
|
1205 |
__func__, eaddr, ret, ctx->raddr);
|
1206 |
}
|
1207 |
#endif
|
1208 |
|
1209 |
return ret;
|
1210 |
} |
1211 |
|
1212 |
target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
1213 |
{ |
1214 |
mmu_ctx_t ctx; |
1215 |
|
1216 |
if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0)) |
1217 |
return -1; |
1218 |
|
1219 |
return ctx.raddr & TARGET_PAGE_MASK;
|
1220 |
} |
1221 |
|
1222 |
/* Perform address translation */
|
1223 |
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
1224 |
int is_user, int is_softmmu) |
1225 |
{ |
1226 |
mmu_ctx_t ctx; |
1227 |
int exception = 0, error_code = 0; |
1228 |
int access_type;
|
1229 |
int ret = 0; |
1230 |
|
1231 |
if (rw == 2) { |
1232 |
/* code access */
|
1233 |
rw = 0;
|
1234 |
access_type = ACCESS_CODE; |
1235 |
} else {
|
1236 |
/* data access */
|
1237 |
/* XXX: put correct access by using cpu_restore_state()
|
1238 |
correctly */
|
1239 |
access_type = ACCESS_INT; |
1240 |
// access_type = env->access_type;
|
1241 |
} |
1242 |
ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
|
1243 |
if (ret == 0) { |
1244 |
ret = tlb_set_page(env, address & TARGET_PAGE_MASK, |
1245 |
ctx.raddr & TARGET_PAGE_MASK, ctx.prot, |
1246 |
is_user, is_softmmu); |
1247 |
} else if (ret < 0) { |
1248 |
#if defined (DEBUG_MMU)
|
1249 |
if (loglevel != 0) |
1250 |
cpu_dump_state(env, logfile, fprintf, 0);
|
1251 |
#endif
|
1252 |
if (access_type == ACCESS_CODE) {
|
1253 |
exception = EXCP_ISI; |
1254 |
switch (ret) {
|
1255 |
case -1: |
1256 |
/* No matches in page tables or TLB */
|
1257 |
switch (env->mmu_model) {
|
1258 |
case POWERPC_MMU_SOFT_6xx:
|
1259 |
exception = EXCP_I_TLBMISS; |
1260 |
env->spr[SPR_IMISS] = address; |
1261 |
env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
|
1262 |
error_code = 1 << 18; |
1263 |
goto tlb_miss;
|
1264 |
case POWERPC_MMU_SOFT_4xx:
|
1265 |
case POWERPC_MMU_SOFT_4xx_Z:
|
1266 |
exception = EXCP_40x_ITLBMISS; |
1267 |
error_code = 0;
|
1268 |
env->spr[SPR_40x_DEAR] = address; |
1269 |
env->spr[SPR_40x_ESR] = 0x00000000;
|
1270 |
break;
|
1271 |
case POWERPC_MMU_32B:
|
1272 |
error_code = 0x40000000;
|
1273 |
break;
|
1274 |
#if defined(TARGET_PPC64)
|
1275 |
case POWERPC_MMU_64B:
|
1276 |
/* XXX: TODO */
|
1277 |
cpu_abort(env, "MMU model not implemented\n");
|
1278 |
return -1; |
1279 |
case POWERPC_MMU_64BRIDGE:
|
1280 |
/* XXX: TODO */
|
1281 |
cpu_abort(env, "MMU model not implemented\n");
|
1282 |
return -1; |
1283 |
#endif
|
1284 |
case POWERPC_MMU_601:
|
1285 |
/* XXX: TODO */
|
1286 |
cpu_abort(env, "MMU model not implemented\n");
|
1287 |
return -1; |
1288 |
case POWERPC_MMU_BOOKE:
|
1289 |
/* XXX: TODO */
|
1290 |
cpu_abort(env, "MMU model not implemented\n");
|
1291 |
return -1; |
1292 |
case POWERPC_MMU_BOOKE_FSL:
|
1293 |
/* XXX: TODO */
|
1294 |
cpu_abort(env, "MMU model not implemented\n");
|
1295 |
return -1; |
1296 |
case POWERPC_MMU_REAL_4xx:
|
1297 |
cpu_abort(env, "PowerPC 401 should never raise any MMU "
|
1298 |
"exceptions\n");
|
1299 |
return -1; |
1300 |
default:
|
1301 |
cpu_abort(env, "Unknown or invalid MMU model\n");
|
1302 |
return -1; |
1303 |
} |
1304 |
break;
|
1305 |
case -2: |
1306 |
/* Access rights violation */
|
1307 |
error_code = 0x08000000;
|
1308 |
break;
|
1309 |
case -3: |
1310 |
/* No execute protection violation */
|
1311 |
error_code = 0x10000000;
|
1312 |
break;
|
1313 |
case -4: |
1314 |
/* Direct store exception */
|
1315 |
/* No code fetch is allowed in direct-store areas */
|
1316 |
error_code = 0x10000000;
|
1317 |
break;
|
1318 |
case -5: |
1319 |
/* No match in segment table */
|
1320 |
exception = EXCP_ISEG; |
1321 |
error_code = 0;
|
1322 |
break;
|
1323 |
} |
1324 |
} else {
|
1325 |
exception = EXCP_DSI; |
1326 |
switch (ret) {
|
1327 |
case -1: |
1328 |
/* No matches in page tables or TLB */
|
1329 |
switch (env->mmu_model) {
|
1330 |
case POWERPC_MMU_SOFT_6xx:
|
1331 |
if (rw == 1) { |
1332 |
exception = EXCP_DS_TLBMISS; |
1333 |
error_code = 1 << 16; |
1334 |
} else {
|
1335 |
exception = EXCP_DL_TLBMISS; |
1336 |
error_code = 0;
|
1337 |
} |
1338 |
env->spr[SPR_DMISS] = address; |
1339 |
env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
|
1340 |
tlb_miss:
|
1341 |
error_code |= ctx.key << 19;
|
1342 |
env->spr[SPR_HASH1] = ctx.pg_addr[0];
|
1343 |
env->spr[SPR_HASH2] = ctx.pg_addr[1];
|
1344 |
/* Do not alter DAR nor DSISR */
|
1345 |
goto out;
|
1346 |
case POWERPC_MMU_SOFT_4xx:
|
1347 |
case POWERPC_MMU_SOFT_4xx_Z:
|
1348 |
exception = EXCP_40x_DTLBMISS; |
1349 |
error_code = 0;
|
1350 |
env->spr[SPR_40x_DEAR] = address; |
1351 |
if (rw)
|
1352 |
env->spr[SPR_40x_ESR] = 0x00800000;
|
1353 |
else
|
1354 |
env->spr[SPR_40x_ESR] = 0x00000000;
|
1355 |
break;
|
1356 |
case POWERPC_MMU_32B:
|
1357 |
error_code = 0x40000000;
|
1358 |
break;
|
1359 |
#if defined(TARGET_PPC64)
|
1360 |
case POWERPC_MMU_64B:
|
1361 |
/* XXX: TODO */
|
1362 |
cpu_abort(env, "MMU model not implemented\n");
|
1363 |
return -1; |
1364 |
case POWERPC_MMU_64BRIDGE:
|
1365 |
/* XXX: TODO */
|
1366 |
cpu_abort(env, "MMU model not implemented\n");
|
1367 |
return -1; |
1368 |
#endif
|
1369 |
case POWERPC_MMU_601:
|
1370 |
/* XXX: TODO */
|
1371 |
cpu_abort(env, "MMU model not implemented\n");
|
1372 |
return -1; |
1373 |
case POWERPC_MMU_BOOKE:
|
1374 |
/* XXX: TODO */
|
1375 |
cpu_abort(env, "MMU model not implemented\n");
|
1376 |
return -1; |
1377 |
case POWERPC_MMU_BOOKE_FSL:
|
1378 |
/* XXX: TODO */
|
1379 |
cpu_abort(env, "MMU model not implemented\n");
|
1380 |
return -1; |
1381 |
case POWERPC_MMU_REAL_4xx:
|
1382 |
cpu_abort(env, "PowerPC 401 should never raise any MMU "
|
1383 |
"exceptions\n");
|
1384 |
return -1; |
1385 |
default:
|
1386 |
cpu_abort(env, "Unknown or invalid MMU model\n");
|
1387 |
return -1; |
1388 |
} |
1389 |
break;
|
1390 |
case -2: |
1391 |
/* Access rights violation */
|
1392 |
error_code = 0x08000000;
|
1393 |
break;
|
1394 |
case -4: |
1395 |
/* Direct store exception */
|
1396 |
switch (access_type) {
|
1397 |
case ACCESS_FLOAT:
|
1398 |
/* Floating point load/store */
|
1399 |
exception = EXCP_ALIGN; |
1400 |
error_code = EXCP_ALIGN_FP; |
1401 |
break;
|
1402 |
case ACCESS_RES:
|
1403 |
/* lwarx, ldarx or srwcx. */
|
1404 |
error_code = 0x04000000;
|
1405 |
break;
|
1406 |
case ACCESS_EXT:
|
1407 |
/* eciwx or ecowx */
|
1408 |
error_code = 0x04100000;
|
1409 |
break;
|
1410 |
default:
|
1411 |
printf("DSI: invalid exception (%d)\n", ret);
|
1412 |
exception = EXCP_PROGRAM; |
1413 |
error_code = EXCP_INVAL | EXCP_INVAL_INVAL; |
1414 |
break;
|
1415 |
} |
1416 |
break;
|
1417 |
case -5: |
1418 |
/* No match in segment table */
|
1419 |
exception = EXCP_DSEG; |
1420 |
error_code = 0;
|
1421 |
break;
|
1422 |
} |
1423 |
if (exception == EXCP_DSI && rw == 1) |
1424 |
error_code |= 0x02000000;
|
1425 |
/* Store fault address */
|
1426 |
env->spr[SPR_DAR] = address; |
1427 |
env->spr[SPR_DSISR] = error_code; |
1428 |
} |
1429 |
out:
|
1430 |
#if 0
|
1431 |
printf("%s: set exception to %d %02x\n",
|
1432 |
__func__, exception, error_code);
|
1433 |
#endif
|
1434 |
env->exception_index = exception; |
1435 |
env->error_code = error_code; |
1436 |
ret = 1;
|
1437 |
} |
1438 |
|
1439 |
return ret;
|
1440 |
} |
1441 |
|
1442 |
/*****************************************************************************/
|
1443 |
/* BATs management */
|
1444 |
#if !defined(FLUSH_ALL_TLBS)
|
1445 |
static inline void do_invalidate_BAT (CPUPPCState *env, |
1446 |
target_ulong BATu, target_ulong mask) |
1447 |
{ |
1448 |
target_ulong base, end, page; |
1449 |
|
1450 |
base = BATu & ~0x0001FFFF;
|
1451 |
end = base + mask + 0x00020000;
|
1452 |
#if defined (DEBUG_BATS)
|
1453 |
if (loglevel != 0) { |
1454 |
fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n", |
1455 |
base, end, mask); |
1456 |
} |
1457 |
#endif
|
1458 |
for (page = base; page != end; page += TARGET_PAGE_SIZE)
|
1459 |
tlb_flush_page(env, page); |
1460 |
#if defined (DEBUG_BATS)
|
1461 |
if (loglevel != 0) |
1462 |
fprintf(logfile, "Flush done\n");
|
1463 |
#endif
|
1464 |
} |
1465 |
#endif
|
1466 |
|
1467 |
static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr, |
1468 |
target_ulong value) |
1469 |
{ |
1470 |
#if defined (DEBUG_BATS)
|
1471 |
if (loglevel != 0) { |
1472 |
fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n", |
1473 |
ID, nr, ul == 0 ? 'u' : 'l', value, env->nip); |
1474 |
} |
1475 |
#endif
|
1476 |
} |
1477 |
|
1478 |
target_ulong do_load_ibatu (CPUPPCState *env, int nr)
|
1479 |
{ |
1480 |
return env->IBAT[0][nr]; |
1481 |
} |
1482 |
|
1483 |
target_ulong do_load_ibatl (CPUPPCState *env, int nr)
|
1484 |
{ |
1485 |
return env->IBAT[1][nr]; |
1486 |
} |
1487 |
|
1488 |
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
1489 |
{ |
1490 |
target_ulong mask; |
1491 |
|
1492 |
dump_store_bat(env, 'I', 0, nr, value); |
1493 |
if (env->IBAT[0][nr] != value) { |
1494 |
mask = (value << 15) & 0x0FFE0000UL; |
1495 |
#if !defined(FLUSH_ALL_TLBS)
|
1496 |
do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1497 |
#endif
|
1498 |
/* When storing valid upper BAT, mask BEPI and BRPN
|
1499 |
* and invalidate all TLBs covered by this BAT
|
1500 |
*/
|
1501 |
mask = (value << 15) & 0x0FFE0000UL; |
1502 |
env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
1503 |
(value & ~0x0001FFFFUL & ~mask);
|
1504 |
env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) | |
1505 |
(env->IBAT[1][nr] & ~0x0001FFFF & ~mask); |
1506 |
#if !defined(FLUSH_ALL_TLBS)
|
1507 |
do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1508 |
#else
|
1509 |
tlb_flush(env, 1);
|
1510 |
#endif
|
1511 |
} |
1512 |
} |
1513 |
|
1514 |
void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value) |
1515 |
{ |
1516 |
dump_store_bat(env, 'I', 1, nr, value); |
1517 |
env->IBAT[1][nr] = value;
|
1518 |
} |
1519 |
|
1520 |
target_ulong do_load_dbatu (CPUPPCState *env, int nr)
|
1521 |
{ |
1522 |
return env->DBAT[0][nr]; |
1523 |
} |
1524 |
|
1525 |
target_ulong do_load_dbatl (CPUPPCState *env, int nr)
|
1526 |
{ |
1527 |
return env->DBAT[1][nr]; |
1528 |
} |
1529 |
|
1530 |
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value) |
1531 |
{ |
1532 |
target_ulong mask; |
1533 |
|
1534 |
dump_store_bat(env, 'D', 0, nr, value); |
1535 |
if (env->DBAT[0][nr] != value) { |
1536 |
/* When storing valid upper BAT, mask BEPI and BRPN
|
1537 |
* and invalidate all TLBs covered by this BAT
|
1538 |
*/
|
1539 |
mask = (value << 15) & 0x0FFE0000UL; |
1540 |
#if !defined(FLUSH_ALL_TLBS)
|
1541 |
do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1542 |
#endif
|
1543 |
mask = (value << 15) & 0x0FFE0000UL; |
1544 |
env->DBAT[0][nr] = (value & 0x00001FFFUL) | |
1545 |
(value & ~0x0001FFFFUL & ~mask);
|
1546 |
env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) | |
1547 |
(env->DBAT[1][nr] & ~0x0001FFFF & ~mask); |
1548 |
#if !defined(FLUSH_ALL_TLBS)
|
1549 |
do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1550 |
#else
|
1551 |
tlb_flush(env, 1);
|
1552 |
#endif
|
1553 |
} |
1554 |
} |
1555 |
|
1556 |
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value) |
1557 |
{ |
1558 |
dump_store_bat(env, 'D', 1, nr, value); |
1559 |
env->DBAT[1][nr] = value;
|
1560 |
} |
1561 |
|
1562 |
|
1563 |
/*****************************************************************************/
|
1564 |
/* TLB management */
|
1565 |
void ppc_tlb_invalidate_all (CPUPPCState *env)
|
1566 |
{ |
1567 |
if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
|
1568 |
ppc6xx_tlb_invalidate_all(env); |
1569 |
} else if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_4xx)) { |
1570 |
ppc4xx_tlb_invalidate_all(env); |
1571 |
} else {
|
1572 |
tlb_flush(env, 1);
|
1573 |
} |
1574 |
} |
1575 |
|
1576 |
/*****************************************************************************/
|
1577 |
/* Special registers manipulation */
|
1578 |
#if defined(TARGET_PPC64)
|
1579 |
target_ulong ppc_load_asr (CPUPPCState *env) |
1580 |
{ |
1581 |
return env->asr;
|
1582 |
} |
1583 |
|
1584 |
void ppc_store_asr (CPUPPCState *env, target_ulong value)
|
1585 |
{ |
1586 |
if (env->asr != value) {
|
1587 |
env->asr = value; |
1588 |
tlb_flush(env, 1);
|
1589 |
} |
1590 |
} |
1591 |
#endif
|
1592 |
|
1593 |
target_ulong do_load_sdr1 (CPUPPCState *env) |
1594 |
{ |
1595 |
return env->sdr1;
|
1596 |
} |
1597 |
|
1598 |
void do_store_sdr1 (CPUPPCState *env, target_ulong value)
|
1599 |
{ |
1600 |
#if defined (DEBUG_MMU)
|
1601 |
if (loglevel != 0) { |
1602 |
fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value); |
1603 |
} |
1604 |
#endif
|
1605 |
if (env->sdr1 != value) {
|
1606 |
env->sdr1 = value; |
1607 |
tlb_flush(env, 1);
|
1608 |
} |
1609 |
} |
1610 |
|
1611 |
target_ulong do_load_sr (CPUPPCState *env, int srnum)
|
1612 |
{ |
1613 |
return env->sr[srnum];
|
1614 |
} |
1615 |
|
1616 |
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value) |
1617 |
{ |
1618 |
#if defined (DEBUG_MMU)
|
1619 |
if (loglevel != 0) { |
1620 |
fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n", |
1621 |
__func__, srnum, value, env->sr[srnum]); |
1622 |
} |
1623 |
#endif
|
1624 |
if (env->sr[srnum] != value) {
|
1625 |
env->sr[srnum] = value; |
1626 |
#if !defined(FLUSH_ALL_TLBS) && 0 |
1627 |
{ |
1628 |
target_ulong page, end; |
1629 |
/* Invalidate 256 MB of virtual memory */
|
1630 |
page = (16 << 20) * srnum; |
1631 |
end = page + (16 << 20); |
1632 |
for (; page != end; page += TARGET_PAGE_SIZE)
|
1633 |
tlb_flush_page(env, page); |
1634 |
} |
1635 |
#else
|
1636 |
tlb_flush(env, 1);
|
1637 |
#endif
|
1638 |
} |
1639 |
} |
1640 |
#endif /* !defined (CONFIG_USER_ONLY) */ |
1641 |
|
1642 |
uint32_t ppc_load_xer (CPUPPCState *env) |
1643 |
{ |
1644 |
return (xer_so << XER_SO) |
|
1645 |
(xer_ov << XER_OV) | |
1646 |
(xer_ca << XER_CA) | |
1647 |
(xer_bc << XER_BC) | |
1648 |
(xer_cmp << XER_CMP); |
1649 |
} |
1650 |
|
1651 |
void ppc_store_xer (CPUPPCState *env, uint32_t value)
|
1652 |
{ |
1653 |
xer_so = (value >> XER_SO) & 0x01;
|
1654 |
xer_ov = (value >> XER_OV) & 0x01;
|
1655 |
xer_ca = (value >> XER_CA) & 0x01;
|
1656 |
xer_cmp = (value >> XER_CMP) & 0xFF;
|
1657 |
xer_bc = (value >> XER_BC) & 0x7F;
|
1658 |
} |
1659 |
|
1660 |
/* Swap temporary saved registers with GPRs */
|
1661 |
static inline void swap_gpr_tgpr (CPUPPCState *env) |
1662 |
{ |
1663 |
ppc_gpr_t tmp; |
1664 |
|
1665 |
tmp = env->gpr[0];
|
1666 |
env->gpr[0] = env->tgpr[0]; |
1667 |
env->tgpr[0] = tmp;
|
1668 |
tmp = env->gpr[1];
|
1669 |
env->gpr[1] = env->tgpr[1]; |
1670 |
env->tgpr[1] = tmp;
|
1671 |
tmp = env->gpr[2];
|
1672 |
env->gpr[2] = env->tgpr[2]; |
1673 |
env->tgpr[2] = tmp;
|
1674 |
tmp = env->gpr[3];
|
1675 |
env->gpr[3] = env->tgpr[3]; |
1676 |
env->tgpr[3] = tmp;
|
1677 |
} |
1678 |
|
1679 |
/* GDBstub can read and write MSR... */
|
1680 |
target_ulong do_load_msr (CPUPPCState *env) |
1681 |
{ |
1682 |
return
|
1683 |
#if defined (TARGET_PPC64)
|
1684 |
((target_ulong)msr_sf << MSR_SF) | |
1685 |
((target_ulong)msr_isf << MSR_ISF) | |
1686 |
((target_ulong)msr_hv << MSR_HV) | |
1687 |
#endif
|
1688 |
((target_ulong)msr_ucle << MSR_UCLE) | |
1689 |
((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
|
1690 |
((target_ulong)msr_ap << MSR_AP) | |
1691 |
((target_ulong)msr_sa << MSR_SA) | |
1692 |
((target_ulong)msr_key << MSR_KEY) | |
1693 |
((target_ulong)msr_pow << MSR_POW) | /* POW / WE */
|
1694 |
((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
|
1695 |
((target_ulong)msr_ile << MSR_ILE) | |
1696 |
((target_ulong)msr_ee << MSR_EE) | |
1697 |
((target_ulong)msr_pr << MSR_PR) | |
1698 |
((target_ulong)msr_fp << MSR_FP) | |
1699 |
((target_ulong)msr_me << MSR_ME) | |
1700 |
((target_ulong)msr_fe0 << MSR_FE0) | |
1701 |
((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
|
1702 |
((target_ulong)msr_be << MSR_BE) | /* BE / DE */
|
1703 |
((target_ulong)msr_fe1 << MSR_FE1) | |
1704 |
((target_ulong)msr_al << MSR_AL) | |
1705 |
((target_ulong)msr_ip << MSR_IP) | |
1706 |
((target_ulong)msr_ir << MSR_IR) | /* IR / IS */
|
1707 |
((target_ulong)msr_dr << MSR_DR) | /* DR / DS */
|
1708 |
((target_ulong)msr_pe << MSR_PE) | /* PE / EP */
|
1709 |
((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
|
1710 |
((target_ulong)msr_ri << MSR_RI) | |
1711 |
((target_ulong)msr_le << MSR_LE); |
1712 |
} |
1713 |
|
1714 |
void do_store_msr (CPUPPCState *env, target_ulong value)
|
1715 |
{ |
1716 |
int enter_pm;
|
1717 |
|
1718 |
value &= env->msr_mask; |
1719 |
if (((value >> MSR_IR) & 1) != msr_ir || |
1720 |
((value >> MSR_DR) & 1) != msr_dr) {
|
1721 |
/* Flush all tlb when changing translation mode */
|
1722 |
tlb_flush(env, 1);
|
1723 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1724 |
} |
1725 |
#if 0
|
1726 |
if (loglevel != 0) {
|
1727 |
fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
|
1728 |
}
|
1729 |
#endif
|
1730 |
switch (env->excp_model) {
|
1731 |
case POWERPC_EXCP_602:
|
1732 |
case POWERPC_EXCP_603:
|
1733 |
case POWERPC_EXCP_603E:
|
1734 |
case POWERPC_EXCP_G2:
|
1735 |
if (((value >> MSR_TGPR) & 1) != msr_tgpr) { |
1736 |
/* Swap temporary saved registers with GPRs */
|
1737 |
swap_gpr_tgpr(env); |
1738 |
} |
1739 |
break;
|
1740 |
default:
|
1741 |
break;
|
1742 |
} |
1743 |
#if defined (TARGET_PPC64)
|
1744 |
msr_sf = (value >> MSR_SF) & 1;
|
1745 |
msr_isf = (value >> MSR_ISF) & 1;
|
1746 |
msr_hv = (value >> MSR_HV) & 1;
|
1747 |
#endif
|
1748 |
msr_ucle = (value >> MSR_UCLE) & 1;
|
1749 |
msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */ |
1750 |
msr_ap = (value >> MSR_AP) & 1;
|
1751 |
msr_sa = (value >> MSR_SA) & 1;
|
1752 |
msr_key = (value >> MSR_KEY) & 1;
|
1753 |
msr_pow = (value >> MSR_POW) & 1; /* POW / WE */ |
1754 |
msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */ |
1755 |
msr_ile = (value >> MSR_ILE) & 1;
|
1756 |
msr_ee = (value >> MSR_EE) & 1;
|
1757 |
msr_pr = (value >> MSR_PR) & 1;
|
1758 |
msr_fp = (value >> MSR_FP) & 1;
|
1759 |
msr_me = (value >> MSR_ME) & 1;
|
1760 |
msr_fe0 = (value >> MSR_FE0) & 1;
|
1761 |
msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */ |
1762 |
msr_be = (value >> MSR_BE) & 1; /* BE / DE */ |
1763 |
msr_fe1 = (value >> MSR_FE1) & 1;
|
1764 |
msr_al = (value >> MSR_AL) & 1;
|
1765 |
msr_ip = (value >> MSR_IP) & 1;
|
1766 |
msr_ir = (value >> MSR_IR) & 1; /* IR / IS */ |
1767 |
msr_dr = (value >> MSR_DR) & 1; /* DR / DS */ |
1768 |
msr_pe = (value >> MSR_PE) & 1; /* PE / EP */ |
1769 |
msr_px = (value >> MSR_PX) & 1; /* PX / PMM */ |
1770 |
msr_ri = (value >> MSR_RI) & 1;
|
1771 |
msr_le = (value >> MSR_LE) & 1;
|
1772 |
do_compute_hflags(env); |
1773 |
|
1774 |
enter_pm = 0;
|
1775 |
switch (env->excp_model) {
|
1776 |
case POWERPC_EXCP_603:
|
1777 |
case POWERPC_EXCP_603E:
|
1778 |
case POWERPC_EXCP_G2:
|
1779 |
/* Don't handle SLEEP mode: we should disable all clocks...
|
1780 |
* No dynamic power-management.
|
1781 |
*/
|
1782 |
if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0) |
1783 |
enter_pm = 1;
|
1784 |
break;
|
1785 |
case POWERPC_EXCP_604:
|
1786 |
if (msr_pow == 1) |
1787 |
enter_pm = 1;
|
1788 |
break;
|
1789 |
case POWERPC_EXCP_7x0:
|
1790 |
if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0) |
1791 |
enter_pm = 1;
|
1792 |
break;
|
1793 |
default:
|
1794 |
break;
|
1795 |
} |
1796 |
if (enter_pm) {
|
1797 |
if (likely(!env->halted)) {
|
1798 |
/* power save: exit cpu loop */
|
1799 |
env->halted = 1;
|
1800 |
env->exception_index = EXCP_HLT; |
1801 |
cpu_loop_exit(); |
1802 |
} |
1803 |
} |
1804 |
} |
1805 |
|
1806 |
#if defined(TARGET_PPC64)
|
1807 |
void ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
|
1808 |
{ |
1809 |
do_store_msr(env, |
1810 |
(do_load_msr(env) & ~0xFFFFFFFFULL) | (value & 0xFFFFFFFF)); |
1811 |
} |
1812 |
#endif
|
1813 |
|
1814 |
void do_compute_hflags (CPUPPCState *env)
|
1815 |
{ |
1816 |
/* Compute current hflags */
|
1817 |
env->hflags = (msr_vr << MSR_VR) | |
1818 |
(msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) | |
1819 |
(msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) | |
1820 |
(msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE); |
1821 |
#if defined (TARGET_PPC64)
|
1822 |
env->hflags |= msr_cm << MSR_CM; |
1823 |
env->hflags |= (uint64_t)msr_sf << MSR_SF; |
1824 |
env->hflags |= (uint64_t)msr_hv << MSR_HV; |
1825 |
#endif
|
1826 |
} |
1827 |
|
1828 |
/*****************************************************************************/
|
1829 |
/* Exception processing */
|
1830 |
#if defined (CONFIG_USER_ONLY)
|
1831 |
void do_interrupt (CPUState *env)
|
1832 |
{ |
1833 |
env->exception_index = -1;
|
1834 |
} |
1835 |
|
1836 |
void ppc_hw_interrupt (CPUState *env)
|
1837 |
{ |
1838 |
env->exception_index = -1;
|
1839 |
} |
1840 |
#else /* defined (CONFIG_USER_ONLY) */ |
1841 |
static void dump_syscall (CPUState *env) |
1842 |
{ |
1843 |
fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX |
1844 |
" r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n", |
1845 |
env->gpr[0], env->gpr[3], env->gpr[4], |
1846 |
env->gpr[5], env->gpr[6], env->nip); |
1847 |
} |
1848 |
|
1849 |
void do_interrupt (CPUState *env)
|
1850 |
{ |
1851 |
target_ulong msr, *srr_0, *srr_1, *asrr_0, *asrr_1; |
1852 |
int excp, idx;
|
1853 |
|
1854 |
excp = env->exception_index; |
1855 |
msr = do_load_msr(env); |
1856 |
/* The default is to use SRR0 & SRR1 to save the exception context */
|
1857 |
srr_0 = &env->spr[SPR_SRR0]; |
1858 |
srr_1 = &env->spr[SPR_SRR1]; |
1859 |
asrr_0 = NULL;
|
1860 |
asrr_1 = NULL;
|
1861 |
#if defined (DEBUG_EXCEPTIONS)
|
1862 |
if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) { |
1863 |
if (loglevel != 0) { |
1864 |
fprintf(logfile, |
1865 |
"Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n", |
1866 |
env->nip, excp, env->error_code); |
1867 |
cpu_dump_state(env, logfile, fprintf, 0);
|
1868 |
} |
1869 |
} |
1870 |
#endif
|
1871 |
if (loglevel & CPU_LOG_INT) {
|
1872 |
fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n", |
1873 |
env->nip, excp, env->error_code); |
1874 |
} |
1875 |
msr_pow = 0;
|
1876 |
idx = -1;
|
1877 |
/* Generate informations in save/restore registers */
|
1878 |
switch (excp) {
|
1879 |
/* Generic PowerPC exceptions */
|
1880 |
case EXCP_RESET: /* 0x0100 */ |
1881 |
switch (env->excp_model) {
|
1882 |
case POWERPC_EXCP_40x:
|
1883 |
srr_0 = &env->spr[SPR_40x_SRR2]; |
1884 |
srr_1 = &env->spr[SPR_40x_SRR3]; |
1885 |
break;
|
1886 |
case POWERPC_EXCP_BOOKE:
|
1887 |
idx = 0;
|
1888 |
srr_0 = &env->spr[SPR_BOOKE_CSRR0]; |
1889 |
srr_1 = &env->spr[SPR_BOOKE_CSRR1]; |
1890 |
break;
|
1891 |
default:
|
1892 |
if (msr_ip)
|
1893 |
excp += 0xFFC00;
|
1894 |
excp |= 0xFFC00000;
|
1895 |
break;
|
1896 |
} |
1897 |
goto store_next;
|
1898 |
case EXCP_MACHINE_CHECK: /* 0x0200 */ |
1899 |
switch (env->excp_model) {
|
1900 |
case POWERPC_EXCP_40x:
|
1901 |
srr_0 = &env->spr[SPR_40x_SRR2]; |
1902 |
srr_1 = &env->spr[SPR_40x_SRR3]; |
1903 |
break;
|
1904 |
case POWERPC_EXCP_BOOKE:
|
1905 |
idx = 1;
|
1906 |
srr_0 = &env->spr[SPR_BOOKE_MCSRR0]; |
1907 |
srr_1 = &env->spr[SPR_BOOKE_MCSRR1]; |
1908 |
asrr_0 = &env->spr[SPR_BOOKE_CSRR0]; |
1909 |
asrr_1 = &env->spr[SPR_BOOKE_CSRR1]; |
1910 |
msr_ce = 0;
|
1911 |
break;
|
1912 |
default:
|
1913 |
break;
|
1914 |
} |
1915 |
msr_me = 0;
|
1916 |
break;
|
1917 |
case EXCP_DSI: /* 0x0300 */ |
1918 |
/* Store exception cause */
|
1919 |
/* data location address has been stored
|
1920 |
* when the fault has been detected
|
1921 |
*/
|
1922 |
idx = 2;
|
1923 |
msr &= ~0xFFFF0000;
|
1924 |
#if defined (DEBUG_EXCEPTIONS)
|
1925 |
if (loglevel != 0) { |
1926 |
fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX |
1927 |
"\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
|
1928 |
} |
1929 |
#endif
|
1930 |
goto store_next;
|
1931 |
case EXCP_ISI: /* 0x0400 */ |
1932 |
/* Store exception cause */
|
1933 |
idx = 3;
|
1934 |
msr &= ~0xFFFF0000;
|
1935 |
msr |= env->error_code; |
1936 |
#if defined (DEBUG_EXCEPTIONS)
|
1937 |
if (loglevel != 0) { |
1938 |
fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX |
1939 |
"\n", msr, env->nip);
|
1940 |
} |
1941 |
#endif
|
1942 |
goto store_next;
|
1943 |
case EXCP_EXTERNAL: /* 0x0500 */ |
1944 |
idx = 4;
|
1945 |
goto store_next;
|
1946 |
case EXCP_ALIGN: /* 0x0600 */ |
1947 |
if (likely(env->excp_model != POWERPC_EXCP_601)) {
|
1948 |
/* Store exception cause */
|
1949 |
idx = 5;
|
1950 |
/* Get rS/rD and rA from faulting opcode */
|
1951 |
env->spr[SPR_DSISR] |= |
1952 |
(ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
1953 |
/* data location address has been stored
|
1954 |
* when the fault has been detected
|
1955 |
*/
|
1956 |
} else {
|
1957 |
/* IO error exception on PowerPC 601 */
|
1958 |
/* XXX: TODO */
|
1959 |
cpu_abort(env, |
1960 |
"601 IO error exception is not implemented yet !\n");
|
1961 |
} |
1962 |
goto store_current;
|
1963 |
case EXCP_PROGRAM: /* 0x0700 */ |
1964 |
idx = 6;
|
1965 |
msr &= ~0xFFFF0000;
|
1966 |
switch (env->error_code & ~0xF) { |
1967 |
case EXCP_FP:
|
1968 |
if (msr_fe0 == 0 && msr_fe1 == 0) { |
1969 |
#if defined (DEBUG_EXCEPTIONS)
|
1970 |
if (loglevel != 0) { |
1971 |
fprintf(logfile, "Ignore floating point exception\n");
|
1972 |
} |
1973 |
#endif
|
1974 |
return;
|
1975 |
} |
1976 |
msr |= 0x00100000;
|
1977 |
/* Set FX */
|
1978 |
env->fpscr[7] |= 0x8; |
1979 |
/* Finally, update FEX */
|
1980 |
if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) & |
1981 |
((env->fpscr[1] << 1) | (env->fpscr[0] >> 3))) |
1982 |
env->fpscr[7] |= 0x4; |
1983 |
break;
|
1984 |
case EXCP_INVAL:
|
1985 |
#if defined (DEBUG_EXCEPTIONS)
|
1986 |
if (loglevel != 0) { |
1987 |
fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n", |
1988 |
env->nip); |
1989 |
} |
1990 |
#endif
|
1991 |
msr |= 0x00080000;
|
1992 |
break;
|
1993 |
case EXCP_PRIV:
|
1994 |
msr |= 0x00040000;
|
1995 |
break;
|
1996 |
case EXCP_TRAP:
|
1997 |
idx = 15;
|
1998 |
msr |= 0x00020000;
|
1999 |
break;
|
2000 |
default:
|
2001 |
/* Should never occur */
|
2002 |
break;
|
2003 |
} |
2004 |
msr |= 0x00010000;
|
2005 |
goto store_current;
|
2006 |
case EXCP_NO_FP: /* 0x0800 */ |
2007 |
idx = 7;
|
2008 |
msr &= ~0xFFFF0000;
|
2009 |
goto store_current;
|
2010 |
case EXCP_DECR:
|
2011 |
goto store_next;
|
2012 |
case EXCP_SYSCALL: /* 0x0C00 */ |
2013 |
idx = 8;
|
2014 |
/* NOTE: this is a temporary hack to support graphics OSI
|
2015 |
calls from the MOL driver */
|
2016 |
if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && |
2017 |
env->osi_call) { |
2018 |
if (env->osi_call(env) != 0) |
2019 |
return;
|
2020 |
} |
2021 |
if (loglevel & CPU_LOG_INT) {
|
2022 |
dump_syscall(env); |
2023 |
} |
2024 |
goto store_next;
|
2025 |
case EXCP_TRACE: /* 0x0D00 */ |
2026 |
goto store_next;
|
2027 |
case EXCP_PERF: /* 0x0F00 */ |
2028 |
/* XXX: TODO */
|
2029 |
cpu_abort(env, |
2030 |
"Performance counter exception is not implemented yet !\n");
|
2031 |
goto store_next;
|
2032 |
/* 32 bits PowerPC specific exceptions */
|
2033 |
case EXCP_FP_ASSIST: /* 0x0E00 */ |
2034 |
/* XXX: TODO */
|
2035 |
cpu_abort(env, "Floating point assist exception "
|
2036 |
"is not implemented yet !\n");
|
2037 |
goto store_next;
|
2038 |
/* 64 bits PowerPC exceptions */
|
2039 |
case EXCP_DSEG: /* 0x0380 */ |
2040 |
/* XXX: TODO */
|
2041 |
cpu_abort(env, "Data segment exception is not implemented yet !\n");
|
2042 |
goto store_next;
|
2043 |
case EXCP_ISEG: /* 0x0480 */ |
2044 |
/* XXX: TODO */
|
2045 |
cpu_abort(env, |
2046 |
"Instruction segment exception is not implemented yet !\n");
|
2047 |
goto store_next;
|
2048 |
case EXCP_HDECR: /* 0x0980 */ |
2049 |
/* XXX: TODO */
|
2050 |
cpu_abort(env, "Hypervisor decrementer exception is not implemented "
|
2051 |
"yet !\n");
|
2052 |
goto store_next;
|
2053 |
/* Implementation specific exceptions */
|
2054 |
case 0x0A00: |
2055 |
switch (env->excp_model) {
|
2056 |
case POWERPC_EXCP_G2:
|
2057 |
/* Critical interrupt on G2 */
|
2058 |
/* XXX: TODO */
|
2059 |
cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
|
2060 |
goto store_next;
|
2061 |
default:
|
2062 |
cpu_abort(env, "Invalid exception 0x0A00 !\n");
|
2063 |
break;
|
2064 |
} |
2065 |
return;
|
2066 |
case 0x0F20: |
2067 |
idx = 9;
|
2068 |
switch (env->excp_model) {
|
2069 |
case POWERPC_EXCP_40x:
|
2070 |
/* APU unavailable on 405 */
|
2071 |
/* XXX: TODO */
|
2072 |
cpu_abort(env, |
2073 |
"APU unavailable exception is not implemented yet !\n");
|
2074 |
goto store_next;
|
2075 |
case POWERPC_EXCP_74xx:
|
2076 |
/* Altivec unavailable */
|
2077 |
/* XXX: TODO */
|
2078 |
cpu_abort(env, "Altivec unavailable exception "
|
2079 |
"is not implemented yet !\n");
|
2080 |
goto store_next;
|
2081 |
default:
|
2082 |
cpu_abort(env, "Invalid exception 0x0F20 !\n");
|
2083 |
break;
|
2084 |
} |
2085 |
return;
|
2086 |
case 0x1000: |
2087 |
idx = 10;
|
2088 |
switch (env->excp_model) {
|
2089 |
case POWERPC_EXCP_40x:
|
2090 |
/* PIT on 4xx */
|
2091 |
msr &= ~0xFFFF0000;
|
2092 |
#if defined (DEBUG_EXCEPTIONS)
|
2093 |
if (loglevel != 0) |
2094 |
fprintf(logfile, "PIT exception\n");
|
2095 |
#endif
|
2096 |
goto store_next;
|
2097 |
case POWERPC_EXCP_602:
|
2098 |
case POWERPC_EXCP_603:
|
2099 |
case POWERPC_EXCP_603E:
|
2100 |
case POWERPC_EXCP_G2:
|
2101 |
/* ITLBMISS on 602/603 */
|
2102 |
goto store_gprs;
|
2103 |
case POWERPC_EXCP_7x5:
|
2104 |
/* ITLBMISS on 745/755 */
|
2105 |
goto tlb_miss;
|
2106 |
default:
|
2107 |
cpu_abort(env, "Invalid exception 0x1000 !\n");
|
2108 |
break;
|
2109 |
} |
2110 |
return;
|
2111 |
case 0x1010: |
2112 |
idx = 11;
|
2113 |
switch (env->excp_model) {
|
2114 |
case POWERPC_EXCP_40x:
|
2115 |
/* FIT on 4xx */
|
2116 |
msr &= ~0xFFFF0000;
|
2117 |
#if defined (DEBUG_EXCEPTIONS)
|
2118 |
if (loglevel != 0) |
2119 |
fprintf(logfile, "FIT exception\n");
|
2120 |
#endif
|
2121 |
goto store_next;
|
2122 |
default:
|
2123 |
cpu_abort(env, "Invalid exception 0x1010 !\n");
|
2124 |
break;
|
2125 |
} |
2126 |
return;
|
2127 |
case 0x1020: |
2128 |
idx = 12;
|
2129 |
switch (env->excp_model) {
|
2130 |
case POWERPC_EXCP_40x:
|
2131 |
/* Watchdog on 4xx */
|
2132 |
msr &= ~0xFFFF0000;
|
2133 |
#if defined (DEBUG_EXCEPTIONS)
|
2134 |
if (loglevel != 0) |
2135 |
fprintf(logfile, "WDT exception\n");
|
2136 |
#endif
|
2137 |
goto store_next;
|
2138 |
case POWERPC_EXCP_BOOKE:
|
2139 |
srr_0 = &env->spr[SPR_BOOKE_CSRR0]; |
2140 |
srr_1 = &env->spr[SPR_BOOKE_CSRR1]; |
2141 |
break;
|
2142 |
default:
|
2143 |
cpu_abort(env, "Invalid exception 0x1020 !\n");
|
2144 |
break;
|
2145 |
} |
2146 |
return;
|
2147 |
case 0x1100: |
2148 |
idx = 13;
|
2149 |
switch (env->excp_model) {
|
2150 |
case POWERPC_EXCP_40x:
|
2151 |
/* DTLBMISS on 4xx */
|
2152 |
msr &= ~0xFFFF0000;
|
2153 |
goto store_next;
|
2154 |
case POWERPC_EXCP_602:
|
2155 |
case POWERPC_EXCP_603:
|
2156 |
case POWERPC_EXCP_603E:
|
2157 |
case POWERPC_EXCP_G2:
|
2158 |
/* DLTLBMISS on 602/603 */
|
2159 |
goto store_gprs;
|
2160 |
case POWERPC_EXCP_7x5:
|
2161 |
/* DLTLBMISS on 745/755 */
|
2162 |
goto tlb_miss;
|
2163 |
default:
|
2164 |
cpu_abort(env, "Invalid exception 0x1100 !\n");
|
2165 |
break;
|
2166 |
} |
2167 |
return;
|
2168 |
case 0x1200: |
2169 |
idx = 14;
|
2170 |
switch (env->excp_model) {
|
2171 |
case POWERPC_EXCP_40x:
|
2172 |
/* ITLBMISS on 4xx */
|
2173 |
msr &= ~0xFFFF0000;
|
2174 |
goto store_next;
|
2175 |
case POWERPC_EXCP_602:
|
2176 |
case POWERPC_EXCP_603:
|
2177 |
case POWERPC_EXCP_603E:
|
2178 |
case POWERPC_EXCP_G2:
|
2179 |
/* DSTLBMISS on 602/603 */
|
2180 |
store_gprs:
|
2181 |
/* Swap temporary saved registers with GPRs */
|
2182 |
swap_gpr_tgpr(env); |
2183 |
msr_tgpr = 1;
|
2184 |
#if defined (DEBUG_SOFTWARE_TLB)
|
2185 |
if (loglevel != 0) { |
2186 |
const unsigned char *es; |
2187 |
target_ulong *miss, *cmp; |
2188 |
int en;
|
2189 |
if (excp == 0x1000) { |
2190 |
es = "I";
|
2191 |
en = 'I';
|
2192 |
miss = &env->spr[SPR_IMISS]; |
2193 |
cmp = &env->spr[SPR_ICMP]; |
2194 |
} else {
|
2195 |
if (excp == 0x1100) |
2196 |
es = "DL";
|
2197 |
else
|
2198 |
es = "DS";
|
2199 |
en = 'D';
|
2200 |
miss = &env->spr[SPR_DMISS]; |
2201 |
cmp = &env->spr[SPR_DCMP]; |
2202 |
} |
2203 |
fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
2204 |
" H1 " ADDRX " H2 " ADDRX " %08x\n", |
2205 |
es, en, *miss, en, *cmp, |
2206 |
env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
2207 |
env->error_code); |
2208 |
} |
2209 |
#endif
|
2210 |
goto tlb_miss;
|
2211 |
case POWERPC_EXCP_7x5:
|
2212 |
/* DSTLBMISS on 745/755 */
|
2213 |
tlb_miss:
|
2214 |
msr &= ~0xF83F0000;
|
2215 |
msr |= env->crf[0] << 28; |
2216 |
msr |= env->error_code; /* key, D/I, S/L bits */
|
2217 |
/* Set way using a LRU mechanism */
|
2218 |
msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; |
2219 |
goto store_next;
|
2220 |
default:
|
2221 |
cpu_abort(env, "Invalid exception 0x1200 !\n");
|
2222 |
break;
|
2223 |
} |
2224 |
return;
|
2225 |
case 0x1300: |
2226 |
switch (env->excp_model) {
|
2227 |
case POWERPC_EXCP_601:
|
2228 |
case POWERPC_EXCP_602:
|
2229 |
case POWERPC_EXCP_603:
|
2230 |
case POWERPC_EXCP_603E:
|
2231 |
case POWERPC_EXCP_G2:
|
2232 |
case POWERPC_EXCP_604:
|
2233 |
case POWERPC_EXCP_7x0:
|
2234 |
case POWERPC_EXCP_7x5:
|
2235 |
/* IABR on 6xx/7xx */
|
2236 |
/* XXX: TODO */
|
2237 |
cpu_abort(env, "IABR exception is not implemented yet !\n");
|
2238 |
goto store_next;
|
2239 |
default:
|
2240 |
cpu_abort(env, "Invalid exception 0x1300 !\n");
|
2241 |
break;
|
2242 |
} |
2243 |
return;
|
2244 |
case 0x1400: |
2245 |
switch (env->excp_model) {
|
2246 |
case POWERPC_EXCP_601:
|
2247 |
case POWERPC_EXCP_602:
|
2248 |
case POWERPC_EXCP_603:
|
2249 |
case POWERPC_EXCP_603E:
|
2250 |
case POWERPC_EXCP_G2:
|
2251 |
case POWERPC_EXCP_604:
|
2252 |
case POWERPC_EXCP_7x0:
|
2253 |
case POWERPC_EXCP_7x5:
|
2254 |
/* SMI on 6xx/7xx */
|
2255 |
/* XXX: TODO */
|
2256 |
cpu_abort(env, "SMI exception is not implemented yet !\n");
|
2257 |
goto store_next;
|
2258 |
default:
|
2259 |
cpu_abort(env, "Invalid exception 0x1400 !\n");
|
2260 |
break;
|
2261 |
} |
2262 |
return;
|
2263 |
case 0x1500: |
2264 |
switch (env->excp_model) {
|
2265 |
case POWERPC_EXCP_602:
|
2266 |
/* Watchdog on 602 */
|
2267 |
/* XXX: TODO */
|
2268 |
cpu_abort(env, |
2269 |
"602 watchdog exception is not implemented yet !\n");
|
2270 |
goto store_next;
|
2271 |
case POWERPC_EXCP_970:
|
2272 |
/* Soft patch exception on 970 */
|
2273 |
/* XXX: TODO */
|
2274 |
cpu_abort(env, |
2275 |
"970 soft-patch exception is not implemented yet !\n");
|
2276 |
goto store_next;
|
2277 |
case POWERPC_EXCP_74xx:
|
2278 |
/* VPU assist on 74xx */
|
2279 |
/* XXX: TODO */
|
2280 |
cpu_abort(env, "VPU assist exception is not implemented yet !\n");
|
2281 |
goto store_next;
|
2282 |
default:
|
2283 |
cpu_abort(env, "Invalid exception 0x1500 !\n");
|
2284 |
break;
|
2285 |
} |
2286 |
return;
|
2287 |
case 0x1600: |
2288 |
switch (env->excp_model) {
|
2289 |
case POWERPC_EXCP_602:
|
2290 |
/* Emulation trap on 602 */
|
2291 |
/* XXX: TODO */
|
2292 |
cpu_abort(env, "602 emulation trap exception "
|
2293 |
"is not implemented yet !\n");
|
2294 |
goto store_next;
|
2295 |
case POWERPC_EXCP_970:
|
2296 |
/* Maintenance exception on 970 */
|
2297 |
/* XXX: TODO */
|
2298 |
cpu_abort(env, |
2299 |
"970 maintenance exception is not implemented yet !\n");
|
2300 |
goto store_next;
|
2301 |
default:
|
2302 |
cpu_abort(env, "Invalid exception 0x1600 !\n");
|
2303 |
break;
|
2304 |
} |
2305 |
return;
|
2306 |
case 0x1700: |
2307 |
switch (env->excp_model) {
|
2308 |
case POWERPC_EXCP_7x0:
|
2309 |
case POWERPC_EXCP_7x5:
|
2310 |
/* Thermal management interrupt on G3 */
|
2311 |
/* XXX: TODO */
|
2312 |
cpu_abort(env, "G3 thermal management exception "
|
2313 |
"is not implemented yet !\n");
|
2314 |
goto store_next;
|
2315 |
case POWERPC_EXCP_970:
|
2316 |
/* VPU assist on 970 */
|
2317 |
/* XXX: TODO */
|
2318 |
cpu_abort(env, |
2319 |
"970 VPU assist exception is not implemented yet !\n");
|
2320 |
goto store_next;
|
2321 |
default:
|
2322 |
cpu_abort(env, "Invalid exception 0x1700 !\n");
|
2323 |
break;
|
2324 |
} |
2325 |
return;
|
2326 |
case 0x1800: |
2327 |
switch (env->excp_model) {
|
2328 |
case POWERPC_EXCP_970:
|
2329 |
/* Thermal exception on 970 */
|
2330 |
/* XXX: TODO */
|
2331 |
cpu_abort(env, "970 thermal management exception "
|
2332 |
"is not implemented yet !\n");
|
2333 |
goto store_next;
|
2334 |
default:
|
2335 |
cpu_abort(env, "Invalid exception 0x1800 !\n");
|
2336 |
break;
|
2337 |
} |
2338 |
return;
|
2339 |
case 0x2000: |
2340 |
switch (env->excp_model) {
|
2341 |
case POWERPC_EXCP_40x:
|
2342 |
/* DEBUG on 4xx */
|
2343 |
/* XXX: TODO */
|
2344 |
cpu_abort(env, "40x debug exception is not implemented yet !\n");
|
2345 |
goto store_next;
|
2346 |
case POWERPC_EXCP_601:
|
2347 |
/* Run mode exception on 601 */
|
2348 |
/* XXX: TODO */
|
2349 |
cpu_abort(env, |
2350 |
"601 run mode exception is not implemented yet !\n");
|
2351 |
goto store_next;
|
2352 |
case POWERPC_EXCP_BOOKE:
|
2353 |
srr_0 = &env->spr[SPR_BOOKE_CSRR0]; |
2354 |
srr_1 = &env->spr[SPR_BOOKE_CSRR1]; |
2355 |
break;
|
2356 |
default:
|
2357 |
cpu_abort(env, "Invalid exception 0x1800 !\n");
|
2358 |
break;
|
2359 |
} |
2360 |
return;
|
2361 |
/* Other exceptions */
|
2362 |
/* Qemu internal exceptions:
|
2363 |
* we should never come here with those values: abort execution
|
2364 |
*/
|
2365 |
default:
|
2366 |
cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp);
|
2367 |
return;
|
2368 |
store_current:
|
2369 |
/* save current instruction location */
|
2370 |
*srr_0 = env->nip - 4;
|
2371 |
break;
|
2372 |
store_next:
|
2373 |
/* save next instruction location */
|
2374 |
*srr_0 = env->nip; |
2375 |
break;
|
2376 |
} |
2377 |
/* Save msr */
|
2378 |
*srr_1 = msr; |
2379 |
if (asrr_0 != NULL) |
2380 |
*asrr_0 = *srr_0; |
2381 |
if (asrr_1 != NULL) |
2382 |
*asrr_1 = *srr_1; |
2383 |
/* If we disactivated any translation, flush TLBs */
|
2384 |
if (msr_ir || msr_dr) {
|
2385 |
tlb_flush(env, 1);
|
2386 |
} |
2387 |
/* reload MSR with correct bits */
|
2388 |
msr_ee = 0;
|
2389 |
msr_pr = 0;
|
2390 |
msr_fp = 0;
|
2391 |
msr_fe0 = 0;
|
2392 |
msr_se = 0;
|
2393 |
msr_be = 0;
|
2394 |
msr_fe1 = 0;
|
2395 |
msr_ir = 0;
|
2396 |
msr_dr = 0;
|
2397 |
msr_ri = 0;
|
2398 |
msr_le = msr_ile; |
2399 |
if (env->excp_model == POWERPC_EXCP_BOOKE) {
|
2400 |
msr_cm = msr_icm; |
2401 |
if (idx == -1 || (idx >= 16 && idx < 32)) { |
2402 |
cpu_abort(env, "Invalid exception index for excp %d %08x idx %d\n",
|
2403 |
excp, excp, idx); |
2404 |
} |
2405 |
#if defined(TARGET_PPC64)
|
2406 |
if (msr_cm)
|
2407 |
env->nip = (uint64_t)env->spr[SPR_BOOKE_IVPR]; |
2408 |
else
|
2409 |
#endif
|
2410 |
env->nip = (uint32_t)env->spr[SPR_BOOKE_IVPR]; |
2411 |
if (idx < 16) |
2412 |
env->nip |= env->spr[SPR_BOOKE_IVOR0 + idx]; |
2413 |
else if (idx < 38) |
2414 |
env->nip |= env->spr[SPR_BOOKE_IVOR32 + idx - 32];
|
2415 |
} else {
|
2416 |
msr_sf = msr_isf; |
2417 |
env->nip = excp; |
2418 |
} |
2419 |
do_compute_hflags(env); |
2420 |
/* Jump to handler */
|
2421 |
env->exception_index = EXCP_NONE; |
2422 |
} |
2423 |
|
2424 |
void ppc_hw_interrupt (CPUPPCState *env)
|
2425 |
{ |
2426 |
int raised = 0; |
2427 |
|
2428 |
#if 1 |
2429 |
if (loglevel & CPU_LOG_INT) {
|
2430 |
fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
|
2431 |
__func__, env, env->pending_interrupts, |
2432 |
env->interrupt_request, msr_me, msr_ee); |
2433 |
} |
2434 |
#endif
|
2435 |
/* Raise it */
|
2436 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { |
2437 |
/* External reset / critical input */
|
2438 |
/* XXX: critical input should be handled another way.
|
2439 |
* This code is not correct !
|
2440 |
*/
|
2441 |
env->exception_index = EXCP_RESET; |
2442 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
|
2443 |
raised = 1;
|
2444 |
} |
2445 |
if (raised == 0 && msr_me != 0) { |
2446 |
/* Machine check exception */
|
2447 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { |
2448 |
env->exception_index = EXCP_MACHINE_CHECK; |
2449 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
|
2450 |
raised = 1;
|
2451 |
} |
2452 |
} |
2453 |
if (raised == 0 && msr_ee != 0) { |
2454 |
#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */ |
2455 |
/* Hypervisor decrementer exception */
|
2456 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { |
2457 |
env->exception_index = EXCP_HDECR; |
2458 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
|
2459 |
raised = 1;
|
2460 |
} else
|
2461 |
#endif
|
2462 |
/* Decrementer exception */
|
2463 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { |
2464 |
env->exception_index = EXCP_DECR; |
2465 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
|
2466 |
raised = 1;
|
2467 |
/* Programmable interval timer on embedded PowerPC */
|
2468 |
} else if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { |
2469 |
env->exception_index = EXCP_40x_PIT; |
2470 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
|
2471 |
raised = 1;
|
2472 |
/* Fixed interval timer on embedded PowerPC */
|
2473 |
} else if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { |
2474 |
env->exception_index = EXCP_40x_FIT; |
2475 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
|
2476 |
raised = 1;
|
2477 |
/* Watchdog timer on embedded PowerPC */
|
2478 |
} else if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { |
2479 |
env->exception_index = EXCP_40x_WATCHDOG; |
2480 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
|
2481 |
raised = 1;
|
2482 |
/* External interrupt */
|
2483 |
} else if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
2484 |
env->exception_index = EXCP_EXTERNAL; |
2485 |
/* Taking an external interrupt does not clear the external
|
2486 |
* interrupt status
|
2487 |
*/
|
2488 |
#if 0
|
2489 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
|
2490 |
#endif
|
2491 |
raised = 1;
|
2492 |
#if 0 // TODO
|
2493 |
/* Thermal interrupt */
|
2494 |
} else if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
|
2495 |
env->exception_index = EXCP_970_THRM;
|
2496 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
|
2497 |
raised = 1;
|
2498 |
#endif
|
2499 |
} |
2500 |
#if 0 // TODO
|
2501 |
/* External debug exception */
|
2502 |
} else if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
|
2503 |
env->exception_index = EXCP_xxx;
|
2504 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
|
2505 |
raised = 1;
|
2506 |
#endif
|
2507 |
} |
2508 |
if (raised != 0) { |
2509 |
env->error_code = 0;
|
2510 |
do_interrupt(env); |
2511 |
} |
2512 |
} |
2513 |
#endif /* !CONFIG_USER_ONLY */ |
2514 |
|
2515 |
void cpu_dump_EA (target_ulong EA)
|
2516 |
{ |
2517 |
FILE *f; |
2518 |
|
2519 |
if (logfile) {
|
2520 |
f = logfile; |
2521 |
} else {
|
2522 |
f = stdout; |
2523 |
return;
|
2524 |
} |
2525 |
fprintf(f, "Memory access at address " ADDRX "\n", EA); |
2526 |
} |
2527 |
|
2528 |
void cpu_dump_rfi (target_ulong RA, target_ulong msr)
|
2529 |
{ |
2530 |
FILE *f; |
2531 |
|
2532 |
if (logfile) {
|
2533 |
f = logfile; |
2534 |
} else {
|
2535 |
f = stdout; |
2536 |
return;
|
2537 |
} |
2538 |
fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n", |
2539 |
RA, msr); |
2540 |
} |
2541 |
|
2542 |
void cpu_ppc_reset (void *opaque) |
2543 |
{ |
2544 |
CPUPPCState *env; |
2545 |
int i;
|
2546 |
|
2547 |
env = opaque; |
2548 |
/* XXX: some of those flags initialisation values could depend
|
2549 |
* on the actual PowerPC implementation
|
2550 |
*/
|
2551 |
for (i = 0; i < 63; i++) |
2552 |
env->msr[i] = 0;
|
2553 |
#if defined(TARGET_PPC64)
|
2554 |
msr_hv = 0; /* Should be 1... */ |
2555 |
#endif
|
2556 |
msr_ap = 0; /* TO BE CHECKED */ |
2557 |
msr_sa = 0; /* TO BE CHECKED */ |
2558 |
msr_ip = 0; /* TO BE CHECKED */ |
2559 |
#if defined (DO_SINGLE_STEP) && 0 |
2560 |
/* Single step trace mode */
|
2561 |
msr_se = 1;
|
2562 |
msr_be = 1;
|
2563 |
#endif
|
2564 |
#if defined(CONFIG_USER_ONLY)
|
2565 |
msr_fp = 1; /* Allow floating point exceptions */ |
2566 |
msr_pr = 1;
|
2567 |
#else
|
2568 |
env->nip = 0xFFFFFFFC;
|
2569 |
ppc_tlb_invalidate_all(env); |
2570 |
#endif
|
2571 |
do_compute_hflags(env); |
2572 |
env->reserve = -1;
|
2573 |
/* Be sure no exception or interrupt is pending */
|
2574 |
env->pending_interrupts = 0;
|
2575 |
env->exception_index = EXCP_NONE; |
2576 |
/* Flush all TLBs */
|
2577 |
tlb_flush(env, 1);
|
2578 |
} |
2579 |
|
2580 |
CPUPPCState *cpu_ppc_init (void)
|
2581 |
{ |
2582 |
CPUPPCState *env; |
2583 |
|
2584 |
env = qemu_mallocz(sizeof(CPUPPCState));
|
2585 |
if (!env)
|
2586 |
return NULL; |
2587 |
cpu_exec_init(env); |
2588 |
cpu_ppc_reset(env); |
2589 |
|
2590 |
return env;
|
2591 |
} |
2592 |
|
2593 |
void cpu_ppc_close (CPUPPCState *env)
|
2594 |
{ |
2595 |
/* Should also remove all opcode tables... */
|
2596 |
free(env); |
2597 |
} |