Revision 417454b0 target-sparc/op_helper.c
| b/target-sparc/op_helper.c | ||
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cpu_loop_exit(); |
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} |
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void check_ieee_exceptions() |
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{
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T0 = get_float_exception_flags(&env->fp_status); |
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if (T0) |
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{
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/* Copy IEEE 754 flags into FSR */ |
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if (T0 & float_flag_invalid) |
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env->fsr |= FSR_NVC; |
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if (T0 & float_flag_overflow) |
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env->fsr |= FSR_OFC; |
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if (T0 & float_flag_underflow) |
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env->fsr |= FSR_UFC; |
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if (T0 & float_flag_divbyzero) |
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env->fsr |= FSR_DZC; |
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if (T0 & float_flag_inexact) |
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env->fsr |= FSR_NXC; |
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if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) |
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{
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/* Unmasked exception, generate a trap */ |
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env->fsr |= FSR_FTT_IEEE_EXCP; |
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raise_exception(TT_FP_EXCP); |
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} |
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else |
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{
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/* Accumulate exceptions */ |
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env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5; |
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} |
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} |
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} |
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#ifdef USE_INT_TO_FLOAT_HELPERS |
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void do_fitos(void) |
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{
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set_float_exception_flags(0, &env->fp_status); |
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FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status); |
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check_ieee_exceptions(); |
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} |
| 17 | 50 |
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void do_fitod(void) |
| ... | ... | |
| 35 | 68 |
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void do_fsqrts(void) |
| 37 | 70 |
{
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set_float_exception_flags(0, &env->fp_status); |
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FT0 = float32_sqrt(FT1, &env->fp_status); |
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check_ieee_exceptions(); |
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} |
| 40 | 75 |
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void do_fsqrtd(void) |
| 42 | 77 |
{
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set_float_exception_flags(0, &env->fp_status); |
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DT0 = float64_sqrt(DT1, &env->fp_status); |
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check_ieee_exceptions(); |
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} |
| 45 | 82 |
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#define GEN_FCMP(name, size, reg1, reg2, FS) \
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#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
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void glue(do_, name) (void) \ |
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{ \
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
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switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
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case float_relation_unordered: \ |
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; \ |
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if (env->fsr & FSR_NVM) { \
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if ((env->fsr & FSR_NVM) || TRAP) { \
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env->fsr |= T0; \ |
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env->fsr |= FSR_NVC; \ |
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env->fsr |= FSR_FTT_IEEE_EXCP; \ |
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raise_exception(TT_FP_EXCP); \ |
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} else { \
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env->fsr |= FSR_NVA; \ |
| ... | ... | |
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env->fsr |= T0; \ |
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} |
| 72 | 111 |
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GEN_FCMP(fcmps, float32, FT0, FT1, 0); |
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GEN_FCMP(fcmpd, float64, DT0, DT1, 0); |
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GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0); |
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GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0); |
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GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1); |
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GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1); |
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#ifdef TARGET_SPARC64 |
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GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22); |
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GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22); |
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GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0); |
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GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); |
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GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0); |
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GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0); |
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GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0); |
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GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0); |
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GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1); |
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GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1); |
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GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24);
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GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24);
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GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
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GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
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GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26);
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GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26);
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GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
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GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
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| 85 | 136 |
#endif |
| 86 | 137 |
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| 87 | 138 |
#if defined(CONFIG_USER_ONLY) |
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