Revision 41d9ea80
| b/include/elf.h | ||
|---|---|---|
| 411 | 411 |
#define R_SPARC_5 44 |
| 412 | 412 |
#define R_SPARC_6 45 |
| 413 | 413 |
|
| 414 |
/* Bits present in AT_HWCAP for ARM. */ |
|
| 415 |
|
|
| 416 |
#define HWCAP_ARM_SWP (1 << 0) |
|
| 417 |
#define HWCAP_ARM_HALF (1 << 1) |
|
| 418 |
#define HWCAP_ARM_THUMB (1 << 2) |
|
| 419 |
#define HWCAP_ARM_26BIT (1 << 3) |
|
| 420 |
#define HWCAP_ARM_FAST_MULT (1 << 4) |
|
| 421 |
#define HWCAP_ARM_FPA (1 << 5) |
|
| 422 |
#define HWCAP_ARM_VFP (1 << 6) |
|
| 423 |
#define HWCAP_ARM_EDSP (1 << 7) |
|
| 424 |
#define HWCAP_ARM_JAVA (1 << 8) |
|
| 425 |
#define HWCAP_ARM_IWMMXT (1 << 9) |
|
| 426 |
#define HWCAP_ARM_CRUNCH (1 << 10) |
|
| 427 |
#define HWCAP_ARM_THUMBEE (1 << 11) |
|
| 428 |
#define HWCAP_ARM_NEON (1 << 12) |
|
| 429 |
#define HWCAP_ARM_VFPv3 (1 << 13) |
|
| 430 |
#define HWCAP_ARM_VFPv3D16 (1 << 14) /* also set for VFPv4-D16 */ |
|
| 431 |
#define HWCAP_ARM_TLS (1 << 15) |
|
| 432 |
#define HWCAP_ARM_VFPv4 (1 << 16) |
|
| 433 |
#define HWCAP_ARM_IDIVA (1 << 17) |
|
| 434 |
#define HWCAP_ARM_IDIVT (1 << 18) |
|
| 435 |
#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT) |
|
| 436 |
#define HWCAP_VFPD32 (1 << 19) /* set if VFP has 32 regs */ |
|
| 437 |
#define HWCAP_LPAE (1 << 20) |
|
| 438 |
|
|
| 414 | 439 |
/* Bits present in AT_HWCAP for PowerPC. */ |
| 415 | 440 |
|
| 416 | 441 |
#define PPC_FEATURE_32 0x80000000 |
| b/tcg/arm/tcg-target.c | ||
|---|---|---|
| 22 | 22 |
* THE SOFTWARE. |
| 23 | 23 |
*/ |
| 24 | 24 |
|
| 25 |
#include "elf.h" |
|
| 25 | 26 |
#include "tcg-be-ldst.h" |
| 26 | 27 |
|
| 27 | 28 |
/* The __ARM_ARCH define is provided by gcc 4.8. Construct it otherwise. */ |
| ... | ... | |
| 58 | 59 |
#ifndef use_idiv_instructions |
| 59 | 60 |
bool use_idiv_instructions; |
| 60 | 61 |
#endif |
| 61 |
#ifdef CONFIG_GETAUXVAL |
|
| 62 |
# include <sys/auxv.h> |
|
| 63 |
#endif |
|
| 64 | 62 |
|
| 65 | 63 |
#ifndef NDEBUG |
| 66 | 64 |
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
|
| ... | ... | |
| 2036 | 2034 |
|
| 2037 | 2035 |
static void tcg_target_init(TCGContext *s) |
| 2038 | 2036 |
{
|
| 2039 |
#if defined(CONFIG_GETAUXVAL) |
|
| 2040 | 2037 |
/* Only probe for the platform and capabilities if we havn't already |
| 2041 | 2038 |
determined maximum values at compile time. */ |
| 2042 |
# if !defined(use_idiv_instructions)
|
|
| 2039 |
#ifndef use_idiv_instructions
|
|
| 2043 | 2040 |
{
|
| 2044 |
unsigned long hwcap = getauxval(AT_HWCAP); |
|
| 2041 |
unsigned long hwcap = qemu_getauxval(AT_HWCAP);
|
|
| 2045 | 2042 |
use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; |
| 2046 | 2043 |
} |
| 2047 |
# endif
|
|
| 2044 |
#endif |
|
| 2048 | 2045 |
if (__ARM_ARCH < 7) {
|
| 2049 |
const char *pl = (const char *)getauxval(AT_PLATFORM); |
|
| 2046 |
const char *pl = (const char *)qemu_getauxval(AT_PLATFORM);
|
|
| 2050 | 2047 |
if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
|
| 2051 | 2048 |
arm_arch = pl[1] - '0'; |
| 2052 | 2049 |
} |
| 2053 | 2050 |
} |
| 2054 |
#endif /* GETAUXVAL */ |
|
| 2055 | 2051 |
|
| 2056 | 2052 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); |
| 2057 | 2053 |
tcg_regset_set32(tcg_target_call_clobber_regs, 0, |
Also available in: Unified diff