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1 | 420557e8 | bellard | /*
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2 | 420557e8 | bellard | * QEMU Sun4m System Emulator
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3 | 420557e8 | bellard | *
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4 | 420557e8 | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 420557e8 | bellard | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 420557e8 | bellard | #include "vl.h" |
25 | 420557e8 | bellard | |
26 | 420557e8 | bellard | #define PHYS_JJ_TCX_FB 0x50800000 /* Start address, frame buffer body */ |
27 | 420557e8 | bellard | #define PHYS_JJ_TCX_0E 0x5E000000 /* Top address, one byte used. */ |
28 | 420557e8 | bellard | |
29 | 420557e8 | bellard | #define MAXX 1024 |
30 | 420557e8 | bellard | #define MAXY 768 |
31 | 420557e8 | bellard | #define XSZ (8*80) |
32 | 420557e8 | bellard | #define YSZ (24*11) |
33 | 420557e8 | bellard | #define XOFF (MAXX-XSZ)
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34 | 420557e8 | bellard | #define YOFF (MAXY-YSZ)
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35 | 420557e8 | bellard | |
36 | 420557e8 | bellard | #define DEBUG_VGA_MEM
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37 | 420557e8 | bellard | |
38 | 420557e8 | bellard | typedef struct TCXState { |
39 | 420557e8 | bellard | uint8_t *vram_ptr; |
40 | 420557e8 | bellard | unsigned long vram_offset; |
41 | 420557e8 | bellard | unsigned int vram_size; |
42 | 420557e8 | bellard | DisplayState *ds; |
43 | 420557e8 | bellard | } TCXState; |
44 | 420557e8 | bellard | |
45 | 420557e8 | bellard | static TCXState *ts;
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46 | 420557e8 | bellard | |
47 | 420557e8 | bellard | static int tcx_io_memory; |
48 | 420557e8 | bellard | |
49 | 420557e8 | bellard | void vga_update_display()
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50 | 420557e8 | bellard | { |
51 | 420557e8 | bellard | dpy_update(ts->ds, 0, 0, XSZ, YSZ); |
52 | 420557e8 | bellard | } |
53 | 420557e8 | bellard | |
54 | 420557e8 | bellard | static uint32_t tcx_mem_readb(void *opaque, target_phys_addr_t addr) |
55 | 420557e8 | bellard | { |
56 | 420557e8 | bellard | TCXState *s = opaque; |
57 | 420557e8 | bellard | uint32_t saddr; |
58 | 420557e8 | bellard | unsigned int x, y; |
59 | 420557e8 | bellard | char *sptr;
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60 | 420557e8 | bellard | |
61 | 420557e8 | bellard | saddr = addr - PHYS_JJ_TCX_FB - YOFF*MAXX - XOFF; |
62 | 420557e8 | bellard | y = saddr / MAXX; |
63 | 420557e8 | bellard | x = saddr - y * MAXX; |
64 | 420557e8 | bellard | if (x < MAXX && y < MAXY) {
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65 | 420557e8 | bellard | sptr = s->ds->data; |
66 | 420557e8 | bellard | if (sptr)
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67 | 420557e8 | bellard | return sptr[y * s->ds->linesize + x*4]; |
68 | 420557e8 | bellard | } |
69 | 420557e8 | bellard | return 0; |
70 | 420557e8 | bellard | } |
71 | 420557e8 | bellard | |
72 | 420557e8 | bellard | static uint32_t tcx_mem_readw(void *opaque, target_phys_addr_t addr) |
73 | 420557e8 | bellard | { |
74 | 420557e8 | bellard | uint32_t v; |
75 | 420557e8 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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76 | 420557e8 | bellard | v = tcx_mem_readb(opaque, addr) << 8;
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77 | 420557e8 | bellard | v |= tcx_mem_readb(opaque, addr + 1);
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78 | 420557e8 | bellard | #else
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79 | 420557e8 | bellard | v = tcx_mem_readb(opaque, addr); |
80 | 420557e8 | bellard | v |= tcx_mem_readb(opaque, addr + 1) << 8; |
81 | 420557e8 | bellard | #endif
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82 | 420557e8 | bellard | return v;
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83 | 420557e8 | bellard | } |
84 | 420557e8 | bellard | |
85 | 420557e8 | bellard | static uint32_t tcx_mem_readl(void *opaque, target_phys_addr_t addr) |
86 | 420557e8 | bellard | { |
87 | 420557e8 | bellard | uint32_t v; |
88 | 420557e8 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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89 | 420557e8 | bellard | v = tcx_mem_readb(opaque, addr) << 24;
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90 | 420557e8 | bellard | v |= tcx_mem_readb(opaque, addr + 1) << 16; |
91 | 420557e8 | bellard | v |= tcx_mem_readb(opaque, addr + 2) << 8; |
92 | 420557e8 | bellard | v |= tcx_mem_readb(opaque, addr + 3);
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93 | 420557e8 | bellard | #else
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94 | 420557e8 | bellard | v = tcx_mem_readb(opaque, addr); |
95 | 420557e8 | bellard | v |= tcx_mem_readb(opaque, addr + 1) << 8; |
96 | 420557e8 | bellard | v |= tcx_mem_readb(opaque, addr + 2) << 16; |
97 | 420557e8 | bellard | v |= tcx_mem_readb(opaque, addr + 3) << 24; |
98 | 420557e8 | bellard | #endif
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99 | 420557e8 | bellard | return v;
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100 | 420557e8 | bellard | } |
101 | 420557e8 | bellard | |
102 | 420557e8 | bellard | /* called for accesses between 0xa0000 and 0xc0000 */
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103 | 420557e8 | bellard | static void tcx_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
104 | 420557e8 | bellard | { |
105 | 420557e8 | bellard | TCXState *s = opaque; |
106 | 420557e8 | bellard | uint32_t saddr; |
107 | 420557e8 | bellard | unsigned int x, y; |
108 | 420557e8 | bellard | char *sptr;
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109 | 420557e8 | bellard | |
110 | 420557e8 | bellard | saddr = addr - PHYS_JJ_TCX_FB - YOFF*MAXX - XOFF; |
111 | 420557e8 | bellard | y = saddr / MAXX; |
112 | 420557e8 | bellard | x = saddr - y * MAXX; |
113 | 420557e8 | bellard | if (x < MAXX && y < MAXY) {
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114 | 420557e8 | bellard | sptr = s->ds->data; |
115 | 420557e8 | bellard | if (sptr) {
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116 | 420557e8 | bellard | sptr[y * s->ds->linesize + x*4] = val;
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117 | 420557e8 | bellard | sptr[y * s->ds->linesize + x*4+1] = val; |
118 | 420557e8 | bellard | sptr[y * s->ds->linesize + x*4+2] = val; |
119 | 420557e8 | bellard | cpu_physical_memory_set_dirty(addr); |
120 | 420557e8 | bellard | } |
121 | 420557e8 | bellard | } |
122 | 420557e8 | bellard | } |
123 | 420557e8 | bellard | |
124 | 420557e8 | bellard | static void tcx_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
125 | 420557e8 | bellard | { |
126 | 420557e8 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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127 | 420557e8 | bellard | tcx_mem_writeb(opaque, addr, (val >> 8) & 0xff); |
128 | 420557e8 | bellard | tcx_mem_writeb(opaque, addr + 1, val & 0xff); |
129 | 420557e8 | bellard | #else
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130 | 420557e8 | bellard | tcx_mem_writeb(opaque, addr, val & 0xff);
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131 | 420557e8 | bellard | tcx_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
132 | 420557e8 | bellard | #endif
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133 | 420557e8 | bellard | } |
134 | 420557e8 | bellard | |
135 | 420557e8 | bellard | static void tcx_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
136 | 420557e8 | bellard | { |
137 | 420557e8 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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138 | 420557e8 | bellard | tcx_mem_writeb(opaque, addr, (val >> 24) & 0xff); |
139 | 420557e8 | bellard | tcx_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
140 | 420557e8 | bellard | tcx_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
141 | 420557e8 | bellard | tcx_mem_writeb(opaque, addr + 3, val & 0xff); |
142 | 420557e8 | bellard | #else
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143 | 420557e8 | bellard | tcx_mem_writeb(opaque, addr, val & 0xff);
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144 | 420557e8 | bellard | tcx_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
145 | 420557e8 | bellard | tcx_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
146 | 420557e8 | bellard | tcx_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
147 | 420557e8 | bellard | #endif
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148 | 420557e8 | bellard | } |
149 | 420557e8 | bellard | |
150 | 420557e8 | bellard | static CPUReadMemoryFunc *tcx_mem_read[3] = { |
151 | 420557e8 | bellard | tcx_mem_readb, |
152 | 420557e8 | bellard | tcx_mem_readw, |
153 | 420557e8 | bellard | tcx_mem_readl, |
154 | 420557e8 | bellard | }; |
155 | 420557e8 | bellard | |
156 | 420557e8 | bellard | static CPUWriteMemoryFunc *tcx_mem_write[3] = { |
157 | 420557e8 | bellard | tcx_mem_writeb, |
158 | 420557e8 | bellard | tcx_mem_writew, |
159 | 420557e8 | bellard | tcx_mem_writel, |
160 | 420557e8 | bellard | }; |
161 | 420557e8 | bellard | |
162 | 420557e8 | bellard | void tcx_init(DisplayState *ds)
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163 | 420557e8 | bellard | { |
164 | 420557e8 | bellard | TCXState *s; |
165 | 420557e8 | bellard | |
166 | 420557e8 | bellard | s = qemu_mallocz(sizeof(TCXState));
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167 | 420557e8 | bellard | if (!s)
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168 | 420557e8 | bellard | return;
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169 | 420557e8 | bellard | s->ds = ds; |
170 | 420557e8 | bellard | ts = s; |
171 | 420557e8 | bellard | tcx_io_memory = cpu_register_io_memory(0, tcx_mem_read, tcx_mem_write, s);
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172 | 420557e8 | bellard | cpu_register_physical_memory(PHYS_JJ_TCX_FB, 0x100000,
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173 | 420557e8 | bellard | tcx_io_memory); |
174 | 420557e8 | bellard | dpy_resize(s->ds, XSZ, YSZ); |
175 | 420557e8 | bellard | } |