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/*
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 * QEMU Floppy disk emulator (Intel 82078)
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 *
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 * Copyright (c) 2003, 2007 Jocelyn Mayer
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 * Copyright (c) 2008 Herv? Poussineau
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/*
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 * The controller is used in Sun4m systems in a slightly different
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 * way. There are changes in DOR register and DMA is not available.
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 */
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#include "hw.h"
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#include "fdc.h"
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#include "block.h"
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#include "qemu-timer.h"
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#include "isa.h"
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#include "sysbus.h"
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#include "qdev-addr.h"
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/********************************************************/
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/* debug Floppy devices */
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//#define DEBUG_FLOPPY
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#ifdef DEBUG_FLOPPY
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#define FLOPPY_DPRINTF(fmt, ...)                                \
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    do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define FLOPPY_DPRINTF(fmt, ...)
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#endif
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#define FLOPPY_ERROR(fmt, ...)                                          \
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    do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
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/********************************************************/
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/* Floppy drive emulation                               */
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#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
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#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
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/* Will always be a fixed parameter for us */
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#define FD_SECTOR_LEN          512
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#define FD_SECTOR_SC           2   /* Sector size code */
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#define FD_RESET_SENSEI_COUNT  4   /* Number of sense interrupts on RESET */
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/* Floppy disk drive emulation */
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typedef enum fdisk_type_t {
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    FDRIVE_DISK_288   = 0x01, /* 2.88 MB disk           */
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    FDRIVE_DISK_144   = 0x02, /* 1.44 MB disk           */
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    FDRIVE_DISK_720   = 0x03, /* 720 kB disk            */
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    FDRIVE_DISK_USER  = 0x04, /* User defined geometry  */
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    FDRIVE_DISK_NONE  = 0x05, /* No disk                */
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} fdisk_type_t;
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typedef enum fdrive_type_t {
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    FDRIVE_DRV_144  = 0x00,   /* 1.44 MB 3"5 drive      */
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    FDRIVE_DRV_288  = 0x01,   /* 2.88 MB 3"5 drive      */
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    FDRIVE_DRV_120  = 0x02,   /* 1.2  MB 5"25 drive     */
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    FDRIVE_DRV_NONE = 0x03,   /* No drive connected     */
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} fdrive_type_t;
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typedef enum fdisk_flags_t {
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    FDISK_DBL_SIDES  = 0x01,
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} fdisk_flags_t;
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typedef struct fdrive_t {
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    DriveInfo *dinfo;
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    BlockDriverState *bs;
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    /* Drive status */
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    fdrive_type_t drive;
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    uint8_t perpendicular;    /* 2.88 MB access mode    */
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    /* Position */
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    uint8_t head;
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    uint8_t track;
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    uint8_t sect;
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    /* Media */
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    fdisk_flags_t flags;
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    uint8_t last_sect;        /* Nb sector per track    */
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    uint8_t max_track;        /* Nb of tracks           */
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    uint16_t bps;             /* Bytes per sector       */
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    uint8_t ro;               /* Is read-only           */
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} fdrive_t;
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static void fd_init (fdrive_t *drv)
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{
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    /* Drive */
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    drv->bs = drv->dinfo ? drv->dinfo->bdrv : NULL;
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    drv->drive = FDRIVE_DRV_NONE;
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    drv->perpendicular = 0;
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    /* Disk */
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    drv->last_sect = 0;
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    drv->max_track = 0;
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}
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static int _fd_sector (uint8_t head, uint8_t track,
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                       uint8_t sect, uint8_t last_sect)
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{
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    return (((track * 2) + head) * last_sect) + sect - 1;
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}
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/* Returns current position, in sectors, for given drive */
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static int fd_sector (fdrive_t *drv)
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{
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    return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
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}
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/* Seek to a new position:
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 * returns 0 if already on right track
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 * returns 1 if track changed
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 * returns 2 if track is invalid
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 * returns 3 if sector is invalid
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 * returns 4 if seek is disabled
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 */
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static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
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                    int enable_seek)
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{
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    uint32_t sector;
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    int ret;
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    if (track > drv->max_track ||
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        (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 2;
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    }
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    if (sect > drv->last_sect) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 3;
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    }
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    sector = _fd_sector(head, track, sect, drv->last_sect);
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    ret = 0;
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    if (sector != fd_sector(drv)) {
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#if 0
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        if (!enable_seek) {
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            FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
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                         head, track, sect, 1, drv->max_track, drv->last_sect);
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            return 4;
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        }
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#endif
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        drv->head = head;
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        if (drv->track != track)
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            ret = 1;
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        drv->track = track;
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        drv->sect = sect;
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    }
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    return ret;
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}
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/* Set drive back to track 0 */
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static void fd_recalibrate (fdrive_t *drv)
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{
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    FLOPPY_DPRINTF("recalibrate\n");
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    drv->head = 0;
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    drv->track = 0;
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    drv->sect = 1;
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}
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/* Recognize floppy formats */
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typedef struct fd_format_t {
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    fdrive_type_t drive;
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    fdisk_type_t  disk;
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    uint8_t last_sect;
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    uint8_t max_track;
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    uint8_t max_head;
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    const char *str;
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} fd_format_t;
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static const fd_format_t fd_formats[] = {
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    /* First entry is default format */
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    /* 1.44 MB 3"1/2 floppy disks */
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1,  "1.6 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
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    /* 2.88 MB 3"1/2 floppy disks */
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1,  "3.2 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
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    /* 720 kB 3"1/2 floppy disks */
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    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 1,  "720 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1,  "800 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1,  "820 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1,  "830 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
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    /* 1.2 MB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1,  "1.2 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1,  "1.6 MB 5\"1/4", },
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    /* 720 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 80, 1,  "720 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1,  "880 kB 5\"1/4", },
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    /* 360 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 1,  "360 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 0,  "180 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1,  "410 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1,  "420 kB 5\"1/4", },
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    /* 320 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 1,  "320 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 0,  "160 kB 5\"1/4", },
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    /* 360 kB must match 5"1/4 better than 3"1/2... */
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    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 0,  "360 kB 3\"1/2", },
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    /* end */
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    { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
236 a541f297 bellard
};
237 a541f297 bellard
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/* Revalidate a disk drive after a disk change */
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static void fd_revalidate (fdrive_t *drv)
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{
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    const fd_format_t *parse;
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    uint64_t nb_sectors, size;
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    int i, first_match, match;
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    int nb_heads, max_track, last_sect, ro;
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    FLOPPY_DPRINTF("revalidate\n");
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    if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
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        ro = bdrv_is_read_only(drv->bs);
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        bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
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        if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
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            FLOPPY_DPRINTF("User defined disk (%d %d %d)",
252 ed5fd2cc bellard
                           nb_heads - 1, max_track, last_sect);
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        } else {
254 4f431960 j_mayer
            bdrv_get_geometry(drv->bs, &nb_sectors);
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            match = -1;
256 4f431960 j_mayer
            first_match = -1;
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            for (i = 0;; i++) {
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                parse = &fd_formats[i];
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                if (parse->drive == FDRIVE_DRV_NONE)
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                    break;
261 4f431960 j_mayer
                if (drv->drive == parse->drive ||
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                    drv->drive == FDRIVE_DRV_NONE) {
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                    size = (parse->max_head + 1) * parse->max_track *
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                        parse->last_sect;
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                    if (nb_sectors == size) {
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                        match = i;
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                        break;
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                    }
269 4f431960 j_mayer
                    if (first_match == -1)
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                        first_match = i;
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                }
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            }
273 4f431960 j_mayer
            if (match == -1) {
274 4f431960 j_mayer
                if (first_match == -1)
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                    match = 1;
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                else
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                    match = first_match;
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                parse = &fd_formats[match];
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            }
280 4f431960 j_mayer
            nb_heads = parse->max_head + 1;
281 4f431960 j_mayer
            max_track = parse->max_track;
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            last_sect = parse->last_sect;
283 4f431960 j_mayer
            drv->drive = parse->drive;
284 4f431960 j_mayer
            FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
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                           nb_heads, max_track, last_sect, ro ? "ro" : "rw");
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        }
287 4f431960 j_mayer
        if (nb_heads == 1) {
288 4f431960 j_mayer
            drv->flags &= ~FDISK_DBL_SIDES;
289 4f431960 j_mayer
        } else {
290 4f431960 j_mayer
            drv->flags |= FDISK_DBL_SIDES;
291 4f431960 j_mayer
        }
292 4f431960 j_mayer
        drv->max_track = max_track;
293 4f431960 j_mayer
        drv->last_sect = last_sect;
294 4f431960 j_mayer
        drv->ro = ro;
295 8977f3c1 bellard
    } else {
296 4f431960 j_mayer
        FLOPPY_DPRINTF("No disk in drive\n");
297 baca51fa bellard
        drv->last_sect = 0;
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        drv->max_track = 0;
299 4f431960 j_mayer
        drv->flags &= ~FDISK_DBL_SIDES;
300 8977f3c1 bellard
    }
301 caed8802 bellard
}
302 caed8802 bellard
303 8977f3c1 bellard
/********************************************************/
304 4b19ec0c bellard
/* Intel 82078 floppy disk controller emulation          */
305 8977f3c1 bellard
306 c227f099 Anthony Liguori
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
307 c227f099 Anthony Liguori
static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
308 85571bc7 bellard
static int fdctrl_transfer_handler (void *opaque, int nchan,
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                                    int dma_pos, int dma_len);
310 c227f099 Anthony Liguori
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
311 c227f099 Anthony Liguori
312 c227f099 Anthony Liguori
static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
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static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
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static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
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static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
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static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
318 c227f099 Anthony Liguori
static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
319 c227f099 Anthony Liguori
static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
320 c227f099 Anthony Liguori
static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
321 c227f099 Anthony Liguori
static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
322 c227f099 Anthony Liguori
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
323 8977f3c1 bellard
324 8977f3c1 bellard
enum {
325 8977f3c1 bellard
    FD_DIR_WRITE   = 0,
326 8977f3c1 bellard
    FD_DIR_READ    = 1,
327 8977f3c1 bellard
    FD_DIR_SCANE   = 2,
328 8977f3c1 bellard
    FD_DIR_SCANL   = 3,
329 8977f3c1 bellard
    FD_DIR_SCANH   = 4,
330 8977f3c1 bellard
};
331 8977f3c1 bellard
332 8977f3c1 bellard
enum {
333 b9b3d225 blueswir1
    FD_STATE_MULTI  = 0x01,        /* multi track flag */
334 b9b3d225 blueswir1
    FD_STATE_FORMAT = 0x02,        /* format flag */
335 b9b3d225 blueswir1
    FD_STATE_SEEK   = 0x04,        /* seek flag */
336 8977f3c1 bellard
};
337 8977f3c1 bellard
338 9fea808a blueswir1
enum {
339 8c6a4d77 blueswir1
    FD_REG_SRA = 0x00,
340 8c6a4d77 blueswir1
    FD_REG_SRB = 0x01,
341 9fea808a blueswir1
    FD_REG_DOR = 0x02,
342 9fea808a blueswir1
    FD_REG_TDR = 0x03,
343 9fea808a blueswir1
    FD_REG_MSR = 0x04,
344 9fea808a blueswir1
    FD_REG_DSR = 0x04,
345 9fea808a blueswir1
    FD_REG_FIFO = 0x05,
346 9fea808a blueswir1
    FD_REG_DIR = 0x07,
347 9fea808a blueswir1
};
348 9fea808a blueswir1
349 9fea808a blueswir1
enum {
350 65cef780 blueswir1
    FD_CMD_READ_TRACK = 0x02,
351 9fea808a blueswir1
    FD_CMD_SPECIFY = 0x03,
352 9fea808a blueswir1
    FD_CMD_SENSE_DRIVE_STATUS = 0x04,
353 65cef780 blueswir1
    FD_CMD_WRITE = 0x05,
354 65cef780 blueswir1
    FD_CMD_READ = 0x06,
355 9fea808a blueswir1
    FD_CMD_RECALIBRATE = 0x07,
356 9fea808a blueswir1
    FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
357 65cef780 blueswir1
    FD_CMD_WRITE_DELETED = 0x09,
358 65cef780 blueswir1
    FD_CMD_READ_ID = 0x0a,
359 65cef780 blueswir1
    FD_CMD_READ_DELETED = 0x0c,
360 65cef780 blueswir1
    FD_CMD_FORMAT_TRACK = 0x0d,
361 9fea808a blueswir1
    FD_CMD_DUMPREG = 0x0e,
362 9fea808a blueswir1
    FD_CMD_SEEK = 0x0f,
363 9fea808a blueswir1
    FD_CMD_VERSION = 0x10,
364 65cef780 blueswir1
    FD_CMD_SCAN_EQUAL = 0x11,
365 9fea808a blueswir1
    FD_CMD_PERPENDICULAR_MODE = 0x12,
366 9fea808a blueswir1
    FD_CMD_CONFIGURE = 0x13,
367 65cef780 blueswir1
    FD_CMD_LOCK = 0x14,
368 65cef780 blueswir1
    FD_CMD_VERIFY = 0x16,
369 9fea808a blueswir1
    FD_CMD_POWERDOWN_MODE = 0x17,
370 9fea808a blueswir1
    FD_CMD_PART_ID = 0x18,
371 65cef780 blueswir1
    FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
372 65cef780 blueswir1
    FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
373 9fea808a blueswir1
    FD_CMD_SAVE = 0x2c,
374 9fea808a blueswir1
    FD_CMD_OPTION = 0x33,
375 9fea808a blueswir1
    FD_CMD_RESTORE = 0x4c,
376 9fea808a blueswir1
    FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
377 9fea808a blueswir1
    FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
378 9fea808a blueswir1
    FD_CMD_FORMAT_AND_WRITE = 0xcd,
379 9fea808a blueswir1
    FD_CMD_RELATIVE_SEEK_IN = 0xcf,
380 9fea808a blueswir1
};
381 9fea808a blueswir1
382 9fea808a blueswir1
enum {
383 9fea808a blueswir1
    FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
384 9fea808a blueswir1
    FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
385 9fea808a blueswir1
    FD_CONFIG_POLL  = 0x10, /* Poll enabled */
386 9fea808a blueswir1
    FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
387 9fea808a blueswir1
    FD_CONFIG_EIS   = 0x40, /* No implied seeks */
388 9fea808a blueswir1
};
389 9fea808a blueswir1
390 9fea808a blueswir1
enum {
391 9fea808a blueswir1
    FD_SR0_EQPMT    = 0x10,
392 9fea808a blueswir1
    FD_SR0_SEEK     = 0x20,
393 9fea808a blueswir1
    FD_SR0_ABNTERM  = 0x40,
394 9fea808a blueswir1
    FD_SR0_INVCMD   = 0x80,
395 9fea808a blueswir1
    FD_SR0_RDYCHG   = 0xc0,
396 9fea808a blueswir1
};
397 9fea808a blueswir1
398 9fea808a blueswir1
enum {
399 77370520 blueswir1
    FD_SR1_EC       = 0x80, /* End of cylinder */
400 77370520 blueswir1
};
401 77370520 blueswir1
402 77370520 blueswir1
enum {
403 77370520 blueswir1
    FD_SR2_SNS      = 0x04, /* Scan not satisfied */
404 77370520 blueswir1
    FD_SR2_SEH      = 0x08, /* Scan equal hit */
405 77370520 blueswir1
};
406 77370520 blueswir1
407 77370520 blueswir1
enum {
408 8c6a4d77 blueswir1
    FD_SRA_DIR      = 0x01,
409 8c6a4d77 blueswir1
    FD_SRA_nWP      = 0x02,
410 8c6a4d77 blueswir1
    FD_SRA_nINDX    = 0x04,
411 8c6a4d77 blueswir1
    FD_SRA_HDSEL    = 0x08,
412 8c6a4d77 blueswir1
    FD_SRA_nTRK0    = 0x10,
413 8c6a4d77 blueswir1
    FD_SRA_STEP     = 0x20,
414 8c6a4d77 blueswir1
    FD_SRA_nDRV2    = 0x40,
415 8c6a4d77 blueswir1
    FD_SRA_INTPEND  = 0x80,
416 8c6a4d77 blueswir1
};
417 8c6a4d77 blueswir1
418 8c6a4d77 blueswir1
enum {
419 8c6a4d77 blueswir1
    FD_SRB_MTR0     = 0x01,
420 8c6a4d77 blueswir1
    FD_SRB_MTR1     = 0x02,
421 8c6a4d77 blueswir1
    FD_SRB_WGATE    = 0x04,
422 8c6a4d77 blueswir1
    FD_SRB_RDATA    = 0x08,
423 8c6a4d77 blueswir1
    FD_SRB_WDATA    = 0x10,
424 8c6a4d77 blueswir1
    FD_SRB_DR0      = 0x20,
425 8c6a4d77 blueswir1
};
426 8c6a4d77 blueswir1
427 8c6a4d77 blueswir1
enum {
428 78ae820c blueswir1
#if MAX_FD == 4
429 78ae820c blueswir1
    FD_DOR_SELMASK  = 0x03,
430 78ae820c blueswir1
#else
431 9fea808a blueswir1
    FD_DOR_SELMASK  = 0x01,
432 78ae820c blueswir1
#endif
433 9fea808a blueswir1
    FD_DOR_nRESET   = 0x04,
434 9fea808a blueswir1
    FD_DOR_DMAEN    = 0x08,
435 9fea808a blueswir1
    FD_DOR_MOTEN0   = 0x10,
436 9fea808a blueswir1
    FD_DOR_MOTEN1   = 0x20,
437 9fea808a blueswir1
    FD_DOR_MOTEN2   = 0x40,
438 9fea808a blueswir1
    FD_DOR_MOTEN3   = 0x80,
439 9fea808a blueswir1
};
440 9fea808a blueswir1
441 9fea808a blueswir1
enum {
442 78ae820c blueswir1
#if MAX_FD == 4
443 9fea808a blueswir1
    FD_TDR_BOOTSEL  = 0x0c,
444 78ae820c blueswir1
#else
445 78ae820c blueswir1
    FD_TDR_BOOTSEL  = 0x04,
446 78ae820c blueswir1
#endif
447 9fea808a blueswir1
};
448 9fea808a blueswir1
449 9fea808a blueswir1
enum {
450 9fea808a blueswir1
    FD_DSR_DRATEMASK= 0x03,
451 9fea808a blueswir1
    FD_DSR_PWRDOWN  = 0x40,
452 9fea808a blueswir1
    FD_DSR_SWRESET  = 0x80,
453 9fea808a blueswir1
};
454 9fea808a blueswir1
455 9fea808a blueswir1
enum {
456 9fea808a blueswir1
    FD_MSR_DRV0BUSY = 0x01,
457 9fea808a blueswir1
    FD_MSR_DRV1BUSY = 0x02,
458 9fea808a blueswir1
    FD_MSR_DRV2BUSY = 0x04,
459 9fea808a blueswir1
    FD_MSR_DRV3BUSY = 0x08,
460 9fea808a blueswir1
    FD_MSR_CMDBUSY  = 0x10,
461 9fea808a blueswir1
    FD_MSR_NONDMA   = 0x20,
462 9fea808a blueswir1
    FD_MSR_DIO      = 0x40,
463 9fea808a blueswir1
    FD_MSR_RQM      = 0x80,
464 9fea808a blueswir1
};
465 9fea808a blueswir1
466 9fea808a blueswir1
enum {
467 9fea808a blueswir1
    FD_DIR_DSKCHG   = 0x80,
468 9fea808a blueswir1
};
469 9fea808a blueswir1
470 8977f3c1 bellard
#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
471 8977f3c1 bellard
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
472 baca51fa bellard
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
473 8977f3c1 bellard
474 c227f099 Anthony Liguori
struct fdctrl_t {
475 4b19ec0c bellard
    /* Controller's identification */
476 8977f3c1 bellard
    uint8_t version;
477 8977f3c1 bellard
    /* HW */
478 d537cf6c pbrook
    qemu_irq irq;
479 8977f3c1 bellard
    int dma_chann;
480 4b19ec0c bellard
    /* Controller state */
481 ed5fd2cc bellard
    QEMUTimer *result_timer;
482 8c6a4d77 blueswir1
    uint8_t sra;
483 8c6a4d77 blueswir1
    uint8_t srb;
484 368df94d blueswir1
    uint8_t dor;
485 d7a6c270 Juan Quintela
    uint8_t dor_vmstate; /* only used as temp during vmstate */
486 46d3233b blueswir1
    uint8_t tdr;
487 b9b3d225 blueswir1
    uint8_t dsr;
488 368df94d blueswir1
    uint8_t msr;
489 8977f3c1 bellard
    uint8_t cur_drv;
490 77370520 blueswir1
    uint8_t status0;
491 77370520 blueswir1
    uint8_t status1;
492 77370520 blueswir1
    uint8_t status2;
493 8977f3c1 bellard
    /* Command FIFO */
494 33f00271 balrog
    uint8_t *fifo;
495 d7a6c270 Juan Quintela
    int32_t fifo_size;
496 8977f3c1 bellard
    uint32_t data_pos;
497 8977f3c1 bellard
    uint32_t data_len;
498 8977f3c1 bellard
    uint8_t data_state;
499 8977f3c1 bellard
    uint8_t data_dir;
500 890fa6be bellard
    uint8_t eot; /* last wanted sector */
501 8977f3c1 bellard
    /* States kept only to be returned back */
502 8977f3c1 bellard
    /* Timers state */
503 8977f3c1 bellard
    uint8_t timer0;
504 8977f3c1 bellard
    uint8_t timer1;
505 8977f3c1 bellard
    /* precompensation */
506 8977f3c1 bellard
    uint8_t precomp_trk;
507 8977f3c1 bellard
    uint8_t config;
508 8977f3c1 bellard
    uint8_t lock;
509 8977f3c1 bellard
    /* Power down config (also with status regB access mode */
510 8977f3c1 bellard
    uint8_t pwrd;
511 741402f9 blueswir1
    /* Sun4m quirks? */
512 a06e5a3c blueswir1
    int sun4m;
513 8977f3c1 bellard
    /* Floppy drives */
514 d7a6c270 Juan Quintela
    uint8_t num_floppies;
515 c227f099 Anthony Liguori
    fdrive_t drives[MAX_FD];
516 f2d81b33 blueswir1
    int reset_sensei;
517 baca51fa bellard
};
518 baca51fa bellard
519 c227f099 Anthony Liguori
typedef struct fdctrl_sysbus_t {
520 8baf73ad Gerd Hoffmann
    SysBusDevice busdev;
521 c227f099 Anthony Liguori
    struct fdctrl_t state;
522 c227f099 Anthony Liguori
} fdctrl_sysbus_t;
523 8baf73ad Gerd Hoffmann
524 c227f099 Anthony Liguori
typedef struct fdctrl_isabus_t {
525 8baf73ad Gerd Hoffmann
    ISADevice busdev;
526 c227f099 Anthony Liguori
    struct fdctrl_t state;
527 c227f099 Anthony Liguori
} fdctrl_isabus_t;
528 8baf73ad Gerd Hoffmann
529 baca51fa bellard
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
530 baca51fa bellard
{
531 c227f099 Anthony Liguori
    fdctrl_t *fdctrl = opaque;
532 baca51fa bellard
    uint32_t retval;
533 baca51fa bellard
534 e64d7d59 blueswir1
    switch (reg) {
535 8c6a4d77 blueswir1
    case FD_REG_SRA:
536 8c6a4d77 blueswir1
        retval = fdctrl_read_statusA(fdctrl);
537 4f431960 j_mayer
        break;
538 8c6a4d77 blueswir1
    case FD_REG_SRB:
539 4f431960 j_mayer
        retval = fdctrl_read_statusB(fdctrl);
540 4f431960 j_mayer
        break;
541 9fea808a blueswir1
    case FD_REG_DOR:
542 4f431960 j_mayer
        retval = fdctrl_read_dor(fdctrl);
543 4f431960 j_mayer
        break;
544 9fea808a blueswir1
    case FD_REG_TDR:
545 baca51fa bellard
        retval = fdctrl_read_tape(fdctrl);
546 4f431960 j_mayer
        break;
547 9fea808a blueswir1
    case FD_REG_MSR:
548 baca51fa bellard
        retval = fdctrl_read_main_status(fdctrl);
549 4f431960 j_mayer
        break;
550 9fea808a blueswir1
    case FD_REG_FIFO:
551 baca51fa bellard
        retval = fdctrl_read_data(fdctrl);
552 4f431960 j_mayer
        break;
553 9fea808a blueswir1
    case FD_REG_DIR:
554 baca51fa bellard
        retval = fdctrl_read_dir(fdctrl);
555 4f431960 j_mayer
        break;
556 a541f297 bellard
    default:
557 4f431960 j_mayer
        retval = (uint32_t)(-1);
558 4f431960 j_mayer
        break;
559 a541f297 bellard
    }
560 ed5fd2cc bellard
    FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
561 baca51fa bellard
562 baca51fa bellard
    return retval;
563 baca51fa bellard
}
564 baca51fa bellard
565 baca51fa bellard
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
566 baca51fa bellard
{
567 c227f099 Anthony Liguori
    fdctrl_t *fdctrl = opaque;
568 baca51fa bellard
569 ed5fd2cc bellard
    FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
570 ed5fd2cc bellard
571 e64d7d59 blueswir1
    switch (reg) {
572 9fea808a blueswir1
    case FD_REG_DOR:
573 4f431960 j_mayer
        fdctrl_write_dor(fdctrl, value);
574 4f431960 j_mayer
        break;
575 9fea808a blueswir1
    case FD_REG_TDR:
576 baca51fa bellard
        fdctrl_write_tape(fdctrl, value);
577 4f431960 j_mayer
        break;
578 9fea808a blueswir1
    case FD_REG_DSR:
579 baca51fa bellard
        fdctrl_write_rate(fdctrl, value);
580 4f431960 j_mayer
        break;
581 9fea808a blueswir1
    case FD_REG_FIFO:
582 baca51fa bellard
        fdctrl_write_data(fdctrl, value);
583 4f431960 j_mayer
        break;
584 a541f297 bellard
    default:
585 4f431960 j_mayer
        break;
586 a541f297 bellard
    }
587 baca51fa bellard
}
588 baca51fa bellard
589 e64d7d59 blueswir1
static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
590 e64d7d59 blueswir1
{
591 e64d7d59 blueswir1
    return fdctrl_read(opaque, reg & 7);
592 e64d7d59 blueswir1
}
593 e64d7d59 blueswir1
594 e64d7d59 blueswir1
static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
595 e64d7d59 blueswir1
{
596 e64d7d59 blueswir1
    fdctrl_write(opaque, reg & 7, value);
597 e64d7d59 blueswir1
}
598 e64d7d59 blueswir1
599 c227f099 Anthony Liguori
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
600 62a46c61 bellard
{
601 5dcb6b91 blueswir1
    return fdctrl_read(opaque, (uint32_t)reg);
602 62a46c61 bellard
}
603 62a46c61 bellard
604 5fafdf24 ths
static void fdctrl_write_mem (void *opaque,
605 c227f099 Anthony Liguori
                              target_phys_addr_t reg, uint32_t value)
606 62a46c61 bellard
{
607 5dcb6b91 blueswir1
    fdctrl_write(opaque, (uint32_t)reg, value);
608 62a46c61 bellard
}
609 62a46c61 bellard
610 d60efc6b Blue Swirl
static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
611 62a46c61 bellard
    fdctrl_read_mem,
612 62a46c61 bellard
    fdctrl_read_mem,
613 62a46c61 bellard
    fdctrl_read_mem,
614 e80cfcfc bellard
};
615 e80cfcfc bellard
616 d60efc6b Blue Swirl
static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
617 62a46c61 bellard
    fdctrl_write_mem,
618 62a46c61 bellard
    fdctrl_write_mem,
619 62a46c61 bellard
    fdctrl_write_mem,
620 e80cfcfc bellard
};
621 e80cfcfc bellard
622 d60efc6b Blue Swirl
static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
623 7c560456 blueswir1
    fdctrl_read_mem,
624 7c560456 blueswir1
    NULL,
625 7c560456 blueswir1
    NULL,
626 7c560456 blueswir1
};
627 7c560456 blueswir1
628 d60efc6b Blue Swirl
static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
629 7c560456 blueswir1
    fdctrl_write_mem,
630 7c560456 blueswir1
    NULL,
631 7c560456 blueswir1
    NULL,
632 7c560456 blueswir1
};
633 7c560456 blueswir1
634 d7a6c270 Juan Quintela
static const VMStateDescription vmstate_fdrive = {
635 d7a6c270 Juan Quintela
    .name = "fdrive",
636 d7a6c270 Juan Quintela
    .version_id = 1,
637 d7a6c270 Juan Quintela
    .minimum_version_id = 1,
638 d7a6c270 Juan Quintela
    .minimum_version_id_old = 1,
639 d7a6c270 Juan Quintela
    .fields      = (VMStateField []) {
640 c227f099 Anthony Liguori
        VMSTATE_UINT8(head, fdrive_t),
641 c227f099 Anthony Liguori
        VMSTATE_UINT8(track, fdrive_t),
642 c227f099 Anthony Liguori
        VMSTATE_UINT8(sect, fdrive_t),
643 d7a6c270 Juan Quintela
        VMSTATE_END_OF_LIST()
644 d7a6c270 Juan Quintela
    }
645 d7a6c270 Juan Quintela
};
646 3ccacc4a blueswir1
647 d4bfa4d7 Juan Quintela
static void fdc_pre_save(void *opaque)
648 3ccacc4a blueswir1
{
649 d4bfa4d7 Juan Quintela
    fdctrl_t *s = opaque;
650 3ccacc4a blueswir1
651 d7a6c270 Juan Quintela
    s->dor_vmstate = s->dor | GET_CUR_DRV(s);
652 3ccacc4a blueswir1
}
653 3ccacc4a blueswir1
654 e59fb374 Juan Quintela
static int fdc_post_load(void *opaque, int version_id)
655 3ccacc4a blueswir1
{
656 c227f099 Anthony Liguori
    fdctrl_t *s = opaque;
657 3ccacc4a blueswir1
658 d7a6c270 Juan Quintela
    SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
659 d7a6c270 Juan Quintela
    s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
660 3ccacc4a blueswir1
    return 0;
661 3ccacc4a blueswir1
}
662 3ccacc4a blueswir1
663 d7a6c270 Juan Quintela
static const VMStateDescription vmstate_fdc = {
664 2966b390 Juan Quintela
    .name = "fdctrl",
665 d7a6c270 Juan Quintela
    .version_id = 2,
666 d7a6c270 Juan Quintela
    .minimum_version_id = 2,
667 d7a6c270 Juan Quintela
    .minimum_version_id_old = 2,
668 d7a6c270 Juan Quintela
    .pre_save = fdc_pre_save,
669 d7a6c270 Juan Quintela
    .post_load = fdc_post_load,
670 d7a6c270 Juan Quintela
    .fields      = (VMStateField []) {
671 d7a6c270 Juan Quintela
        /* Controller State */
672 c227f099 Anthony Liguori
        VMSTATE_UINT8(sra, fdctrl_t),
673 c227f099 Anthony Liguori
        VMSTATE_UINT8(srb, fdctrl_t),
674 c227f099 Anthony Liguori
        VMSTATE_UINT8(dor_vmstate, fdctrl_t),
675 c227f099 Anthony Liguori
        VMSTATE_UINT8(tdr, fdctrl_t),
676 c227f099 Anthony Liguori
        VMSTATE_UINT8(dsr, fdctrl_t),
677 c227f099 Anthony Liguori
        VMSTATE_UINT8(msr, fdctrl_t),
678 c227f099 Anthony Liguori
        VMSTATE_UINT8(status0, fdctrl_t),
679 c227f099 Anthony Liguori
        VMSTATE_UINT8(status1, fdctrl_t),
680 c227f099 Anthony Liguori
        VMSTATE_UINT8(status2, fdctrl_t),
681 d7a6c270 Juan Quintela
        /* Command FIFO */
682 d6698281 Juan Quintela
        VMSTATE_VARRAY_INT32(fifo, fdctrl_t, fifo_size, 0, vmstate_info_uint8, uint8),
683 c227f099 Anthony Liguori
        VMSTATE_UINT32(data_pos, fdctrl_t),
684 c227f099 Anthony Liguori
        VMSTATE_UINT32(data_len, fdctrl_t),
685 c227f099 Anthony Liguori
        VMSTATE_UINT8(data_state, fdctrl_t),
686 c227f099 Anthony Liguori
        VMSTATE_UINT8(data_dir, fdctrl_t),
687 c227f099 Anthony Liguori
        VMSTATE_UINT8(eot, fdctrl_t),
688 d7a6c270 Juan Quintela
        /* States kept only to be returned back */
689 c227f099 Anthony Liguori
        VMSTATE_UINT8(timer0, fdctrl_t),
690 c227f099 Anthony Liguori
        VMSTATE_UINT8(timer1, fdctrl_t),
691 c227f099 Anthony Liguori
        VMSTATE_UINT8(precomp_trk, fdctrl_t),
692 c227f099 Anthony Liguori
        VMSTATE_UINT8(config, fdctrl_t),
693 c227f099 Anthony Liguori
        VMSTATE_UINT8(lock, fdctrl_t),
694 c227f099 Anthony Liguori
        VMSTATE_UINT8(pwrd, fdctrl_t),
695 c227f099 Anthony Liguori
        VMSTATE_UINT8_EQUAL(num_floppies, fdctrl_t),
696 c227f099 Anthony Liguori
        VMSTATE_STRUCT_ARRAY(drives, fdctrl_t, MAX_FD, 1,
697 c227f099 Anthony Liguori
                             vmstate_fdrive, fdrive_t),
698 d7a6c270 Juan Quintela
        VMSTATE_END_OF_LIST()
699 78ae820c blueswir1
    }
700 d7a6c270 Juan Quintela
};
701 3ccacc4a blueswir1
702 2966b390 Juan Quintela
static const VMStateDescription vmstate_fdc_isa = {
703 2966b390 Juan Quintela
    .name = "fdc",
704 2966b390 Juan Quintela
    .version_id = 2,
705 2966b390 Juan Quintela
    .minimum_version_id = 2,
706 2966b390 Juan Quintela
    .minimum_version_id_old = 2,
707 2966b390 Juan Quintela
    .fields      = (VMStateField []) {
708 2966b390 Juan Quintela
        /* Controller State */
709 2966b390 Juan Quintela
        VMSTATE_STRUCT(state, fdctrl_isabus_t, 0, vmstate_fdc, fdctrl_t),
710 2966b390 Juan Quintela
        VMSTATE_END_OF_LIST()
711 2966b390 Juan Quintela
    }
712 2966b390 Juan Quintela
};
713 2966b390 Juan Quintela
714 2966b390 Juan Quintela
static const VMStateDescription vmstate_fdc_sysbus = {
715 2966b390 Juan Quintela
    .name = "fdc",
716 2966b390 Juan Quintela
    .version_id = 2,
717 2966b390 Juan Quintela
    .minimum_version_id = 2,
718 2966b390 Juan Quintela
    .minimum_version_id_old = 2,
719 2966b390 Juan Quintela
    .fields      = (VMStateField []) {
720 2966b390 Juan Quintela
        /* Controller State */
721 2966b390 Juan Quintela
        VMSTATE_STRUCT(state, fdctrl_sysbus_t, 0, vmstate_fdc, fdctrl_t),
722 2966b390 Juan Quintela
        VMSTATE_END_OF_LIST()
723 2966b390 Juan Quintela
    }
724 2966b390 Juan Quintela
};
725 2966b390 Juan Quintela
726 2966b390 Juan Quintela
727 2be37833 Blue Swirl
static void fdctrl_external_reset_sysbus(DeviceState *d)
728 3ccacc4a blueswir1
{
729 2be37833 Blue Swirl
    fdctrl_sysbus_t *sys = container_of(d, fdctrl_sysbus_t, busdev.qdev);
730 2be37833 Blue Swirl
    fdctrl_t *s = &sys->state;
731 2be37833 Blue Swirl
732 2be37833 Blue Swirl
    fdctrl_reset(s, 0);
733 2be37833 Blue Swirl
}
734 2be37833 Blue Swirl
735 2be37833 Blue Swirl
static void fdctrl_external_reset_isa(DeviceState *d)
736 2be37833 Blue Swirl
{
737 2be37833 Blue Swirl
    fdctrl_isabus_t *isa = container_of(d, fdctrl_isabus_t, busdev.qdev);
738 2be37833 Blue Swirl
    fdctrl_t *s = &isa->state;
739 3ccacc4a blueswir1
740 3ccacc4a blueswir1
    fdctrl_reset(s, 0);
741 3ccacc4a blueswir1
}
742 3ccacc4a blueswir1
743 2be17ebd blueswir1
static void fdctrl_handle_tc(void *opaque, int irq, int level)
744 2be17ebd blueswir1
{
745 c227f099 Anthony Liguori
    //fdctrl_t *s = opaque;
746 2be17ebd blueswir1
747 2be17ebd blueswir1
    if (level) {
748 2be17ebd blueswir1
        // XXX
749 2be17ebd blueswir1
        FLOPPY_DPRINTF("TC pulsed\n");
750 2be17ebd blueswir1
    }
751 2be17ebd blueswir1
}
752 2be17ebd blueswir1
753 baca51fa bellard
/* XXX: may change if moved to bdrv */
754 c227f099 Anthony Liguori
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
755 caed8802 bellard
{
756 baca51fa bellard
    return fdctrl->drives[drive_num].drive;
757 8977f3c1 bellard
}
758 8977f3c1 bellard
759 8977f3c1 bellard
/* Change IRQ state */
760 c227f099 Anthony Liguori
static void fdctrl_reset_irq (fdctrl_t *fdctrl)
761 8977f3c1 bellard
{
762 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND))
763 8c6a4d77 blueswir1
        return;
764 ed5fd2cc bellard
    FLOPPY_DPRINTF("Reset interrupt\n");
765 d537cf6c pbrook
    qemu_set_irq(fdctrl->irq, 0);
766 8c6a4d77 blueswir1
    fdctrl->sra &= ~FD_SRA_INTPEND;
767 8977f3c1 bellard
}
768 8977f3c1 bellard
769 c227f099 Anthony Liguori
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
770 8977f3c1 bellard
{
771 b9b3d225 blueswir1
    /* Sparc mutation */
772 b9b3d225 blueswir1
    if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
773 b9b3d225 blueswir1
        /* XXX: not sure */
774 b9b3d225 blueswir1
        fdctrl->msr &= ~FD_MSR_CMDBUSY;
775 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
776 77370520 blueswir1
        fdctrl->status0 = status0;
777 4f431960 j_mayer
        return;
778 6f7e9aec bellard
    }
779 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND)) {
780 d537cf6c pbrook
        qemu_set_irq(fdctrl->irq, 1);
781 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_INTPEND;
782 8977f3c1 bellard
    }
783 f2d81b33 blueswir1
    fdctrl->reset_sensei = 0;
784 77370520 blueswir1
    fdctrl->status0 = status0;
785 77370520 blueswir1
    FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
786 8977f3c1 bellard
}
787 8977f3c1 bellard
788 4b19ec0c bellard
/* Reset controller */
789 c227f099 Anthony Liguori
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
790 8977f3c1 bellard
{
791 8977f3c1 bellard
    int i;
792 8977f3c1 bellard
793 4b19ec0c bellard
    FLOPPY_DPRINTF("reset controller\n");
794 baca51fa bellard
    fdctrl_reset_irq(fdctrl);
795 4b19ec0c bellard
    /* Initialise controller */
796 8c6a4d77 blueswir1
    fdctrl->sra = 0;
797 8c6a4d77 blueswir1
    fdctrl->srb = 0xc0;
798 8c6a4d77 blueswir1
    if (!fdctrl->drives[1].bs)
799 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_nDRV2;
800 baca51fa bellard
    fdctrl->cur_drv = 0;
801 1c346df2 blueswir1
    fdctrl->dor = FD_DOR_nRESET;
802 368df94d blueswir1
    fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
803 b9b3d225 blueswir1
    fdctrl->msr = FD_MSR_RQM;
804 8977f3c1 bellard
    /* FIFO state */
805 baca51fa bellard
    fdctrl->data_pos = 0;
806 baca51fa bellard
    fdctrl->data_len = 0;
807 b9b3d225 blueswir1
    fdctrl->data_state = 0;
808 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
809 8977f3c1 bellard
    for (i = 0; i < MAX_FD; i++)
810 1c346df2 blueswir1
        fd_recalibrate(&fdctrl->drives[i]);
811 baca51fa bellard
    fdctrl_reset_fifo(fdctrl);
812 77370520 blueswir1
    if (do_irq) {
813 9fea808a blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
814 f2d81b33 blueswir1
        fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
815 77370520 blueswir1
    }
816 baca51fa bellard
}
817 baca51fa bellard
818 c227f099 Anthony Liguori
static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
819 baca51fa bellard
{
820 46d3233b blueswir1
    return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
821 baca51fa bellard
}
822 baca51fa bellard
823 c227f099 Anthony Liguori
static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
824 baca51fa bellard
{
825 46d3233b blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
826 46d3233b blueswir1
        return &fdctrl->drives[1];
827 46d3233b blueswir1
    else
828 46d3233b blueswir1
        return &fdctrl->drives[0];
829 baca51fa bellard
}
830 baca51fa bellard
831 78ae820c blueswir1
#if MAX_FD == 4
832 c227f099 Anthony Liguori
static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
833 78ae820c blueswir1
{
834 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
835 78ae820c blueswir1
        return &fdctrl->drives[2];
836 78ae820c blueswir1
    else
837 78ae820c blueswir1
        return &fdctrl->drives[1];
838 78ae820c blueswir1
}
839 78ae820c blueswir1
840 c227f099 Anthony Liguori
static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
841 78ae820c blueswir1
{
842 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
843 78ae820c blueswir1
        return &fdctrl->drives[3];
844 78ae820c blueswir1
    else
845 78ae820c blueswir1
        return &fdctrl->drives[2];
846 78ae820c blueswir1
}
847 78ae820c blueswir1
#endif
848 78ae820c blueswir1
849 c227f099 Anthony Liguori
static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
850 baca51fa bellard
{
851 78ae820c blueswir1
    switch (fdctrl->cur_drv) {
852 78ae820c blueswir1
        case 0: return drv0(fdctrl);
853 78ae820c blueswir1
        case 1: return drv1(fdctrl);
854 78ae820c blueswir1
#if MAX_FD == 4
855 78ae820c blueswir1
        case 2: return drv2(fdctrl);
856 78ae820c blueswir1
        case 3: return drv3(fdctrl);
857 78ae820c blueswir1
#endif
858 78ae820c blueswir1
        default: return NULL;
859 78ae820c blueswir1
    }
860 8977f3c1 bellard
}
861 8977f3c1 bellard
862 8c6a4d77 blueswir1
/* Status A register : 0x00 (read-only) */
863 c227f099 Anthony Liguori
static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
864 8c6a4d77 blueswir1
{
865 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->sra;
866 8c6a4d77 blueswir1
867 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
868 8c6a4d77 blueswir1
869 8c6a4d77 blueswir1
    return retval;
870 8c6a4d77 blueswir1
}
871 8c6a4d77 blueswir1
872 8977f3c1 bellard
/* Status B register : 0x01 (read-only) */
873 c227f099 Anthony Liguori
static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
874 8977f3c1 bellard
{
875 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->srb;
876 8c6a4d77 blueswir1
877 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
878 8c6a4d77 blueswir1
879 8c6a4d77 blueswir1
    return retval;
880 8977f3c1 bellard
}
881 8977f3c1 bellard
882 8977f3c1 bellard
/* Digital output register : 0x02 */
883 c227f099 Anthony Liguori
static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
884 8977f3c1 bellard
{
885 1c346df2 blueswir1
    uint32_t retval = fdctrl->dor;
886 8977f3c1 bellard
887 8977f3c1 bellard
    /* Selected drive */
888 baca51fa bellard
    retval |= fdctrl->cur_drv;
889 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
890 8977f3c1 bellard
891 8977f3c1 bellard
    return retval;
892 8977f3c1 bellard
}
893 8977f3c1 bellard
894 c227f099 Anthony Liguori
static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
895 8977f3c1 bellard
{
896 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
897 8c6a4d77 blueswir1
898 8c6a4d77 blueswir1
    /* Motors */
899 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN0)
900 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR0;
901 8c6a4d77 blueswir1
    else
902 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR0;
903 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN1)
904 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR1;
905 8c6a4d77 blueswir1
    else
906 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR1;
907 8c6a4d77 blueswir1
908 8c6a4d77 blueswir1
    /* Drive */
909 8c6a4d77 blueswir1
    if (value & 1)
910 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_DR0;
911 8c6a4d77 blueswir1
    else
912 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_DR0;
913 8c6a4d77 blueswir1
914 8977f3c1 bellard
    /* Reset */
915 9fea808a blueswir1
    if (!(value & FD_DOR_nRESET)) {
916 1c346df2 blueswir1
        if (fdctrl->dor & FD_DOR_nRESET) {
917 4b19ec0c bellard
            FLOPPY_DPRINTF("controller enter RESET state\n");
918 8977f3c1 bellard
        }
919 8977f3c1 bellard
    } else {
920 1c346df2 blueswir1
        if (!(fdctrl->dor & FD_DOR_nRESET)) {
921 4b19ec0c bellard
            FLOPPY_DPRINTF("controller out of RESET state\n");
922 fb6cf1d0 bellard
            fdctrl_reset(fdctrl, 1);
923 b9b3d225 blueswir1
            fdctrl->dsr &= ~FD_DSR_PWRDOWN;
924 8977f3c1 bellard
        }
925 8977f3c1 bellard
    }
926 8977f3c1 bellard
    /* Selected drive */
927 9fea808a blueswir1
    fdctrl->cur_drv = value & FD_DOR_SELMASK;
928 368df94d blueswir1
929 368df94d blueswir1
    fdctrl->dor = value;
930 8977f3c1 bellard
}
931 8977f3c1 bellard
932 8977f3c1 bellard
/* Tape drive register : 0x03 */
933 c227f099 Anthony Liguori
static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
934 8977f3c1 bellard
{
935 46d3233b blueswir1
    uint32_t retval = fdctrl->tdr;
936 8977f3c1 bellard
937 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
938 8977f3c1 bellard
939 8977f3c1 bellard
    return retval;
940 8977f3c1 bellard
}
941 8977f3c1 bellard
942 c227f099 Anthony Liguori
static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
943 8977f3c1 bellard
{
944 8977f3c1 bellard
    /* Reset mode */
945 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
946 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
947 8977f3c1 bellard
        return;
948 8977f3c1 bellard
    }
949 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
950 8977f3c1 bellard
    /* Disk boot selection indicator */
951 46d3233b blueswir1
    fdctrl->tdr = value & FD_TDR_BOOTSEL;
952 8977f3c1 bellard
    /* Tape indicators: never allow */
953 8977f3c1 bellard
}
954 8977f3c1 bellard
955 8977f3c1 bellard
/* Main status register : 0x04 (read) */
956 c227f099 Anthony Liguori
static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
957 8977f3c1 bellard
{
958 b9b3d225 blueswir1
    uint32_t retval = fdctrl->msr;
959 8977f3c1 bellard
960 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
961 1c346df2 blueswir1
    fdctrl->dor |= FD_DOR_nRESET;
962 b9b3d225 blueswir1
963 8977f3c1 bellard
    FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
964 8977f3c1 bellard
965 8977f3c1 bellard
    return retval;
966 8977f3c1 bellard
}
967 8977f3c1 bellard
968 8977f3c1 bellard
/* Data select rate register : 0x04 (write) */
969 c227f099 Anthony Liguori
static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
970 8977f3c1 bellard
{
971 8977f3c1 bellard
    /* Reset mode */
972 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
973 4f431960 j_mayer
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
974 4f431960 j_mayer
        return;
975 4f431960 j_mayer
    }
976 8977f3c1 bellard
    FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
977 8977f3c1 bellard
    /* Reset: autoclear */
978 9fea808a blueswir1
    if (value & FD_DSR_SWRESET) {
979 1c346df2 blueswir1
        fdctrl->dor &= ~FD_DOR_nRESET;
980 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
981 1c346df2 blueswir1
        fdctrl->dor |= FD_DOR_nRESET;
982 8977f3c1 bellard
    }
983 9fea808a blueswir1
    if (value & FD_DSR_PWRDOWN) {
984 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
985 8977f3c1 bellard
    }
986 b9b3d225 blueswir1
    fdctrl->dsr = value;
987 8977f3c1 bellard
}
988 8977f3c1 bellard
989 c227f099 Anthony Liguori
static int fdctrl_media_changed(fdrive_t *drv)
990 ea185bbd bellard
{
991 ea185bbd bellard
    int ret;
992 4f431960 j_mayer
993 5fafdf24 ths
    if (!drv->bs)
994 ea185bbd bellard
        return 0;
995 ea185bbd bellard
    ret = bdrv_media_changed(drv->bs);
996 ea185bbd bellard
    if (ret) {
997 ea185bbd bellard
        fd_revalidate(drv);
998 ea185bbd bellard
    }
999 ea185bbd bellard
    return ret;
1000 ea185bbd bellard
}
1001 ea185bbd bellard
1002 8977f3c1 bellard
/* Digital input register : 0x07 (read-only) */
1003 c227f099 Anthony Liguori
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
1004 8977f3c1 bellard
{
1005 8977f3c1 bellard
    uint32_t retval = 0;
1006 8977f3c1 bellard
1007 78ae820c blueswir1
    if (fdctrl_media_changed(drv0(fdctrl))
1008 78ae820c blueswir1
     || fdctrl_media_changed(drv1(fdctrl))
1009 78ae820c blueswir1
#if MAX_FD == 4
1010 78ae820c blueswir1
     || fdctrl_media_changed(drv2(fdctrl))
1011 78ae820c blueswir1
     || fdctrl_media_changed(drv3(fdctrl))
1012 78ae820c blueswir1
#endif
1013 78ae820c blueswir1
        )
1014 9fea808a blueswir1
        retval |= FD_DIR_DSKCHG;
1015 8977f3c1 bellard
    if (retval != 0)
1016 baca51fa bellard
        FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1017 8977f3c1 bellard
1018 8977f3c1 bellard
    return retval;
1019 8977f3c1 bellard
}
1020 8977f3c1 bellard
1021 8977f3c1 bellard
/* FIFO state control */
1022 c227f099 Anthony Liguori
static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
1023 8977f3c1 bellard
{
1024 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
1025 baca51fa bellard
    fdctrl->data_pos = 0;
1026 b9b3d225 blueswir1
    fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1027 8977f3c1 bellard
}
1028 8977f3c1 bellard
1029 8977f3c1 bellard
/* Set FIFO status for the host to read */
1030 c227f099 Anthony Liguori
static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
1031 8977f3c1 bellard
{
1032 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
1033 baca51fa bellard
    fdctrl->data_len = fifo_len;
1034 baca51fa bellard
    fdctrl->data_pos = 0;
1035 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1036 8977f3c1 bellard
    if (do_irq)
1037 baca51fa bellard
        fdctrl_raise_irq(fdctrl, 0x00);
1038 8977f3c1 bellard
}
1039 8977f3c1 bellard
1040 8977f3c1 bellard
/* Set an error: unimplemented/unknown command */
1041 c227f099 Anthony Liguori
static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1042 8977f3c1 bellard
{
1043 77370520 blueswir1
    FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1044 9fea808a blueswir1
    fdctrl->fifo[0] = FD_SR0_INVCMD;
1045 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 1, 0);
1046 8977f3c1 bellard
}
1047 8977f3c1 bellard
1048 746d6de7 blueswir1
/* Seek to next sector */
1049 c227f099 Anthony Liguori
static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1050 746d6de7 blueswir1
{
1051 746d6de7 blueswir1
    FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1052 746d6de7 blueswir1
                   cur_drv->head, cur_drv->track, cur_drv->sect,
1053 746d6de7 blueswir1
                   fd_sector(cur_drv));
1054 746d6de7 blueswir1
    /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1055 746d6de7 blueswir1
       error in fact */
1056 746d6de7 blueswir1
    if (cur_drv->sect >= cur_drv->last_sect ||
1057 746d6de7 blueswir1
        cur_drv->sect == fdctrl->eot) {
1058 746d6de7 blueswir1
        cur_drv->sect = 1;
1059 746d6de7 blueswir1
        if (FD_MULTI_TRACK(fdctrl->data_state)) {
1060 746d6de7 blueswir1
            if (cur_drv->head == 0 &&
1061 746d6de7 blueswir1
                (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1062 746d6de7 blueswir1
                cur_drv->head = 1;
1063 746d6de7 blueswir1
            } else {
1064 746d6de7 blueswir1
                cur_drv->head = 0;
1065 746d6de7 blueswir1
                cur_drv->track++;
1066 746d6de7 blueswir1
                if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1067 746d6de7 blueswir1
                    return 0;
1068 746d6de7 blueswir1
            }
1069 746d6de7 blueswir1
        } else {
1070 746d6de7 blueswir1
            cur_drv->track++;
1071 746d6de7 blueswir1
            return 0;
1072 746d6de7 blueswir1
        }
1073 746d6de7 blueswir1
        FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1074 746d6de7 blueswir1
                       cur_drv->head, cur_drv->track,
1075 746d6de7 blueswir1
                       cur_drv->sect, fd_sector(cur_drv));
1076 746d6de7 blueswir1
    } else {
1077 746d6de7 blueswir1
        cur_drv->sect++;
1078 746d6de7 blueswir1
    }
1079 746d6de7 blueswir1
    return 1;
1080 746d6de7 blueswir1
}
1081 746d6de7 blueswir1
1082 8977f3c1 bellard
/* Callback for transfer end (stop or abort) */
1083 c227f099 Anthony Liguori
static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1084 4f431960 j_mayer
                                  uint8_t status1, uint8_t status2)
1085 8977f3c1 bellard
{
1086 c227f099 Anthony Liguori
    fdrive_t *cur_drv;
1087 8977f3c1 bellard
1088 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1089 8977f3c1 bellard
    FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1090 8977f3c1 bellard
                   status0, status1, status2,
1091 cefec4f5 blueswir1
                   status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1092 cefec4f5 blueswir1
    fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1093 baca51fa bellard
    fdctrl->fifo[1] = status1;
1094 baca51fa bellard
    fdctrl->fifo[2] = status2;
1095 baca51fa bellard
    fdctrl->fifo[3] = cur_drv->track;
1096 baca51fa bellard
    fdctrl->fifo[4] = cur_drv->head;
1097 baca51fa bellard
    fdctrl->fifo[5] = cur_drv->sect;
1098 baca51fa bellard
    fdctrl->fifo[6] = FD_SECTOR_SC;
1099 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
1100 368df94d blueswir1
    if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1101 baca51fa bellard
        DMA_release_DREQ(fdctrl->dma_chann);
1102 ed5fd2cc bellard
    }
1103 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1104 368df94d blueswir1
    fdctrl->msr &= ~FD_MSR_NONDMA;
1105 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 7, 1);
1106 8977f3c1 bellard
}
1107 8977f3c1 bellard
1108 8977f3c1 bellard
/* Prepare a data transfer (either DMA or FIFO) */
1109 c227f099 Anthony Liguori
static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1110 8977f3c1 bellard
{
1111 c227f099 Anthony Liguori
    fdrive_t *cur_drv;
1112 8977f3c1 bellard
    uint8_t kh, kt, ks;
1113 77370520 blueswir1
    int did_seek = 0;
1114 8977f3c1 bellard
1115 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1116 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1117 baca51fa bellard
    kt = fdctrl->fifo[2];
1118 baca51fa bellard
    kh = fdctrl->fifo[3];
1119 baca51fa bellard
    ks = fdctrl->fifo[4];
1120 4b19ec0c bellard
    FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1121 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1122 8977f3c1 bellard
                   _fd_sector(kh, kt, ks, cur_drv->last_sect));
1123 77370520 blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1124 8977f3c1 bellard
    case 2:
1125 8977f3c1 bellard
        /* sect too big */
1126 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1127 baca51fa bellard
        fdctrl->fifo[3] = kt;
1128 baca51fa bellard
        fdctrl->fifo[4] = kh;
1129 baca51fa bellard
        fdctrl->fifo[5] = ks;
1130 8977f3c1 bellard
        return;
1131 8977f3c1 bellard
    case 3:
1132 8977f3c1 bellard
        /* track too big */
1133 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1134 baca51fa bellard
        fdctrl->fifo[3] = kt;
1135 baca51fa bellard
        fdctrl->fifo[4] = kh;
1136 baca51fa bellard
        fdctrl->fifo[5] = ks;
1137 8977f3c1 bellard
        return;
1138 8977f3c1 bellard
    case 4:
1139 8977f3c1 bellard
        /* No seek enabled */
1140 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1141 baca51fa bellard
        fdctrl->fifo[3] = kt;
1142 baca51fa bellard
        fdctrl->fifo[4] = kh;
1143 baca51fa bellard
        fdctrl->fifo[5] = ks;
1144 8977f3c1 bellard
        return;
1145 8977f3c1 bellard
    case 1:
1146 8977f3c1 bellard
        did_seek = 1;
1147 8977f3c1 bellard
        break;
1148 8977f3c1 bellard
    default:
1149 8977f3c1 bellard
        break;
1150 8977f3c1 bellard
    }
1151 b9b3d225 blueswir1
1152 8977f3c1 bellard
    /* Set the FIFO state */
1153 baca51fa bellard
    fdctrl->data_dir = direction;
1154 baca51fa bellard
    fdctrl->data_pos = 0;
1155 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY;
1156 baca51fa bellard
    if (fdctrl->fifo[0] & 0x80)
1157 baca51fa bellard
        fdctrl->data_state |= FD_STATE_MULTI;
1158 baca51fa bellard
    else
1159 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_MULTI;
1160 8977f3c1 bellard
    if (did_seek)
1161 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1162 baca51fa bellard
    else
1163 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_SEEK;
1164 baca51fa bellard
    if (fdctrl->fifo[5] == 00) {
1165 baca51fa bellard
        fdctrl->data_len = fdctrl->fifo[8];
1166 baca51fa bellard
    } else {
1167 4f431960 j_mayer
        int tmp;
1168 3bcb80f1 ths
        fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1169 771effeb blueswir1
        tmp = (fdctrl->fifo[6] - ks + 1);
1170 baca51fa bellard
        if (fdctrl->fifo[0] & 0x80)
1171 771effeb blueswir1
            tmp += fdctrl->fifo[6];
1172 4f431960 j_mayer
        fdctrl->data_len *= tmp;
1173 baca51fa bellard
    }
1174 890fa6be bellard
    fdctrl->eot = fdctrl->fifo[6];
1175 368df94d blueswir1
    if (fdctrl->dor & FD_DOR_DMAEN) {
1176 8977f3c1 bellard
        int dma_mode;
1177 8977f3c1 bellard
        /* DMA transfer are enabled. Check if DMA channel is well programmed */
1178 baca51fa bellard
        dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1179 8977f3c1 bellard
        dma_mode = (dma_mode >> 2) & 3;
1180 baca51fa bellard
        FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1181 4f431960 j_mayer
                       dma_mode, direction,
1182 baca51fa bellard
                       (128 << fdctrl->fifo[5]) *
1183 4f431960 j_mayer
                       (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1184 8977f3c1 bellard
        if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1185 8977f3c1 bellard
              direction == FD_DIR_SCANH) && dma_mode == 0) ||
1186 8977f3c1 bellard
            (direction == FD_DIR_WRITE && dma_mode == 2) ||
1187 8977f3c1 bellard
            (direction == FD_DIR_READ && dma_mode == 1)) {
1188 8977f3c1 bellard
            /* No access is allowed until DMA transfer has completed */
1189 b9b3d225 blueswir1
            fdctrl->msr &= ~FD_MSR_RQM;
1190 4b19ec0c bellard
            /* Now, we just have to wait for the DMA controller to
1191 8977f3c1 bellard
             * recall us...
1192 8977f3c1 bellard
             */
1193 baca51fa bellard
            DMA_hold_DREQ(fdctrl->dma_chann);
1194 baca51fa bellard
            DMA_schedule(fdctrl->dma_chann);
1195 8977f3c1 bellard
            return;
1196 baca51fa bellard
        } else {
1197 4f431960 j_mayer
            FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1198 8977f3c1 bellard
        }
1199 8977f3c1 bellard
    }
1200 8977f3c1 bellard
    FLOPPY_DPRINTF("start non-DMA transfer\n");
1201 368df94d blueswir1
    fdctrl->msr |= FD_MSR_NONDMA;
1202 b9b3d225 blueswir1
    if (direction != FD_DIR_WRITE)
1203 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_DIO;
1204 8977f3c1 bellard
    /* IO based transfer: calculate len */
1205 baca51fa bellard
    fdctrl_raise_irq(fdctrl, 0x00);
1206 8977f3c1 bellard
1207 8977f3c1 bellard
    return;
1208 8977f3c1 bellard
}
1209 8977f3c1 bellard
1210 8977f3c1 bellard
/* Prepare a transfer of deleted data */
1211 c227f099 Anthony Liguori
static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1212 8977f3c1 bellard
{
1213 77370520 blueswir1
    FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1214 77370520 blueswir1
1215 8977f3c1 bellard
    /* We don't handle deleted data,
1216 8977f3c1 bellard
     * so we don't return *ANYTHING*
1217 8977f3c1 bellard
     */
1218 9fea808a blueswir1
    fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1219 8977f3c1 bellard
}
1220 8977f3c1 bellard
1221 8977f3c1 bellard
/* handlers for DMA transfers */
1222 85571bc7 bellard
static int fdctrl_transfer_handler (void *opaque, int nchan,
1223 85571bc7 bellard
                                    int dma_pos, int dma_len)
1224 8977f3c1 bellard
{
1225 c227f099 Anthony Liguori
    fdctrl_t *fdctrl;
1226 c227f099 Anthony Liguori
    fdrive_t *cur_drv;
1227 baca51fa bellard
    int len, start_pos, rel_pos;
1228 8977f3c1 bellard
    uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1229 8977f3c1 bellard
1230 baca51fa bellard
    fdctrl = opaque;
1231 b9b3d225 blueswir1
    if (fdctrl->msr & FD_MSR_RQM) {
1232 8977f3c1 bellard
        FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1233 8977f3c1 bellard
        return 0;
1234 8977f3c1 bellard
    }
1235 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1236 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1237 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1238 77370520 blueswir1
        status2 = FD_SR2_SNS;
1239 85571bc7 bellard
    if (dma_len > fdctrl->data_len)
1240 85571bc7 bellard
        dma_len = fdctrl->data_len;
1241 890fa6be bellard
    if (cur_drv->bs == NULL) {
1242 4f431960 j_mayer
        if (fdctrl->data_dir == FD_DIR_WRITE)
1243 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1244 4f431960 j_mayer
        else
1245 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1246 4f431960 j_mayer
        len = 0;
1247 890fa6be bellard
        goto transfer_error;
1248 890fa6be bellard
    }
1249 baca51fa bellard
    rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1250 85571bc7 bellard
    for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1251 85571bc7 bellard
        len = dma_len - fdctrl->data_pos;
1252 baca51fa bellard
        if (len + rel_pos > FD_SECTOR_LEN)
1253 baca51fa bellard
            len = FD_SECTOR_LEN - rel_pos;
1254 6f7e9aec bellard
        FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1255 6f7e9aec bellard
                       "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1256 cefec4f5 blueswir1
                       fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1257 baca51fa bellard
                       cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1258 9fea808a blueswir1
                       fd_sector(cur_drv) * FD_SECTOR_LEN);
1259 baca51fa bellard
        if (fdctrl->data_dir != FD_DIR_WRITE ||
1260 4f431960 j_mayer
            len < FD_SECTOR_LEN || rel_pos != 0) {
1261 baca51fa bellard
            /* READ & SCAN commands and realign to a sector for WRITE */
1262 baca51fa bellard
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1263 4f431960 j_mayer
                          fdctrl->fifo, 1) < 0) {
1264 8977f3c1 bellard
                FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1265 8977f3c1 bellard
                               fd_sector(cur_drv));
1266 8977f3c1 bellard
                /* Sure, image size is too small... */
1267 baca51fa bellard
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1268 8977f3c1 bellard
            }
1269 890fa6be bellard
        }
1270 4f431960 j_mayer
        switch (fdctrl->data_dir) {
1271 4f431960 j_mayer
        case FD_DIR_READ:
1272 4f431960 j_mayer
            /* READ commands */
1273 85571bc7 bellard
            DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1274 85571bc7 bellard
                              fdctrl->data_pos, len);
1275 4f431960 j_mayer
            break;
1276 4f431960 j_mayer
        case FD_DIR_WRITE:
1277 baca51fa bellard
            /* WRITE commands */
1278 85571bc7 bellard
            DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1279 85571bc7 bellard
                             fdctrl->data_pos, len);
1280 baca51fa bellard
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1281 4f431960 j_mayer
                           fdctrl->fifo, 1) < 0) {
1282 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1283 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1284 baca51fa bellard
                goto transfer_error;
1285 890fa6be bellard
            }
1286 4f431960 j_mayer
            break;
1287 4f431960 j_mayer
        default:
1288 4f431960 j_mayer
            /* SCAN commands */
1289 baca51fa bellard
            {
1290 4f431960 j_mayer
                uint8_t tmpbuf[FD_SECTOR_LEN];
1291 baca51fa bellard
                int ret;
1292 85571bc7 bellard
                DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1293 baca51fa bellard
                ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1294 8977f3c1 bellard
                if (ret == 0) {
1295 77370520 blueswir1
                    status2 = FD_SR2_SEH;
1296 8977f3c1 bellard
                    goto end_transfer;
1297 8977f3c1 bellard
                }
1298 baca51fa bellard
                if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1299 baca51fa bellard
                    (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1300 8977f3c1 bellard
                    status2 = 0x00;
1301 8977f3c1 bellard
                    goto end_transfer;
1302 8977f3c1 bellard
                }
1303 8977f3c1 bellard
            }
1304 4f431960 j_mayer
            break;
1305 8977f3c1 bellard
        }
1306 4f431960 j_mayer
        fdctrl->data_pos += len;
1307 4f431960 j_mayer
        rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1308 baca51fa bellard
        if (rel_pos == 0) {
1309 8977f3c1 bellard
            /* Seek to next sector */
1310 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1311 746d6de7 blueswir1
                break;
1312 8977f3c1 bellard
        }
1313 8977f3c1 bellard
    }
1314 4f431960 j_mayer
 end_transfer:
1315 baca51fa bellard
    len = fdctrl->data_pos - start_pos;
1316 baca51fa bellard
    FLOPPY_DPRINTF("end transfer %d %d %d\n",
1317 4f431960 j_mayer
                   fdctrl->data_pos, len, fdctrl->data_len);
1318 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE ||
1319 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANL ||
1320 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1321 77370520 blueswir1
        status2 = FD_SR2_SEH;
1322 baca51fa bellard
    if (FD_DID_SEEK(fdctrl->data_state))
1323 9fea808a blueswir1
        status0 |= FD_SR0_SEEK;
1324 baca51fa bellard
    fdctrl->data_len -= len;
1325 890fa6be bellard
    fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1326 4f431960 j_mayer
 transfer_error:
1327 8977f3c1 bellard
1328 baca51fa bellard
    return len;
1329 8977f3c1 bellard
}
1330 8977f3c1 bellard
1331 8977f3c1 bellard
/* Data register : 0x05 */
1332 c227f099 Anthony Liguori
static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1333 8977f3c1 bellard
{
1334 c227f099 Anthony Liguori
    fdrive_t *cur_drv;
1335 8977f3c1 bellard
    uint32_t retval = 0;
1336 746d6de7 blueswir1
    int pos;
1337 8977f3c1 bellard
1338 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1339 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1340 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1341 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for reading\n");
1342 8977f3c1 bellard
        return 0;
1343 8977f3c1 bellard
    }
1344 baca51fa bellard
    pos = fdctrl->data_pos;
1345 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1346 8977f3c1 bellard
        pos %= FD_SECTOR_LEN;
1347 8977f3c1 bellard
        if (pos == 0) {
1348 746d6de7 blueswir1
            if (fdctrl->data_pos != 0)
1349 746d6de7 blueswir1
                if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1350 746d6de7 blueswir1
                    FLOPPY_DPRINTF("error seeking to next sector %d\n",
1351 746d6de7 blueswir1
                                   fd_sector(cur_drv));
1352 746d6de7 blueswir1
                    return 0;
1353 746d6de7 blueswir1
                }
1354 77370520 blueswir1
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1355 77370520 blueswir1
                FLOPPY_DPRINTF("error getting sector %d\n",
1356 77370520 blueswir1
                               fd_sector(cur_drv));
1357 77370520 blueswir1
                /* Sure, image size is too small... */
1358 77370520 blueswir1
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1359 77370520 blueswir1
            }
1360 8977f3c1 bellard
        }
1361 8977f3c1 bellard
    }
1362 baca51fa bellard
    retval = fdctrl->fifo[pos];
1363 baca51fa bellard
    if (++fdctrl->data_pos == fdctrl->data_len) {
1364 baca51fa bellard
        fdctrl->data_pos = 0;
1365 890fa6be bellard
        /* Switch from transfer mode to status mode
1366 8977f3c1 bellard
         * then from status mode to command mode
1367 8977f3c1 bellard
         */
1368 368df94d blueswir1
        if (fdctrl->msr & FD_MSR_NONDMA) {
1369 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1370 ed5fd2cc bellard
        } else {
1371 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1372 ed5fd2cc bellard
            fdctrl_reset_irq(fdctrl);
1373 ed5fd2cc bellard
        }
1374 8977f3c1 bellard
    }
1375 8977f3c1 bellard
    FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1376 8977f3c1 bellard
1377 8977f3c1 bellard
    return retval;
1378 8977f3c1 bellard
}
1379 8977f3c1 bellard
1380 c227f099 Anthony Liguori
static void fdctrl_format_sector (fdctrl_t *fdctrl)
1381 8977f3c1 bellard
{
1382 c227f099 Anthony Liguori
    fdrive_t *cur_drv;
1383 baca51fa bellard
    uint8_t kh, kt, ks;
1384 8977f3c1 bellard
1385 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1386 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1387 baca51fa bellard
    kt = fdctrl->fifo[6];
1388 baca51fa bellard
    kh = fdctrl->fifo[7];
1389 baca51fa bellard
    ks = fdctrl->fifo[8];
1390 baca51fa bellard
    FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1391 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1392 baca51fa bellard
                   _fd_sector(kh, kt, ks, cur_drv->last_sect));
1393 9fea808a blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1394 baca51fa bellard
    case 2:
1395 baca51fa bellard
        /* sect too big */
1396 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1397 baca51fa bellard
        fdctrl->fifo[3] = kt;
1398 baca51fa bellard
        fdctrl->fifo[4] = kh;
1399 baca51fa bellard
        fdctrl->fifo[5] = ks;
1400 baca51fa bellard
        return;
1401 baca51fa bellard
    case 3:
1402 baca51fa bellard
        /* track too big */
1403 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1404 baca51fa bellard
        fdctrl->fifo[3] = kt;
1405 baca51fa bellard
        fdctrl->fifo[4] = kh;
1406 baca51fa bellard
        fdctrl->fifo[5] = ks;
1407 baca51fa bellard
        return;
1408 baca51fa bellard
    case 4:
1409 baca51fa bellard
        /* No seek enabled */
1410 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1411 baca51fa bellard
        fdctrl->fifo[3] = kt;
1412 baca51fa bellard
        fdctrl->fifo[4] = kh;
1413 baca51fa bellard
        fdctrl->fifo[5] = ks;
1414 baca51fa bellard
        return;
1415 baca51fa bellard
    case 1:
1416 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1417 baca51fa bellard
        break;
1418 baca51fa bellard
    default:
1419 baca51fa bellard
        break;
1420 baca51fa bellard
    }
1421 baca51fa bellard
    memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1422 baca51fa bellard
    if (cur_drv->bs == NULL ||
1423 baca51fa bellard
        bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1424 37a4c539 ths
        FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1425 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1426 baca51fa bellard
    } else {
1427 4f431960 j_mayer
        if (cur_drv->sect == cur_drv->last_sect) {
1428 4f431960 j_mayer
            fdctrl->data_state &= ~FD_STATE_FORMAT;
1429 4f431960 j_mayer
            /* Last sector done */
1430 4f431960 j_mayer
            if (FD_DID_SEEK(fdctrl->data_state))
1431 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1432 4f431960 j_mayer
            else
1433 4f431960 j_mayer
                fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1434 4f431960 j_mayer
        } else {
1435 4f431960 j_mayer
            /* More to do */
1436 4f431960 j_mayer
            fdctrl->data_pos = 0;
1437 4f431960 j_mayer
            fdctrl->data_len = 4;
1438 4f431960 j_mayer
        }
1439 baca51fa bellard
    }
1440 baca51fa bellard
}
1441 baca51fa bellard
1442 c227f099 Anthony Liguori
static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1443 65cef780 blueswir1
{
1444 65cef780 blueswir1
    fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1445 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->lock << 4;
1446 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1447 65cef780 blueswir1
}
1448 65cef780 blueswir1
1449 c227f099 Anthony Liguori
static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1450 65cef780 blueswir1
{
1451 c227f099 Anthony Liguori
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1452 65cef780 blueswir1
1453 65cef780 blueswir1
    /* Drives position */
1454 65cef780 blueswir1
    fdctrl->fifo[0] = drv0(fdctrl)->track;
1455 65cef780 blueswir1
    fdctrl->fifo[1] = drv1(fdctrl)->track;
1456 78ae820c blueswir1
#if MAX_FD == 4
1457 78ae820c blueswir1
    fdctrl->fifo[2] = drv2(fdctrl)->track;
1458 78ae820c blueswir1
    fdctrl->fifo[3] = drv3(fdctrl)->track;
1459 78ae820c blueswir1
#else
1460 65cef780 blueswir1
    fdctrl->fifo[2] = 0;
1461 65cef780 blueswir1
    fdctrl->fifo[3] = 0;
1462 78ae820c blueswir1
#endif
1463 65cef780 blueswir1
    /* timers */
1464 65cef780 blueswir1
    fdctrl->fifo[4] = fdctrl->timer0;
1465 368df94d blueswir1
    fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1466 65cef780 blueswir1
    fdctrl->fifo[6] = cur_drv->last_sect;
1467 65cef780 blueswir1
    fdctrl->fifo[7] = (fdctrl->lock << 7) |
1468 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1469 65cef780 blueswir1
    fdctrl->fifo[8] = fdctrl->config;
1470 65cef780 blueswir1
    fdctrl->fifo[9] = fdctrl->precomp_trk;
1471 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 10, 0);
1472 65cef780 blueswir1
}
1473 65cef780 blueswir1
1474 c227f099 Anthony Liguori
static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1475 65cef780 blueswir1
{
1476 65cef780 blueswir1
    /* Controller's version */
1477 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->version;
1478 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1479 65cef780 blueswir1
}
1480 65cef780 blueswir1
1481 c227f099 Anthony Liguori
static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1482 65cef780 blueswir1
{
1483 65cef780 blueswir1
    fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1484 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1485 65cef780 blueswir1
}
1486 65cef780 blueswir1
1487 c227f099 Anthony Liguori
static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1488 65cef780 blueswir1
{
1489 c227f099 Anthony Liguori
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1490 65cef780 blueswir1
1491 65cef780 blueswir1
    /* Drives position */
1492 65cef780 blueswir1
    drv0(fdctrl)->track = fdctrl->fifo[3];
1493 65cef780 blueswir1
    drv1(fdctrl)->track = fdctrl->fifo[4];
1494 78ae820c blueswir1
#if MAX_FD == 4
1495 78ae820c blueswir1
    drv2(fdctrl)->track = fdctrl->fifo[5];
1496 78ae820c blueswir1
    drv3(fdctrl)->track = fdctrl->fifo[6];
1497 78ae820c blueswir1
#endif
1498 65cef780 blueswir1
    /* timers */
1499 65cef780 blueswir1
    fdctrl->timer0 = fdctrl->fifo[7];
1500 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[8];
1501 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[9];
1502 65cef780 blueswir1
    fdctrl->lock = fdctrl->fifo[10] >> 7;
1503 65cef780 blueswir1
    cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1504 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[11];
1505 65cef780 blueswir1
    fdctrl->precomp_trk = fdctrl->fifo[12];
1506 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[13];
1507 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1508 65cef780 blueswir1
}
1509 65cef780 blueswir1
1510 c227f099 Anthony Liguori
static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1511 65cef780 blueswir1
{
1512 c227f099 Anthony Liguori
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1513 65cef780 blueswir1
1514 65cef780 blueswir1
    fdctrl->fifo[0] = 0;
1515 65cef780 blueswir1
    fdctrl->fifo[1] = 0;
1516 65cef780 blueswir1
    /* Drives position */
1517 65cef780 blueswir1
    fdctrl->fifo[2] = drv0(fdctrl)->track;
1518 65cef780 blueswir1
    fdctrl->fifo[3] = drv1(fdctrl)->track;
1519 78ae820c blueswir1
#if MAX_FD == 4
1520 78ae820c blueswir1
    fdctrl->fifo[4] = drv2(fdctrl)->track;
1521 78ae820c blueswir1
    fdctrl->fifo[5] = drv3(fdctrl)->track;
1522 78ae820c blueswir1
#else
1523 65cef780 blueswir1
    fdctrl->fifo[4] = 0;
1524 65cef780 blueswir1
    fdctrl->fifo[5] = 0;
1525 78ae820c blueswir1
#endif
1526 65cef780 blueswir1
    /* timers */
1527 65cef780 blueswir1
    fdctrl->fifo[6] = fdctrl->timer0;
1528 65cef780 blueswir1
    fdctrl->fifo[7] = fdctrl->timer1;
1529 65cef780 blueswir1
    fdctrl->fifo[8] = cur_drv->last_sect;
1530 65cef780 blueswir1
    fdctrl->fifo[9] = (fdctrl->lock << 7) |
1531 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1532 65cef780 blueswir1
    fdctrl->fifo[10] = fdctrl->config;
1533 65cef780 blueswir1
    fdctrl->fifo[11] = fdctrl->precomp_trk;
1534 65cef780 blueswir1
    fdctrl->fifo[12] = fdctrl->pwrd;
1535 65cef780 blueswir1
    fdctrl->fifo[13] = 0;
1536 65cef780 blueswir1
    fdctrl->fifo[14] = 0;
1537 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 15, 1);
1538 65cef780 blueswir1
}
1539 65cef780 blueswir1
1540 c227f099 Anthony Liguori
static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1541 65cef780 blueswir1
{
1542 c227f099 Anthony Liguori
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1543 65cef780 blueswir1
1544 65cef780 blueswir1
    /* XXX: should set main status register to busy */
1545 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1546 65cef780 blueswir1
    qemu_mod_timer(fdctrl->result_timer,
1547 6ee093c9 Juan Quintela
                   qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
1548 65cef780 blueswir1
}
1549 65cef780 blueswir1
1550 c227f099 Anthony Liguori
static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1551 65cef780 blueswir1
{
1552 c227f099 Anthony Liguori
    fdrive_t *cur_drv;
1553 65cef780 blueswir1
1554 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1555 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1556 65cef780 blueswir1
    fdctrl->data_state |= FD_STATE_FORMAT;
1557 65cef780 blueswir1
    if (fdctrl->fifo[0] & 0x80)
1558 65cef780 blueswir1
        fdctrl->data_state |= FD_STATE_MULTI;
1559 65cef780 blueswir1
    else
1560 65cef780 blueswir1
        fdctrl->data_state &= ~FD_STATE_MULTI;
1561 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_SEEK;
1562 65cef780 blueswir1
    cur_drv->bps =
1563 65cef780 blueswir1
        fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1564 65cef780 blueswir1
#if 0
1565 65cef780 blueswir1
    cur_drv->last_sect =
1566 65cef780 blueswir1
        cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1567 65cef780 blueswir1
        fdctrl->fifo[3] / 2;
1568 65cef780 blueswir1
#else
1569 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[3];
1570 65cef780 blueswir1
#endif
1571 65cef780 blueswir1
    /* TODO: implement format using DMA expected by the Bochs BIOS
1572 65cef780 blueswir1
     * and Linux fdformat (read 3 bytes per sector via DMA and fill
1573 65cef780 blueswir1
     * the sector with the specified fill byte
1574 65cef780 blueswir1
     */
1575 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_FORMAT;
1576 65cef780 blueswir1
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1577 65cef780 blueswir1
}
1578 65cef780 blueswir1
1579 c227f099 Anthony Liguori
static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1580 65cef780 blueswir1
{
1581 65cef780 blueswir1
    fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1582 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1583 368df94d blueswir1
    if (fdctrl->fifo[2] & 1)
1584 368df94d blueswir1
        fdctrl->dor &= ~FD_DOR_DMAEN;
1585 368df94d blueswir1
    else
1586 368df94d blueswir1
        fdctrl->dor |= FD_DOR_DMAEN;
1587 65cef780 blueswir1
    /* No result back */
1588 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1589 65cef780 blueswir1
}
1590 65cef780 blueswir1
1591 c227f099 Anthony Liguori
static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1592 65cef780 blueswir1
{
1593 c227f099 Anthony Liguori
    fdrive_t *cur_drv;
1594 65cef780 blueswir1
1595 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1596 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1597 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1598 65cef780 blueswir1
    /* 1 Byte status back */
1599 65cef780 blueswir1
    fdctrl->fifo[0] = (cur_drv->ro << 6) |
1600 65cef780 blueswir1
        (cur_drv->track == 0 ? 0x10 : 0x00) |
1601 65cef780 blueswir1
        (cur_drv->head << 2) |
1602 cefec4f5 blueswir1
        GET_CUR_DRV(fdctrl) |
1603 65cef780 blueswir1
        0x28;
1604 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1605 65cef780 blueswir1
}
1606 65cef780 blueswir1
1607 c227f099 Anthony Liguori
static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1608 65cef780 blueswir1
{
1609 c227f099 Anthony Liguori
    fdrive_t *cur_drv;
1610 65cef780 blueswir1
1611 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1612 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1613 65cef780 blueswir1
    fd_recalibrate(cur_drv);
1614 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1615 65cef780 blueswir1
    /* Raise Interrupt */
1616 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1617 65cef780 blueswir1
}
1618 65cef780 blueswir1
1619 c227f099 Anthony Liguori
static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1620 65cef780 blueswir1
{
1621 c227f099 Anthony Liguori
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1622 65cef780 blueswir1
1623 f2d81b33 blueswir1
    if(fdctrl->reset_sensei > 0) {
1624 f2d81b33 blueswir1
        fdctrl->fifo[0] =
1625 f2d81b33 blueswir1
            FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1626 f2d81b33 blueswir1
        fdctrl->reset_sensei--;
1627 f2d81b33 blueswir1
    } else {
1628 f2d81b33 blueswir1
        /* XXX: status0 handling is broken for read/write
1629 f2d81b33 blueswir1
           commands, so we do this hack. It should be suppressed
1630 f2d81b33 blueswir1
           ASAP */
1631 f2d81b33 blueswir1
        fdctrl->fifo[0] =
1632 f2d81b33 blueswir1
            FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1633 f2d81b33 blueswir1
    }
1634 f2d81b33 blueswir1
1635 65cef780 blueswir1
    fdctrl->fifo[1] = cur_drv->track;
1636 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 2, 0);
1637 65cef780 blueswir1
    fdctrl_reset_irq(fdctrl);
1638 77370520 blueswir1
    fdctrl->status0 = FD_SR0_RDYCHG;
1639 65cef780 blueswir1
}
1640 65cef780 blueswir1
1641 c227f099 Anthony Liguori
static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1642 65cef780 blueswir1
{
1643 c227f099 Anthony Liguori
    fdrive_t *cur_drv;
1644 65cef780 blueswir1
1645 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1646 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1647 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1648 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->max_track) {
1649 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1650 65cef780 blueswir1
    } else {
1651 65cef780 blueswir1
        cur_drv->track = fdctrl->fifo[2];
1652 65cef780 blueswir1
        /* Raise Interrupt */
1653 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1654 65cef780 blueswir1
    }
1655 65cef780 blueswir1
}
1656 65cef780 blueswir1
1657 c227f099 Anthony Liguori
static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1658 65cef780 blueswir1
{
1659 c227f099 Anthony Liguori
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1660 65cef780 blueswir1
1661 65cef780 blueswir1
    if (fdctrl->fifo[1] & 0x80)
1662 65cef780 blueswir1
        cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1663 65cef780 blueswir1
    /* No result back */
1664 1c346df2 blueswir1
    fdctrl_reset_fifo(fdctrl);
1665 65cef780 blueswir1
}
1666 65cef780 blueswir1
1667 c227f099 Anthony Liguori
static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1668 65cef780 blueswir1
{
1669 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[2];
1670 65cef780 blueswir1
    fdctrl->precomp_trk =  fdctrl->fifo[3];
1671 65cef780 blueswir1
    /* No result back */
1672 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1673 65cef780 blueswir1
}
1674 65cef780 blueswir1
1675 c227f099 Anthony Liguori
static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1676 65cef780 blueswir1
{
1677 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[1];
1678 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->fifo[1];
1679 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1680 65cef780 blueswir1
}
1681 65cef780 blueswir1
1682 c227f099 Anthony Liguori
static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1683 65cef780 blueswir1
{
1684 65cef780 blueswir1
    /* No result back */
1685 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1686 65cef780 blueswir1
}
1687 65cef780 blueswir1
1688 c227f099 Anthony Liguori
static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1689 65cef780 blueswir1
{
1690 c227f099 Anthony Liguori
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1691 65cef780 blueswir1
1692 65cef780 blueswir1
    if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1693 65cef780 blueswir1
        /* Command parameters done */
1694 65cef780 blueswir1
        if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1695 65cef780 blueswir1
            fdctrl->fifo[0] = fdctrl->fifo[1];
1696 65cef780 blueswir1
            fdctrl->fifo[2] = 0;
1697 65cef780 blueswir1
            fdctrl->fifo[3] = 0;
1698 65cef780 blueswir1
            fdctrl_set_fifo(fdctrl, 4, 1);
1699 65cef780 blueswir1
        } else {
1700 65cef780 blueswir1
            fdctrl_reset_fifo(fdctrl);
1701 65cef780 blueswir1
        }
1702 65cef780 blueswir1
    } else if (fdctrl->data_len > 7) {
1703 65cef780 blueswir1
        /* ERROR */
1704 65cef780 blueswir1
        fdctrl->fifo[0] = 0x80 |
1705 cefec4f5 blueswir1
            (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1706 65cef780 blueswir1
        fdctrl_set_fifo(fdctrl, 1, 1);
1707 65cef780 blueswir1
    }
1708 65cef780 blueswir1
}
1709 65cef780 blueswir1
1710 c227f099 Anthony Liguori
static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1711 65cef780 blueswir1
{
1712 c227f099 Anthony Liguori
    fdrive_t *cur_drv;
1713 65cef780 blueswir1
1714 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1715 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1716 65cef780 blueswir1
    if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1717 65cef780 blueswir1
        cur_drv->track = cur_drv->max_track - 1;
1718 65cef780 blueswir1
    } else {
1719 65cef780 blueswir1
        cur_drv->track += fdctrl->fifo[2];
1720 65cef780 blueswir1
    }
1721 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1722 77370520 blueswir1
    /* Raise Interrupt */
1723 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1724 65cef780 blueswir1
}
1725 65cef780 blueswir1
1726 c227f099 Anthony Liguori
static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1727 65cef780 blueswir1
{
1728 c227f099 Anthony Liguori
    fdrive_t *cur_drv;
1729 65cef780 blueswir1
1730 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1731 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1732 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->track) {
1733 65cef780 blueswir1
        cur_drv->track = 0;
1734 65cef780 blueswir1
    } else {
1735 65cef780 blueswir1
        cur_drv->track -= fdctrl->fifo[2];
1736 65cef780 blueswir1
    }
1737 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1738 65cef780 blueswir1
    /* Raise Interrupt */
1739 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1740 65cef780 blueswir1
}
1741 65cef780 blueswir1
1742 678803ab blueswir1
static const struct {
1743 678803ab blueswir1
    uint8_t value;
1744 678803ab blueswir1
    uint8_t mask;
1745 678803ab blueswir1
    const char* name;
1746 678803ab blueswir1
    int parameters;
1747 c227f099 Anthony Liguori
    void (*handler)(fdctrl_t *fdctrl, int direction);
1748 678803ab blueswir1
    int direction;
1749 678803ab blueswir1
} handlers[] = {
1750 678803ab blueswir1
    { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1751 678803ab blueswir1
    { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1752 678803ab blueswir1
    { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1753 678803ab blueswir1
    { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1754 678803ab blueswir1
    { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1755 678803ab blueswir1
    { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1756 678803ab blueswir1
    { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1757 678803ab blueswir1
    { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1758 678803ab blueswir1
    { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1759 678803ab blueswir1
    { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1760 678803ab blueswir1
    { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1761 678803ab blueswir1
    { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1762 678803ab blueswir1
    { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1763 678803ab blueswir1
    { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1764 678803ab blueswir1
    { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1765 678803ab blueswir1
    { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1766 678803ab blueswir1
    { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1767 678803ab blueswir1
    { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1768 678803ab blueswir1
    { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1769 678803ab blueswir1
    { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1770 678803ab blueswir1
    { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1771 678803ab blueswir1
    { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1772 678803ab blueswir1
    { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1773 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1774 678803ab blueswir1
    { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1775 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1776 678803ab blueswir1
    { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1777 678803ab blueswir1
    { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1778 678803ab blueswir1
    { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1779 678803ab blueswir1
    { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1780 678803ab blueswir1
    { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1781 678803ab blueswir1
    { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1782 678803ab blueswir1
};
1783 678803ab blueswir1
/* Associate command to an index in the 'handlers' array */
1784 678803ab blueswir1
static uint8_t command_to_handler[256];
1785 678803ab blueswir1
1786 c227f099 Anthony Liguori
static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1787 baca51fa bellard
{
1788 c227f099 Anthony Liguori
    fdrive_t *cur_drv;
1789 65cef780 blueswir1
    int pos;
1790 baca51fa bellard
1791 8977f3c1 bellard
    /* Reset mode */
1792 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
1793 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1794 8977f3c1 bellard
        return;
1795 8977f3c1 bellard
    }
1796 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1797 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for writing\n");
1798 8977f3c1 bellard
        return;
1799 8977f3c1 bellard
    }
1800 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1801 8977f3c1 bellard
    /* Is it write command time ? */
1802 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1803 8977f3c1 bellard
        /* FIFO data write */
1804 b3bc1540 blueswir1
        pos = fdctrl->data_pos++;
1805 b3bc1540 blueswir1
        pos %= FD_SECTOR_LEN;
1806 b3bc1540 blueswir1
        fdctrl->fifo[pos] = value;
1807 b3bc1540 blueswir1
        if (pos == FD_SECTOR_LEN - 1 ||
1808 baca51fa bellard
            fdctrl->data_pos == fdctrl->data_len) {
1809 77370520 blueswir1
            cur_drv = get_cur_drv(fdctrl);
1810 77370520 blueswir1
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1811 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1812 77370520 blueswir1
                return;
1813 77370520 blueswir1
            }
1814 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1815 746d6de7 blueswir1
                FLOPPY_DPRINTF("error seeking to next sector %d\n",
1816 746d6de7 blueswir1
                               fd_sector(cur_drv));
1817 746d6de7 blueswir1
                return;
1818 746d6de7 blueswir1
            }
1819 8977f3c1 bellard
        }
1820 890fa6be bellard
        /* Switch from transfer mode to status mode
1821 8977f3c1 bellard
         * then from status mode to command mode
1822 8977f3c1 bellard
         */
1823 b9b3d225 blueswir1
        if (fdctrl->data_pos == fdctrl->data_len)
1824 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1825 8977f3c1 bellard
        return;
1826 8977f3c1 bellard
    }
1827 baca51fa bellard
    if (fdctrl->data_pos == 0) {
1828 8977f3c1 bellard
        /* Command */
1829 678803ab blueswir1
        pos = command_to_handler[value & 0xff];
1830 678803ab blueswir1
        FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1831 678803ab blueswir1
        fdctrl->data_len = handlers[pos].parameters + 1;
1832 8977f3c1 bellard
    }
1833 678803ab blueswir1
1834 baca51fa bellard
    FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1835 77370520 blueswir1
    fdctrl->fifo[fdctrl->data_pos++] = value;
1836 77370520 blueswir1
    if (fdctrl->data_pos == fdctrl->data_len) {
1837 8977f3c1 bellard
        /* We now have all parameters
1838 8977f3c1 bellard
         * and will be able to treat the command
1839 8977f3c1 bellard
         */
1840 4f431960 j_mayer
        if (fdctrl->data_state & FD_STATE_FORMAT) {
1841 4f431960 j_mayer
            fdctrl_format_sector(fdctrl);
1842 8977f3c1 bellard
            return;
1843 8977f3c1 bellard
        }
1844 65cef780 blueswir1
1845 678803ab blueswir1
        pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1846 678803ab blueswir1
        FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1847 678803ab blueswir1
        (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1848 8977f3c1 bellard
    }
1849 8977f3c1 bellard
}
1850 ed5fd2cc bellard
1851 ed5fd2cc bellard
static void fdctrl_result_timer(void *opaque)
1852 ed5fd2cc bellard
{
1853 c227f099 Anthony Liguori
    fdctrl_t *fdctrl = opaque;
1854 c227f099 Anthony Liguori
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1855 4f431960 j_mayer
1856 b7ffa3b1 ths
    /* Pretend we are spinning.
1857 b7ffa3b1 ths
     * This is needed for Coherent, which uses READ ID to check for
1858 b7ffa3b1 ths
     * sector interleaving.
1859 b7ffa3b1 ths
     */
1860 b7ffa3b1 ths
    if (cur_drv->last_sect != 0) {
1861 b7ffa3b1 ths
        cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1862 b7ffa3b1 ths
    }
1863 ed5fd2cc bellard
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1864 ed5fd2cc bellard
}
1865 678803ab blueswir1
1866 678803ab blueswir1
/* Init functions */
1867 fd8014e1 Gerd Hoffmann
static void fdctrl_connect_drives(fdctrl_t *fdctrl)
1868 678803ab blueswir1
{
1869 12a71a02 Blue Swirl
    unsigned int i;
1870 678803ab blueswir1
1871 678803ab blueswir1
    for (i = 0; i < MAX_FD; i++) {
1872 fd8014e1 Gerd Hoffmann
        fd_init(&fdctrl->drives[i]);
1873 678803ab blueswir1
        fd_revalidate(&fdctrl->drives[i]);
1874 678803ab blueswir1
    }
1875 678803ab blueswir1
}
1876 678803ab blueswir1
1877 fd8014e1 Gerd Hoffmann
fdctrl_t *fdctrl_init_isa(DriveInfo **fds)
1878 678803ab blueswir1
{
1879 2091ba23 Gerd Hoffmann
    ISADevice *dev;
1880 678803ab blueswir1
1881 fd8014e1 Gerd Hoffmann
    dev = isa_create("isa-fdc");
1882 fd8014e1 Gerd Hoffmann
    qdev_prop_set_drive(&dev->qdev, "driveA", fds[0]);
1883 fd8014e1 Gerd Hoffmann
    qdev_prop_set_drive(&dev->qdev, "driveB", fds[1]);
1884 5c17ca25 Markus Armbruster
    if (qdev_init(&dev->qdev) < 0)
1885 fd8014e1 Gerd Hoffmann
        return NULL;
1886 99244fa1 Gerd Hoffmann
    return &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state);
1887 2091ba23 Gerd Hoffmann
}
1888 2091ba23 Gerd Hoffmann
1889 c227f099 Anthony Liguori
fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1890 c227f099 Anthony Liguori
                             target_phys_addr_t mmio_base,
1891 fd8014e1 Gerd Hoffmann
                             DriveInfo **fds)
1892 2091ba23 Gerd Hoffmann
{
1893 c227f099 Anthony Liguori
    fdctrl_t *fdctrl;
1894 2091ba23 Gerd Hoffmann
    DeviceState *dev;
1895 c227f099 Anthony Liguori
    fdctrl_sysbus_t *sys;
1896 2091ba23 Gerd Hoffmann
1897 2091ba23 Gerd Hoffmann
    dev = qdev_create(NULL, "sysbus-fdc");
1898 99244fa1 Gerd Hoffmann
    sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
1899 99244fa1 Gerd Hoffmann
    fdctrl = &sys->state;
1900 99244fa1 Gerd Hoffmann
    fdctrl->dma_chann = dma_chann; /* FIXME */
1901 fd8014e1 Gerd Hoffmann
    qdev_prop_set_drive(dev, "driveA", fds[0]);
1902 fd8014e1 Gerd Hoffmann
    qdev_prop_set_drive(dev, "driveB", fds[1]);
1903 e23a1b33 Markus Armbruster
    qdev_init_nofail(dev);
1904 2091ba23 Gerd Hoffmann
    sysbus_connect_irq(&sys->busdev, 0, irq);
1905 2091ba23 Gerd Hoffmann
    sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1906 8baf73ad Gerd Hoffmann
1907 678803ab blueswir1
    return fdctrl;
1908 678803ab blueswir1
}
1909 678803ab blueswir1
1910 c227f099 Anthony Liguori
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1911 fd8014e1 Gerd Hoffmann
                             DriveInfo **fds, qemu_irq *fdc_tc)
1912 678803ab blueswir1
{
1913 f64ab228 Blue Swirl
    DeviceState *dev;
1914 c227f099 Anthony Liguori
    fdctrl_sysbus_t *sys;
1915 c227f099 Anthony Liguori
    fdctrl_t *fdctrl;
1916 678803ab blueswir1
1917 12a71a02 Blue Swirl
    dev = qdev_create(NULL, "SUNW,fdtwo");
1918 fd8014e1 Gerd Hoffmann
    qdev_prop_set_drive(dev, "drive", fds[0]);
1919 e23a1b33 Markus Armbruster
    qdev_init_nofail(dev);
1920 c227f099 Anthony Liguori
    sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
1921 8baf73ad Gerd Hoffmann
    fdctrl = &sys->state;
1922 8baf73ad Gerd Hoffmann
    sysbus_connect_irq(&sys->busdev, 0, irq);
1923 8baf73ad Gerd Hoffmann
    sysbus_mmio_map(&sys->busdev, 0, io_base);
1924 f64ab228 Blue Swirl
    *fdc_tc = qdev_get_gpio_in(dev, 0);
1925 f64ab228 Blue Swirl
1926 678803ab blueswir1
    return fdctrl;
1927 678803ab blueswir1
}
1928 f64ab228 Blue Swirl
1929 c227f099 Anthony Liguori
static int fdctrl_init_common(fdctrl_t *fdctrl)
1930 f64ab228 Blue Swirl
{
1931 12a71a02 Blue Swirl
    int i, j;
1932 12a71a02 Blue Swirl
    static int command_tables_inited = 0;
1933 f64ab228 Blue Swirl
1934 12a71a02 Blue Swirl
    /* Fill 'command_to_handler' lookup table */
1935 12a71a02 Blue Swirl
    if (!command_tables_inited) {
1936 12a71a02 Blue Swirl
        command_tables_inited = 1;
1937 12a71a02 Blue Swirl
        for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1938 12a71a02 Blue Swirl
            for (j = 0; j < sizeof(command_to_handler); j++) {
1939 12a71a02 Blue Swirl
                if ((j & handlers[i].mask) == handlers[i].value) {
1940 12a71a02 Blue Swirl
                    command_to_handler[j] = i;
1941 12a71a02 Blue Swirl
                }
1942 12a71a02 Blue Swirl
            }
1943 12a71a02 Blue Swirl
        }
1944 12a71a02 Blue Swirl
    }
1945 12a71a02 Blue Swirl
1946 12a71a02 Blue Swirl
    FLOPPY_DPRINTF("init controller\n");
1947 12a71a02 Blue Swirl
    fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1948 d7a6c270 Juan Quintela
    fdctrl->fifo_size = 512;
1949 12a71a02 Blue Swirl
    fdctrl->result_timer = qemu_new_timer(vm_clock,
1950 12a71a02 Blue Swirl
                                          fdctrl_result_timer, fdctrl);
1951 12a71a02 Blue Swirl
1952 12a71a02 Blue Swirl
    fdctrl->version = 0x90; /* Intel 82078 controller */
1953 12a71a02 Blue Swirl
    fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1954 d7a6c270 Juan Quintela
    fdctrl->num_floppies = MAX_FD;
1955 12a71a02 Blue Swirl
1956 99244fa1 Gerd Hoffmann
    if (fdctrl->dma_chann != -1)
1957 99244fa1 Gerd Hoffmann
        DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1958 99244fa1 Gerd Hoffmann
    fdctrl_connect_drives(fdctrl);
1959 99244fa1 Gerd Hoffmann
1960 81a322d4 Gerd Hoffmann
    return 0;
1961 f64ab228 Blue Swirl
}
1962 f64ab228 Blue Swirl
1963 81a322d4 Gerd Hoffmann
static int isabus_fdc_init1(ISADevice *dev)
1964 8baf73ad Gerd Hoffmann
{
1965 c227f099 Anthony Liguori
    fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev);
1966 c227f099 Anthony Liguori
    fdctrl_t *fdctrl = &isa->state;
1967 86c86157 Gerd Hoffmann
    int iobase = 0x3f0;
1968 2e15e23b Gerd Hoffmann
    int isairq = 6;
1969 99244fa1 Gerd Hoffmann
    int dma_chann = 2;
1970 2be37833 Blue Swirl
    int ret;
1971 8baf73ad Gerd Hoffmann
1972 86c86157 Gerd Hoffmann
    register_ioport_read(iobase + 0x01, 5, 1,
1973 8baf73ad Gerd Hoffmann
                         &fdctrl_read_port, fdctrl);
1974 86c86157 Gerd Hoffmann
    register_ioport_read(iobase + 0x07, 1, 1,
1975 8baf73ad Gerd Hoffmann
                         &fdctrl_read_port, fdctrl);
1976 86c86157 Gerd Hoffmann
    register_ioport_write(iobase + 0x01, 5, 1,
1977 8baf73ad Gerd Hoffmann
                          &fdctrl_write_port, fdctrl);
1978 86c86157 Gerd Hoffmann
    register_ioport_write(iobase + 0x07, 1, 1,
1979 8baf73ad Gerd Hoffmann
                          &fdctrl_write_port, fdctrl);
1980 2e15e23b Gerd Hoffmann
    isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1981 99244fa1 Gerd Hoffmann
    fdctrl->dma_chann = dma_chann;
1982 8baf73ad Gerd Hoffmann
1983 2be37833 Blue Swirl
    ret = fdctrl_init_common(fdctrl);
1984 2be37833 Blue Swirl
1985 2be37833 Blue Swirl
    return ret;
1986 8baf73ad Gerd Hoffmann
}
1987 8baf73ad Gerd Hoffmann
1988 81a322d4 Gerd Hoffmann
static int sysbus_fdc_init1(SysBusDevice *dev)
1989 12a71a02 Blue Swirl
{
1990 2be37833 Blue Swirl
    fdctrl_sysbus_t *sys = DO_UPCAST(fdctrl_sysbus_t, busdev, dev);
1991 2be37833 Blue Swirl
    fdctrl_t *fdctrl = &sys->state;
1992 12a71a02 Blue Swirl
    int io;
1993 2be37833 Blue Swirl
    int ret;
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    io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
1996 8baf73ad Gerd Hoffmann
    sysbus_init_mmio(dev, 0x08, io);
1997 8baf73ad Gerd Hoffmann
    sysbus_init_irq(dev, &fdctrl->irq);
1998 8baf73ad Gerd Hoffmann
    qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1999 99244fa1 Gerd Hoffmann
    fdctrl->dma_chann = -1;
2000 8baf73ad Gerd Hoffmann
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    ret = fdctrl_init_common(fdctrl);
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    return ret;
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}
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2006 81a322d4 Gerd Hoffmann
static int sun4m_fdc_init1(SysBusDevice *dev)
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{
2008 c227f099 Anthony Liguori
    fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
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    int io;
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2011 12a71a02 Blue Swirl
    io = cpu_register_io_memory(fdctrl_mem_read_strict,
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                                fdctrl_mem_write_strict, fdctrl);
2013 8baf73ad Gerd Hoffmann
    sysbus_init_mmio(dev, 0x08, io);
2014 8baf73ad Gerd Hoffmann
    sysbus_init_irq(dev, &fdctrl->irq);
2015 8baf73ad Gerd Hoffmann
    qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2016 8baf73ad Gerd Hoffmann
2017 8baf73ad Gerd Hoffmann
    fdctrl->sun4m = 1;
2018 81a322d4 Gerd Hoffmann
    return fdctrl_init_common(fdctrl);
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}
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2021 8baf73ad Gerd Hoffmann
static ISADeviceInfo isa_fdc_info = {
2022 8baf73ad Gerd Hoffmann
    .init = isabus_fdc_init1,
2023 8baf73ad Gerd Hoffmann
    .qdev.name  = "isa-fdc",
2024 c227f099 Anthony Liguori
    .qdev.size  = sizeof(fdctrl_isabus_t),
2025 39a51dfd Markus Armbruster
    .qdev.no_user = 1,
2026 2966b390 Juan Quintela
    .qdev.vmsd  = &vmstate_fdc_isa,
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    .qdev.reset = fdctrl_external_reset_isa,
2028 fd8014e1 Gerd Hoffmann
    .qdev.props = (Property[]) {
2029 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_DRIVE("driveA", fdctrl_isabus_t, state.drives[0].dinfo),
2030 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_DRIVE("driveB", fdctrl_isabus_t, state.drives[1].dinfo),
2031 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_END_OF_LIST(),
2032 fd8014e1 Gerd Hoffmann
    },
2033 8baf73ad Gerd Hoffmann
};
2034 8baf73ad Gerd Hoffmann
2035 8baf73ad Gerd Hoffmann
static SysBusDeviceInfo sysbus_fdc_info = {
2036 8baf73ad Gerd Hoffmann
    .init = sysbus_fdc_init1,
2037 8baf73ad Gerd Hoffmann
    .qdev.name  = "sysbus-fdc",
2038 c227f099 Anthony Liguori
    .qdev.size  = sizeof(fdctrl_sysbus_t),
2039 2966b390 Juan Quintela
    .qdev.vmsd  = &vmstate_fdc_sysbus,
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    .qdev.reset = fdctrl_external_reset_sysbus,
2041 fd8014e1 Gerd Hoffmann
    .qdev.props = (Property[]) {
2042 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_DRIVE("driveA", fdctrl_sysbus_t, state.drives[0].dinfo),
2043 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_DRIVE("driveB", fdctrl_sysbus_t, state.drives[1].dinfo),
2044 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_END_OF_LIST(),
2045 fd8014e1 Gerd Hoffmann
    },
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};
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static SysBusDeviceInfo sun4m_fdc_info = {
2049 12a71a02 Blue Swirl
    .init = sun4m_fdc_init1,
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    .qdev.name  = "SUNW,fdtwo",
2051 c227f099 Anthony Liguori
    .qdev.size  = sizeof(fdctrl_sysbus_t),
2052 2966b390 Juan Quintela
    .qdev.vmsd  = &vmstate_fdc_sysbus,
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    .qdev.reset = fdctrl_external_reset_sysbus,
2054 fd8014e1 Gerd Hoffmann
    .qdev.props = (Property[]) {
2055 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_DRIVE("drive", fdctrl_sysbus_t, state.drives[0].dinfo),
2056 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_END_OF_LIST(),
2057 fd8014e1 Gerd Hoffmann
    },
2058 f64ab228 Blue Swirl
};
2059 f64ab228 Blue Swirl
2060 f64ab228 Blue Swirl
static void fdc_register_devices(void)
2061 f64ab228 Blue Swirl
{
2062 8baf73ad Gerd Hoffmann
    isa_qdev_register(&isa_fdc_info);
2063 8baf73ad Gerd Hoffmann
    sysbus_register_withprop(&sysbus_fdc_info);
2064 12a71a02 Blue Swirl
    sysbus_register_withprop(&sun4m_fdc_info);
2065 f64ab228 Blue Swirl
}
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2067 f64ab228 Blue Swirl
device_init(fdc_register_devices)