root / hw / sh_pci.c @ 42ee76fe
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1 | 1e5459a3 | balrog | /*
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2 | 1e5459a3 | balrog | * SuperH on-chip PCIC emulation.
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3 | 1e5459a3 | balrog | *
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4 | 1e5459a3 | balrog | * Copyright (c) 2008 Takashi YOSHII
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5 | 1e5459a3 | balrog | *
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6 | 1e5459a3 | balrog | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 1e5459a3 | balrog | * of this software and associated documentation files (the "Software"), to deal
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8 | 1e5459a3 | balrog | * in the Software without restriction, including without limitation the rights
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9 | 1e5459a3 | balrog | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 1e5459a3 | balrog | * copies of the Software, and to permit persons to whom the Software is
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11 | 1e5459a3 | balrog | * furnished to do so, subject to the following conditions:
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12 | 1e5459a3 | balrog | *
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13 | 1e5459a3 | balrog | * The above copyright notice and this permission notice shall be included in
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14 | 1e5459a3 | balrog | * all copies or substantial portions of the Software.
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15 | 1e5459a3 | balrog | *
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16 | 1e5459a3 | balrog | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 1e5459a3 | balrog | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 1e5459a3 | balrog | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 1e5459a3 | balrog | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 1e5459a3 | balrog | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 1e5459a3 | balrog | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 1e5459a3 | balrog | * THE SOFTWARE.
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23 | 1e5459a3 | balrog | */
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24 | 1e5459a3 | balrog | #include "hw.h" |
25 | 1e5459a3 | balrog | #include "sh.h" |
26 | 1e5459a3 | balrog | #include "pci.h" |
27 | b6243d99 | Isaku Yamahata | #include "pci_host.h" |
28 | 18e08a55 | Michael S. Tsirkin | #include "sh_pci.h" |
29 | 1e5459a3 | balrog | #include "bswap.h" |
30 | 1e5459a3 | balrog | |
31 | 1e5459a3 | balrog | typedef struct { |
32 | 1e5459a3 | balrog | PCIBus *bus; |
33 | 1e5459a3 | balrog | PCIDevice *dev; |
34 | 1e5459a3 | balrog | uint32_t par; |
35 | 1e5459a3 | balrog | uint32_t mbr; |
36 | 1e5459a3 | balrog | uint32_t iobr; |
37 | 1e5459a3 | balrog | } SHPCIC; |
38 | 1e5459a3 | balrog | |
39 | c227f099 | Anthony Liguori | static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) |
40 | 1e5459a3 | balrog | { |
41 | 1e5459a3 | balrog | SHPCIC *pcic = p; |
42 | 1e5459a3 | balrog | switch(addr) {
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43 | 1e5459a3 | balrog | case 0 ... 0xfc: |
44 | 1e5459a3 | balrog | cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val); |
45 | 1e5459a3 | balrog | break;
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46 | 1e5459a3 | balrog | case 0x1c0: |
47 | 1e5459a3 | balrog | pcic->par = val; |
48 | 1e5459a3 | balrog | break;
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49 | 1e5459a3 | balrog | case 0x1c4: |
50 | 1e5459a3 | balrog | pcic->mbr = val; |
51 | 1e5459a3 | balrog | break;
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52 | 1e5459a3 | balrog | case 0x1c8: |
53 | 1e5459a3 | balrog | pcic->iobr = val; |
54 | 1e5459a3 | balrog | break;
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55 | 1e5459a3 | balrog | case 0x220: |
56 | 1e5459a3 | balrog | pci_data_write(pcic->bus, pcic->par, val, 4);
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57 | 1e5459a3 | balrog | break;
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58 | 1e5459a3 | balrog | } |
59 | 1e5459a3 | balrog | } |
60 | 1e5459a3 | balrog | |
61 | c227f099 | Anthony Liguori | static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) |
62 | 1e5459a3 | balrog | { |
63 | 1e5459a3 | balrog | SHPCIC *pcic = p; |
64 | 1e5459a3 | balrog | switch(addr) {
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65 | 1e5459a3 | balrog | case 0 ... 0xfc: |
66 | 1e5459a3 | balrog | return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
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67 | 1e5459a3 | balrog | case 0x1c0: |
68 | 1e5459a3 | balrog | return pcic->par;
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69 | 1e5459a3 | balrog | case 0x220: |
70 | 1e5459a3 | balrog | return pci_data_read(pcic->bus, pcic->par, 4); |
71 | 1e5459a3 | balrog | } |
72 | 1e5459a3 | balrog | return 0; |
73 | 1e5459a3 | balrog | } |
74 | 1e5459a3 | balrog | |
75 | c227f099 | Anthony Liguori | static void sh_pci_data_write (SHPCIC *pcic, target_phys_addr_t addr, |
76 | 1e5459a3 | balrog | uint32_t val, int size)
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77 | 1e5459a3 | balrog | { |
78 | d0ef528a | balrog | pci_data_write(pcic->bus, addr + pcic->mbr, val, size); |
79 | 1e5459a3 | balrog | } |
80 | 1e5459a3 | balrog | |
81 | c227f099 | Anthony Liguori | static uint32_t sh_pci_mem_read (SHPCIC *pcic, target_phys_addr_t addr,
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82 | 1e5459a3 | balrog | int size)
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83 | 1e5459a3 | balrog | { |
84 | d0ef528a | balrog | return pci_data_read(pcic->bus, addr + pcic->mbr, size);
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85 | 1e5459a3 | balrog | } |
86 | 1e5459a3 | balrog | |
87 | c227f099 | Anthony Liguori | static void sh_pci_writeb (void *p, target_phys_addr_t addr, uint32_t val) |
88 | 1e5459a3 | balrog | { |
89 | 1e5459a3 | balrog | sh_pci_data_write(p, addr, val, 1);
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90 | 1e5459a3 | balrog | } |
91 | 1e5459a3 | balrog | |
92 | c227f099 | Anthony Liguori | static void sh_pci_writew (void *p, target_phys_addr_t addr, uint32_t val) |
93 | 1e5459a3 | balrog | { |
94 | 1e5459a3 | balrog | sh_pci_data_write(p, addr, val, 2);
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95 | 1e5459a3 | balrog | } |
96 | 1e5459a3 | balrog | |
97 | c227f099 | Anthony Liguori | static void sh_pci_writel (void *p, target_phys_addr_t addr, uint32_t val) |
98 | 1e5459a3 | balrog | { |
99 | 1e5459a3 | balrog | sh_pci_data_write(p, addr, val, 4);
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100 | 1e5459a3 | balrog | } |
101 | 1e5459a3 | balrog | |
102 | c227f099 | Anthony Liguori | static uint32_t sh_pci_readb (void *p, target_phys_addr_t addr) |
103 | 1e5459a3 | balrog | { |
104 | 1e5459a3 | balrog | return sh_pci_mem_read(p, addr, 1); |
105 | 1e5459a3 | balrog | } |
106 | 1e5459a3 | balrog | |
107 | c227f099 | Anthony Liguori | static uint32_t sh_pci_readw (void *p, target_phys_addr_t addr) |
108 | 1e5459a3 | balrog | { |
109 | 1e5459a3 | balrog | return sh_pci_mem_read(p, addr, 2); |
110 | 1e5459a3 | balrog | } |
111 | 1e5459a3 | balrog | |
112 | c227f099 | Anthony Liguori | static uint32_t sh_pci_readl (void *p, target_phys_addr_t addr) |
113 | 1e5459a3 | balrog | { |
114 | 1e5459a3 | balrog | return sh_pci_mem_read(p, addr, 4); |
115 | 1e5459a3 | balrog | } |
116 | 1e5459a3 | balrog | |
117 | c227f099 | Anthony Liguori | static int sh_pci_addr2port(SHPCIC *pcic, target_phys_addr_t addr) |
118 | 1e5459a3 | balrog | { |
119 | d0ef528a | balrog | return addr + pcic->iobr;
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120 | 1e5459a3 | balrog | } |
121 | 1e5459a3 | balrog | |
122 | c227f099 | Anthony Liguori | static void sh_pci_outb (void *p, target_phys_addr_t addr, uint32_t val) |
123 | 1e5459a3 | balrog | { |
124 | afcea8cb | Blue Swirl | cpu_outb(sh_pci_addr2port(p, addr), val); |
125 | 1e5459a3 | balrog | } |
126 | 1e5459a3 | balrog | |
127 | c227f099 | Anthony Liguori | static void sh_pci_outw (void *p, target_phys_addr_t addr, uint32_t val) |
128 | 1e5459a3 | balrog | { |
129 | afcea8cb | Blue Swirl | cpu_outw(sh_pci_addr2port(p, addr), val); |
130 | 1e5459a3 | balrog | } |
131 | 1e5459a3 | balrog | |
132 | c227f099 | Anthony Liguori | static void sh_pci_outl (void *p, target_phys_addr_t addr, uint32_t val) |
133 | 1e5459a3 | balrog | { |
134 | afcea8cb | Blue Swirl | cpu_outl(sh_pci_addr2port(p, addr), val); |
135 | 1e5459a3 | balrog | } |
136 | 1e5459a3 | balrog | |
137 | c227f099 | Anthony Liguori | static uint32_t sh_pci_inb (void *p, target_phys_addr_t addr) |
138 | 1e5459a3 | balrog | { |
139 | afcea8cb | Blue Swirl | return cpu_inb(sh_pci_addr2port(p, addr));
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140 | 1e5459a3 | balrog | } |
141 | 1e5459a3 | balrog | |
142 | c227f099 | Anthony Liguori | static uint32_t sh_pci_inw (void *p, target_phys_addr_t addr) |
143 | 1e5459a3 | balrog | { |
144 | afcea8cb | Blue Swirl | return cpu_inw(sh_pci_addr2port(p, addr));
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145 | 1e5459a3 | balrog | } |
146 | 1e5459a3 | balrog | |
147 | c227f099 | Anthony Liguori | static uint32_t sh_pci_inl (void *p, target_phys_addr_t addr) |
148 | 1e5459a3 | balrog | { |
149 | afcea8cb | Blue Swirl | return cpu_inl(sh_pci_addr2port(p, addr));
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150 | 1e5459a3 | balrog | } |
151 | 1e5459a3 | balrog | |
152 | 1e5459a3 | balrog | typedef struct { |
153 | d60efc6b | Blue Swirl | CPUReadMemoryFunc * const r[3]; |
154 | d60efc6b | Blue Swirl | CPUWriteMemoryFunc * const w[3]; |
155 | 1e5459a3 | balrog | } MemOp; |
156 | 1e5459a3 | balrog | |
157 | 1e5459a3 | balrog | static MemOp sh_pci_reg = {
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158 | 1e5459a3 | balrog | { NULL, NULL, sh_pci_reg_read }, |
159 | 1e5459a3 | balrog | { NULL, NULL, sh_pci_reg_write }, |
160 | 1e5459a3 | balrog | }; |
161 | 1e5459a3 | balrog | |
162 | 1e5459a3 | balrog | static MemOp sh_pci_mem = {
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163 | 1e5459a3 | balrog | { sh_pci_readb, sh_pci_readw, sh_pci_readl }, |
164 | 1e5459a3 | balrog | { sh_pci_writeb, sh_pci_writew, sh_pci_writel }, |
165 | 1e5459a3 | balrog | }; |
166 | 1e5459a3 | balrog | |
167 | 1e5459a3 | balrog | static MemOp sh_pci_iop = {
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168 | 1e5459a3 | balrog | { sh_pci_inb, sh_pci_inw, sh_pci_inl }, |
169 | 1e5459a3 | balrog | { sh_pci_outb, sh_pci_outw, sh_pci_outl }, |
170 | 1e5459a3 | balrog | }; |
171 | 1e5459a3 | balrog | |
172 | 1e5459a3 | balrog | PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
173 | 5d4e84c8 | Juan Quintela | void *opaque, int devfn_min, int nirq) |
174 | 1e5459a3 | balrog | { |
175 | 1e5459a3 | balrog | SHPCIC *p; |
176 | 1e5459a3 | balrog | int mem, reg, iop;
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177 | 1e5459a3 | balrog | |
178 | 1e5459a3 | balrog | p = qemu_mallocz(sizeof(SHPCIC));
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179 | 02e2da45 | Paul Brook | p->bus = pci_register_bus(NULL, "pci", |
180 | 5d4e84c8 | Juan Quintela | set_irq, map_irq, opaque, devfn_min, nirq); |
181 | 1e5459a3 | balrog | |
182 | 1e5459a3 | balrog | p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice), |
183 | 1e5459a3 | balrog | -1, NULL, NULL); |
184 | 1eed09cb | Avi Kivity | reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p); |
185 | 1eed09cb | Avi Kivity | iop = cpu_register_io_memory(sh_pci_iop.r, sh_pci_iop.w, p); |
186 | 1eed09cb | Avi Kivity | mem = cpu_register_io_memory(sh_pci_mem.r, sh_pci_mem.w, p); |
187 | ac2e8522 | aurel32 | cpu_register_physical_memory(0x1e200000, 0x224, reg); |
188 | ac2e8522 | aurel32 | cpu_register_physical_memory(0x1e240000, 0x40000, iop); |
189 | ac2e8522 | aurel32 | cpu_register_physical_memory(0x1d000000, 0x1000000, mem); |
190 | ac2e8522 | aurel32 | cpu_register_physical_memory(0xfe200000, 0x224, reg); |
191 | ac2e8522 | aurel32 | cpu_register_physical_memory(0xfe240000, 0x40000, iop); |
192 | ac2e8522 | aurel32 | cpu_register_physical_memory(0xfd000000, 0x1000000, mem); |
193 | 1e5459a3 | balrog | |
194 | deb54399 | aliguori | pci_config_set_vendor_id(p->dev->config, PCI_VENDOR_ID_HITACHI); |
195 | a770dc7e | aliguori | pci_config_set_device_id(p->dev->config, PCI_DEVICE_ID_HITACHI_SH7751R); |
196 | 1e5459a3 | balrog | p->dev->config[0x04] = 0x80; |
197 | 1e5459a3 | balrog | p->dev->config[0x05] = 0x00; |
198 | 1e5459a3 | balrog | p->dev->config[0x06] = 0x90; |
199 | 1e5459a3 | balrog | p->dev->config[0x07] = 0x02; |
200 | 1e5459a3 | balrog | |
201 | 1e5459a3 | balrog | return p->bus;
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202 | 1e5459a3 | balrog | } |