Revision 42f1ced2
b/hw/esp.c | ||
---|---|---|
401 | 401 |
{ |
402 | 402 |
ESPState *s = opaque; |
403 | 403 |
|
404 |
esp_lower_irq(s); |
|
405 |
|
|
406 | 404 |
memset(s->rregs, 0, ESP_REGS); |
407 | 405 |
memset(s->wregs, 0, ESP_REGS); |
408 | 406 |
s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a |
b/hw/iommu.c | ||
---|---|---|
362 | 362 |
s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; |
363 | 363 |
s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB; |
364 | 364 |
s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; |
365 |
qemu_irq_lower(s->irq); |
|
366 | 365 |
} |
367 | 366 |
|
368 | 367 |
void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
b/hw/sbi.c | ||
---|---|---|
47 | 47 |
|
48 | 48 |
#define SBI_SIZE (SBI_NREGS * 4) |
49 | 49 |
|
50 |
static void sbi_check_interrupts(void *opaque) |
|
51 |
{ |
|
52 |
} |
|
53 |
|
|
54 | 50 |
static void sbi_set_irq(void *opaque, int irq, int level) |
55 | 51 |
{ |
56 | 52 |
} |
... | ... | |
122 | 118 |
for (i = 0; i < MAX_CPUS; i++) { |
123 | 119 |
qemu_get_be32s(f, &s->intreg_pending[i]); |
124 | 120 |
} |
125 |
sbi_check_interrupts(s); |
|
126 | 121 |
|
127 | 122 |
return 0; |
128 | 123 |
} |
... | ... | |
135 | 130 |
for (i = 0; i < MAX_CPUS; i++) { |
136 | 131 |
s->intreg_pending[i] = 0; |
137 | 132 |
} |
138 |
sbi_check_interrupts(s); |
|
139 | 133 |
} |
140 | 134 |
|
141 | 135 |
void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq, |
b/hw/slavio_timer.c | ||
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359 | 359 |
ptimer_run(s->timer, 0); |
360 | 360 |
} |
361 | 361 |
s->running = 1; |
362 |
qemu_irq_lower(s->irq); |
|
363 | 362 |
} |
364 | 363 |
|
365 | 364 |
static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr, |
b/hw/sun4c_intctl.c | ||
---|---|---|
183 | 183 |
|
184 | 184 |
qemu_get_8s(f, &s->reg); |
185 | 185 |
qemu_get_8s(f, &s->pending); |
186 |
sun4c_check_interrupts(s); |
|
187 | 186 |
|
188 | 187 |
return 0; |
189 | 188 |
} |
... | ... | |
194 | 193 |
|
195 | 194 |
s->reg = 1; |
196 | 195 |
s->pending = 0; |
197 |
sun4c_check_interrupts(s); |
|
198 | 196 |
} |
199 | 197 |
|
200 | 198 |
void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq, |
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