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| 1 | 7d13299d | bellard | /*
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| 2 | 7d13299d | bellard | * i386 emulator main execution loop
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| 3 | 7d13299d | bellard | *
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| 4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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| 5 | 7d13299d | bellard | *
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| 6 | 3ef693a0 | bellard | * This library is free software; you can redistribute it and/or
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| 7 | 3ef693a0 | bellard | * modify it under the terms of the GNU Lesser General Public
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| 8 | 3ef693a0 | bellard | * License as published by the Free Software Foundation; either
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| 9 | 3ef693a0 | bellard | * version 2 of the License, or (at your option) any later version.
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| 10 | 7d13299d | bellard | *
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| 11 | 3ef693a0 | bellard | * This library is distributed in the hope that it will be useful,
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| 12 | 3ef693a0 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | 3ef693a0 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 14 | 3ef693a0 | bellard | * Lesser General Public License for more details.
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| 15 | 7d13299d | bellard | *
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| 16 | 3ef693a0 | bellard | * You should have received a copy of the GNU Lesser General Public
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| 17 | 3ef693a0 | bellard | * License along with this library; if not, write to the Free Software
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| 18 | 3ef693a0 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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| 19 | 7d13299d | bellard | */
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| 20 | e4533c7a | bellard | #include "config.h" |
| 21 | 93ac68bc | bellard | #include "exec.h" |
| 22 | 956034d7 | bellard | #include "disas.h" |
| 23 | 7d13299d | bellard | |
| 24 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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| 25 | fbf9eeb3 | bellard | #undef EAX
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| 26 | fbf9eeb3 | bellard | #undef ECX
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| 27 | fbf9eeb3 | bellard | #undef EDX
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| 28 | fbf9eeb3 | bellard | #undef EBX
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| 29 | fbf9eeb3 | bellard | #undef ESP
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| 30 | fbf9eeb3 | bellard | #undef EBP
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| 31 | fbf9eeb3 | bellard | #undef ESI
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| 32 | fbf9eeb3 | bellard | #undef EDI
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| 33 | fbf9eeb3 | bellard | #undef EIP
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| 34 | fbf9eeb3 | bellard | #include <signal.h> |
| 35 | fbf9eeb3 | bellard | #include <sys/ucontext.h> |
| 36 | fbf9eeb3 | bellard | #endif
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| 37 | fbf9eeb3 | bellard | |
| 38 | 36bdbe54 | bellard | int tb_invalidated_flag;
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| 39 | 36bdbe54 | bellard | |
| 40 | dc99065b | bellard | //#define DEBUG_EXEC
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| 41 | 9de5e440 | bellard | //#define DEBUG_SIGNAL
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| 42 | 7d13299d | bellard | |
| 43 | 93ac68bc | bellard | #if defined(TARGET_ARM) || defined(TARGET_SPARC)
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| 44 | e4533c7a | bellard | /* XXX: unify with i386 target */
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| 45 | e4533c7a | bellard | void cpu_loop_exit(void) |
| 46 | e4533c7a | bellard | {
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| 47 | e4533c7a | bellard | longjmp(env->jmp_env, 1);
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| 48 | e4533c7a | bellard | } |
| 49 | e4533c7a | bellard | #endif
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| 50 | 9c2a9ea1 | pbrook | #if !(defined(TARGET_SPARC) || defined(TARGET_SH4))
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| 51 | 3475187d | bellard | #define reg_T2
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| 52 | 3475187d | bellard | #endif
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| 53 | e4533c7a | bellard | |
| 54 | fbf9eeb3 | bellard | /* exit the current TB from a signal handler. The host registers are
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| 55 | fbf9eeb3 | bellard | restored in a state compatible with the CPU emulator
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| 56 | fbf9eeb3 | bellard | */
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| 57 | fbf9eeb3 | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc) |
| 58 | fbf9eeb3 | bellard | {
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| 59 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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| 60 | fbf9eeb3 | bellard | struct ucontext *uc = puc;
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| 61 | fbf9eeb3 | bellard | #endif
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| 62 | fbf9eeb3 | bellard | |
| 63 | fbf9eeb3 | bellard | env = env1; |
| 64 | fbf9eeb3 | bellard | |
| 65 | fbf9eeb3 | bellard | /* XXX: restore cpu registers saved in host registers */
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| 66 | fbf9eeb3 | bellard | |
| 67 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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| 68 | fbf9eeb3 | bellard | if (puc) {
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| 69 | fbf9eeb3 | bellard | /* XXX: use siglongjmp ? */
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| 70 | fbf9eeb3 | bellard | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
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| 71 | fbf9eeb3 | bellard | } |
| 72 | fbf9eeb3 | bellard | #endif
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| 73 | fbf9eeb3 | bellard | longjmp(env->jmp_env, 1);
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| 74 | fbf9eeb3 | bellard | } |
| 75 | fbf9eeb3 | bellard | |
| 76 | 8a40a180 | bellard | |
| 77 | 8a40a180 | bellard | static TranslationBlock *tb_find_slow(target_ulong pc,
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| 78 | 8a40a180 | bellard | target_ulong cs_base, |
| 79 | 8a40a180 | bellard | unsigned int flags) |
| 80 | 8a40a180 | bellard | {
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| 81 | 8a40a180 | bellard | TranslationBlock *tb, **ptb1; |
| 82 | 8a40a180 | bellard | int code_gen_size;
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| 83 | 8a40a180 | bellard | unsigned int h; |
| 84 | 8a40a180 | bellard | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; |
| 85 | 8a40a180 | bellard | uint8_t *tc_ptr; |
| 86 | 8a40a180 | bellard | |
| 87 | 8a40a180 | bellard | spin_lock(&tb_lock); |
| 88 | 8a40a180 | bellard | |
| 89 | 8a40a180 | bellard | tb_invalidated_flag = 0;
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| 90 | 8a40a180 | bellard | |
| 91 | 8a40a180 | bellard | regs_to_env(); /* XXX: do it just before cpu_gen_code() */
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| 92 | 8a40a180 | bellard | |
| 93 | 8a40a180 | bellard | /* find translated block using physical mappings */
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| 94 | 8a40a180 | bellard | phys_pc = get_phys_addr_code(env, pc); |
| 95 | 8a40a180 | bellard | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
| 96 | 8a40a180 | bellard | phys_page2 = -1;
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| 97 | 8a40a180 | bellard | h = tb_phys_hash_func(phys_pc); |
| 98 | 8a40a180 | bellard | ptb1 = &tb_phys_hash[h]; |
| 99 | 8a40a180 | bellard | for(;;) {
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| 100 | 8a40a180 | bellard | tb = *ptb1; |
| 101 | 8a40a180 | bellard | if (!tb)
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| 102 | 8a40a180 | bellard | goto not_found;
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| 103 | 8a40a180 | bellard | if (tb->pc == pc &&
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| 104 | 8a40a180 | bellard | tb->page_addr[0] == phys_page1 &&
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| 105 | 8a40a180 | bellard | tb->cs_base == cs_base && |
| 106 | 8a40a180 | bellard | tb->flags == flags) {
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| 107 | 8a40a180 | bellard | /* check next page if needed */
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| 108 | 8a40a180 | bellard | if (tb->page_addr[1] != -1) { |
| 109 | 8a40a180 | bellard | virt_page2 = (pc & TARGET_PAGE_MASK) + |
| 110 | 8a40a180 | bellard | TARGET_PAGE_SIZE; |
| 111 | 8a40a180 | bellard | phys_page2 = get_phys_addr_code(env, virt_page2); |
| 112 | 8a40a180 | bellard | if (tb->page_addr[1] == phys_page2) |
| 113 | 8a40a180 | bellard | goto found;
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| 114 | 8a40a180 | bellard | } else {
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| 115 | 8a40a180 | bellard | goto found;
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| 116 | 8a40a180 | bellard | } |
| 117 | 8a40a180 | bellard | } |
| 118 | 8a40a180 | bellard | ptb1 = &tb->phys_hash_next; |
| 119 | 8a40a180 | bellard | } |
| 120 | 8a40a180 | bellard | not_found:
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| 121 | 8a40a180 | bellard | /* if no translated code available, then translate it now */
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| 122 | 8a40a180 | bellard | tb = tb_alloc(pc); |
| 123 | 8a40a180 | bellard | if (!tb) {
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| 124 | 8a40a180 | bellard | /* flush must be done */
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| 125 | 8a40a180 | bellard | tb_flush(env); |
| 126 | 8a40a180 | bellard | /* cannot fail at this point */
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| 127 | 8a40a180 | bellard | tb = tb_alloc(pc); |
| 128 | 8a40a180 | bellard | /* don't forget to invalidate previous TB info */
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| 129 | 15388002 | bellard | tb_invalidated_flag = 1;
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| 130 | 8a40a180 | bellard | } |
| 131 | 8a40a180 | bellard | tc_ptr = code_gen_ptr; |
| 132 | 8a40a180 | bellard | tb->tc_ptr = tc_ptr; |
| 133 | 8a40a180 | bellard | tb->cs_base = cs_base; |
| 134 | 8a40a180 | bellard | tb->flags = flags; |
| 135 | 8a40a180 | bellard | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
| 136 | 8a40a180 | bellard | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
| 137 | 8a40a180 | bellard | |
| 138 | 8a40a180 | bellard | /* check next page if needed */
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| 139 | 8a40a180 | bellard | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
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| 140 | 8a40a180 | bellard | phys_page2 = -1;
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| 141 | 8a40a180 | bellard | if ((pc & TARGET_PAGE_MASK) != virt_page2) {
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| 142 | 8a40a180 | bellard | phys_page2 = get_phys_addr_code(env, virt_page2); |
| 143 | 8a40a180 | bellard | } |
| 144 | 8a40a180 | bellard | tb_link_phys(tb, phys_pc, phys_page2); |
| 145 | 8a40a180 | bellard | |
| 146 | 8a40a180 | bellard | found:
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| 147 | 8a40a180 | bellard | /* we add the TB in the virtual pc hash table */
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| 148 | 8a40a180 | bellard | env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; |
| 149 | 8a40a180 | bellard | spin_unlock(&tb_lock); |
| 150 | 8a40a180 | bellard | return tb;
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| 151 | 8a40a180 | bellard | } |
| 152 | 8a40a180 | bellard | |
| 153 | 8a40a180 | bellard | static inline TranslationBlock *tb_find_fast(void) |
| 154 | 8a40a180 | bellard | {
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| 155 | 8a40a180 | bellard | TranslationBlock *tb; |
| 156 | 8a40a180 | bellard | target_ulong cs_base, pc; |
| 157 | 8a40a180 | bellard | unsigned int flags; |
| 158 | 8a40a180 | bellard | |
| 159 | 8a40a180 | bellard | /* we record a subset of the CPU state. It will
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| 160 | 8a40a180 | bellard | always be the same before a given translated block
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| 161 | 8a40a180 | bellard | is executed. */
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| 162 | 8a40a180 | bellard | #if defined(TARGET_I386)
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| 163 | 8a40a180 | bellard | flags = env->hflags; |
| 164 | 8a40a180 | bellard | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
| 165 | 8a40a180 | bellard | cs_base = env->segs[R_CS].base; |
| 166 | 8a40a180 | bellard | pc = cs_base + env->eip; |
| 167 | 8a40a180 | bellard | #elif defined(TARGET_ARM)
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| 168 | 8a40a180 | bellard | flags = env->thumb | (env->vfp.vec_len << 1)
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| 169 | b5ff1b31 | bellard | | (env->vfp.vec_stride << 4);
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| 170 | b5ff1b31 | bellard | if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
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| 171 | b5ff1b31 | bellard | flags |= (1 << 6); |
| 172 | 40f137e1 | pbrook | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) |
| 173 | 40f137e1 | pbrook | flags |= (1 << 7); |
| 174 | 8a40a180 | bellard | cs_base = 0;
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| 175 | 8a40a180 | bellard | pc = env->regs[15];
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| 176 | 8a40a180 | bellard | #elif defined(TARGET_SPARC)
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| 177 | 8a40a180 | bellard | #ifdef TARGET_SPARC64
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| 178 | a80dde08 | bellard | // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
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| 179 | a80dde08 | bellard | flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2)) |
| 180 | a80dde08 | bellard | | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
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| 181 | 8a40a180 | bellard | #else
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| 182 | a80dde08 | bellard | // FPU enable . MMU enabled . MMU no-fault . Supervisor
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| 183 | a80dde08 | bellard | flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1) |
| 184 | a80dde08 | bellard | | env->psrs; |
| 185 | 8a40a180 | bellard | #endif
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| 186 | 8a40a180 | bellard | cs_base = env->npc; |
| 187 | 8a40a180 | bellard | pc = env->pc; |
| 188 | 8a40a180 | bellard | #elif defined(TARGET_PPC)
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| 189 | 8a40a180 | bellard | flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | |
| 190 | 8a40a180 | bellard | (msr_se << MSR_SE) | (msr_le << MSR_LE); |
| 191 | 8a40a180 | bellard | cs_base = 0;
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| 192 | 8a40a180 | bellard | pc = env->nip; |
| 193 | 8a40a180 | bellard | #elif defined(TARGET_MIPS)
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| 194 | 56b19403 | pbrook | flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); |
| 195 | cc9442b9 | bellard | cs_base = 0;
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| 196 | 8a40a180 | bellard | pc = env->PC; |
| 197 | fdf9b3e8 | bellard | #elif defined(TARGET_SH4)
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| 198 | fdf9b3e8 | bellard | flags = env->sr & (SR_MD | SR_RB); |
| 199 | fdf9b3e8 | bellard | cs_base = 0; /* XXXXX */ |
| 200 | fdf9b3e8 | bellard | pc = env->pc; |
| 201 | 8a40a180 | bellard | #else
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| 202 | 8a40a180 | bellard | #error unsupported CPU
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| 203 | 8a40a180 | bellard | #endif
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| 204 | 8a40a180 | bellard | tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; |
| 205 | 8a40a180 | bellard | if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
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| 206 | 8a40a180 | bellard | tb->flags != flags, 0)) {
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| 207 | 8a40a180 | bellard | tb = tb_find_slow(pc, cs_base, flags); |
| 208 | 15388002 | bellard | /* Note: we do it here to avoid a gcc bug on Mac OS X when
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| 209 | 15388002 | bellard | doing it in tb_find_slow */
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| 210 | 15388002 | bellard | if (tb_invalidated_flag) {
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| 211 | 15388002 | bellard | /* as some TB could have been invalidated because
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| 212 | 15388002 | bellard | of memory exceptions while generating the code, we
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| 213 | 15388002 | bellard | must recompute the hash index here */
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| 214 | 15388002 | bellard | T0 = 0;
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| 215 | 15388002 | bellard | } |
| 216 | 8a40a180 | bellard | } |
| 217 | 8a40a180 | bellard | return tb;
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| 218 | 8a40a180 | bellard | } |
| 219 | 8a40a180 | bellard | |
| 220 | 8a40a180 | bellard | |
| 221 | 7d13299d | bellard | /* main execution loop */
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| 222 | 7d13299d | bellard | |
| 223 | e4533c7a | bellard | int cpu_exec(CPUState *env1)
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| 224 | 7d13299d | bellard | {
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| 225 | 3475187d | bellard | int saved_T0, saved_T1;
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| 226 | 3475187d | bellard | #if defined(reg_T2)
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| 227 | 3475187d | bellard | int saved_T2;
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| 228 | 3475187d | bellard | #endif
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| 229 | e4533c7a | bellard | CPUState *saved_env; |
| 230 | 3475187d | bellard | #if defined(TARGET_I386)
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| 231 | 04369ff2 | bellard | #ifdef reg_EAX
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| 232 | 04369ff2 | bellard | int saved_EAX;
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| 233 | 04369ff2 | bellard | #endif
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| 234 | 04369ff2 | bellard | #ifdef reg_ECX
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| 235 | 04369ff2 | bellard | int saved_ECX;
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| 236 | 04369ff2 | bellard | #endif
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| 237 | 04369ff2 | bellard | #ifdef reg_EDX
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| 238 | 04369ff2 | bellard | int saved_EDX;
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| 239 | 04369ff2 | bellard | #endif
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| 240 | 04369ff2 | bellard | #ifdef reg_EBX
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| 241 | 04369ff2 | bellard | int saved_EBX;
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| 242 | 04369ff2 | bellard | #endif
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| 243 | 04369ff2 | bellard | #ifdef reg_ESP
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| 244 | 04369ff2 | bellard | int saved_ESP;
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| 245 | 04369ff2 | bellard | #endif
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| 246 | 04369ff2 | bellard | #ifdef reg_EBP
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| 247 | 04369ff2 | bellard | int saved_EBP;
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| 248 | 04369ff2 | bellard | #endif
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| 249 | 04369ff2 | bellard | #ifdef reg_ESI
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| 250 | 04369ff2 | bellard | int saved_ESI;
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| 251 | 04369ff2 | bellard | #endif
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| 252 | 04369ff2 | bellard | #ifdef reg_EDI
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| 253 | 04369ff2 | bellard | int saved_EDI;
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| 254 | 04369ff2 | bellard | #endif
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| 255 | 3475187d | bellard | #elif defined(TARGET_SPARC)
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| 256 | 3475187d | bellard | #if defined(reg_REGWPTR)
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| 257 | 3475187d | bellard | uint32_t *saved_regwptr; |
| 258 | 3475187d | bellard | #endif
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| 259 | 3475187d | bellard | #endif
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| 260 | fdbb4691 | bellard | #if defined(__sparc__) && !defined(HOST_SOLARIS)
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| 261 | 8c6939c0 | bellard | int saved_i7, tmp_T0;
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| 262 | 8c6939c0 | bellard | #endif
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| 263 | 8a40a180 | bellard | int ret, interrupt_request;
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| 264 | 7d13299d | bellard | void (*gen_func)(void); |
| 265 | 8a40a180 | bellard | TranslationBlock *tb; |
| 266 | c27004ec | bellard | uint8_t *tc_ptr; |
| 267 | 8c6939c0 | bellard | |
| 268 | 5a1e3cfc | bellard | #if defined(TARGET_I386)
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| 269 | 5a1e3cfc | bellard | /* handle exit of HALTED state */
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| 270 | 5a1e3cfc | bellard | if (env1->hflags & HF_HALTED_MASK) {
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| 271 | 5a1e3cfc | bellard | /* disable halt condition */
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| 272 | 5a1e3cfc | bellard | if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
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| 273 | 5a1e3cfc | bellard | (env1->eflags & IF_MASK)) {
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| 274 | 5a1e3cfc | bellard | env1->hflags &= ~HF_HALTED_MASK; |
| 275 | 5a1e3cfc | bellard | } else {
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| 276 | 5a1e3cfc | bellard | return EXCP_HALTED;
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| 277 | e80e1cc4 | bellard | } |
| 278 | e80e1cc4 | bellard | } |
| 279 | e80e1cc4 | bellard | #elif defined(TARGET_PPC)
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| 280 | 50443c98 | bellard | if (env1->halted) {
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| 281 | e80e1cc4 | bellard | if (env1->msr[MSR_EE] &&
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| 282 | e80e1cc4 | bellard | (env1->interrupt_request & |
| 283 | e80e1cc4 | bellard | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
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| 284 | 50443c98 | bellard | env1->halted = 0;
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| 285 | e80e1cc4 | bellard | } else {
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| 286 | e80e1cc4 | bellard | return EXCP_HALTED;
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| 287 | 5a1e3cfc | bellard | } |
| 288 | 5a1e3cfc | bellard | } |
| 289 | ba3c64fb | bellard | #elif defined(TARGET_SPARC)
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| 290 | ba3c64fb | bellard | if (env1->halted) {
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| 291 | ba3c64fb | bellard | if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
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| 292 | ba3c64fb | bellard | (env1->psret != 0)) {
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| 293 | ba3c64fb | bellard | env1->halted = 0;
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| 294 | ba3c64fb | bellard | } else {
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| 295 | ba3c64fb | bellard | return EXCP_HALTED;
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| 296 | ba3c64fb | bellard | } |
| 297 | ba3c64fb | bellard | } |
| 298 | 9332f9da | bellard | #elif defined(TARGET_ARM)
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| 299 | 9332f9da | bellard | if (env1->halted) {
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| 300 | 9332f9da | bellard | /* An interrupt wakes the CPU even if the I and F CPSR bits are
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| 301 | 9332f9da | bellard | set. */
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| 302 | 9332f9da | bellard | if (env1->interrupt_request
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| 303 | 9332f9da | bellard | & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
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| 304 | 9332f9da | bellard | env1->halted = 0;
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| 305 | 9332f9da | bellard | } else {
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| 306 | 9332f9da | bellard | return EXCP_HALTED;
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| 307 | 9332f9da | bellard | } |
| 308 | 9332f9da | bellard | } |
| 309 | 6810e154 | bellard | #elif defined(TARGET_MIPS)
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| 310 | 6810e154 | bellard | if (env1->halted) {
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| 311 | 6810e154 | bellard | if (env1->interrupt_request &
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| 312 | 6810e154 | bellard | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
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| 313 | 6810e154 | bellard | env1->halted = 0;
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| 314 | 6810e154 | bellard | } else {
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| 315 | 6810e154 | bellard | return EXCP_HALTED;
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| 316 | 6810e154 | bellard | } |
| 317 | 6810e154 | bellard | } |
| 318 | 5a1e3cfc | bellard | #endif
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| 319 | 5a1e3cfc | bellard | |
| 320 | 6a00d601 | bellard | cpu_single_env = env1; |
| 321 | 6a00d601 | bellard | |
| 322 | 7d13299d | bellard | /* first we save global registers */
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| 323 | c27004ec | bellard | saved_env = env; |
| 324 | c27004ec | bellard | env = env1; |
| 325 | 7d13299d | bellard | saved_T0 = T0; |
| 326 | 7d13299d | bellard | saved_T1 = T1; |
| 327 | 3475187d | bellard | #if defined(reg_T2)
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| 328 | e4533c7a | bellard | saved_T2 = T2; |
| 329 | 3475187d | bellard | #endif
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| 330 | fdbb4691 | bellard | #if defined(__sparc__) && !defined(HOST_SOLARIS)
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| 331 | e4533c7a | bellard | /* we also save i7 because longjmp may not restore it */
|
| 332 | e4533c7a | bellard | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
| 333 | e4533c7a | bellard | #endif
|
| 334 | e4533c7a | bellard | |
| 335 | e4533c7a | bellard | #if defined(TARGET_I386)
|
| 336 | 04369ff2 | bellard | #ifdef reg_EAX
|
| 337 | 04369ff2 | bellard | saved_EAX = EAX; |
| 338 | 04369ff2 | bellard | #endif
|
| 339 | 04369ff2 | bellard | #ifdef reg_ECX
|
| 340 | 04369ff2 | bellard | saved_ECX = ECX; |
| 341 | 04369ff2 | bellard | #endif
|
| 342 | 04369ff2 | bellard | #ifdef reg_EDX
|
| 343 | 04369ff2 | bellard | saved_EDX = EDX; |
| 344 | 04369ff2 | bellard | #endif
|
| 345 | 04369ff2 | bellard | #ifdef reg_EBX
|
| 346 | 04369ff2 | bellard | saved_EBX = EBX; |
| 347 | 04369ff2 | bellard | #endif
|
| 348 | 04369ff2 | bellard | #ifdef reg_ESP
|
| 349 | 04369ff2 | bellard | saved_ESP = ESP; |
| 350 | 04369ff2 | bellard | #endif
|
| 351 | 04369ff2 | bellard | #ifdef reg_EBP
|
| 352 | 04369ff2 | bellard | saved_EBP = EBP; |
| 353 | 04369ff2 | bellard | #endif
|
| 354 | 04369ff2 | bellard | #ifdef reg_ESI
|
| 355 | 04369ff2 | bellard | saved_ESI = ESI; |
| 356 | 04369ff2 | bellard | #endif
|
| 357 | 04369ff2 | bellard | #ifdef reg_EDI
|
| 358 | 04369ff2 | bellard | saved_EDI = EDI; |
| 359 | 04369ff2 | bellard | #endif
|
| 360 | 0d1a29f9 | bellard | |
| 361 | 0d1a29f9 | bellard | env_to_regs(); |
| 362 | 9de5e440 | bellard | /* put eflags in CPU temporary format */
|
| 363 | fc2b4c48 | bellard | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 364 | fc2b4c48 | bellard | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
| 365 | 9de5e440 | bellard | CC_OP = CC_OP_EFLAGS; |
| 366 | fc2b4c48 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 367 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
| 368 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
| 369 | 3475187d | bellard | #if defined(reg_REGWPTR)
|
| 370 | 3475187d | bellard | saved_regwptr = REGWPTR; |
| 371 | 3475187d | bellard | #endif
|
| 372 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
| 373 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
| 374 | fdf9b3e8 | bellard | #elif defined(TARGET_SH4)
|
| 375 | fdf9b3e8 | bellard | /* XXXXX */
|
| 376 | e4533c7a | bellard | #else
|
| 377 | e4533c7a | bellard | #error unsupported target CPU
|
| 378 | e4533c7a | bellard | #endif
|
| 379 | 3fb2ded1 | bellard | env->exception_index = -1;
|
| 380 | 9d27abd9 | bellard | |
| 381 | 7d13299d | bellard | /* prepare setjmp context for exception handling */
|
| 382 | 3fb2ded1 | bellard | for(;;) {
|
| 383 | 3fb2ded1 | bellard | if (setjmp(env->jmp_env) == 0) { |
| 384 | ee8b7021 | bellard | env->current_tb = NULL;
|
| 385 | 3fb2ded1 | bellard | /* if an exception is pending, we execute it here */
|
| 386 | 3fb2ded1 | bellard | if (env->exception_index >= 0) { |
| 387 | 3fb2ded1 | bellard | if (env->exception_index >= EXCP_INTERRUPT) {
|
| 388 | 3fb2ded1 | bellard | /* exit request from the cpu execution loop */
|
| 389 | 3fb2ded1 | bellard | ret = env->exception_index; |
| 390 | 3fb2ded1 | bellard | break;
|
| 391 | 3fb2ded1 | bellard | } else if (env->user_mode_only) { |
| 392 | 3fb2ded1 | bellard | /* if user mode only, we simulate a fake exception
|
| 393 | 3fb2ded1 | bellard | which will be hanlded outside the cpu execution
|
| 394 | 3fb2ded1 | bellard | loop */
|
| 395 | 83479e77 | bellard | #if defined(TARGET_I386)
|
| 396 | 3fb2ded1 | bellard | do_interrupt_user(env->exception_index, |
| 397 | 3fb2ded1 | bellard | env->exception_is_int, |
| 398 | 3fb2ded1 | bellard | env->error_code, |
| 399 | 3fb2ded1 | bellard | env->exception_next_eip); |
| 400 | 83479e77 | bellard | #endif
|
| 401 | 3fb2ded1 | bellard | ret = env->exception_index; |
| 402 | 3fb2ded1 | bellard | break;
|
| 403 | 3fb2ded1 | bellard | } else {
|
| 404 | 83479e77 | bellard | #if defined(TARGET_I386)
|
| 405 | 3fb2ded1 | bellard | /* simulate a real cpu exception. On i386, it can
|
| 406 | 3fb2ded1 | bellard | trigger new exceptions, but we do not handle
|
| 407 | 3fb2ded1 | bellard | double or triple faults yet. */
|
| 408 | 3fb2ded1 | bellard | do_interrupt(env->exception_index, |
| 409 | 3fb2ded1 | bellard | env->exception_is_int, |
| 410 | 3fb2ded1 | bellard | env->error_code, |
| 411 | d05e66d2 | bellard | env->exception_next_eip, 0);
|
| 412 | ce09776b | bellard | #elif defined(TARGET_PPC)
|
| 413 | ce09776b | bellard | do_interrupt(env); |
| 414 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
| 415 | 6af0bf9c | bellard | do_interrupt(env); |
| 416 | e95c8d51 | bellard | #elif defined(TARGET_SPARC)
|
| 417 | 1a0c3292 | bellard | do_interrupt(env->exception_index); |
| 418 | b5ff1b31 | bellard | #elif defined(TARGET_ARM)
|
| 419 | b5ff1b31 | bellard | do_interrupt(env); |
| 420 | fdf9b3e8 | bellard | #elif defined(TARGET_SH4)
|
| 421 | fdf9b3e8 | bellard | do_interrupt(env); |
| 422 | 83479e77 | bellard | #endif
|
| 423 | 3fb2ded1 | bellard | } |
| 424 | 3fb2ded1 | bellard | env->exception_index = -1;
|
| 425 | 9df217a3 | bellard | } |
| 426 | 9df217a3 | bellard | #ifdef USE_KQEMU
|
| 427 | 9df217a3 | bellard | if (kqemu_is_ok(env) && env->interrupt_request == 0) { |
| 428 | 9df217a3 | bellard | int ret;
|
| 429 | 9df217a3 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
| 430 | 9df217a3 | bellard | ret = kqemu_cpu_exec(env); |
| 431 | 9df217a3 | bellard | /* put eflags in CPU temporary format */
|
| 432 | 9df217a3 | bellard | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 433 | 9df217a3 | bellard | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
| 434 | 9df217a3 | bellard | CC_OP = CC_OP_EFLAGS; |
| 435 | 9df217a3 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 436 | 9df217a3 | bellard | if (ret == 1) { |
| 437 | 9df217a3 | bellard | /* exception */
|
| 438 | 9df217a3 | bellard | longjmp(env->jmp_env, 1);
|
| 439 | 9df217a3 | bellard | } else if (ret == 2) { |
| 440 | 9df217a3 | bellard | /* softmmu execution needed */
|
| 441 | 9df217a3 | bellard | } else {
|
| 442 | 9df217a3 | bellard | if (env->interrupt_request != 0) { |
| 443 | 9df217a3 | bellard | /* hardware interrupt will be executed just after */
|
| 444 | 9df217a3 | bellard | } else {
|
| 445 | 9df217a3 | bellard | /* otherwise, we restart */
|
| 446 | 9df217a3 | bellard | longjmp(env->jmp_env, 1);
|
| 447 | 9df217a3 | bellard | } |
| 448 | 9df217a3 | bellard | } |
| 449 | 3fb2ded1 | bellard | } |
| 450 | 9df217a3 | bellard | #endif
|
| 451 | 9df217a3 | bellard | |
| 452 | 3fb2ded1 | bellard | T0 = 0; /* force lookup of first TB */ |
| 453 | 3fb2ded1 | bellard | for(;;) {
|
| 454 | fdbb4691 | bellard | #if defined(__sparc__) && !defined(HOST_SOLARIS)
|
| 455 | 3fb2ded1 | bellard | /* g1 can be modified by some libc? functions */
|
| 456 | 3fb2ded1 | bellard | tmp_T0 = T0; |
| 457 | 8c6939c0 | bellard | #endif
|
| 458 | 68a79315 | bellard | interrupt_request = env->interrupt_request; |
| 459 | 2e255c6b | bellard | if (__builtin_expect(interrupt_request, 0)) { |
| 460 | 68a79315 | bellard | #if defined(TARGET_I386)
|
| 461 | 3b21e03e | bellard | if ((interrupt_request & CPU_INTERRUPT_SMI) &&
|
| 462 | 3b21e03e | bellard | !(env->hflags & HF_SMM_MASK)) {
|
| 463 | 3b21e03e | bellard | env->interrupt_request &= ~CPU_INTERRUPT_SMI; |
| 464 | 3b21e03e | bellard | do_smm_enter(); |
| 465 | 3b21e03e | bellard | #if defined(__sparc__) && !defined(HOST_SOLARIS)
|
| 466 | 3b21e03e | bellard | tmp_T0 = 0;
|
| 467 | 3b21e03e | bellard | #else
|
| 468 | 3b21e03e | bellard | T0 = 0;
|
| 469 | 3b21e03e | bellard | #endif
|
| 470 | 3b21e03e | bellard | } else if ((interrupt_request & CPU_INTERRUPT_HARD) && |
| 471 | 3f337316 | bellard | (env->eflags & IF_MASK) && |
| 472 | 3f337316 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
|
| 473 | 68a79315 | bellard | int intno;
|
| 474 | fbf9eeb3 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
| 475 | a541f297 | bellard | intno = cpu_get_pic_interrupt(env); |
| 476 | f193c797 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
| 477 | 68a79315 | bellard | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
|
| 478 | 68a79315 | bellard | } |
| 479 | d05e66d2 | bellard | do_interrupt(intno, 0, 0, 0, 1); |
| 480 | 907a5b26 | bellard | /* ensure that no TB jump will be modified as
|
| 481 | 907a5b26 | bellard | the program flow was changed */
|
| 482 | fdbb4691 | bellard | #if defined(__sparc__) && !defined(HOST_SOLARIS)
|
| 483 | 907a5b26 | bellard | tmp_T0 = 0;
|
| 484 | 907a5b26 | bellard | #else
|
| 485 | 907a5b26 | bellard | T0 = 0;
|
| 486 | 907a5b26 | bellard | #endif
|
| 487 | 68a79315 | bellard | } |
| 488 | ce09776b | bellard | #elif defined(TARGET_PPC)
|
| 489 | 9fddaa0c | bellard | #if 0
|
| 490 | 9fddaa0c | bellard | if ((interrupt_request & CPU_INTERRUPT_RESET)) {
|
| 491 | 9fddaa0c | bellard | cpu_ppc_reset(env);
|
| 492 | 9fddaa0c | bellard | }
|
| 493 | 9fddaa0c | bellard | #endif
|
| 494 | 9fddaa0c | bellard | if (msr_ee != 0) { |
| 495 | 8a40a180 | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD)) {
|
| 496 | 9fddaa0c | bellard | /* Raise it */
|
| 497 | 9fddaa0c | bellard | env->exception_index = EXCP_EXTERNAL; |
| 498 | 9fddaa0c | bellard | env->error_code = 0;
|
| 499 | ce09776b | bellard | do_interrupt(env); |
| 500 | 8a40a180 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
| 501 | fdbb4691 | bellard | #if defined(__sparc__) && !defined(HOST_SOLARIS)
|
| 502 | 8a40a180 | bellard | tmp_T0 = 0;
|
| 503 | 8a40a180 | bellard | #else
|
| 504 | 8a40a180 | bellard | T0 = 0;
|
| 505 | 8a40a180 | bellard | #endif
|
| 506 | 8a40a180 | bellard | } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) { |
| 507 | 8a40a180 | bellard | /* Raise it */
|
| 508 | 8a40a180 | bellard | env->exception_index = EXCP_DECR; |
| 509 | 8a40a180 | bellard | env->error_code = 0;
|
| 510 | 8a40a180 | bellard | do_interrupt(env); |
| 511 | 9fddaa0c | bellard | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
| 512 | fdbb4691 | bellard | #if defined(__sparc__) && !defined(HOST_SOLARIS)
|
| 513 | 8a40a180 | bellard | tmp_T0 = 0;
|
| 514 | 8a40a180 | bellard | #else
|
| 515 | 8a40a180 | bellard | T0 = 0;
|
| 516 | 8a40a180 | bellard | #endif
|
| 517 | 8a40a180 | bellard | } |
| 518 | ce09776b | bellard | } |
| 519 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
| 520 | 6af0bf9c | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD) &&
|
| 521 | 6af0bf9c | bellard | (env->CP0_Status & (1 << CP0St_IE)) &&
|
| 522 | 7ebab699 | bellard | (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
|
| 523 | 6af0bf9c | bellard | !(env->hflags & MIPS_HFLAG_EXL) && |
| 524 | 6af0bf9c | bellard | !(env->hflags & MIPS_HFLAG_ERL) && |
| 525 | 6af0bf9c | bellard | !(env->hflags & MIPS_HFLAG_DM)) {
|
| 526 | 6af0bf9c | bellard | /* Raise it */
|
| 527 | 6af0bf9c | bellard | env->exception_index = EXCP_EXT_INTERRUPT; |
| 528 | 6af0bf9c | bellard | env->error_code = 0;
|
| 529 | 6af0bf9c | bellard | do_interrupt(env); |
| 530 | 6af0bf9c | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
| 531 | fdbb4691 | bellard | #if defined(__sparc__) && !defined(HOST_SOLARIS)
|
| 532 | 8a40a180 | bellard | tmp_T0 = 0;
|
| 533 | 8a40a180 | bellard | #else
|
| 534 | 8a40a180 | bellard | T0 = 0;
|
| 535 | 8a40a180 | bellard | #endif
|
| 536 | 6af0bf9c | bellard | } |
| 537 | e95c8d51 | bellard | #elif defined(TARGET_SPARC)
|
| 538 | 66321a11 | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD) &&
|
| 539 | 66321a11 | bellard | (env->psret != 0)) {
|
| 540 | 66321a11 | bellard | int pil = env->interrupt_index & 15; |
| 541 | 66321a11 | bellard | int type = env->interrupt_index & 0xf0; |
| 542 | 66321a11 | bellard | |
| 543 | 66321a11 | bellard | if (((type == TT_EXTINT) &&
|
| 544 | 66321a11 | bellard | (pil == 15 || pil > env->psrpil)) ||
|
| 545 | 66321a11 | bellard | type != TT_EXTINT) {
|
| 546 | 66321a11 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
| 547 | 66321a11 | bellard | do_interrupt(env->interrupt_index); |
| 548 | 66321a11 | bellard | env->interrupt_index = 0;
|
| 549 | fdbb4691 | bellard | #if defined(__sparc__) && !defined(HOST_SOLARIS)
|
| 550 | 8a40a180 | bellard | tmp_T0 = 0;
|
| 551 | 8a40a180 | bellard | #else
|
| 552 | 8a40a180 | bellard | T0 = 0;
|
| 553 | 8a40a180 | bellard | #endif
|
| 554 | 66321a11 | bellard | } |
| 555 | e95c8d51 | bellard | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
| 556 | e95c8d51 | bellard | //do_interrupt(0, 0, 0, 0, 0);
|
| 557 | e95c8d51 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
| 558 | ba3c64fb | bellard | } else if (interrupt_request & CPU_INTERRUPT_HALT) { |
| 559 | df52b000 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HALT; |
| 560 | df52b000 | bellard | env->halted = 1;
|
| 561 | df52b000 | bellard | env->exception_index = EXCP_HLT; |
| 562 | df52b000 | bellard | cpu_loop_exit(); |
| 563 | ba3c64fb | bellard | } |
| 564 | b5ff1b31 | bellard | #elif defined(TARGET_ARM)
|
| 565 | b5ff1b31 | bellard | if (interrupt_request & CPU_INTERRUPT_FIQ
|
| 566 | b5ff1b31 | bellard | && !(env->uncached_cpsr & CPSR_F)) {
|
| 567 | b5ff1b31 | bellard | env->exception_index = EXCP_FIQ; |
| 568 | b5ff1b31 | bellard | do_interrupt(env); |
| 569 | b5ff1b31 | bellard | } |
| 570 | b5ff1b31 | bellard | if (interrupt_request & CPU_INTERRUPT_HARD
|
| 571 | b5ff1b31 | bellard | && !(env->uncached_cpsr & CPSR_I)) {
|
| 572 | b5ff1b31 | bellard | env->exception_index = EXCP_IRQ; |
| 573 | b5ff1b31 | bellard | do_interrupt(env); |
| 574 | b5ff1b31 | bellard | } |
| 575 | fdf9b3e8 | bellard | #elif defined(TARGET_SH4)
|
| 576 | fdf9b3e8 | bellard | /* XXXXX */
|
| 577 | 68a79315 | bellard | #endif
|
| 578 | 9d05095e | bellard | /* Don't use the cached interupt_request value,
|
| 579 | 9d05095e | bellard | do_interrupt may have updated the EXITTB flag. */
|
| 580 | b5ff1b31 | bellard | if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
|
| 581 | bf3e8bf1 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
| 582 | bf3e8bf1 | bellard | /* ensure that no TB jump will be modified as
|
| 583 | bf3e8bf1 | bellard | the program flow was changed */
|
| 584 | fdbb4691 | bellard | #if defined(__sparc__) && !defined(HOST_SOLARIS)
|
| 585 | bf3e8bf1 | bellard | tmp_T0 = 0;
|
| 586 | bf3e8bf1 | bellard | #else
|
| 587 | bf3e8bf1 | bellard | T0 = 0;
|
| 588 | bf3e8bf1 | bellard | #endif
|
| 589 | bf3e8bf1 | bellard | } |
| 590 | 68a79315 | bellard | if (interrupt_request & CPU_INTERRUPT_EXIT) {
|
| 591 | 68a79315 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
| 592 | 68a79315 | bellard | env->exception_index = EXCP_INTERRUPT; |
| 593 | 68a79315 | bellard | cpu_loop_exit(); |
| 594 | 68a79315 | bellard | } |
| 595 | 3fb2ded1 | bellard | } |
| 596 | 7d13299d | bellard | #ifdef DEBUG_EXEC
|
| 597 | b5ff1b31 | bellard | if ((loglevel & CPU_LOG_TB_CPU)) {
|
| 598 | e4533c7a | bellard | #if defined(TARGET_I386)
|
| 599 | 3fb2ded1 | bellard | /* restore flags in standard format */
|
| 600 | fc9f715d | bellard | #ifdef reg_EAX
|
| 601 | 3fb2ded1 | bellard | env->regs[R_EAX] = EAX; |
| 602 | fc9f715d | bellard | #endif
|
| 603 | fc9f715d | bellard | #ifdef reg_EBX
|
| 604 | 3fb2ded1 | bellard | env->regs[R_EBX] = EBX; |
| 605 | fc9f715d | bellard | #endif
|
| 606 | fc9f715d | bellard | #ifdef reg_ECX
|
| 607 | 3fb2ded1 | bellard | env->regs[R_ECX] = ECX; |
| 608 | fc9f715d | bellard | #endif
|
| 609 | fc9f715d | bellard | #ifdef reg_EDX
|
| 610 | 3fb2ded1 | bellard | env->regs[R_EDX] = EDX; |
| 611 | fc9f715d | bellard | #endif
|
| 612 | fc9f715d | bellard | #ifdef reg_ESI
|
| 613 | 3fb2ded1 | bellard | env->regs[R_ESI] = ESI; |
| 614 | fc9f715d | bellard | #endif
|
| 615 | fc9f715d | bellard | #ifdef reg_EDI
|
| 616 | 3fb2ded1 | bellard | env->regs[R_EDI] = EDI; |
| 617 | fc9f715d | bellard | #endif
|
| 618 | fc9f715d | bellard | #ifdef reg_EBP
|
| 619 | 3fb2ded1 | bellard | env->regs[R_EBP] = EBP; |
| 620 | fc9f715d | bellard | #endif
|
| 621 | fc9f715d | bellard | #ifdef reg_ESP
|
| 622 | 3fb2ded1 | bellard | env->regs[R_ESP] = ESP; |
| 623 | fc9f715d | bellard | #endif
|
| 624 | 3fb2ded1 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
| 625 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
| 626 | 3fb2ded1 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 627 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
| 628 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
| 629 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
| 630 | 3475187d | bellard | REGWPTR = env->regbase + (env->cwp * 16);
|
| 631 | 3475187d | bellard | env->regwptr = REGWPTR; |
| 632 | 3475187d | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
| 633 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
| 634 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
| 635 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
| 636 | 6af0bf9c | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
| 637 | fdf9b3e8 | bellard | #elif defined(TARGET_SH4)
|
| 638 | fdf9b3e8 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
| 639 | e4533c7a | bellard | #else
|
| 640 | e4533c7a | bellard | #error unsupported target CPU
|
| 641 | e4533c7a | bellard | #endif
|
| 642 | 3fb2ded1 | bellard | } |
| 643 | 7d13299d | bellard | #endif
|
| 644 | 8a40a180 | bellard | tb = tb_find_fast(); |
| 645 | 9d27abd9 | bellard | #ifdef DEBUG_EXEC
|
| 646 | c1135f61 | bellard | if ((loglevel & CPU_LOG_EXEC)) {
|
| 647 | c27004ec | bellard | fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
| 648 | c27004ec | bellard | (long)tb->tc_ptr, tb->pc,
|
| 649 | c27004ec | bellard | lookup_symbol(tb->pc)); |
| 650 | 3fb2ded1 | bellard | } |
| 651 | 9d27abd9 | bellard | #endif
|
| 652 | fdbb4691 | bellard | #if defined(__sparc__) && !defined(HOST_SOLARIS)
|
| 653 | 3fb2ded1 | bellard | T0 = tmp_T0; |
| 654 | 8c6939c0 | bellard | #endif
|
| 655 | 8a40a180 | bellard | /* see if we can patch the calling TB. When the TB
|
| 656 | 8a40a180 | bellard | spans two pages, we cannot safely do a direct
|
| 657 | 8a40a180 | bellard | jump. */
|
| 658 | c27004ec | bellard | {
|
| 659 | 8a40a180 | bellard | if (T0 != 0 && |
| 660 | f32fc648 | bellard | #if USE_KQEMU
|
| 661 | f32fc648 | bellard | (env->kqemu_enabled != 2) &&
|
| 662 | f32fc648 | bellard | #endif
|
| 663 | 8a40a180 | bellard | tb->page_addr[1] == -1 |
| 664 | bf3e8bf1 | bellard | #if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
| 665 | bf3e8bf1 | bellard | && (tb->cflags & CF_CODE_COPY) == |
| 666 | bf3e8bf1 | bellard | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
|
| 667 | bf3e8bf1 | bellard | #endif
|
| 668 | bf3e8bf1 | bellard | ) {
|
| 669 | 3fb2ded1 | bellard | spin_lock(&tb_lock); |
| 670 | c27004ec | bellard | tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
| 671 | 97eb5b14 | bellard | #if defined(USE_CODE_COPY)
|
| 672 | 97eb5b14 | bellard | /* propagates the FP use info */
|
| 673 | 97eb5b14 | bellard | ((TranslationBlock *)(T0 & ~3))->cflags |=
|
| 674 | 97eb5b14 | bellard | (tb->cflags & CF_FP_USED); |
| 675 | 97eb5b14 | bellard | #endif
|
| 676 | 3fb2ded1 | bellard | spin_unlock(&tb_lock); |
| 677 | 3fb2ded1 | bellard | } |
| 678 | c27004ec | bellard | } |
| 679 | 3fb2ded1 | bellard | tc_ptr = tb->tc_ptr; |
| 680 | 83479e77 | bellard | env->current_tb = tb; |
| 681 | 3fb2ded1 | bellard | /* execute the generated code */
|
| 682 | 3fb2ded1 | bellard | gen_func = (void *)tc_ptr;
|
| 683 | 8c6939c0 | bellard | #if defined(__sparc__)
|
| 684 | 3fb2ded1 | bellard | __asm__ __volatile__("call %0\n\t"
|
| 685 | 3fb2ded1 | bellard | "mov %%o7,%%i0"
|
| 686 | 3fb2ded1 | bellard | : /* no outputs */
|
| 687 | 3fb2ded1 | bellard | : "r" (gen_func)
|
| 688 | fdbb4691 | bellard | : "i0", "i1", "i2", "i3", "i4", "i5", |
| 689 | fdbb4691 | bellard | "l0", "l1", "l2", "l3", "l4", "l5", |
| 690 | fdbb4691 | bellard | "l6", "l7"); |
| 691 | 8c6939c0 | bellard | #elif defined(__arm__)
|
| 692 | 3fb2ded1 | bellard | asm volatile ("mov pc, %0\n\t" |
| 693 | 3fb2ded1 | bellard | ".global exec_loop\n\t"
|
| 694 | 3fb2ded1 | bellard | "exec_loop:\n\t"
|
| 695 | 3fb2ded1 | bellard | : /* no outputs */
|
| 696 | 3fb2ded1 | bellard | : "r" (gen_func)
|
| 697 | 3fb2ded1 | bellard | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
| 698 | bf3e8bf1 | bellard | #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
|
| 699 | bf3e8bf1 | bellard | {
|
| 700 | bf3e8bf1 | bellard | if (!(tb->cflags & CF_CODE_COPY)) {
|
| 701 | 97eb5b14 | bellard | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
|
| 702 | 97eb5b14 | bellard | save_native_fp_state(env); |
| 703 | 97eb5b14 | bellard | } |
| 704 | bf3e8bf1 | bellard | gen_func(); |
| 705 | bf3e8bf1 | bellard | } else {
|
| 706 | 97eb5b14 | bellard | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
|
| 707 | 97eb5b14 | bellard | restore_native_fp_state(env); |
| 708 | 97eb5b14 | bellard | } |
| 709 | bf3e8bf1 | bellard | /* we work with native eflags */
|
| 710 | bf3e8bf1 | bellard | CC_SRC = cc_table[CC_OP].compute_all(); |
| 711 | bf3e8bf1 | bellard | CC_OP = CC_OP_EFLAGS; |
| 712 | bf3e8bf1 | bellard | asm(".globl exec_loop\n" |
| 713 | bf3e8bf1 | bellard | "\n"
|
| 714 | bf3e8bf1 | bellard | "debug1:\n"
|
| 715 | bf3e8bf1 | bellard | " pushl %%ebp\n"
|
| 716 | bf3e8bf1 | bellard | " fs movl %10, %9\n"
|
| 717 | bf3e8bf1 | bellard | " fs movl %11, %%eax\n"
|
| 718 | bf3e8bf1 | bellard | " andl $0x400, %%eax\n"
|
| 719 | bf3e8bf1 | bellard | " fs orl %8, %%eax\n"
|
| 720 | bf3e8bf1 | bellard | " pushl %%eax\n"
|
| 721 | bf3e8bf1 | bellard | " popf\n"
|
| 722 | bf3e8bf1 | bellard | " fs movl %%esp, %12\n"
|
| 723 | bf3e8bf1 | bellard | " fs movl %0, %%eax\n"
|
| 724 | bf3e8bf1 | bellard | " fs movl %1, %%ecx\n"
|
| 725 | bf3e8bf1 | bellard | " fs movl %2, %%edx\n"
|
| 726 | bf3e8bf1 | bellard | " fs movl %3, %%ebx\n"
|
| 727 | bf3e8bf1 | bellard | " fs movl %4, %%esp\n"
|
| 728 | bf3e8bf1 | bellard | " fs movl %5, %%ebp\n"
|
| 729 | bf3e8bf1 | bellard | " fs movl %6, %%esi\n"
|
| 730 | bf3e8bf1 | bellard | " fs movl %7, %%edi\n"
|
| 731 | bf3e8bf1 | bellard | " fs jmp *%9\n"
|
| 732 | bf3e8bf1 | bellard | "exec_loop:\n"
|
| 733 | bf3e8bf1 | bellard | " fs movl %%esp, %4\n"
|
| 734 | bf3e8bf1 | bellard | " fs movl %12, %%esp\n"
|
| 735 | bf3e8bf1 | bellard | " fs movl %%eax, %0\n"
|
| 736 | bf3e8bf1 | bellard | " fs movl %%ecx, %1\n"
|
| 737 | bf3e8bf1 | bellard | " fs movl %%edx, %2\n"
|
| 738 | bf3e8bf1 | bellard | " fs movl %%ebx, %3\n"
|
| 739 | bf3e8bf1 | bellard | " fs movl %%ebp, %5\n"
|
| 740 | bf3e8bf1 | bellard | " fs movl %%esi, %6\n"
|
| 741 | bf3e8bf1 | bellard | " fs movl %%edi, %7\n"
|
| 742 | bf3e8bf1 | bellard | " pushf\n"
|
| 743 | bf3e8bf1 | bellard | " popl %%eax\n"
|
| 744 | bf3e8bf1 | bellard | " movl %%eax, %%ecx\n"
|
| 745 | bf3e8bf1 | bellard | " andl $0x400, %%ecx\n"
|
| 746 | bf3e8bf1 | bellard | " shrl $9, %%ecx\n"
|
| 747 | bf3e8bf1 | bellard | " andl $0x8d5, %%eax\n"
|
| 748 | bf3e8bf1 | bellard | " fs movl %%eax, %8\n"
|
| 749 | bf3e8bf1 | bellard | " movl $1, %%eax\n"
|
| 750 | bf3e8bf1 | bellard | " subl %%ecx, %%eax\n"
|
| 751 | bf3e8bf1 | bellard | " fs movl %%eax, %11\n"
|
| 752 | bf3e8bf1 | bellard | " fs movl %9, %%ebx\n" /* get T0 value */ |
| 753 | bf3e8bf1 | bellard | " popl %%ebp\n"
|
| 754 | bf3e8bf1 | bellard | : |
| 755 | bf3e8bf1 | bellard | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), |
| 756 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), |
| 757 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), |
| 758 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), |
| 759 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), |
| 760 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), |
| 761 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), |
| 762 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), |
| 763 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
|
| 764 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
|
| 765 | bf3e8bf1 | bellard | "a" (gen_func),
|
| 766 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, df)),
|
| 767 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
|
| 768 | bf3e8bf1 | bellard | : "%ecx", "%edx" |
| 769 | bf3e8bf1 | bellard | ); |
| 770 | bf3e8bf1 | bellard | } |
| 771 | bf3e8bf1 | bellard | } |
| 772 | b8076a74 | bellard | #elif defined(__ia64)
|
| 773 | b8076a74 | bellard | struct fptr {
|
| 774 | b8076a74 | bellard | void *ip;
|
| 775 | b8076a74 | bellard | void *gp;
|
| 776 | b8076a74 | bellard | } fp; |
| 777 | b8076a74 | bellard | |
| 778 | b8076a74 | bellard | fp.ip = tc_ptr; |
| 779 | b8076a74 | bellard | fp.gp = code_gen_buffer + 2 * (1 << 20); |
| 780 | b8076a74 | bellard | (*(void (*)(void)) &fp)(); |
| 781 | ae228531 | bellard | #else
|
| 782 | 3fb2ded1 | bellard | gen_func(); |
| 783 | ae228531 | bellard | #endif
|
| 784 | 83479e77 | bellard | env->current_tb = NULL;
|
| 785 | 4cbf74b6 | bellard | /* reset soft MMU for next block (it can currently
|
| 786 | 4cbf74b6 | bellard | only be set by a memory fault) */
|
| 787 | 4cbf74b6 | bellard | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
|
| 788 | 3f337316 | bellard | if (env->hflags & HF_SOFTMMU_MASK) {
|
| 789 | 3f337316 | bellard | env->hflags &= ~HF_SOFTMMU_MASK; |
| 790 | 4cbf74b6 | bellard | /* do not allow linking to another block */
|
| 791 | 4cbf74b6 | bellard | T0 = 0;
|
| 792 | 4cbf74b6 | bellard | } |
| 793 | 4cbf74b6 | bellard | #endif
|
| 794 | f32fc648 | bellard | #if defined(USE_KQEMU)
|
| 795 | f32fc648 | bellard | #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000) |
| 796 | f32fc648 | bellard | if (kqemu_is_ok(env) &&
|
| 797 | f32fc648 | bellard | (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
|
| 798 | f32fc648 | bellard | cpu_loop_exit(); |
| 799 | f32fc648 | bellard | } |
| 800 | f32fc648 | bellard | #endif
|
| 801 | 3fb2ded1 | bellard | } |
| 802 | 3fb2ded1 | bellard | } else {
|
| 803 | 0d1a29f9 | bellard | env_to_regs(); |
| 804 | 7d13299d | bellard | } |
| 805 | 3fb2ded1 | bellard | } /* for(;;) */
|
| 806 | 3fb2ded1 | bellard | |
| 807 | 7d13299d | bellard | |
| 808 | e4533c7a | bellard | #if defined(TARGET_I386)
|
| 809 | 97eb5b14 | bellard | #if defined(USE_CODE_COPY)
|
| 810 | 97eb5b14 | bellard | if (env->native_fp_regs) {
|
| 811 | 97eb5b14 | bellard | save_native_fp_state(env); |
| 812 | 97eb5b14 | bellard | } |
| 813 | 97eb5b14 | bellard | #endif
|
| 814 | 9de5e440 | bellard | /* restore flags in standard format */
|
| 815 | fc2b4c48 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
| 816 | 9de5e440 | bellard | |
| 817 | 7d13299d | bellard | /* restore global registers */
|
| 818 | 04369ff2 | bellard | #ifdef reg_EAX
|
| 819 | 04369ff2 | bellard | EAX = saved_EAX; |
| 820 | 04369ff2 | bellard | #endif
|
| 821 | 04369ff2 | bellard | #ifdef reg_ECX
|
| 822 | 04369ff2 | bellard | ECX = saved_ECX; |
| 823 | 04369ff2 | bellard | #endif
|
| 824 | 04369ff2 | bellard | #ifdef reg_EDX
|
| 825 | 04369ff2 | bellard | EDX = saved_EDX; |
| 826 | 04369ff2 | bellard | #endif
|
| 827 | 04369ff2 | bellard | #ifdef reg_EBX
|
| 828 | 04369ff2 | bellard | EBX = saved_EBX; |
| 829 | 04369ff2 | bellard | #endif
|
| 830 | 04369ff2 | bellard | #ifdef reg_ESP
|
| 831 | 04369ff2 | bellard | ESP = saved_ESP; |
| 832 | 04369ff2 | bellard | #endif
|
| 833 | 04369ff2 | bellard | #ifdef reg_EBP
|
| 834 | 04369ff2 | bellard | EBP = saved_EBP; |
| 835 | 04369ff2 | bellard | #endif
|
| 836 | 04369ff2 | bellard | #ifdef reg_ESI
|
| 837 | 04369ff2 | bellard | ESI = saved_ESI; |
| 838 | 04369ff2 | bellard | #endif
|
| 839 | 04369ff2 | bellard | #ifdef reg_EDI
|
| 840 | 04369ff2 | bellard | EDI = saved_EDI; |
| 841 | 04369ff2 | bellard | #endif
|
| 842 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
| 843 | b7bcbe95 | bellard | /* XXX: Save/restore host fpu exception state?. */
|
| 844 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
| 845 | 3475187d | bellard | #if defined(reg_REGWPTR)
|
| 846 | 3475187d | bellard | REGWPTR = saved_regwptr; |
| 847 | 3475187d | bellard | #endif
|
| 848 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
| 849 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
| 850 | fdf9b3e8 | bellard | #elif defined(TARGET_SH4)
|
| 851 | fdf9b3e8 | bellard | /* XXXXX */
|
| 852 | e4533c7a | bellard | #else
|
| 853 | e4533c7a | bellard | #error unsupported target CPU
|
| 854 | e4533c7a | bellard | #endif
|
| 855 | fdbb4691 | bellard | #if defined(__sparc__) && !defined(HOST_SOLARIS)
|
| 856 | 8c6939c0 | bellard | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
| 857 | 8c6939c0 | bellard | #endif
|
| 858 | 7d13299d | bellard | T0 = saved_T0; |
| 859 | 7d13299d | bellard | T1 = saved_T1; |
| 860 | 3475187d | bellard | #if defined(reg_T2)
|
| 861 | e4533c7a | bellard | T2 = saved_T2; |
| 862 | 3475187d | bellard | #endif
|
| 863 | 7d13299d | bellard | env = saved_env; |
| 864 | 6a00d601 | bellard | /* fail safe : never use cpu_single_env outside cpu_exec() */
|
| 865 | 6a00d601 | bellard | cpu_single_env = NULL;
|
| 866 | 7d13299d | bellard | return ret;
|
| 867 | 7d13299d | bellard | } |
| 868 | 6dbad63e | bellard | |
| 869 | fbf9eeb3 | bellard | /* must only be called from the generated code as an exception can be
|
| 870 | fbf9eeb3 | bellard | generated */
|
| 871 | fbf9eeb3 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end)
|
| 872 | fbf9eeb3 | bellard | {
|
| 873 | dc5d0b3d | bellard | /* XXX: cannot enable it yet because it yields to MMU exception
|
| 874 | dc5d0b3d | bellard | where NIP != read address on PowerPC */
|
| 875 | dc5d0b3d | bellard | #if 0
|
| 876 | fbf9eeb3 | bellard | target_ulong phys_addr;
|
| 877 | fbf9eeb3 | bellard | phys_addr = get_phys_addr_code(env, start);
|
| 878 | fbf9eeb3 | bellard | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
|
| 879 | dc5d0b3d | bellard | #endif
|
| 880 | fbf9eeb3 | bellard | } |
| 881 | fbf9eeb3 | bellard | |
| 882 | 1a18c71b | bellard | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
|
| 883 | e4533c7a | bellard | |
| 884 | 6dbad63e | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
| 885 | 6dbad63e | bellard | {
|
| 886 | 6dbad63e | bellard | CPUX86State *saved_env; |
| 887 | 6dbad63e | bellard | |
| 888 | 6dbad63e | bellard | saved_env = env; |
| 889 | 6dbad63e | bellard | env = s; |
| 890 | a412ac57 | bellard | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
| 891 | a513fe19 | bellard | selector &= 0xffff;
|
| 892 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, seg_reg, selector, |
| 893 | c27004ec | bellard | (selector << 4), 0xffff, 0); |
| 894 | a513fe19 | bellard | } else {
|
| 895 | b453b70b | bellard | load_seg(seg_reg, selector); |
| 896 | a513fe19 | bellard | } |
| 897 | 6dbad63e | bellard | env = saved_env; |
| 898 | 6dbad63e | bellard | } |
| 899 | 9de5e440 | bellard | |
| 900 | d0a1ffc9 | bellard | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
| 901 | d0a1ffc9 | bellard | {
|
| 902 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
| 903 | d0a1ffc9 | bellard | |
| 904 | d0a1ffc9 | bellard | saved_env = env; |
| 905 | d0a1ffc9 | bellard | env = s; |
| 906 | d0a1ffc9 | bellard | |
| 907 | c27004ec | bellard | helper_fsave((target_ulong)ptr, data32); |
| 908 | d0a1ffc9 | bellard | |
| 909 | d0a1ffc9 | bellard | env = saved_env; |
| 910 | d0a1ffc9 | bellard | } |
| 911 | d0a1ffc9 | bellard | |
| 912 | d0a1ffc9 | bellard | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
| 913 | d0a1ffc9 | bellard | {
|
| 914 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
| 915 | d0a1ffc9 | bellard | |
| 916 | d0a1ffc9 | bellard | saved_env = env; |
| 917 | d0a1ffc9 | bellard | env = s; |
| 918 | d0a1ffc9 | bellard | |
| 919 | c27004ec | bellard | helper_frstor((target_ulong)ptr, data32); |
| 920 | d0a1ffc9 | bellard | |
| 921 | d0a1ffc9 | bellard | env = saved_env; |
| 922 | d0a1ffc9 | bellard | } |
| 923 | d0a1ffc9 | bellard | |
| 924 | e4533c7a | bellard | #endif /* TARGET_I386 */ |
| 925 | e4533c7a | bellard | |
| 926 | 67b915a5 | bellard | #if !defined(CONFIG_SOFTMMU)
|
| 927 | 67b915a5 | bellard | |
| 928 | 3fb2ded1 | bellard | #if defined(TARGET_I386)
|
| 929 | 3fb2ded1 | bellard | |
| 930 | b56dad1c | bellard | /* 'pc' is the host PC at which the exception was raised. 'address' is
|
| 931 | fd6ce8f6 | bellard | the effective address of the memory exception. 'is_write' is 1 if a
|
| 932 | fd6ce8f6 | bellard | write caused the exception and otherwise 0'. 'old_set' is the
|
| 933 | fd6ce8f6 | bellard | signal set which should be restored */
|
| 934 | 2b413144 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 935 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
| 936 | bf3e8bf1 | bellard | void *puc)
|
| 937 | 9de5e440 | bellard | {
|
| 938 | a513fe19 | bellard | TranslationBlock *tb; |
| 939 | a513fe19 | bellard | int ret;
|
| 940 | 68a79315 | bellard | |
| 941 | 83479e77 | bellard | if (cpu_single_env)
|
| 942 | 83479e77 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
| 943 | fd6ce8f6 | bellard | #if defined(DEBUG_SIGNAL)
|
| 944 | bf3e8bf1 | bellard | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
| 945 | bf3e8bf1 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
| 946 | 9de5e440 | bellard | #endif
|
| 947 | 25eb4484 | bellard | /* XXX: locking issue */
|
| 948 | 53a5960a | pbrook | if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
| 949 | fd6ce8f6 | bellard | return 1; |
| 950 | fd6ce8f6 | bellard | } |
| 951 | fbf9eeb3 | bellard | |
| 952 | 3fb2ded1 | bellard | /* see if it is an MMU fault */
|
| 953 | 93a40ea9 | bellard | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
| 954 | 93a40ea9 | bellard | ((env->hflags & HF_CPL_MASK) == 3), 0); |
| 955 | 3fb2ded1 | bellard | if (ret < 0) |
| 956 | 3fb2ded1 | bellard | return 0; /* not an MMU fault */ |
| 957 | 3fb2ded1 | bellard | if (ret == 0) |
| 958 | 3fb2ded1 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 959 | 3fb2ded1 | bellard | /* now we have a real cpu fault */
|
| 960 | a513fe19 | bellard | tb = tb_find_pc(pc); |
| 961 | a513fe19 | bellard | if (tb) {
|
| 962 | 9de5e440 | bellard | /* the PC is inside the translated code. It means that we have
|
| 963 | 9de5e440 | bellard | a virtual CPU fault */
|
| 964 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, puc); |
| 965 | 3fb2ded1 | bellard | } |
| 966 | 4cbf74b6 | bellard | if (ret == 1) { |
| 967 | 3fb2ded1 | bellard | #if 0
|
| 968 | 4cbf74b6 | bellard | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
|
| 969 | 4cbf74b6 | bellard | env->eip, env->cr[2], env->error_code);
|
| 970 | 3fb2ded1 | bellard | #endif
|
| 971 | 4cbf74b6 | bellard | /* we restore the process signal mask as the sigreturn should
|
| 972 | 4cbf74b6 | bellard | do it (XXX: use sigsetjmp) */
|
| 973 | 4cbf74b6 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
| 974 | 54ca9095 | bellard | raise_exception_err(env->exception_index, env->error_code); |
| 975 | 4cbf74b6 | bellard | } else {
|
| 976 | 4cbf74b6 | bellard | /* activate soft MMU for this block */
|
| 977 | 3f337316 | bellard | env->hflags |= HF_SOFTMMU_MASK; |
| 978 | fbf9eeb3 | bellard | cpu_resume_from_signal(env, puc); |
| 979 | 4cbf74b6 | bellard | } |
| 980 | 3fb2ded1 | bellard | /* never comes here */
|
| 981 | 3fb2ded1 | bellard | return 1; |
| 982 | 3fb2ded1 | bellard | } |
| 983 | 3fb2ded1 | bellard | |
| 984 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
| 985 | 3fb2ded1 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 986 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
| 987 | bf3e8bf1 | bellard | void *puc)
|
| 988 | 3fb2ded1 | bellard | {
|
| 989 | 68016c62 | bellard | TranslationBlock *tb; |
| 990 | 68016c62 | bellard | int ret;
|
| 991 | 68016c62 | bellard | |
| 992 | 68016c62 | bellard | if (cpu_single_env)
|
| 993 | 68016c62 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
| 994 | 68016c62 | bellard | #if defined(DEBUG_SIGNAL)
|
| 995 | 68016c62 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
| 996 | 68016c62 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
| 997 | 68016c62 | bellard | #endif
|
| 998 | 9f0777ed | bellard | /* XXX: locking issue */
|
| 999 | 53a5960a | pbrook | if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
| 1000 | 9f0777ed | bellard | return 1; |
| 1001 | 9f0777ed | bellard | } |
| 1002 | 68016c62 | bellard | /* see if it is an MMU fault */
|
| 1003 | 68016c62 | bellard | ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0); |
| 1004 | 68016c62 | bellard | if (ret < 0) |
| 1005 | 68016c62 | bellard | return 0; /* not an MMU fault */ |
| 1006 | 68016c62 | bellard | if (ret == 0) |
| 1007 | 68016c62 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1008 | 68016c62 | bellard | /* now we have a real cpu fault */
|
| 1009 | 68016c62 | bellard | tb = tb_find_pc(pc); |
| 1010 | 68016c62 | bellard | if (tb) {
|
| 1011 | 68016c62 | bellard | /* the PC is inside the translated code. It means that we have
|
| 1012 | 68016c62 | bellard | a virtual CPU fault */
|
| 1013 | 68016c62 | bellard | cpu_restore_state(tb, env, pc, puc); |
| 1014 | 68016c62 | bellard | } |
| 1015 | 68016c62 | bellard | /* we restore the process signal mask as the sigreturn should
|
| 1016 | 68016c62 | bellard | do it (XXX: use sigsetjmp) */
|
| 1017 | 68016c62 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
| 1018 | 68016c62 | bellard | cpu_loop_exit(); |
| 1019 | 3fb2ded1 | bellard | } |
| 1020 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
| 1021 | 93ac68bc | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1022 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
| 1023 | bf3e8bf1 | bellard | void *puc)
|
| 1024 | 93ac68bc | bellard | {
|
| 1025 | 68016c62 | bellard | TranslationBlock *tb; |
| 1026 | 68016c62 | bellard | int ret;
|
| 1027 | 68016c62 | bellard | |
| 1028 | 68016c62 | bellard | if (cpu_single_env)
|
| 1029 | 68016c62 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
| 1030 | 68016c62 | bellard | #if defined(DEBUG_SIGNAL)
|
| 1031 | 68016c62 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
| 1032 | 68016c62 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
| 1033 | 68016c62 | bellard | #endif
|
| 1034 | b453b70b | bellard | /* XXX: locking issue */
|
| 1035 | 53a5960a | pbrook | if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
| 1036 | b453b70b | bellard | return 1; |
| 1037 | b453b70b | bellard | } |
| 1038 | 68016c62 | bellard | /* see if it is an MMU fault */
|
| 1039 | 68016c62 | bellard | ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0); |
| 1040 | 68016c62 | bellard | if (ret < 0) |
| 1041 | 68016c62 | bellard | return 0; /* not an MMU fault */ |
| 1042 | 68016c62 | bellard | if (ret == 0) |
| 1043 | 68016c62 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1044 | 68016c62 | bellard | /* now we have a real cpu fault */
|
| 1045 | 68016c62 | bellard | tb = tb_find_pc(pc); |
| 1046 | 68016c62 | bellard | if (tb) {
|
| 1047 | 68016c62 | bellard | /* the PC is inside the translated code. It means that we have
|
| 1048 | 68016c62 | bellard | a virtual CPU fault */
|
| 1049 | 68016c62 | bellard | cpu_restore_state(tb, env, pc, puc); |
| 1050 | 68016c62 | bellard | } |
| 1051 | 68016c62 | bellard | /* we restore the process signal mask as the sigreturn should
|
| 1052 | 68016c62 | bellard | do it (XXX: use sigsetjmp) */
|
| 1053 | 68016c62 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
| 1054 | 68016c62 | bellard | cpu_loop_exit(); |
| 1055 | 93ac68bc | bellard | } |
| 1056 | 67867308 | bellard | #elif defined (TARGET_PPC)
|
| 1057 | 67867308 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1058 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
| 1059 | bf3e8bf1 | bellard | void *puc)
|
| 1060 | 67867308 | bellard | {
|
| 1061 | 67867308 | bellard | TranslationBlock *tb; |
| 1062 | ce09776b | bellard | int ret;
|
| 1063 | 67867308 | bellard | |
| 1064 | 67867308 | bellard | if (cpu_single_env)
|
| 1065 | 67867308 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
| 1066 | 67867308 | bellard | #if defined(DEBUG_SIGNAL)
|
| 1067 | 67867308 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
| 1068 | 67867308 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
| 1069 | 67867308 | bellard | #endif
|
| 1070 | 67867308 | bellard | /* XXX: locking issue */
|
| 1071 | 53a5960a | pbrook | if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
| 1072 | 67867308 | bellard | return 1; |
| 1073 | 67867308 | bellard | } |
| 1074 | 67867308 | bellard | |
| 1075 | ce09776b | bellard | /* see if it is an MMU fault */
|
| 1076 | 7f957d28 | bellard | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
|
| 1077 | ce09776b | bellard | if (ret < 0) |
| 1078 | ce09776b | bellard | return 0; /* not an MMU fault */ |
| 1079 | ce09776b | bellard | if (ret == 0) |
| 1080 | ce09776b | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1081 | ce09776b | bellard | |
| 1082 | 67867308 | bellard | /* now we have a real cpu fault */
|
| 1083 | 67867308 | bellard | tb = tb_find_pc(pc); |
| 1084 | 67867308 | bellard | if (tb) {
|
| 1085 | 67867308 | bellard | /* the PC is inside the translated code. It means that we have
|
| 1086 | 67867308 | bellard | a virtual CPU fault */
|
| 1087 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, puc); |
| 1088 | 67867308 | bellard | } |
| 1089 | ce09776b | bellard | if (ret == 1) { |
| 1090 | 67867308 | bellard | #if 0
|
| 1091 | ce09776b | bellard | printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
| 1092 | ce09776b | bellard | env->nip, env->error_code, tb);
|
| 1093 | 67867308 | bellard | #endif
|
| 1094 | 67867308 | bellard | /* we restore the process signal mask as the sigreturn should
|
| 1095 | 67867308 | bellard | do it (XXX: use sigsetjmp) */
|
| 1096 | bf3e8bf1 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
| 1097 | 9fddaa0c | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
| 1098 | ce09776b | bellard | } else {
|
| 1099 | ce09776b | bellard | /* activate soft MMU for this block */
|
| 1100 | fbf9eeb3 | bellard | cpu_resume_from_signal(env, puc); |
| 1101 | ce09776b | bellard | } |
| 1102 | 67867308 | bellard | /* never comes here */
|
| 1103 | 67867308 | bellard | return 1; |
| 1104 | 67867308 | bellard | } |
| 1105 | 6af0bf9c | bellard | |
| 1106 | 6af0bf9c | bellard | #elif defined (TARGET_MIPS)
|
| 1107 | 6af0bf9c | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1108 | 6af0bf9c | bellard | int is_write, sigset_t *old_set,
|
| 1109 | 6af0bf9c | bellard | void *puc)
|
| 1110 | 6af0bf9c | bellard | {
|
| 1111 | 6af0bf9c | bellard | TranslationBlock *tb; |
| 1112 | 6af0bf9c | bellard | int ret;
|
| 1113 | 6af0bf9c | bellard | |
| 1114 | 6af0bf9c | bellard | if (cpu_single_env)
|
| 1115 | 6af0bf9c | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
| 1116 | 6af0bf9c | bellard | #if defined(DEBUG_SIGNAL)
|
| 1117 | 6af0bf9c | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
| 1118 | 6af0bf9c | bellard | pc, address, is_write, *(unsigned long *)old_set); |
| 1119 | 6af0bf9c | bellard | #endif
|
| 1120 | 6af0bf9c | bellard | /* XXX: locking issue */
|
| 1121 | 53a5960a | pbrook | if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
| 1122 | 6af0bf9c | bellard | return 1; |
| 1123 | 6af0bf9c | bellard | } |
| 1124 | 6af0bf9c | bellard | |
| 1125 | 6af0bf9c | bellard | /* see if it is an MMU fault */
|
| 1126 | cc9442b9 | bellard | ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0); |
| 1127 | 6af0bf9c | bellard | if (ret < 0) |
| 1128 | 6af0bf9c | bellard | return 0; /* not an MMU fault */ |
| 1129 | 6af0bf9c | bellard | if (ret == 0) |
| 1130 | 6af0bf9c | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1131 | 6af0bf9c | bellard | |
| 1132 | 6af0bf9c | bellard | /* now we have a real cpu fault */
|
| 1133 | 6af0bf9c | bellard | tb = tb_find_pc(pc); |
| 1134 | 6af0bf9c | bellard | if (tb) {
|
| 1135 | 6af0bf9c | bellard | /* the PC is inside the translated code. It means that we have
|
| 1136 | 6af0bf9c | bellard | a virtual CPU fault */
|
| 1137 | 6af0bf9c | bellard | cpu_restore_state(tb, env, pc, puc); |
| 1138 | 6af0bf9c | bellard | } |
| 1139 | 6af0bf9c | bellard | if (ret == 1) { |
| 1140 | 6af0bf9c | bellard | #if 0
|
| 1141 | 6af0bf9c | bellard | printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
| 1142 | 6af0bf9c | bellard | env->nip, env->error_code, tb);
|
| 1143 | 6af0bf9c | bellard | #endif
|
| 1144 | 6af0bf9c | bellard | /* we restore the process signal mask as the sigreturn should
|
| 1145 | 6af0bf9c | bellard | do it (XXX: use sigsetjmp) */
|
| 1146 | 6af0bf9c | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
| 1147 | 6af0bf9c | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
| 1148 | 6af0bf9c | bellard | } else {
|
| 1149 | 6af0bf9c | bellard | /* activate soft MMU for this block */
|
| 1150 | 6af0bf9c | bellard | cpu_resume_from_signal(env, puc); |
| 1151 | 6af0bf9c | bellard | } |
| 1152 | 6af0bf9c | bellard | /* never comes here */
|
| 1153 | 6af0bf9c | bellard | return 1; |
| 1154 | 6af0bf9c | bellard | } |
| 1155 | 6af0bf9c | bellard | |
| 1156 | fdf9b3e8 | bellard | #elif defined (TARGET_SH4)
|
| 1157 | fdf9b3e8 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1158 | fdf9b3e8 | bellard | int is_write, sigset_t *old_set,
|
| 1159 | fdf9b3e8 | bellard | void *puc)
|
| 1160 | fdf9b3e8 | bellard | {
|
| 1161 | fdf9b3e8 | bellard | TranslationBlock *tb; |
| 1162 | fdf9b3e8 | bellard | int ret;
|
| 1163 | fdf9b3e8 | bellard | |
| 1164 | fdf9b3e8 | bellard | if (cpu_single_env)
|
| 1165 | fdf9b3e8 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
| 1166 | fdf9b3e8 | bellard | #if defined(DEBUG_SIGNAL)
|
| 1167 | fdf9b3e8 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
| 1168 | fdf9b3e8 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
| 1169 | fdf9b3e8 | bellard | #endif
|
| 1170 | fdf9b3e8 | bellard | /* XXX: locking issue */
|
| 1171 | fdf9b3e8 | bellard | if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
| 1172 | fdf9b3e8 | bellard | return 1; |
| 1173 | fdf9b3e8 | bellard | } |
| 1174 | fdf9b3e8 | bellard | |
| 1175 | fdf9b3e8 | bellard | /* see if it is an MMU fault */
|
| 1176 | fdf9b3e8 | bellard | ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0); |
| 1177 | fdf9b3e8 | bellard | if (ret < 0) |
| 1178 | fdf9b3e8 | bellard | return 0; /* not an MMU fault */ |
| 1179 | fdf9b3e8 | bellard | if (ret == 0) |
| 1180 | fdf9b3e8 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1181 | fdf9b3e8 | bellard | |
| 1182 | fdf9b3e8 | bellard | /* now we have a real cpu fault */
|
| 1183 | fdf9b3e8 | bellard | tb = tb_find_pc(pc); |
| 1184 | fdf9b3e8 | bellard | if (tb) {
|
| 1185 | fdf9b3e8 | bellard | /* the PC is inside the translated code. It means that we have
|
| 1186 | fdf9b3e8 | bellard | a virtual CPU fault */
|
| 1187 | fdf9b3e8 | bellard | cpu_restore_state(tb, env, pc, puc); |
| 1188 | fdf9b3e8 | bellard | } |
| 1189 | fdf9b3e8 | bellard | #if 0
|
| 1190 | fdf9b3e8 | bellard | printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
| 1191 | fdf9b3e8 | bellard | env->nip, env->error_code, tb);
|
| 1192 | fdf9b3e8 | bellard | #endif
|
| 1193 | fdf9b3e8 | bellard | /* we restore the process signal mask as the sigreturn should
|
| 1194 | fdf9b3e8 | bellard | do it (XXX: use sigsetjmp) */
|
| 1195 | 355fb23d | pbrook | sigprocmask(SIG_SETMASK, old_set, NULL);
|
| 1196 | 355fb23d | pbrook | cpu_loop_exit(); |
| 1197 | fdf9b3e8 | bellard | /* never comes here */
|
| 1198 | fdf9b3e8 | bellard | return 1; |
| 1199 | fdf9b3e8 | bellard | } |
| 1200 | e4533c7a | bellard | #else
|
| 1201 | e4533c7a | bellard | #error unsupported target CPU
|
| 1202 | e4533c7a | bellard | #endif
|
| 1203 | 9de5e440 | bellard | |
| 1204 | 2b413144 | bellard | #if defined(__i386__)
|
| 1205 | 2b413144 | bellard | |
| 1206 | bf3e8bf1 | bellard | #if defined(USE_CODE_COPY)
|
| 1207 | bf3e8bf1 | bellard | static void cpu_send_trap(unsigned long pc, int trap, |
| 1208 | bf3e8bf1 | bellard | struct ucontext *uc)
|
| 1209 | bf3e8bf1 | bellard | {
|
| 1210 | bf3e8bf1 | bellard | TranslationBlock *tb; |
| 1211 | bf3e8bf1 | bellard | |
| 1212 | bf3e8bf1 | bellard | if (cpu_single_env)
|
| 1213 | bf3e8bf1 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
| 1214 | bf3e8bf1 | bellard | /* now we have a real cpu fault */
|
| 1215 | bf3e8bf1 | bellard | tb = tb_find_pc(pc); |
| 1216 | bf3e8bf1 | bellard | if (tb) {
|
| 1217 | bf3e8bf1 | bellard | /* the PC is inside the translated code. It means that we have
|
| 1218 | bf3e8bf1 | bellard | a virtual CPU fault */
|
| 1219 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, uc); |
| 1220 | bf3e8bf1 | bellard | } |
| 1221 | bf3e8bf1 | bellard | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
|
| 1222 | bf3e8bf1 | bellard | raise_exception_err(trap, env->error_code); |
| 1223 | bf3e8bf1 | bellard | } |
| 1224 | bf3e8bf1 | bellard | #endif
|
| 1225 | bf3e8bf1 | bellard | |
| 1226 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 1227 | e4533c7a | bellard | void *puc)
|
| 1228 | 9de5e440 | bellard | {
|
| 1229 | 9de5e440 | bellard | struct ucontext *uc = puc;
|
| 1230 | 9de5e440 | bellard | unsigned long pc; |
| 1231 | bf3e8bf1 | bellard | int trapno;
|
| 1232 | 97eb5b14 | bellard | |
| 1233 | d691f669 | bellard | #ifndef REG_EIP
|
| 1234 | d691f669 | bellard | /* for glibc 2.1 */
|
| 1235 | fd6ce8f6 | bellard | #define REG_EIP EIP
|
| 1236 | fd6ce8f6 | bellard | #define REG_ERR ERR
|
| 1237 | fd6ce8f6 | bellard | #define REG_TRAPNO TRAPNO
|
| 1238 | d691f669 | bellard | #endif
|
| 1239 | fc2b4c48 | bellard | pc = uc->uc_mcontext.gregs[REG_EIP]; |
| 1240 | bf3e8bf1 | bellard | trapno = uc->uc_mcontext.gregs[REG_TRAPNO]; |
| 1241 | bf3e8bf1 | bellard | #if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
| 1242 | bf3e8bf1 | bellard | if (trapno == 0x00 || trapno == 0x05) { |
| 1243 | bf3e8bf1 | bellard | /* send division by zero or bound exception */
|
| 1244 | bf3e8bf1 | bellard | cpu_send_trap(pc, trapno, uc); |
| 1245 | bf3e8bf1 | bellard | return 1; |
| 1246 | bf3e8bf1 | bellard | } else
|
| 1247 | bf3e8bf1 | bellard | #endif
|
| 1248 | bf3e8bf1 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1249 | bf3e8bf1 | bellard | trapno == 0xe ?
|
| 1250 | bf3e8bf1 | bellard | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
| 1251 | bf3e8bf1 | bellard | &uc->uc_sigmask, puc); |
| 1252 | 2b413144 | bellard | } |
| 1253 | 2b413144 | bellard | |
| 1254 | bc51c5c9 | bellard | #elif defined(__x86_64__)
|
| 1255 | bc51c5c9 | bellard | |
| 1256 | bc51c5c9 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 1257 | bc51c5c9 | bellard | void *puc)
|
| 1258 | bc51c5c9 | bellard | {
|
| 1259 | bc51c5c9 | bellard | struct ucontext *uc = puc;
|
| 1260 | bc51c5c9 | bellard | unsigned long pc; |
| 1261 | bc51c5c9 | bellard | |
| 1262 | bc51c5c9 | bellard | pc = uc->uc_mcontext.gregs[REG_RIP]; |
| 1263 | bc51c5c9 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1264 | bc51c5c9 | bellard | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
|
| 1265 | bc51c5c9 | bellard | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
| 1266 | bc51c5c9 | bellard | &uc->uc_sigmask, puc); |
| 1267 | bc51c5c9 | bellard | } |
| 1268 | bc51c5c9 | bellard | |
| 1269 | 83fb7adf | bellard | #elif defined(__powerpc__)
|
| 1270 | 2b413144 | bellard | |
| 1271 | 83fb7adf | bellard | /***********************************************************************
|
| 1272 | 83fb7adf | bellard | * signal context platform-specific definitions
|
| 1273 | 83fb7adf | bellard | * From Wine
|
| 1274 | 83fb7adf | bellard | */
|
| 1275 | 83fb7adf | bellard | #ifdef linux
|
| 1276 | 83fb7adf | bellard | /* All Registers access - only for local access */
|
| 1277 | 83fb7adf | bellard | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
|
| 1278 | 83fb7adf | bellard | /* Gpr Registers access */
|
| 1279 | 83fb7adf | bellard | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
|
| 1280 | 83fb7adf | bellard | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ |
| 1281 | 83fb7adf | bellard | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ |
| 1282 | 83fb7adf | bellard | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ |
| 1283 | 83fb7adf | bellard | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ |
| 1284 | 83fb7adf | bellard | # define LR_sig(context) REG_sig(link, context) /* Link register */ |
| 1285 | 83fb7adf | bellard | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ |
| 1286 | 83fb7adf | bellard | /* Float Registers access */
|
| 1287 | 83fb7adf | bellard | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) |
| 1288 | 83fb7adf | bellard | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) |
| 1289 | 83fb7adf | bellard | /* Exception Registers access */
|
| 1290 | 83fb7adf | bellard | # define DAR_sig(context) REG_sig(dar, context)
|
| 1291 | 83fb7adf | bellard | # define DSISR_sig(context) REG_sig(dsisr, context)
|
| 1292 | 83fb7adf | bellard | # define TRAP_sig(context) REG_sig(trap, context)
|
| 1293 | 83fb7adf | bellard | #endif /* linux */ |
| 1294 | 83fb7adf | bellard | |
| 1295 | 83fb7adf | bellard | #ifdef __APPLE__
|
| 1296 | 83fb7adf | bellard | # include <sys/ucontext.h> |
| 1297 | 83fb7adf | bellard | typedef struct ucontext SIGCONTEXT; |
| 1298 | 83fb7adf | bellard | /* All Registers access - only for local access */
|
| 1299 | 83fb7adf | bellard | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
|
| 1300 | 83fb7adf | bellard | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
|
| 1301 | 83fb7adf | bellard | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
|
| 1302 | 83fb7adf | bellard | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
|
| 1303 | 83fb7adf | bellard | /* Gpr Registers access */
|
| 1304 | 83fb7adf | bellard | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
| 1305 | 83fb7adf | bellard | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ |
| 1306 | 83fb7adf | bellard | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ |
| 1307 | 83fb7adf | bellard | # define CTR_sig(context) REG_sig(ctr, context)
|
| 1308 | 83fb7adf | bellard | # define XER_sig(context) REG_sig(xer, context) /* Link register */ |
| 1309 | 83fb7adf | bellard | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ |
| 1310 | 83fb7adf | bellard | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ |
| 1311 | 83fb7adf | bellard | /* Float Registers access */
|
| 1312 | 83fb7adf | bellard | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
|
| 1313 | 83fb7adf | bellard | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) |
| 1314 | 83fb7adf | bellard | /* Exception Registers access */
|
| 1315 | 83fb7adf | bellard | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ |
| 1316 | 83fb7adf | bellard | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
|
| 1317 | 83fb7adf | bellard | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ |
| 1318 | 83fb7adf | bellard | #endif /* __APPLE__ */ |
| 1319 | 83fb7adf | bellard | |
| 1320 | d1d9f421 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 1321 | e4533c7a | bellard | void *puc)
|
| 1322 | 2b413144 | bellard | {
|
| 1323 | 25eb4484 | bellard | struct ucontext *uc = puc;
|
| 1324 | 25eb4484 | bellard | unsigned long pc; |
| 1325 | 25eb4484 | bellard | int is_write;
|
| 1326 | 25eb4484 | bellard | |
| 1327 | 83fb7adf | bellard | pc = IAR_sig(uc); |
| 1328 | 25eb4484 | bellard | is_write = 0;
|
| 1329 | 25eb4484 | bellard | #if 0
|
| 1330 | 25eb4484 | bellard | /* ppc 4xx case */
|
| 1331 | 83fb7adf | bellard | if (DSISR_sig(uc) & 0x00800000)
|
| 1332 | 25eb4484 | bellard | is_write = 1;
|
| 1333 | 25eb4484 | bellard | #else
|
| 1334 | 83fb7adf | bellard | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
| 1335 | 25eb4484 | bellard | is_write = 1;
|
| 1336 | 25eb4484 | bellard | #endif
|
| 1337 | 25eb4484 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1338 | bf3e8bf1 | bellard | is_write, &uc->uc_sigmask, puc); |
| 1339 | 2b413144 | bellard | } |
| 1340 | 2b413144 | bellard | |
| 1341 | 2f87c607 | bellard | #elif defined(__alpha__)
|
| 1342 | 2f87c607 | bellard | |
| 1343 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 1344 | 2f87c607 | bellard | void *puc)
|
| 1345 | 2f87c607 | bellard | {
|
| 1346 | 2f87c607 | bellard | struct ucontext *uc = puc;
|
| 1347 | 2f87c607 | bellard | uint32_t *pc = uc->uc_mcontext.sc_pc; |
| 1348 | 2f87c607 | bellard | uint32_t insn = *pc; |
| 1349 | 2f87c607 | bellard | int is_write = 0; |
| 1350 | 2f87c607 | bellard | |
| 1351 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
| 1352 | 2f87c607 | bellard | switch (insn >> 26) { |
| 1353 | 2f87c607 | bellard | case 0x0d: // stw |
| 1354 | 2f87c607 | bellard | case 0x0e: // stb |
| 1355 | 2f87c607 | bellard | case 0x0f: // stq_u |
| 1356 | 2f87c607 | bellard | case 0x24: // stf |
| 1357 | 2f87c607 | bellard | case 0x25: // stg |
| 1358 | 2f87c607 | bellard | case 0x26: // sts |
| 1359 | 2f87c607 | bellard | case 0x27: // stt |
| 1360 | 2f87c607 | bellard | case 0x2c: // stl |
| 1361 | 2f87c607 | bellard | case 0x2d: // stq |
| 1362 | 2f87c607 | bellard | case 0x2e: // stl_c |
| 1363 | 2f87c607 | bellard | case 0x2f: // stq_c |
| 1364 | 2f87c607 | bellard | is_write = 1;
|
| 1365 | 2f87c607 | bellard | } |
| 1366 | 2f87c607 | bellard | |
| 1367 | 2f87c607 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1368 | bf3e8bf1 | bellard | is_write, &uc->uc_sigmask, puc); |
| 1369 | 2f87c607 | bellard | } |
| 1370 | 8c6939c0 | bellard | #elif defined(__sparc__)
|
| 1371 | 8c6939c0 | bellard | |
| 1372 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 1373 | e4533c7a | bellard | void *puc)
|
| 1374 | 8c6939c0 | bellard | {
|
| 1375 | 8c6939c0 | bellard | uint32_t *regs = (uint32_t *)(info + 1);
|
| 1376 | 8c6939c0 | bellard | void *sigmask = (regs + 20); |
| 1377 | 8c6939c0 | bellard | unsigned long pc; |
| 1378 | 8c6939c0 | bellard | int is_write;
|
| 1379 | 8c6939c0 | bellard | uint32_t insn; |
| 1380 | 8c6939c0 | bellard | |
| 1381 | 8c6939c0 | bellard | /* XXX: is there a standard glibc define ? */
|
| 1382 | 8c6939c0 | bellard | pc = regs[1];
|
| 1383 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
| 1384 | 8c6939c0 | bellard | is_write = 0;
|
| 1385 | 8c6939c0 | bellard | insn = *(uint32_t *)pc; |
| 1386 | 8c6939c0 | bellard | if ((insn >> 30) == 3) { |
| 1387 | 8c6939c0 | bellard | switch((insn >> 19) & 0x3f) { |
| 1388 | 8c6939c0 | bellard | case 0x05: // stb |
| 1389 | 8c6939c0 | bellard | case 0x06: // sth |
| 1390 | 8c6939c0 | bellard | case 0x04: // st |
| 1391 | 8c6939c0 | bellard | case 0x07: // std |
| 1392 | 8c6939c0 | bellard | case 0x24: // stf |
| 1393 | 8c6939c0 | bellard | case 0x27: // stdf |
| 1394 | 8c6939c0 | bellard | case 0x25: // stfsr |
| 1395 | 8c6939c0 | bellard | is_write = 1;
|
| 1396 | 8c6939c0 | bellard | break;
|
| 1397 | 8c6939c0 | bellard | } |
| 1398 | 8c6939c0 | bellard | } |
| 1399 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1400 | bf3e8bf1 | bellard | is_write, sigmask, NULL);
|
| 1401 | 8c6939c0 | bellard | } |
| 1402 | 8c6939c0 | bellard | |
| 1403 | 8c6939c0 | bellard | #elif defined(__arm__)
|
| 1404 | 8c6939c0 | bellard | |
| 1405 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 1406 | e4533c7a | bellard | void *puc)
|
| 1407 | 8c6939c0 | bellard | {
|
| 1408 | 8c6939c0 | bellard | struct ucontext *uc = puc;
|
| 1409 | 8c6939c0 | bellard | unsigned long pc; |
| 1410 | 8c6939c0 | bellard | int is_write;
|
| 1411 | 8c6939c0 | bellard | |
| 1412 | 8c6939c0 | bellard | pc = uc->uc_mcontext.gregs[R15]; |
| 1413 | 8c6939c0 | bellard | /* XXX: compute is_write */
|
| 1414 | 8c6939c0 | bellard | is_write = 0;
|
| 1415 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1416 | 8c6939c0 | bellard | is_write, |
| 1417 | f3a9676a | pbrook | &uc->uc_sigmask, puc); |
| 1418 | 8c6939c0 | bellard | } |
| 1419 | 8c6939c0 | bellard | |
| 1420 | 38e584a0 | bellard | #elif defined(__mc68000)
|
| 1421 | 38e584a0 | bellard | |
| 1422 | 38e584a0 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 1423 | 38e584a0 | bellard | void *puc)
|
| 1424 | 38e584a0 | bellard | {
|
| 1425 | 38e584a0 | bellard | struct ucontext *uc = puc;
|
| 1426 | 38e584a0 | bellard | unsigned long pc; |
| 1427 | 38e584a0 | bellard | int is_write;
|
| 1428 | 38e584a0 | bellard | |
| 1429 | 38e584a0 | bellard | pc = uc->uc_mcontext.gregs[16];
|
| 1430 | 38e584a0 | bellard | /* XXX: compute is_write */
|
| 1431 | 38e584a0 | bellard | is_write = 0;
|
| 1432 | 38e584a0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1433 | 38e584a0 | bellard | is_write, |
| 1434 | bf3e8bf1 | bellard | &uc->uc_sigmask, puc); |
| 1435 | 38e584a0 | bellard | } |
| 1436 | 38e584a0 | bellard | |
| 1437 | b8076a74 | bellard | #elif defined(__ia64)
|
| 1438 | b8076a74 | bellard | |
| 1439 | b8076a74 | bellard | #ifndef __ISR_VALID
|
| 1440 | b8076a74 | bellard | /* This ought to be in <bits/siginfo.h>... */
|
| 1441 | b8076a74 | bellard | # define __ISR_VALID 1 |
| 1442 | b8076a74 | bellard | #endif
|
| 1443 | b8076a74 | bellard | |
| 1444 | b8076a74 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc) |
| 1445 | b8076a74 | bellard | {
|
| 1446 | b8076a74 | bellard | struct ucontext *uc = puc;
|
| 1447 | b8076a74 | bellard | unsigned long ip; |
| 1448 | b8076a74 | bellard | int is_write = 0; |
| 1449 | b8076a74 | bellard | |
| 1450 | b8076a74 | bellard | ip = uc->uc_mcontext.sc_ip; |
| 1451 | b8076a74 | bellard | switch (host_signum) {
|
| 1452 | b8076a74 | bellard | case SIGILL:
|
| 1453 | b8076a74 | bellard | case SIGFPE:
|
| 1454 | b8076a74 | bellard | case SIGSEGV:
|
| 1455 | b8076a74 | bellard | case SIGBUS:
|
| 1456 | b8076a74 | bellard | case SIGTRAP:
|
| 1457 | fd4a43e4 | bellard | if (info->si_code && (info->si_segvflags & __ISR_VALID))
|
| 1458 | b8076a74 | bellard | /* ISR.W (write-access) is bit 33: */
|
| 1459 | b8076a74 | bellard | is_write = (info->si_isr >> 33) & 1; |
| 1460 | b8076a74 | bellard | break;
|
| 1461 | b8076a74 | bellard | |
| 1462 | b8076a74 | bellard | default:
|
| 1463 | b8076a74 | bellard | break;
|
| 1464 | b8076a74 | bellard | } |
| 1465 | b8076a74 | bellard | return handle_cpu_signal(ip, (unsigned long)info->si_addr, |
| 1466 | b8076a74 | bellard | is_write, |
| 1467 | b8076a74 | bellard | &uc->uc_sigmask, puc); |
| 1468 | b8076a74 | bellard | } |
| 1469 | b8076a74 | bellard | |
| 1470 | 90cb9493 | bellard | #elif defined(__s390__)
|
| 1471 | 90cb9493 | bellard | |
| 1472 | 90cb9493 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 1473 | 90cb9493 | bellard | void *puc)
|
| 1474 | 90cb9493 | bellard | {
|
| 1475 | 90cb9493 | bellard | struct ucontext *uc = puc;
|
| 1476 | 90cb9493 | bellard | unsigned long pc; |
| 1477 | 90cb9493 | bellard | int is_write;
|
| 1478 | 90cb9493 | bellard | |
| 1479 | 90cb9493 | bellard | pc = uc->uc_mcontext.psw.addr; |
| 1480 | 90cb9493 | bellard | /* XXX: compute is_write */
|
| 1481 | 90cb9493 | bellard | is_write = 0;
|
| 1482 | 90cb9493 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1483 | 90cb9493 | bellard | is_write, |
| 1484 | 90cb9493 | bellard | &uc->uc_sigmask, puc); |
| 1485 | 90cb9493 | bellard | } |
| 1486 | 90cb9493 | bellard | |
| 1487 | 9de5e440 | bellard | #else
|
| 1488 | 2b413144 | bellard | |
| 1489 | 3fb2ded1 | bellard | #error host CPU specific signal handler needed
|
| 1490 | 2b413144 | bellard | |
| 1491 | 9de5e440 | bellard | #endif
|
| 1492 | 67b915a5 | bellard | |
| 1493 | 67b915a5 | bellard | #endif /* !defined(CONFIG_SOFTMMU) */ |