root / target-ppc / translate.c @ 430116a1
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/*
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* PPC emulation for qemu: main translation routines.
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*
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* Copyright (c) 2003 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "disas.h" |
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//#define DO_SINGLE_STEP
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//#define PPC_DEBUG_DISAS
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enum {
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#define DEF(s, n, copy_size) INDEX_op_ ## s, |
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#include "opc.h" |
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#undef DEF
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NB_OPS, |
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}; |
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static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
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#include "gen-op.h" |
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#define GEN8(func, NAME) \
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static GenOpFunc *NAME ## _table [8] = { \ |
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
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}; \ |
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static inline void func(int n) \ |
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{ \ |
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NAME ## _table[n](); \ |
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} |
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#define GEN16(func, NAME) \
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static GenOpFunc *NAME ## _table [16] = { \ |
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
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}; \ |
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static inline void func(int n) \ |
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{ \ |
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NAME ## _table[n](); \ |
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} |
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#define GEN32(func, NAME) \
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static GenOpFunc *NAME ## _table [32] = { \ |
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
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NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ |
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NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ |
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NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ |
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NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ |
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}; \ |
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static inline void func(int n) \ |
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{ \ |
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NAME ## _table[n](); \ |
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} |
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/* Condition register moves */
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GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf); |
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GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf); |
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GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf); |
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GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf); |
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/* Floating point condition and status register moves */
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GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr); |
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GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr); |
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GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr); |
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static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = { |
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&gen_op_store_T0_fpscri_fpscr0, |
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&gen_op_store_T0_fpscri_fpscr1, |
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&gen_op_store_T0_fpscri_fpscr2, |
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&gen_op_store_T0_fpscri_fpscr3, |
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&gen_op_store_T0_fpscri_fpscr4, |
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&gen_op_store_T0_fpscri_fpscr5, |
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&gen_op_store_T0_fpscri_fpscr6, |
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&gen_op_store_T0_fpscri_fpscr7, |
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}; |
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static inline void gen_op_store_T0_fpscri(int n, uint8_t param) |
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{ |
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(*gen_op_store_T0_fpscri_fpscr_table[n])(param); |
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} |
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/* Segment register moves */
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GEN16(gen_op_load_sr, gen_op_load_sr); |
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GEN16(gen_op_store_sr, gen_op_store_sr); |
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/* General purpose registers moves */
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GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr); |
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GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr); |
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GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr); |
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GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr); |
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GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr); |
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GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr); |
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/* floating point registers moves */
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GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr); |
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GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr); |
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GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr); |
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GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr); |
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GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr); |
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GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr); |
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static uint8_t spr_access[1024 / 2]; |
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/* internal defines */
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typedef struct DisasContext { |
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struct TranslationBlock *tb;
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target_ulong nip; |
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uint32_t opcode; |
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uint32_t exception; |
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/* Routine used to access memory */
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int mem_idx;
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/* Translation flags */
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#if !defined(CONFIG_USER_ONLY)
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int supervisor;
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#endif
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int fpu_enabled;
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} DisasContext; |
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typedef struct opc_handler_t { |
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/* invalid bits */
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uint32_t inval; |
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/* instruction type */
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uint32_t type; |
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/* handler */
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void (*handler)(DisasContext *ctx);
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} opc_handler_t; |
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#define RET_EXCP(ctx, excp, error) \
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do { \
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if ((ctx)->exception == EXCP_NONE) { \
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gen_op_update_nip((ctx)->nip); \ |
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} \ |
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gen_op_raise_exception_err((excp), (error)); \ |
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ctx->exception = (excp); \ |
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} while (0) |
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#define RET_INVAL(ctx) \
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RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL) |
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#define RET_PRIVOPC(ctx) \
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RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC) |
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#define RET_PRIVREG(ctx) \
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RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG) |
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#define RET_MTMSR(ctx) \
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RET_EXCP((ctx), EXCP_MTMSR, 0)
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#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
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static void gen_##name (DisasContext *ctx); \ |
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GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \ |
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static void gen_##name (DisasContext *ctx) |
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typedef struct opcode_t { |
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unsigned char opc1, opc2, opc3; |
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#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */ |
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unsigned char pad[5]; |
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#else
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unsigned char pad[1]; |
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#endif
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opc_handler_t handler; |
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} opcode_t; |
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/*** Instruction decoding ***/
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#define EXTRACT_HELPER(name, shift, nb) \
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static inline uint32_t name (uint32_t opcode) \ |
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{ \ |
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return (opcode >> (shift)) & ((1 << (nb)) - 1); \ |
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} |
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#define EXTRACT_SHELPER(name, shift, nb) \
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static inline int32_t name (uint32_t opcode) \ |
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{ \ |
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return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
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} |
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/* Opcode part 1 */
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EXTRACT_HELPER(opc1, 26, 6); |
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/* Opcode part 2 */
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EXTRACT_HELPER(opc2, 1, 5); |
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/* Opcode part 3 */
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EXTRACT_HELPER(opc3, 6, 5); |
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/* Update Cr0 flags */
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EXTRACT_HELPER(Rc, 0, 1); |
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/* Destination */
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EXTRACT_HELPER(rD, 21, 5); |
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/* Source */
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EXTRACT_HELPER(rS, 21, 5); |
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/* First operand */
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EXTRACT_HELPER(rA, 16, 5); |
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/* Second operand */
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EXTRACT_HELPER(rB, 11, 5); |
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/* Third operand */
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EXTRACT_HELPER(rC, 6, 5); |
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/*** Get CRn ***/
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EXTRACT_HELPER(crfD, 23, 3); |
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EXTRACT_HELPER(crfS, 18, 3); |
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EXTRACT_HELPER(crbD, 21, 5); |
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EXTRACT_HELPER(crbA, 16, 5); |
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EXTRACT_HELPER(crbB, 11, 5); |
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/* SPR / TBL */
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EXTRACT_HELPER(SPR, 11, 10); |
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/*** Get constants ***/
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EXTRACT_HELPER(IMM, 12, 8); |
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/* 16 bits signed immediate value */
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EXTRACT_SHELPER(SIMM, 0, 16); |
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/* 16 bits unsigned immediate value */
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EXTRACT_HELPER(UIMM, 0, 16); |
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/* Bit count */
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EXTRACT_HELPER(NB, 11, 5); |
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/* Shift count */
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EXTRACT_HELPER(SH, 11, 5); |
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/* Mask start */
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EXTRACT_HELPER(MB, 6, 5); |
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/* Mask end */
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EXTRACT_HELPER(ME, 1, 5); |
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/* Trap operand */
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EXTRACT_HELPER(TO, 21, 5); |
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EXTRACT_HELPER(CRM, 12, 8); |
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EXTRACT_HELPER(FM, 17, 8); |
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EXTRACT_HELPER(SR, 16, 4); |
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EXTRACT_HELPER(FPIMM, 20, 4); |
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/*** Jump target decoding ***/
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/* Displacement */
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EXTRACT_SHELPER(d, 0, 16); |
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/* Immediate address */
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static inline uint32_t LI (uint32_t opcode) |
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{ |
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return (opcode >> 0) & 0x03FFFFFC; |
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} |
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static inline uint32_t BD (uint32_t opcode) |
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{ |
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return (opcode >> 0) & 0xFFFC; |
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} |
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EXTRACT_HELPER(BO, 21, 5); |
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EXTRACT_HELPER(BI, 16, 5); |
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/* Absolute/relative address */
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EXTRACT_HELPER(AA, 1, 1); |
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/* Link */
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EXTRACT_HELPER(LK, 0, 1); |
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/* Create a mask between <start> and <end> bits */
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static inline uint32_t MASK (uint32_t start, uint32_t end) |
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{ |
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uint32_t ret; |
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ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1); |
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if (start > end)
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return ~ret;
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return ret;
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} |
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#if defined(__APPLE__)
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#define OPCODES_SECTION \
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__attribute__ ((section("__TEXT,__opcodes"), unused, aligned (8) )) |
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#else
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#define OPCODES_SECTION \
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__attribute__ ((section(".opcodes"), unused, aligned (8) )) |
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#endif
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#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
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OPCODES_SECTION opcode_t opc_##name = { \ |
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.opc1 = op1, \ |
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.opc2 = op2, \ |
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.opc3 = op3, \ |
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.pad = { 0, }, \
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.handler = { \ |
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.inval = invl, \ |
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.type = _typ, \ |
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.handler = &gen_##name, \ |
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}, \ |
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} |
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#define GEN_OPCODE_MARK(name) \
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OPCODES_SECTION opcode_t opc_##name = { \ |
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.opc1 = 0xFF, \
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.opc2 = 0xFF, \
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.opc3 = 0xFF, \
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.pad = { 0, }, \
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.handler = { \ |
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.inval = 0x00000000, \
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.type = 0x00, \
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.handler = NULL, \
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}, \ |
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} |
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/* Start opcode list */
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GEN_OPCODE_MARK(start); |
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/* Invalid instruction */
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GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE) |
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{ |
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RET_INVAL(ctx); |
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} |
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static opc_handler_t invalid_handler = {
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.inval = 0xFFFFFFFF,
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.type = PPC_NONE, |
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.handler = gen_invalid, |
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}; |
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/*** Integer arithmetic ***/
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#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
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GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \ |
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{ \ |
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gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
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gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
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gen_op_##name(); \ |
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if (Rc(ctx->opcode) != 0) \ |
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gen_op_set_Rc0(); \ |
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gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
344 |
} |
345 |
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#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
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GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \ |
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{ \ |
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gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
350 |
gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
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gen_op_##name(); \ |
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if (Rc(ctx->opcode) != 0) \ |
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gen_op_set_Rc0(); \ |
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gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
355 |
} |
356 |
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#define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
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GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
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{ \ |
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gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
361 |
gen_op_##name(); \ |
362 |
if (Rc(ctx->opcode) != 0) \ |
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gen_op_set_Rc0(); \ |
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gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
365 |
} |
366 |
#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
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GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
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{ \ |
369 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
370 |
gen_op_##name(); \ |
371 |
if (Rc(ctx->opcode) != 0) \ |
372 |
gen_op_set_Rc0(); \ |
373 |
gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
374 |
} |
375 |
|
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/* Two operands arithmetic functions */
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#define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
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__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
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__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000) |
380 |
|
381 |
/* Two operands arithmetic functions with no overflow allowed */
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#define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
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__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
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384 |
|
385 |
/* One operand arithmetic functions */
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#define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
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__GEN_INT_ARITH1(name, opc1, opc2, opc3) \ |
388 |
__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10) |
389 |
|
390 |
/* add add. addo addo. */
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GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08); |
392 |
/* addc addc. addco addco. */
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GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00); |
394 |
/* adde adde. addeo addeo. */
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GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04); |
396 |
/* addme addme. addmeo addmeo. */
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GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07); |
398 |
/* addze addze. addzeo addzeo. */
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GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06); |
400 |
/* divw divw. divwo divwo. */
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GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F); |
402 |
/* divwu divwu. divwuo divwuo. */
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GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E); |
404 |
/* mulhw mulhw. */
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GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02); |
406 |
/* mulhwu mulhwu. */
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GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00); |
408 |
/* mullw mullw. mullwo mullwo. */
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GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07); |
410 |
/* neg neg. nego nego. */
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411 |
GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03); |
412 |
/* subf subf. subfo subfo. */
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413 |
GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01); |
414 |
/* subfc subfc. subfco subfco. */
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415 |
GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00); |
416 |
/* subfe subfe. subfeo subfeo. */
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417 |
GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04); |
418 |
/* subfme subfme. subfmeo subfmeo. */
|
419 |
GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07); |
420 |
/* subfze subfze. subfzeo subfzeo. */
|
421 |
GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06); |
422 |
/* addi */
|
423 |
GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
424 |
{ |
425 |
int32_t simm = SIMM(ctx->opcode); |
426 |
|
427 |
if (rA(ctx->opcode) == 0) { |
428 |
gen_op_set_T0(simm); |
429 |
} else {
|
430 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
431 |
gen_op_addi(simm); |
432 |
} |
433 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
434 |
} |
435 |
/* addic */
|
436 |
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
437 |
{ |
438 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
439 |
gen_op_addic(SIMM(ctx->opcode)); |
440 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
441 |
} |
442 |
/* addic. */
|
443 |
GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
444 |
{ |
445 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
446 |
gen_op_addic(SIMM(ctx->opcode)); |
447 |
gen_op_set_Rc0(); |
448 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
449 |
} |
450 |
/* addis */
|
451 |
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
452 |
{ |
453 |
int32_t simm = SIMM(ctx->opcode); |
454 |
|
455 |
if (rA(ctx->opcode) == 0) { |
456 |
gen_op_set_T0(simm << 16);
|
457 |
} else {
|
458 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
459 |
gen_op_addi(simm << 16);
|
460 |
} |
461 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
462 |
} |
463 |
/* mulli */
|
464 |
GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
465 |
{ |
466 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
467 |
gen_op_mulli(SIMM(ctx->opcode)); |
468 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
469 |
} |
470 |
/* subfic */
|
471 |
GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
472 |
{ |
473 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
474 |
gen_op_subfic(SIMM(ctx->opcode)); |
475 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
476 |
} |
477 |
|
478 |
/*** Integer comparison ***/
|
479 |
#define GEN_CMP(name, opc) \
|
480 |
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \ |
481 |
{ \ |
482 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
483 |
gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
484 |
gen_op_##name(); \ |
485 |
gen_op_store_T0_crf(crfD(ctx->opcode)); \ |
486 |
} |
487 |
|
488 |
/* cmp */
|
489 |
GEN_CMP(cmp, 0x00);
|
490 |
/* cmpi */
|
491 |
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) |
492 |
{ |
493 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
494 |
gen_op_cmpi(SIMM(ctx->opcode)); |
495 |
gen_op_store_T0_crf(crfD(ctx->opcode)); |
496 |
} |
497 |
/* cmpl */
|
498 |
GEN_CMP(cmpl, 0x01);
|
499 |
/* cmpli */
|
500 |
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) |
501 |
{ |
502 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
503 |
gen_op_cmpli(UIMM(ctx->opcode)); |
504 |
gen_op_store_T0_crf(crfD(ctx->opcode)); |
505 |
} |
506 |
|
507 |
/*** Integer logical ***/
|
508 |
#define __GEN_LOGICAL2(name, opc2, opc3) \
|
509 |
GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \ |
510 |
{ \ |
511 |
gen_op_load_gpr_T0(rS(ctx->opcode)); \ |
512 |
gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
513 |
gen_op_##name(); \ |
514 |
if (Rc(ctx->opcode) != 0) \ |
515 |
gen_op_set_Rc0(); \ |
516 |
gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
517 |
} |
518 |
#define GEN_LOGICAL2(name, opc) \
|
519 |
__GEN_LOGICAL2(name, 0x1C, opc)
|
520 |
|
521 |
#define GEN_LOGICAL1(name, opc) \
|
522 |
GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \ |
523 |
{ \ |
524 |
gen_op_load_gpr_T0(rS(ctx->opcode)); \ |
525 |
gen_op_##name(); \ |
526 |
if (Rc(ctx->opcode) != 0) \ |
527 |
gen_op_set_Rc0(); \ |
528 |
gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
529 |
} |
530 |
|
531 |
/* and & and. */
|
532 |
GEN_LOGICAL2(and, 0x00);
|
533 |
/* andc & andc. */
|
534 |
GEN_LOGICAL2(andc, 0x01);
|
535 |
/* andi. */
|
536 |
GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
537 |
{ |
538 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
539 |
gen_op_andi_(UIMM(ctx->opcode)); |
540 |
gen_op_set_Rc0(); |
541 |
gen_op_store_T0_gpr(rA(ctx->opcode)); |
542 |
} |
543 |
/* andis. */
|
544 |
GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
545 |
{ |
546 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
547 |
gen_op_andi_(UIMM(ctx->opcode) << 16);
|
548 |
gen_op_set_Rc0(); |
549 |
gen_op_store_T0_gpr(rA(ctx->opcode)); |
550 |
} |
551 |
|
552 |
/* cntlzw */
|
553 |
GEN_LOGICAL1(cntlzw, 0x00);
|
554 |
/* eqv & eqv. */
|
555 |
GEN_LOGICAL2(eqv, 0x08);
|
556 |
/* extsb & extsb. */
|
557 |
GEN_LOGICAL1(extsb, 0x1D);
|
558 |
/* extsh & extsh. */
|
559 |
GEN_LOGICAL1(extsh, 0x1C);
|
560 |
/* nand & nand. */
|
561 |
GEN_LOGICAL2(nand, 0x0E);
|
562 |
/* nor & nor. */
|
563 |
GEN_LOGICAL2(nor, 0x03);
|
564 |
|
565 |
/* or & or. */
|
566 |
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER) |
567 |
{ |
568 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
569 |
/* Optimisation for mr case */
|
570 |
if (rS(ctx->opcode) != rB(ctx->opcode)) {
|
571 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
572 |
gen_op_or(); |
573 |
} |
574 |
if (Rc(ctx->opcode) != 0) |
575 |
gen_op_set_Rc0(); |
576 |
gen_op_store_T0_gpr(rA(ctx->opcode)); |
577 |
} |
578 |
|
579 |
/* orc & orc. */
|
580 |
GEN_LOGICAL2(orc, 0x0C);
|
581 |
/* xor & xor. */
|
582 |
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER) |
583 |
{ |
584 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
585 |
/* Optimisation for "set to zero" case */
|
586 |
if (rS(ctx->opcode) != rB(ctx->opcode)) {
|
587 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
588 |
gen_op_xor(); |
589 |
} else {
|
590 |
gen_op_set_T0(0);
|
591 |
} |
592 |
if (Rc(ctx->opcode) != 0) |
593 |
gen_op_set_Rc0(); |
594 |
gen_op_store_T0_gpr(rA(ctx->opcode)); |
595 |
} |
596 |
/* ori */
|
597 |
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
598 |
{ |
599 |
uint32_t uimm = UIMM(ctx->opcode); |
600 |
|
601 |
if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
602 |
/* NOP */
|
603 |
return;
|
604 |
} |
605 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
606 |
if (uimm != 0) |
607 |
gen_op_ori(uimm); |
608 |
gen_op_store_T0_gpr(rA(ctx->opcode)); |
609 |
} |
610 |
/* oris */
|
611 |
GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
612 |
{ |
613 |
uint32_t uimm = UIMM(ctx->opcode); |
614 |
|
615 |
if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
616 |
/* NOP */
|
617 |
return;
|
618 |
} |
619 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
620 |
if (uimm != 0) |
621 |
gen_op_ori(uimm << 16);
|
622 |
gen_op_store_T0_gpr(rA(ctx->opcode)); |
623 |
} |
624 |
/* xori */
|
625 |
GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
626 |
{ |
627 |
uint32_t uimm = UIMM(ctx->opcode); |
628 |
|
629 |
if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
630 |
/* NOP */
|
631 |
return;
|
632 |
} |
633 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
634 |
if (uimm != 0) |
635 |
gen_op_xori(uimm); |
636 |
gen_op_store_T0_gpr(rA(ctx->opcode)); |
637 |
} |
638 |
|
639 |
/* xoris */
|
640 |
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
641 |
{ |
642 |
uint32_t uimm = UIMM(ctx->opcode); |
643 |
|
644 |
if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
645 |
/* NOP */
|
646 |
return;
|
647 |
} |
648 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
649 |
if (uimm != 0) |
650 |
gen_op_xori(uimm << 16);
|
651 |
gen_op_store_T0_gpr(rA(ctx->opcode)); |
652 |
} |
653 |
|
654 |
/*** Integer rotate ***/
|
655 |
/* rlwimi & rlwimi. */
|
656 |
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
657 |
{ |
658 |
uint32_t mb, me; |
659 |
|
660 |
mb = MB(ctx->opcode); |
661 |
me = ME(ctx->opcode); |
662 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
663 |
gen_op_load_gpr_T1(rA(ctx->opcode)); |
664 |
gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me)); |
665 |
if (Rc(ctx->opcode) != 0) |
666 |
gen_op_set_Rc0(); |
667 |
gen_op_store_T0_gpr(rA(ctx->opcode)); |
668 |
} |
669 |
/* rlwinm & rlwinm. */
|
670 |
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
671 |
{ |
672 |
uint32_t mb, me, sh; |
673 |
|
674 |
sh = SH(ctx->opcode); |
675 |
mb = MB(ctx->opcode); |
676 |
me = ME(ctx->opcode); |
677 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
678 |
#if 1 // TRY |
679 |
if (sh == 0) { |
680 |
gen_op_andi_(MASK(mb, me)); |
681 |
goto store;
|
682 |
} |
683 |
#endif
|
684 |
if (mb == 0) { |
685 |
if (me == 31) { |
686 |
gen_op_rotlwi(sh); |
687 |
goto store;
|
688 |
#if 0
|
689 |
} else if (me == (31 - sh)) {
|
690 |
gen_op_slwi(sh);
|
691 |
goto store;
|
692 |
#endif
|
693 |
} |
694 |
} else if (me == 31) { |
695 |
#if 0
|
696 |
if (sh == (32 - mb)) {
|
697 |
gen_op_srwi(mb);
|
698 |
goto store;
|
699 |
}
|
700 |
#endif
|
701 |
} |
702 |
gen_op_rlwinm(sh, MASK(mb, me)); |
703 |
store:
|
704 |
if (Rc(ctx->opcode) != 0) |
705 |
gen_op_set_Rc0(); |
706 |
gen_op_store_T0_gpr(rA(ctx->opcode)); |
707 |
} |
708 |
/* rlwnm & rlwnm. */
|
709 |
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
710 |
{ |
711 |
uint32_t mb, me; |
712 |
|
713 |
mb = MB(ctx->opcode); |
714 |
me = ME(ctx->opcode); |
715 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
716 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
717 |
if (mb == 0 && me == 31) { |
718 |
gen_op_rotl(); |
719 |
} else
|
720 |
{ |
721 |
gen_op_rlwnm(MASK(mb, me)); |
722 |
} |
723 |
if (Rc(ctx->opcode) != 0) |
724 |
gen_op_set_Rc0(); |
725 |
gen_op_store_T0_gpr(rA(ctx->opcode)); |
726 |
} |
727 |
|
728 |
/*** Integer shift ***/
|
729 |
/* slw & slw. */
|
730 |
__GEN_LOGICAL2(slw, 0x18, 0x00); |
731 |
/* sraw & sraw. */
|
732 |
__GEN_LOGICAL2(sraw, 0x18, 0x18); |
733 |
/* srawi & srawi. */
|
734 |
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) |
735 |
{ |
736 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
737 |
if (SH(ctx->opcode) != 0) |
738 |
gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31)); |
739 |
if (Rc(ctx->opcode) != 0) |
740 |
gen_op_set_Rc0(); |
741 |
gen_op_store_T0_gpr(rA(ctx->opcode)); |
742 |
} |
743 |
/* srw & srw. */
|
744 |
__GEN_LOGICAL2(srw, 0x18, 0x10); |
745 |
|
746 |
/*** Floating-Point arithmetic ***/
|
747 |
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat) \
|
748 |
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \ |
749 |
{ \ |
750 |
if (!ctx->fpu_enabled) { \
|
751 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \
|
752 |
return; \
|
753 |
} \ |
754 |
gen_op_reset_scrfx(); \ |
755 |
gen_op_load_fpr_FT0(rA(ctx->opcode)); \ |
756 |
gen_op_load_fpr_FT1(rC(ctx->opcode)); \ |
757 |
gen_op_load_fpr_FT2(rB(ctx->opcode)); \ |
758 |
gen_op_f##op(); \ |
759 |
if (isfloat) { \
|
760 |
gen_op_frsp(); \ |
761 |
} \ |
762 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
763 |
if (Rc(ctx->opcode)) \
|
764 |
gen_op_set_Rc1(); \ |
765 |
} |
766 |
|
767 |
#define GEN_FLOAT_ACB(name, op2) \
|
768 |
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0); \ |
769 |
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1); |
770 |
|
771 |
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat) \
|
772 |
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \ |
773 |
{ \ |
774 |
if (!ctx->fpu_enabled) { \
|
775 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \
|
776 |
return; \
|
777 |
} \ |
778 |
gen_op_reset_scrfx(); \ |
779 |
gen_op_load_fpr_FT0(rA(ctx->opcode)); \ |
780 |
gen_op_load_fpr_FT1(rB(ctx->opcode)); \ |
781 |
gen_op_f##op(); \ |
782 |
if (isfloat) { \
|
783 |
gen_op_frsp(); \ |
784 |
} \ |
785 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
786 |
if (Rc(ctx->opcode)) \
|
787 |
gen_op_set_Rc1(); \ |
788 |
} |
789 |
#define GEN_FLOAT_AB(name, op2, inval) \
|
790 |
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0); \ |
791 |
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1); |
792 |
|
793 |
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat) \
|
794 |
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \ |
795 |
{ \ |
796 |
if (!ctx->fpu_enabled) { \
|
797 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \
|
798 |
return; \
|
799 |
} \ |
800 |
gen_op_reset_scrfx(); \ |
801 |
gen_op_load_fpr_FT0(rA(ctx->opcode)); \ |
802 |
gen_op_load_fpr_FT1(rC(ctx->opcode)); \ |
803 |
gen_op_f##op(); \ |
804 |
if (isfloat) { \
|
805 |
gen_op_frsp(); \ |
806 |
} \ |
807 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
808 |
if (Rc(ctx->opcode)) \
|
809 |
gen_op_set_Rc1(); \ |
810 |
} |
811 |
#define GEN_FLOAT_AC(name, op2, inval) \
|
812 |
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0); \ |
813 |
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1); |
814 |
|
815 |
#define GEN_FLOAT_B(name, op2, op3) \
|
816 |
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \ |
817 |
{ \ |
818 |
if (!ctx->fpu_enabled) { \
|
819 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \
|
820 |
return; \
|
821 |
} \ |
822 |
gen_op_reset_scrfx(); \ |
823 |
gen_op_load_fpr_FT0(rB(ctx->opcode)); \ |
824 |
gen_op_f##name(); \ |
825 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
826 |
if (Rc(ctx->opcode)) \
|
827 |
gen_op_set_Rc1(); \ |
828 |
} |
829 |
|
830 |
#define GEN_FLOAT_BS(name, op1, op2) \
|
831 |
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \ |
832 |
{ \ |
833 |
if (!ctx->fpu_enabled) { \
|
834 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \
|
835 |
return; \
|
836 |
} \ |
837 |
gen_op_reset_scrfx(); \ |
838 |
gen_op_load_fpr_FT0(rB(ctx->opcode)); \ |
839 |
gen_op_f##name(); \ |
840 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
841 |
if (Rc(ctx->opcode)) \
|
842 |
gen_op_set_Rc1(); \ |
843 |
} |
844 |
|
845 |
/* fadd - fadds */
|
846 |
GEN_FLOAT_AB(add, 0x15, 0x000007C0); |
847 |
/* fdiv - fdivs */
|
848 |
GEN_FLOAT_AB(div, 0x12, 0x000007C0); |
849 |
/* fmul - fmuls */
|
850 |
GEN_FLOAT_AC(mul, 0x19, 0x0000F800); |
851 |
|
852 |
/* fres */
|
853 |
GEN_FLOAT_BS(res, 0x3B, 0x18); |
854 |
|
855 |
/* frsqrte */
|
856 |
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A); |
857 |
|
858 |
/* fsel */
|
859 |
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0); |
860 |
/* fsub - fsubs */
|
861 |
GEN_FLOAT_AB(sub, 0x14, 0x000007C0); |
862 |
/* Optional: */
|
863 |
/* fsqrt */
|
864 |
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT) |
865 |
{ |
866 |
if (!ctx->fpu_enabled) {
|
867 |
RET_EXCP(ctx, EXCP_NO_FP, 0);
|
868 |
return;
|
869 |
} |
870 |
gen_op_reset_scrfx(); |
871 |
gen_op_load_fpr_FT0(rB(ctx->opcode)); |
872 |
gen_op_fsqrt(); |
873 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); |
874 |
if (Rc(ctx->opcode))
|
875 |
gen_op_set_Rc1(); |
876 |
} |
877 |
|
878 |
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT) |
879 |
{ |
880 |
if (!ctx->fpu_enabled) {
|
881 |
RET_EXCP(ctx, EXCP_NO_FP, 0);
|
882 |
return;
|
883 |
} |
884 |
gen_op_reset_scrfx(); |
885 |
gen_op_load_fpr_FT0(rB(ctx->opcode)); |
886 |
gen_op_fsqrt(); |
887 |
gen_op_frsp(); |
888 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); |
889 |
if (Rc(ctx->opcode))
|
890 |
gen_op_set_Rc1(); |
891 |
} |
892 |
|
893 |
/*** Floating-Point multiply-and-add ***/
|
894 |
/* fmadd - fmadds */
|
895 |
GEN_FLOAT_ACB(madd, 0x1D);
|
896 |
/* fmsub - fmsubs */
|
897 |
GEN_FLOAT_ACB(msub, 0x1C);
|
898 |
/* fnmadd - fnmadds */
|
899 |
GEN_FLOAT_ACB(nmadd, 0x1F);
|
900 |
/* fnmsub - fnmsubs */
|
901 |
GEN_FLOAT_ACB(nmsub, 0x1E);
|
902 |
|
903 |
/*** Floating-Point round & convert ***/
|
904 |
/* fctiw */
|
905 |
GEN_FLOAT_B(ctiw, 0x0E, 0x00); |
906 |
/* fctiwz */
|
907 |
GEN_FLOAT_B(ctiwz, 0x0F, 0x00); |
908 |
/* frsp */
|
909 |
GEN_FLOAT_B(rsp, 0x0C, 0x00); |
910 |
|
911 |
/*** Floating-Point compare ***/
|
912 |
/* fcmpo */
|
913 |
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT) |
914 |
{ |
915 |
if (!ctx->fpu_enabled) {
|
916 |
RET_EXCP(ctx, EXCP_NO_FP, 0);
|
917 |
return;
|
918 |
} |
919 |
gen_op_reset_scrfx(); |
920 |
gen_op_load_fpr_FT0(rA(ctx->opcode)); |
921 |
gen_op_load_fpr_FT1(rB(ctx->opcode)); |
922 |
gen_op_fcmpo(); |
923 |
gen_op_store_T0_crf(crfD(ctx->opcode)); |
924 |
} |
925 |
|
926 |
/* fcmpu */
|
927 |
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT) |
928 |
{ |
929 |
if (!ctx->fpu_enabled) {
|
930 |
RET_EXCP(ctx, EXCP_NO_FP, 0);
|
931 |
return;
|
932 |
} |
933 |
gen_op_reset_scrfx(); |
934 |
gen_op_load_fpr_FT0(rA(ctx->opcode)); |
935 |
gen_op_load_fpr_FT1(rB(ctx->opcode)); |
936 |
gen_op_fcmpu(); |
937 |
gen_op_store_T0_crf(crfD(ctx->opcode)); |
938 |
} |
939 |
|
940 |
/*** Floating-point move ***/
|
941 |
/* fabs */
|
942 |
GEN_FLOAT_B(abs, 0x08, 0x08); |
943 |
|
944 |
/* fmr - fmr. */
|
945 |
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT) |
946 |
{ |
947 |
if (!ctx->fpu_enabled) {
|
948 |
RET_EXCP(ctx, EXCP_NO_FP, 0);
|
949 |
return;
|
950 |
} |
951 |
gen_op_reset_scrfx(); |
952 |
gen_op_load_fpr_FT0(rB(ctx->opcode)); |
953 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); |
954 |
if (Rc(ctx->opcode))
|
955 |
gen_op_set_Rc1(); |
956 |
} |
957 |
|
958 |
/* fnabs */
|
959 |
GEN_FLOAT_B(nabs, 0x08, 0x04); |
960 |
/* fneg */
|
961 |
GEN_FLOAT_B(neg, 0x08, 0x01); |
962 |
|
963 |
/*** Floating-Point status & ctrl register ***/
|
964 |
/* mcrfs */
|
965 |
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT) |
966 |
{ |
967 |
if (!ctx->fpu_enabled) {
|
968 |
RET_EXCP(ctx, EXCP_NO_FP, 0);
|
969 |
return;
|
970 |
} |
971 |
gen_op_load_fpscr_T0(crfS(ctx->opcode)); |
972 |
gen_op_store_T0_crf(crfD(ctx->opcode)); |
973 |
gen_op_clear_fpscr(crfS(ctx->opcode)); |
974 |
} |
975 |
|
976 |
/* mffs */
|
977 |
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT) |
978 |
{ |
979 |
if (!ctx->fpu_enabled) {
|
980 |
RET_EXCP(ctx, EXCP_NO_FP, 0);
|
981 |
return;
|
982 |
} |
983 |
gen_op_load_fpscr(); |
984 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); |
985 |
if (Rc(ctx->opcode))
|
986 |
gen_op_set_Rc1(); |
987 |
} |
988 |
|
989 |
/* mtfsb0 */
|
990 |
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT) |
991 |
{ |
992 |
uint8_t crb; |
993 |
|
994 |
if (!ctx->fpu_enabled) {
|
995 |
RET_EXCP(ctx, EXCP_NO_FP, 0);
|
996 |
return;
|
997 |
} |
998 |
crb = crbD(ctx->opcode) >> 2;
|
999 |
gen_op_load_fpscr_T0(crb); |
1000 |
gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03))); |
1001 |
gen_op_store_T0_fpscr(crb); |
1002 |
if (Rc(ctx->opcode))
|
1003 |
gen_op_set_Rc1(); |
1004 |
} |
1005 |
|
1006 |
/* mtfsb1 */
|
1007 |
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT) |
1008 |
{ |
1009 |
uint8_t crb; |
1010 |
|
1011 |
if (!ctx->fpu_enabled) {
|
1012 |
RET_EXCP(ctx, EXCP_NO_FP, 0);
|
1013 |
return;
|
1014 |
} |
1015 |
crb = crbD(ctx->opcode) >> 2;
|
1016 |
gen_op_load_fpscr_T0(crb); |
1017 |
gen_op_ori(1 << (crbD(ctx->opcode) & 0x03)); |
1018 |
gen_op_store_T0_fpscr(crb); |
1019 |
if (Rc(ctx->opcode))
|
1020 |
gen_op_set_Rc1(); |
1021 |
} |
1022 |
|
1023 |
/* mtfsf */
|
1024 |
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) |
1025 |
{ |
1026 |
if (!ctx->fpu_enabled) {
|
1027 |
RET_EXCP(ctx, EXCP_NO_FP, 0);
|
1028 |
return;
|
1029 |
} |
1030 |
gen_op_load_fpr_FT0(rB(ctx->opcode)); |
1031 |
gen_op_store_fpscr(FM(ctx->opcode)); |
1032 |
if (Rc(ctx->opcode))
|
1033 |
gen_op_set_Rc1(); |
1034 |
} |
1035 |
|
1036 |
/* mtfsfi */
|
1037 |
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) |
1038 |
{ |
1039 |
if (!ctx->fpu_enabled) {
|
1040 |
RET_EXCP(ctx, EXCP_NO_FP, 0);
|
1041 |
return;
|
1042 |
} |
1043 |
gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
|
1044 |
if (Rc(ctx->opcode))
|
1045 |
gen_op_set_Rc1(); |
1046 |
} |
1047 |
|
1048 |
/*** Integer load ***/
|
1049 |
#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])() |
1050 |
#if defined(CONFIG_USER_ONLY)
|
1051 |
#define OP_LD_TABLE(width) \
|
1052 |
static GenOpFunc *gen_op_l##width[] = { \ |
1053 |
&gen_op_l##width##_raw, \ |
1054 |
&gen_op_l##width##_le_raw, \ |
1055 |
}; |
1056 |
#define OP_ST_TABLE(width) \
|
1057 |
static GenOpFunc *gen_op_st##width[] = { \ |
1058 |
&gen_op_st##width##_raw, \ |
1059 |
&gen_op_st##width##_le_raw, \ |
1060 |
}; |
1061 |
/* Byte access routine are endian safe */
|
1062 |
#define gen_op_stb_le_raw gen_op_stb_raw
|
1063 |
#define gen_op_lbz_le_raw gen_op_lbz_raw
|
1064 |
#else
|
1065 |
#define OP_LD_TABLE(width) \
|
1066 |
static GenOpFunc *gen_op_l##width[] = { \ |
1067 |
&gen_op_l##width##_user, \ |
1068 |
&gen_op_l##width##_le_user, \ |
1069 |
&gen_op_l##width##_kernel, \ |
1070 |
&gen_op_l##width##_le_kernel, \ |
1071 |
}; |
1072 |
#define OP_ST_TABLE(width) \
|
1073 |
static GenOpFunc *gen_op_st##width[] = { \ |
1074 |
&gen_op_st##width##_user, \ |
1075 |
&gen_op_st##width##_le_user, \ |
1076 |
&gen_op_st##width##_kernel, \ |
1077 |
&gen_op_st##width##_le_kernel, \ |
1078 |
}; |
1079 |
/* Byte access routine are endian safe */
|
1080 |
#define gen_op_stb_le_user gen_op_stb_user
|
1081 |
#define gen_op_lbz_le_user gen_op_lbz_user
|
1082 |
#define gen_op_stb_le_kernel gen_op_stb_kernel
|
1083 |
#define gen_op_lbz_le_kernel gen_op_lbz_kernel
|
1084 |
#endif
|
1085 |
|
1086 |
#define GEN_LD(width, opc) \
|
1087 |
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
1088 |
{ \ |
1089 |
uint32_t simm = SIMM(ctx->opcode); \ |
1090 |
if (rA(ctx->opcode) == 0) { \ |
1091 |
gen_op_set_T0(simm); \ |
1092 |
} else { \
|
1093 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1094 |
if (simm != 0) \ |
1095 |
gen_op_addi(simm); \ |
1096 |
} \ |
1097 |
op_ldst(l##width); \ |
1098 |
gen_op_store_T1_gpr(rD(ctx->opcode)); \ |
1099 |
} |
1100 |
|
1101 |
#define GEN_LDU(width, opc) \
|
1102 |
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
1103 |
{ \ |
1104 |
uint32_t simm = SIMM(ctx->opcode); \ |
1105 |
if (rA(ctx->opcode) == 0 || \ |
1106 |
rA(ctx->opcode) == rD(ctx->opcode)) { \ |
1107 |
RET_INVAL(ctx); \ |
1108 |
return; \
|
1109 |
} \ |
1110 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1111 |
if (simm != 0) \ |
1112 |
gen_op_addi(simm); \ |
1113 |
op_ldst(l##width); \ |
1114 |
gen_op_store_T1_gpr(rD(ctx->opcode)); \ |
1115 |
gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1116 |
} |
1117 |
|
1118 |
#define GEN_LDUX(width, opc) \
|
1119 |
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \ |
1120 |
{ \ |
1121 |
if (rA(ctx->opcode) == 0 || \ |
1122 |
rA(ctx->opcode) == rD(ctx->opcode)) { \ |
1123 |
RET_INVAL(ctx); \ |
1124 |
return; \
|
1125 |
} \ |
1126 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1127 |
gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1128 |
gen_op_add(); \ |
1129 |
op_ldst(l##width); \ |
1130 |
gen_op_store_T1_gpr(rD(ctx->opcode)); \ |
1131 |
gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1132 |
} |
1133 |
|
1134 |
#define GEN_LDX(width, opc2, opc3) \
|
1135 |
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \ |
1136 |
{ \ |
1137 |
if (rA(ctx->opcode) == 0) { \ |
1138 |
gen_op_load_gpr_T0(rB(ctx->opcode)); \ |
1139 |
} else { \
|
1140 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1141 |
gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1142 |
gen_op_add(); \ |
1143 |
} \ |
1144 |
op_ldst(l##width); \ |
1145 |
gen_op_store_T1_gpr(rD(ctx->opcode)); \ |
1146 |
} |
1147 |
|
1148 |
#define GEN_LDS(width, op) \
|
1149 |
OP_LD_TABLE(width); \ |
1150 |
GEN_LD(width, op | 0x20); \
|
1151 |
GEN_LDU(width, op | 0x21); \
|
1152 |
GEN_LDUX(width, op | 0x01); \
|
1153 |
GEN_LDX(width, 0x17, op | 0x00) |
1154 |
|
1155 |
/* lbz lbzu lbzux lbzx */
|
1156 |
GEN_LDS(bz, 0x02);
|
1157 |
/* lha lhau lhaux lhax */
|
1158 |
GEN_LDS(ha, 0x0A);
|
1159 |
/* lhz lhzu lhzux lhzx */
|
1160 |
GEN_LDS(hz, 0x08);
|
1161 |
/* lwz lwzu lwzux lwzx */
|
1162 |
GEN_LDS(wz, 0x00);
|
1163 |
|
1164 |
/*** Integer store ***/
|
1165 |
#define GEN_ST(width, opc) \
|
1166 |
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
1167 |
{ \ |
1168 |
uint32_t simm = SIMM(ctx->opcode); \ |
1169 |
if (rA(ctx->opcode) == 0) { \ |
1170 |
gen_op_set_T0(simm); \ |
1171 |
} else { \
|
1172 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1173 |
if (simm != 0) \ |
1174 |
gen_op_addi(simm); \ |
1175 |
} \ |
1176 |
gen_op_load_gpr_T1(rS(ctx->opcode)); \ |
1177 |
op_ldst(st##width); \ |
1178 |
} |
1179 |
|
1180 |
#define GEN_STU(width, opc) \
|
1181 |
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
1182 |
{ \ |
1183 |
uint32_t simm = SIMM(ctx->opcode); \ |
1184 |
if (rA(ctx->opcode) == 0) { \ |
1185 |
RET_INVAL(ctx); \ |
1186 |
return; \
|
1187 |
} \ |
1188 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1189 |
if (simm != 0) \ |
1190 |
gen_op_addi(simm); \ |
1191 |
gen_op_load_gpr_T1(rS(ctx->opcode)); \ |
1192 |
op_ldst(st##width); \ |
1193 |
gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1194 |
} |
1195 |
|
1196 |
#define GEN_STUX(width, opc) \
|
1197 |
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \ |
1198 |
{ \ |
1199 |
if (rA(ctx->opcode) == 0) { \ |
1200 |
RET_INVAL(ctx); \ |
1201 |
return; \
|
1202 |
} \ |
1203 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1204 |
gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1205 |
gen_op_add(); \ |
1206 |
gen_op_load_gpr_T1(rS(ctx->opcode)); \ |
1207 |
op_ldst(st##width); \ |
1208 |
gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1209 |
} |
1210 |
|
1211 |
#define GEN_STX(width, opc2, opc3) \
|
1212 |
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \ |
1213 |
{ \ |
1214 |
if (rA(ctx->opcode) == 0) { \ |
1215 |
gen_op_load_gpr_T0(rB(ctx->opcode)); \ |
1216 |
} else { \
|
1217 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1218 |
gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1219 |
gen_op_add(); \ |
1220 |
} \ |
1221 |
gen_op_load_gpr_T1(rS(ctx->opcode)); \ |
1222 |
op_ldst(st##width); \ |
1223 |
} |
1224 |
|
1225 |
#define GEN_STS(width, op) \
|
1226 |
OP_ST_TABLE(width); \ |
1227 |
GEN_ST(width, op | 0x20); \
|
1228 |
GEN_STU(width, op | 0x21); \
|
1229 |
GEN_STUX(width, op | 0x01); \
|
1230 |
GEN_STX(width, 0x17, op | 0x00) |
1231 |
|
1232 |
/* stb stbu stbux stbx */
|
1233 |
GEN_STS(b, 0x06);
|
1234 |
/* sth sthu sthux sthx */
|
1235 |
GEN_STS(h, 0x0C);
|
1236 |
/* stw stwu stwux stwx */
|
1237 |
GEN_STS(w, 0x04);
|
1238 |
|
1239 |
/*** Integer load and store with byte reverse ***/
|
1240 |
/* lhbrx */
|
1241 |
OP_LD_TABLE(hbr); |
1242 |
GEN_LDX(hbr, 0x16, 0x18); |
1243 |
/* lwbrx */
|
1244 |
OP_LD_TABLE(wbr); |
1245 |
GEN_LDX(wbr, 0x16, 0x10); |
1246 |
/* sthbrx */
|
1247 |
OP_ST_TABLE(hbr); |
1248 |
GEN_STX(hbr, 0x16, 0x1C); |
1249 |
/* stwbrx */
|
1250 |
OP_ST_TABLE(wbr); |
1251 |
GEN_STX(wbr, 0x16, 0x14); |
1252 |
|
1253 |
/*** Integer load and store multiple ***/
|
1254 |
#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg) |
1255 |
#if defined(CONFIG_USER_ONLY)
|
1256 |
static GenOpFunc1 *gen_op_lmw[] = {
|
1257 |
&gen_op_lmw_raw, |
1258 |
&gen_op_lmw_le_raw, |
1259 |
}; |
1260 |
static GenOpFunc1 *gen_op_stmw[] = {
|
1261 |
&gen_op_stmw_raw, |
1262 |
&gen_op_stmw_le_raw, |
1263 |
}; |
1264 |
#else
|
1265 |
static GenOpFunc1 *gen_op_lmw[] = {
|
1266 |
&gen_op_lmw_user, |
1267 |
&gen_op_lmw_le_user, |
1268 |
&gen_op_lmw_kernel, |
1269 |
&gen_op_lmw_le_kernel, |
1270 |
}; |
1271 |
static GenOpFunc1 *gen_op_stmw[] = {
|
1272 |
&gen_op_stmw_user, |
1273 |
&gen_op_stmw_le_user, |
1274 |
&gen_op_stmw_kernel, |
1275 |
&gen_op_stmw_le_kernel, |
1276 |
}; |
1277 |
#endif
|
1278 |
|
1279 |
/* lmw */
|
1280 |
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1281 |
{ |
1282 |
int simm = SIMM(ctx->opcode);
|
1283 |
|
1284 |
if (rA(ctx->opcode) == 0) { |
1285 |
gen_op_set_T0(simm); |
1286 |
} else {
|
1287 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
1288 |
if (simm != 0) |
1289 |
gen_op_addi(simm); |
1290 |
} |
1291 |
op_ldstm(lmw, rD(ctx->opcode)); |
1292 |
} |
1293 |
|
1294 |
/* stmw */
|
1295 |
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1296 |
{ |
1297 |
int simm = SIMM(ctx->opcode);
|
1298 |
|
1299 |
if (rA(ctx->opcode) == 0) { |
1300 |
gen_op_set_T0(simm); |
1301 |
} else {
|
1302 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
1303 |
if (simm != 0) |
1304 |
gen_op_addi(simm); |
1305 |
} |
1306 |
op_ldstm(stmw, rS(ctx->opcode)); |
1307 |
} |
1308 |
|
1309 |
/*** Integer load and store strings ***/
|
1310 |
#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start) |
1311 |
#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb) |
1312 |
#if defined(CONFIG_USER_ONLY)
|
1313 |
static GenOpFunc1 *gen_op_lswi[] = {
|
1314 |
&gen_op_lswi_raw, |
1315 |
&gen_op_lswi_le_raw, |
1316 |
}; |
1317 |
static GenOpFunc3 *gen_op_lswx[] = {
|
1318 |
&gen_op_lswx_raw, |
1319 |
&gen_op_lswx_le_raw, |
1320 |
}; |
1321 |
static GenOpFunc1 *gen_op_stsw[] = {
|
1322 |
&gen_op_stsw_raw, |
1323 |
&gen_op_stsw_le_raw, |
1324 |
}; |
1325 |
#else
|
1326 |
static GenOpFunc1 *gen_op_lswi[] = {
|
1327 |
&gen_op_lswi_user, |
1328 |
&gen_op_lswi_le_user, |
1329 |
&gen_op_lswi_kernel, |
1330 |
&gen_op_lswi_le_kernel, |
1331 |
}; |
1332 |
static GenOpFunc3 *gen_op_lswx[] = {
|
1333 |
&gen_op_lswx_user, |
1334 |
&gen_op_lswx_le_user, |
1335 |
&gen_op_lswx_kernel, |
1336 |
&gen_op_lswx_le_kernel, |
1337 |
}; |
1338 |
static GenOpFunc1 *gen_op_stsw[] = {
|
1339 |
&gen_op_stsw_user, |
1340 |
&gen_op_stsw_le_user, |
1341 |
&gen_op_stsw_kernel, |
1342 |
&gen_op_stsw_le_kernel, |
1343 |
}; |
1344 |
#endif
|
1345 |
|
1346 |
/* lswi */
|
1347 |
/* PPC32 specification says we must generate an exception if
|
1348 |
* rA is in the range of registers to be loaded.
|
1349 |
* In an other hand, IBM says this is valid, but rA won't be loaded.
|
1350 |
* For now, I'll follow the spec...
|
1351 |
*/
|
1352 |
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER) |
1353 |
{ |
1354 |
int nb = NB(ctx->opcode);
|
1355 |
int start = rD(ctx->opcode);
|
1356 |
int ra = rA(ctx->opcode);
|
1357 |
int nr;
|
1358 |
|
1359 |
if (nb == 0) |
1360 |
nb = 32;
|
1361 |
nr = nb / 4;
|
1362 |
if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) || |
1363 |
((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
|
1364 |
RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX); |
1365 |
return;
|
1366 |
} |
1367 |
if (ra == 0) { |
1368 |
gen_op_set_T0(0);
|
1369 |
} else {
|
1370 |
gen_op_load_gpr_T0(ra); |
1371 |
} |
1372 |
gen_op_set_T1(nb); |
1373 |
op_ldsts(lswi, start); |
1374 |
} |
1375 |
|
1376 |
/* lswx */
|
1377 |
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER) |
1378 |
{ |
1379 |
int ra = rA(ctx->opcode);
|
1380 |
int rb = rB(ctx->opcode);
|
1381 |
|
1382 |
if (ra == 0) { |
1383 |
gen_op_load_gpr_T0(rb); |
1384 |
ra = rb; |
1385 |
} else {
|
1386 |
gen_op_load_gpr_T0(ra); |
1387 |
gen_op_load_gpr_T1(rb); |
1388 |
gen_op_add(); |
1389 |
} |
1390 |
gen_op_load_xer_bc(); |
1391 |
op_ldstsx(lswx, rD(ctx->opcode), ra, rb); |
1392 |
} |
1393 |
|
1394 |
/* stswi */
|
1395 |
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER) |
1396 |
{ |
1397 |
int nb = NB(ctx->opcode);
|
1398 |
|
1399 |
if (rA(ctx->opcode) == 0) { |
1400 |
gen_op_set_T0(0);
|
1401 |
} else {
|
1402 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
1403 |
} |
1404 |
if (nb == 0) |
1405 |
nb = 32;
|
1406 |
gen_op_set_T1(nb); |
1407 |
op_ldsts(stsw, rS(ctx->opcode)); |
1408 |
} |
1409 |
|
1410 |
/* stswx */
|
1411 |
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER) |
1412 |
{ |
1413 |
int ra = rA(ctx->opcode);
|
1414 |
|
1415 |
if (ra == 0) { |
1416 |
gen_op_load_gpr_T0(rB(ctx->opcode)); |
1417 |
ra = rB(ctx->opcode); |
1418 |
} else {
|
1419 |
gen_op_load_gpr_T0(ra); |
1420 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
1421 |
gen_op_add(); |
1422 |
} |
1423 |
gen_op_load_xer_bc(); |
1424 |
op_ldsts(stsw, rS(ctx->opcode)); |
1425 |
} |
1426 |
|
1427 |
/*** Memory synchronisation ***/
|
1428 |
/* eieio */
|
1429 |
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM) |
1430 |
{ |
1431 |
} |
1432 |
|
1433 |
/* isync */
|
1434 |
GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM) |
1435 |
{ |
1436 |
} |
1437 |
|
1438 |
#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
|
1439 |
#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
|
1440 |
#if defined(CONFIG_USER_ONLY)
|
1441 |
static GenOpFunc *gen_op_lwarx[] = {
|
1442 |
&gen_op_lwarx_raw, |
1443 |
&gen_op_lwarx_le_raw, |
1444 |
}; |
1445 |
static GenOpFunc *gen_op_stwcx[] = {
|
1446 |
&gen_op_stwcx_raw, |
1447 |
&gen_op_stwcx_le_raw, |
1448 |
}; |
1449 |
#else
|
1450 |
static GenOpFunc *gen_op_lwarx[] = {
|
1451 |
&gen_op_lwarx_user, |
1452 |
&gen_op_lwarx_le_user, |
1453 |
&gen_op_lwarx_kernel, |
1454 |
&gen_op_lwarx_le_kernel, |
1455 |
}; |
1456 |
static GenOpFunc *gen_op_stwcx[] = {
|
1457 |
&gen_op_stwcx_user, |
1458 |
&gen_op_stwcx_le_user, |
1459 |
&gen_op_stwcx_kernel, |
1460 |
&gen_op_stwcx_le_kernel, |
1461 |
}; |
1462 |
#endif
|
1463 |
|
1464 |
/* lwarx */
|
1465 |
GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES) |
1466 |
{ |
1467 |
if (rA(ctx->opcode) == 0) { |
1468 |
gen_op_load_gpr_T0(rB(ctx->opcode)); |
1469 |
} else {
|
1470 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
1471 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
1472 |
gen_op_add(); |
1473 |
} |
1474 |
op_lwarx(); |
1475 |
gen_op_store_T1_gpr(rD(ctx->opcode)); |
1476 |
} |
1477 |
|
1478 |
/* stwcx. */
|
1479 |
GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES) |
1480 |
{ |
1481 |
if (rA(ctx->opcode) == 0) { |
1482 |
gen_op_load_gpr_T0(rB(ctx->opcode)); |
1483 |
} else {
|
1484 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
1485 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
1486 |
gen_op_add(); |
1487 |
} |
1488 |
gen_op_load_gpr_T1(rS(ctx->opcode)); |
1489 |
op_stwcx(); |
1490 |
} |
1491 |
|
1492 |
/* sync */
|
1493 |
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM) |
1494 |
{ |
1495 |
} |
1496 |
|
1497 |
/*** Floating-point load ***/
|
1498 |
#define GEN_LDF(width, opc) \
|
1499 |
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \ |
1500 |
{ \ |
1501 |
uint32_t simm = SIMM(ctx->opcode); \ |
1502 |
if (!ctx->fpu_enabled) { \
|
1503 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \
|
1504 |
return; \
|
1505 |
} \ |
1506 |
if (rA(ctx->opcode) == 0) { \ |
1507 |
gen_op_set_T0(simm); \ |
1508 |
} else { \
|
1509 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1510 |
if (simm != 0) \ |
1511 |
gen_op_addi(simm); \ |
1512 |
} \ |
1513 |
op_ldst(l##width); \ |
1514 |
gen_op_store_FT1_fpr(rD(ctx->opcode)); \ |
1515 |
} |
1516 |
|
1517 |
#define GEN_LDUF(width, opc) \
|
1518 |
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \ |
1519 |
{ \ |
1520 |
uint32_t simm = SIMM(ctx->opcode); \ |
1521 |
if (!ctx->fpu_enabled) { \
|
1522 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \
|
1523 |
return; \
|
1524 |
} \ |
1525 |
if (rA(ctx->opcode) == 0 || \ |
1526 |
rA(ctx->opcode) == rD(ctx->opcode)) { \ |
1527 |
RET_INVAL(ctx); \ |
1528 |
return; \
|
1529 |
} \ |
1530 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1531 |
if (simm != 0) \ |
1532 |
gen_op_addi(simm); \ |
1533 |
op_ldst(l##width); \ |
1534 |
gen_op_store_FT1_fpr(rD(ctx->opcode)); \ |
1535 |
gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1536 |
} |
1537 |
|
1538 |
#define GEN_LDUXF(width, opc) \
|
1539 |
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \ |
1540 |
{ \ |
1541 |
if (!ctx->fpu_enabled) { \
|
1542 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \
|
1543 |
return; \
|
1544 |
} \ |
1545 |
if (rA(ctx->opcode) == 0 || \ |
1546 |
rA(ctx->opcode) == rD(ctx->opcode)) { \ |
1547 |
RET_INVAL(ctx); \ |
1548 |
return; \
|
1549 |
} \ |
1550 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1551 |
gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1552 |
gen_op_add(); \ |
1553 |
op_ldst(l##width); \ |
1554 |
gen_op_store_FT1_fpr(rD(ctx->opcode)); \ |
1555 |
gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1556 |
} |
1557 |
|
1558 |
#define GEN_LDXF(width, opc2, opc3) \
|
1559 |
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \ |
1560 |
{ \ |
1561 |
if (!ctx->fpu_enabled) { \
|
1562 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \
|
1563 |
return; \
|
1564 |
} \ |
1565 |
if (rA(ctx->opcode) == 0) { \ |
1566 |
gen_op_load_gpr_T0(rB(ctx->opcode)); \ |
1567 |
} else { \
|
1568 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1569 |
gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1570 |
gen_op_add(); \ |
1571 |
} \ |
1572 |
op_ldst(l##width); \ |
1573 |
gen_op_store_FT1_fpr(rD(ctx->opcode)); \ |
1574 |
} |
1575 |
|
1576 |
#define GEN_LDFS(width, op) \
|
1577 |
OP_LD_TABLE(width); \ |
1578 |
GEN_LDF(width, op | 0x20); \
|
1579 |
GEN_LDUF(width, op | 0x21); \
|
1580 |
GEN_LDUXF(width, op | 0x01); \
|
1581 |
GEN_LDXF(width, 0x17, op | 0x00) |
1582 |
|
1583 |
/* lfd lfdu lfdux lfdx */
|
1584 |
GEN_LDFS(fd, 0x12);
|
1585 |
/* lfs lfsu lfsux lfsx */
|
1586 |
GEN_LDFS(fs, 0x10);
|
1587 |
|
1588 |
/*** Floating-point store ***/
|
1589 |
#define GEN_STF(width, opc) \
|
1590 |
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \ |
1591 |
{ \ |
1592 |
uint32_t simm = SIMM(ctx->opcode); \ |
1593 |
if (!ctx->fpu_enabled) { \
|
1594 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \
|
1595 |
return; \
|
1596 |
} \ |
1597 |
if (rA(ctx->opcode) == 0) { \ |
1598 |
gen_op_set_T0(simm); \ |
1599 |
} else { \
|
1600 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1601 |
if (simm != 0) \ |
1602 |
gen_op_addi(simm); \ |
1603 |
} \ |
1604 |
gen_op_load_fpr_FT1(rS(ctx->opcode)); \ |
1605 |
op_ldst(st##width); \ |
1606 |
} |
1607 |
|
1608 |
#define GEN_STUF(width, opc) \
|
1609 |
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \ |
1610 |
{ \ |
1611 |
uint32_t simm = SIMM(ctx->opcode); \ |
1612 |
if (!ctx->fpu_enabled) { \
|
1613 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \
|
1614 |
return; \
|
1615 |
} \ |
1616 |
if (rA(ctx->opcode) == 0) { \ |
1617 |
RET_INVAL(ctx); \ |
1618 |
return; \
|
1619 |
} \ |
1620 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1621 |
if (simm != 0) \ |
1622 |
gen_op_addi(simm); \ |
1623 |
gen_op_load_fpr_FT1(rS(ctx->opcode)); \ |
1624 |
op_ldst(st##width); \ |
1625 |
gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1626 |
} |
1627 |
|
1628 |
#define GEN_STUXF(width, opc) \
|
1629 |
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \ |
1630 |
{ \ |
1631 |
if (!ctx->fpu_enabled) { \
|
1632 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \
|
1633 |
return; \
|
1634 |
} \ |
1635 |
if (rA(ctx->opcode) == 0) { \ |
1636 |
RET_INVAL(ctx); \ |
1637 |
return; \
|
1638 |
} \ |
1639 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1640 |
gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1641 |
gen_op_add(); \ |
1642 |
gen_op_load_fpr_FT1(rS(ctx->opcode)); \ |
1643 |
op_ldst(st##width); \ |
1644 |
gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1645 |
} |
1646 |
|
1647 |
#define GEN_STXF(width, opc2, opc3) \
|
1648 |
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \ |
1649 |
{ \ |
1650 |
if (!ctx->fpu_enabled) { \
|
1651 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \
|
1652 |
return; \
|
1653 |
} \ |
1654 |
if (rA(ctx->opcode) == 0) { \ |
1655 |
gen_op_load_gpr_T0(rB(ctx->opcode)); \ |
1656 |
} else { \
|
1657 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1658 |
gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1659 |
gen_op_add(); \ |
1660 |
} \ |
1661 |
gen_op_load_fpr_FT1(rS(ctx->opcode)); \ |
1662 |
op_ldst(st##width); \ |
1663 |
} |
1664 |
|
1665 |
#define GEN_STFS(width, op) \
|
1666 |
OP_ST_TABLE(width); \ |
1667 |
GEN_STF(width, op | 0x20); \
|
1668 |
GEN_STUF(width, op | 0x21); \
|
1669 |
GEN_STUXF(width, op | 0x01); \
|
1670 |
GEN_STXF(width, 0x17, op | 0x00) |
1671 |
|
1672 |
/* stfd stfdu stfdux stfdx */
|
1673 |
GEN_STFS(fd, 0x16);
|
1674 |
/* stfs stfsu stfsux stfsx */
|
1675 |
GEN_STFS(fs, 0x14);
|
1676 |
|
1677 |
/* Optional: */
|
1678 |
/* stfiwx */
|
1679 |
GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT) |
1680 |
{ |
1681 |
if (!ctx->fpu_enabled) {
|
1682 |
RET_EXCP(ctx, EXCP_NO_FP, 0);
|
1683 |
return;
|
1684 |
} |
1685 |
RET_INVAL(ctx); |
1686 |
} |
1687 |
|
1688 |
/*** Branch ***/
|
1689 |
|
1690 |
/* b ba bl bla */
|
1691 |
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
1692 |
{ |
1693 |
uint32_t li, target; |
1694 |
|
1695 |
/* sign extend LI */
|
1696 |
li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
1697 |
|
1698 |
if (AA(ctx->opcode) == 0) |
1699 |
target = ctx->nip + li - 4;
|
1700 |
else
|
1701 |
target = li; |
1702 |
if (LK(ctx->opcode)) {
|
1703 |
gen_op_setlr(ctx->nip); |
1704 |
} |
1705 |
gen_op_b((long)ctx->tb, target);
|
1706 |
ctx->exception = EXCP_BRANCH; |
1707 |
} |
1708 |
|
1709 |
#define BCOND_IM 0 |
1710 |
#define BCOND_LR 1 |
1711 |
#define BCOND_CTR 2 |
1712 |
|
1713 |
static inline void gen_bcond(DisasContext *ctx, int type) |
1714 |
{ |
1715 |
uint32_t target = 0;
|
1716 |
uint32_t bo = BO(ctx->opcode); |
1717 |
uint32_t bi = BI(ctx->opcode); |
1718 |
uint32_t mask; |
1719 |
uint32_t li; |
1720 |
|
1721 |
if ((bo & 0x4) == 0) |
1722 |
gen_op_dec_ctr(); |
1723 |
switch(type) {
|
1724 |
case BCOND_IM:
|
1725 |
li = (int32_t)((int16_t)(BD(ctx->opcode))); |
1726 |
if (AA(ctx->opcode) == 0) { |
1727 |
target = ctx->nip + li - 4;
|
1728 |
} else {
|
1729 |
target = li; |
1730 |
} |
1731 |
break;
|
1732 |
case BCOND_CTR:
|
1733 |
gen_op_movl_T1_ctr(); |
1734 |
break;
|
1735 |
default:
|
1736 |
case BCOND_LR:
|
1737 |
gen_op_movl_T1_lr(); |
1738 |
break;
|
1739 |
} |
1740 |
if (LK(ctx->opcode)) {
|
1741 |
gen_op_setlr(ctx->nip); |
1742 |
} |
1743 |
if (bo & 0x10) { |
1744 |
/* No CR condition */
|
1745 |
switch (bo & 0x6) { |
1746 |
case 0: |
1747 |
gen_op_test_ctr(); |
1748 |
break;
|
1749 |
case 2: |
1750 |
gen_op_test_ctrz(); |
1751 |
break;
|
1752 |
default:
|
1753 |
case 4: |
1754 |
case 6: |
1755 |
if (type == BCOND_IM) {
|
1756 |
gen_op_b((long)ctx->tb, target);
|
1757 |
} else {
|
1758 |
gen_op_b_T1(); |
1759 |
} |
1760 |
goto no_test;
|
1761 |
} |
1762 |
} else {
|
1763 |
mask = 1 << (3 - (bi & 0x03)); |
1764 |
gen_op_load_crf_T0(bi >> 2);
|
1765 |
if (bo & 0x8) { |
1766 |
switch (bo & 0x6) { |
1767 |
case 0: |
1768 |
gen_op_test_ctr_true(mask); |
1769 |
break;
|
1770 |
case 2: |
1771 |
gen_op_test_ctrz_true(mask); |
1772 |
break;
|
1773 |
default:
|
1774 |
case 4: |
1775 |
case 6: |
1776 |
gen_op_test_true(mask); |
1777 |
break;
|
1778 |
} |
1779 |
} else {
|
1780 |
switch (bo & 0x6) { |
1781 |
case 0: |
1782 |
gen_op_test_ctr_false(mask); |
1783 |
break;
|
1784 |
case 2: |
1785 |
gen_op_test_ctrz_false(mask); |
1786 |
break;
|
1787 |
default:
|
1788 |
case 4: |
1789 |
case 6: |
1790 |
gen_op_test_false(mask); |
1791 |
break;
|
1792 |
} |
1793 |
} |
1794 |
} |
1795 |
if (type == BCOND_IM) {
|
1796 |
gen_op_btest((long)ctx->tb, target, ctx->nip);
|
1797 |
} else {
|
1798 |
gen_op_btest_T1(ctx->nip); |
1799 |
} |
1800 |
no_test:
|
1801 |
ctx->exception = EXCP_BRANCH; |
1802 |
} |
1803 |
|
1804 |
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
1805 |
{ |
1806 |
gen_bcond(ctx, BCOND_IM); |
1807 |
} |
1808 |
|
1809 |
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW) |
1810 |
{ |
1811 |
gen_bcond(ctx, BCOND_CTR); |
1812 |
} |
1813 |
|
1814 |
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW) |
1815 |
{ |
1816 |
gen_bcond(ctx, BCOND_LR); |
1817 |
} |
1818 |
|
1819 |
/*** Condition register logical ***/
|
1820 |
#define GEN_CRLOGIC(op, opc) \
|
1821 |
GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \ |
1822 |
{ \ |
1823 |
gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
|
1824 |
gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \ |
1825 |
gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
|
1826 |
gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \ |
1827 |
gen_op_##op(); \ |
1828 |
gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
|
1829 |
gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \ |
1830 |
3 - (crbD(ctx->opcode) & 0x03)); \ |
1831 |
gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
|
1832 |
} |
1833 |
|
1834 |
/* crand */
|
1835 |
GEN_CRLOGIC(and, 0x08)
|
1836 |
/* crandc */
|
1837 |
GEN_CRLOGIC(andc, 0x04)
|
1838 |
/* creqv */
|
1839 |
GEN_CRLOGIC(eqv, 0x09)
|
1840 |
/* crnand */
|
1841 |
GEN_CRLOGIC(nand, 0x07)
|
1842 |
/* crnor */
|
1843 |
GEN_CRLOGIC(nor, 0x01)
|
1844 |
/* cror */
|
1845 |
GEN_CRLOGIC(or, 0x0E)
|
1846 |
/* crorc */
|
1847 |
GEN_CRLOGIC(orc, 0x0D)
|
1848 |
/* crxor */
|
1849 |
GEN_CRLOGIC(xor, 0x06)
|
1850 |
/* mcrf */
|
1851 |
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER) |
1852 |
{ |
1853 |
gen_op_load_crf_T0(crfS(ctx->opcode)); |
1854 |
gen_op_store_T0_crf(crfD(ctx->opcode)); |
1855 |
} |
1856 |
|
1857 |
/*** System linkage ***/
|
1858 |
/* rfi (supervisor only) */
|
1859 |
GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW) |
1860 |
{ |
1861 |
#if defined(CONFIG_USER_ONLY)
|
1862 |
RET_PRIVOPC(ctx); |
1863 |
#else
|
1864 |
/* Restore CPU state */
|
1865 |
if (!ctx->supervisor) {
|
1866 |
RET_PRIVOPC(ctx); |
1867 |
return;
|
1868 |
} |
1869 |
gen_op_rfi(); |
1870 |
RET_EXCP(ctx, EXCP_RFI, 0);
|
1871 |
#endif
|
1872 |
} |
1873 |
|
1874 |
/* sc */
|
1875 |
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW) |
1876 |
{ |
1877 |
#if defined(CONFIG_USER_ONLY)
|
1878 |
RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
|
1879 |
#else
|
1880 |
RET_EXCP(ctx, EXCP_SYSCALL, 0);
|
1881 |
#endif
|
1882 |
} |
1883 |
|
1884 |
/*** Trap ***/
|
1885 |
/* tw */
|
1886 |
GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW) |
1887 |
{ |
1888 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
1889 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
1890 |
gen_op_tw(TO(ctx->opcode)); |
1891 |
} |
1892 |
|
1893 |
/* twi */
|
1894 |
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
1895 |
{ |
1896 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
1897 |
#if 0
|
1898 |
printf("%s: param=0x%04x T0=0x%04x\n", __func__,
|
1899 |
SIMM(ctx->opcode), TO(ctx->opcode));
|
1900 |
#endif
|
1901 |
gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode)); |
1902 |
} |
1903 |
|
1904 |
/*** Processor control ***/
|
1905 |
static inline int check_spr_access (int spr, int rw, int supervisor) |
1906 |
{ |
1907 |
uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1)); |
1908 |
|
1909 |
#if 0
|
1910 |
if (spr != LR && spr != CTR) {
|
1911 |
if (loglevel > 0) {
|
1912 |
fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
|
1913 |
SPR_ENCODE(spr), supervisor, rw, rights,
|
1914 |
(rights >> ((2 * supervisor) + rw)) & 1);
|
1915 |
} else {
|
1916 |
printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
|
1917 |
SPR_ENCODE(spr), supervisor, rw, rights,
|
1918 |
(rights >> ((2 * supervisor) + rw)) & 1);
|
1919 |
}
|
1920 |
}
|
1921 |
#endif
|
1922 |
if (rights == 0) |
1923 |
return -1; |
1924 |
rights = rights >> (2 * supervisor);
|
1925 |
rights = rights >> rw; |
1926 |
|
1927 |
return rights & 1; |
1928 |
} |
1929 |
|
1930 |
/* mcrxr */
|
1931 |
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC) |
1932 |
{ |
1933 |
gen_op_load_xer_cr(); |
1934 |
gen_op_store_T0_crf(crfD(ctx->opcode)); |
1935 |
gen_op_clear_xer_cr(); |
1936 |
} |
1937 |
|
1938 |
/* mfcr */
|
1939 |
GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC) |
1940 |
{ |
1941 |
gen_op_load_cr(); |
1942 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
1943 |
} |
1944 |
|
1945 |
/* mfmsr */
|
1946 |
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC) |
1947 |
{ |
1948 |
#if defined(CONFIG_USER_ONLY)
|
1949 |
RET_PRIVREG(ctx); |
1950 |
#else
|
1951 |
if (!ctx->supervisor) {
|
1952 |
RET_PRIVREG(ctx); |
1953 |
return;
|
1954 |
} |
1955 |
gen_op_load_msr(); |
1956 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
1957 |
#endif
|
1958 |
} |
1959 |
|
1960 |
/* mfspr */
|
1961 |
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC) |
1962 |
{ |
1963 |
uint32_t sprn = SPR(ctx->opcode); |
1964 |
|
1965 |
#if defined(CONFIG_USER_ONLY)
|
1966 |
switch (check_spr_access(sprn, 0, 0)) |
1967 |
#else
|
1968 |
switch (check_spr_access(sprn, 0, ctx->supervisor)) |
1969 |
#endif
|
1970 |
{ |
1971 |
case -1: |
1972 |
RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR); |
1973 |
return;
|
1974 |
case 0: |
1975 |
RET_PRIVREG(ctx); |
1976 |
return;
|
1977 |
default:
|
1978 |
break;
|
1979 |
} |
1980 |
switch (sprn) {
|
1981 |
case XER:
|
1982 |
gen_op_load_xer(); |
1983 |
break;
|
1984 |
case LR:
|
1985 |
gen_op_load_lr(); |
1986 |
break;
|
1987 |
case CTR:
|
1988 |
gen_op_load_ctr(); |
1989 |
break;
|
1990 |
case IBAT0U:
|
1991 |
gen_op_load_ibat(0, 0); |
1992 |
break;
|
1993 |
case IBAT1U:
|
1994 |
gen_op_load_ibat(0, 1); |
1995 |
break;
|
1996 |
case IBAT2U:
|
1997 |
gen_op_load_ibat(0, 2); |
1998 |
break;
|
1999 |
case IBAT3U:
|
2000 |
gen_op_load_ibat(0, 3); |
2001 |
break;
|
2002 |
case IBAT4U:
|
2003 |
gen_op_load_ibat(0, 4); |
2004 |
break;
|
2005 |
case IBAT5U:
|
2006 |
gen_op_load_ibat(0, 5); |
2007 |
break;
|
2008 |
case IBAT6U:
|
2009 |
gen_op_load_ibat(0, 6); |
2010 |
break;
|
2011 |
case IBAT7U:
|
2012 |
gen_op_load_ibat(0, 7); |
2013 |
break;
|
2014 |
case IBAT0L:
|
2015 |
gen_op_load_ibat(1, 0); |
2016 |
break;
|
2017 |
case IBAT1L:
|
2018 |
gen_op_load_ibat(1, 1); |
2019 |
break;
|
2020 |
case IBAT2L:
|
2021 |
gen_op_load_ibat(1, 2); |
2022 |
break;
|
2023 |
case IBAT3L:
|
2024 |
gen_op_load_ibat(1, 3); |
2025 |
break;
|
2026 |
case IBAT4L:
|
2027 |
gen_op_load_ibat(1, 4); |
2028 |
break;
|
2029 |
case IBAT5L:
|
2030 |
gen_op_load_ibat(1, 5); |
2031 |
break;
|
2032 |
case IBAT6L:
|
2033 |
gen_op_load_ibat(1, 6); |
2034 |
break;
|
2035 |
case IBAT7L:
|
2036 |
gen_op_load_ibat(1, 7); |
2037 |
break;
|
2038 |
case DBAT0U:
|
2039 |
gen_op_load_dbat(0, 0); |
2040 |
break;
|
2041 |
case DBAT1U:
|
2042 |
gen_op_load_dbat(0, 1); |
2043 |
break;
|
2044 |
case DBAT2U:
|
2045 |
gen_op_load_dbat(0, 2); |
2046 |
break;
|
2047 |
case DBAT3U:
|
2048 |
gen_op_load_dbat(0, 3); |
2049 |
break;
|
2050 |
case DBAT4U:
|
2051 |
gen_op_load_dbat(0, 4); |
2052 |
break;
|
2053 |
case DBAT5U:
|
2054 |
gen_op_load_dbat(0, 5); |
2055 |
break;
|
2056 |
case DBAT6U:
|
2057 |
gen_op_load_dbat(0, 6); |
2058 |
break;
|
2059 |
case DBAT7U:
|
2060 |
gen_op_load_dbat(0, 7); |
2061 |
break;
|
2062 |
case DBAT0L:
|
2063 |
gen_op_load_dbat(1, 0); |
2064 |
break;
|
2065 |
case DBAT1L:
|
2066 |
gen_op_load_dbat(1, 1); |
2067 |
break;
|
2068 |
case DBAT2L:
|
2069 |
gen_op_load_dbat(1, 2); |
2070 |
break;
|
2071 |
case DBAT3L:
|
2072 |
gen_op_load_dbat(1, 3); |
2073 |
break;
|
2074 |
case DBAT4L:
|
2075 |
gen_op_load_dbat(1, 4); |
2076 |
break;
|
2077 |
case DBAT5L:
|
2078 |
gen_op_load_dbat(1, 5); |
2079 |
break;
|
2080 |
case DBAT6L:
|
2081 |
gen_op_load_dbat(1, 6); |
2082 |
break;
|
2083 |
case DBAT7L:
|
2084 |
gen_op_load_dbat(1, 7); |
2085 |
break;
|
2086 |
case SDR1:
|
2087 |
gen_op_load_sdr1(); |
2088 |
break;
|
2089 |
case V_TBL:
|
2090 |
gen_op_load_tbl(); |
2091 |
break;
|
2092 |
case V_TBU:
|
2093 |
gen_op_load_tbu(); |
2094 |
break;
|
2095 |
case DECR:
|
2096 |
gen_op_load_decr(); |
2097 |
break;
|
2098 |
default:
|
2099 |
gen_op_load_spr(sprn); |
2100 |
break;
|
2101 |
} |
2102 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
2103 |
} |
2104 |
|
2105 |
/* mftb */
|
2106 |
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC) |
2107 |
{ |
2108 |
uint32_t sprn = SPR(ctx->opcode); |
2109 |
|
2110 |
/* We need to update the time base before reading it */
|
2111 |
switch (sprn) {
|
2112 |
case V_TBL:
|
2113 |
gen_op_load_tbl(); |
2114 |
break;
|
2115 |
case V_TBU:
|
2116 |
gen_op_load_tbu(); |
2117 |
break;
|
2118 |
default:
|
2119 |
RET_INVAL(ctx); |
2120 |
return;
|
2121 |
} |
2122 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
2123 |
} |
2124 |
|
2125 |
/* mtcrf */
|
2126 |
GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC) |
2127 |
{ |
2128 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
2129 |
gen_op_store_cr(CRM(ctx->opcode)); |
2130 |
} |
2131 |
|
2132 |
/* mtmsr */
|
2133 |
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC) |
2134 |
{ |
2135 |
#if defined(CONFIG_USER_ONLY)
|
2136 |
RET_PRIVREG(ctx); |
2137 |
#else
|
2138 |
if (!ctx->supervisor) {
|
2139 |
RET_PRIVREG(ctx); |
2140 |
return;
|
2141 |
} |
2142 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
2143 |
gen_op_store_msr(); |
2144 |
/* Must stop the translation as machine state (may have) changed */
|
2145 |
RET_MTMSR(ctx); |
2146 |
#endif
|
2147 |
} |
2148 |
|
2149 |
/* mtspr */
|
2150 |
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) |
2151 |
{ |
2152 |
uint32_t sprn = SPR(ctx->opcode); |
2153 |
|
2154 |
#if 0
|
2155 |
if (loglevel > 0) {
|
2156 |
fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
|
2157 |
rS(ctx->opcode), sprn);
|
2158 |
}
|
2159 |
#endif
|
2160 |
#if defined(CONFIG_USER_ONLY)
|
2161 |
switch (check_spr_access(sprn, 1, 0)) |
2162 |
#else
|
2163 |
switch (check_spr_access(sprn, 1, ctx->supervisor)) |
2164 |
#endif
|
2165 |
{ |
2166 |
case -1: |
2167 |
RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR); |
2168 |
break;
|
2169 |
case 0: |
2170 |
RET_PRIVREG(ctx); |
2171 |
break;
|
2172 |
default:
|
2173 |
break;
|
2174 |
} |
2175 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
2176 |
switch (sprn) {
|
2177 |
case XER:
|
2178 |
gen_op_store_xer(); |
2179 |
break;
|
2180 |
case LR:
|
2181 |
gen_op_store_lr(); |
2182 |
break;
|
2183 |
case CTR:
|
2184 |
gen_op_store_ctr(); |
2185 |
break;
|
2186 |
case IBAT0U:
|
2187 |
gen_op_store_ibat(0, 0); |
2188 |
RET_MTMSR(ctx); |
2189 |
break;
|
2190 |
case IBAT1U:
|
2191 |
gen_op_store_ibat(0, 1); |
2192 |
RET_MTMSR(ctx); |
2193 |
break;
|
2194 |
case IBAT2U:
|
2195 |
gen_op_store_ibat(0, 2); |
2196 |
RET_MTMSR(ctx); |
2197 |
break;
|
2198 |
case IBAT3U:
|
2199 |
gen_op_store_ibat(0, 3); |
2200 |
RET_MTMSR(ctx); |
2201 |
break;
|
2202 |
case IBAT4U:
|
2203 |
gen_op_store_ibat(0, 4); |
2204 |
RET_MTMSR(ctx); |
2205 |
break;
|
2206 |
case IBAT5U:
|
2207 |
gen_op_store_ibat(0, 5); |
2208 |
RET_MTMSR(ctx); |
2209 |
break;
|
2210 |
case IBAT6U:
|
2211 |
gen_op_store_ibat(0, 6); |
2212 |
RET_MTMSR(ctx); |
2213 |
break;
|
2214 |
case IBAT7U:
|
2215 |
gen_op_store_ibat(0, 7); |
2216 |
RET_MTMSR(ctx); |
2217 |
break;
|
2218 |
case IBAT0L:
|
2219 |
gen_op_store_ibat(1, 0); |
2220 |
RET_MTMSR(ctx); |
2221 |
break;
|
2222 |
case IBAT1L:
|
2223 |
gen_op_store_ibat(1, 1); |
2224 |
RET_MTMSR(ctx); |
2225 |
break;
|
2226 |
case IBAT2L:
|
2227 |
gen_op_store_ibat(1, 2); |
2228 |
RET_MTMSR(ctx); |
2229 |
break;
|
2230 |
case IBAT3L:
|
2231 |
gen_op_store_ibat(1, 3); |
2232 |
RET_MTMSR(ctx); |
2233 |
break;
|
2234 |
case IBAT4L:
|
2235 |
gen_op_store_ibat(1, 4); |
2236 |
RET_MTMSR(ctx); |
2237 |
break;
|
2238 |
case IBAT5L:
|
2239 |
gen_op_store_ibat(1, 5); |
2240 |
RET_MTMSR(ctx); |
2241 |
break;
|
2242 |
case IBAT6L:
|
2243 |
gen_op_store_ibat(1, 6); |
2244 |
RET_MTMSR(ctx); |
2245 |
break;
|
2246 |
case IBAT7L:
|
2247 |
gen_op_store_ibat(1, 7); |
2248 |
RET_MTMSR(ctx); |
2249 |
break;
|
2250 |
case DBAT0U:
|
2251 |
gen_op_store_dbat(0, 0); |
2252 |
RET_MTMSR(ctx); |
2253 |
break;
|
2254 |
case DBAT1U:
|
2255 |
gen_op_store_dbat(0, 1); |
2256 |
RET_MTMSR(ctx); |
2257 |
break;
|
2258 |
case DBAT2U:
|
2259 |
gen_op_store_dbat(0, 2); |
2260 |
RET_MTMSR(ctx); |
2261 |
break;
|
2262 |
case DBAT3U:
|
2263 |
gen_op_store_dbat(0, 3); |
2264 |
RET_MTMSR(ctx); |
2265 |
break;
|
2266 |
case DBAT4U:
|
2267 |
gen_op_store_dbat(0, 4); |
2268 |
RET_MTMSR(ctx); |
2269 |
break;
|
2270 |
case DBAT5U:
|
2271 |
gen_op_store_dbat(0, 5); |
2272 |
RET_MTMSR(ctx); |
2273 |
break;
|
2274 |
case DBAT6U:
|
2275 |
gen_op_store_dbat(0, 6); |
2276 |
RET_MTMSR(ctx); |
2277 |
break;
|
2278 |
case DBAT7U:
|
2279 |
gen_op_store_dbat(0, 7); |
2280 |
RET_MTMSR(ctx); |
2281 |
break;
|
2282 |
case DBAT0L:
|
2283 |
gen_op_store_dbat(1, 0); |
2284 |
RET_MTMSR(ctx); |
2285 |
break;
|
2286 |
case DBAT1L:
|
2287 |
gen_op_store_dbat(1, 1); |
2288 |
RET_MTMSR(ctx); |
2289 |
break;
|
2290 |
case DBAT2L:
|
2291 |
gen_op_store_dbat(1, 2); |
2292 |
RET_MTMSR(ctx); |
2293 |
break;
|
2294 |
case DBAT3L:
|
2295 |
gen_op_store_dbat(1, 3); |
2296 |
RET_MTMSR(ctx); |
2297 |
break;
|
2298 |
case DBAT4L:
|
2299 |
gen_op_store_dbat(1, 4); |
2300 |
RET_MTMSR(ctx); |
2301 |
break;
|
2302 |
case DBAT5L:
|
2303 |
gen_op_store_dbat(1, 5); |
2304 |
RET_MTMSR(ctx); |
2305 |
break;
|
2306 |
case DBAT6L:
|
2307 |
gen_op_store_dbat(1, 6); |
2308 |
RET_MTMSR(ctx); |
2309 |
break;
|
2310 |
case DBAT7L:
|
2311 |
gen_op_store_dbat(1, 7); |
2312 |
RET_MTMSR(ctx); |
2313 |
break;
|
2314 |
case SDR1:
|
2315 |
gen_op_store_sdr1(); |
2316 |
RET_MTMSR(ctx); |
2317 |
break;
|
2318 |
case O_TBL:
|
2319 |
gen_op_store_tbl(); |
2320 |
break;
|
2321 |
case O_TBU:
|
2322 |
gen_op_store_tbu(); |
2323 |
break;
|
2324 |
case DECR:
|
2325 |
gen_op_store_decr(); |
2326 |
break;
|
2327 |
default:
|
2328 |
gen_op_store_spr(sprn); |
2329 |
break;
|
2330 |
} |
2331 |
} |
2332 |
|
2333 |
/*** Cache management ***/
|
2334 |
/* For now, all those will be implemented as nop:
|
2335 |
* this is valid, regarding the PowerPC specs...
|
2336 |
* We just have to flush tb while invalidating instruction cache lines...
|
2337 |
*/
|
2338 |
/* dcbf */
|
2339 |
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE) |
2340 |
{ |
2341 |
if (rA(ctx->opcode) == 0) { |
2342 |
gen_op_load_gpr_T0(rB(ctx->opcode)); |
2343 |
} else {
|
2344 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
2345 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
2346 |
gen_op_add(); |
2347 |
} |
2348 |
op_ldst(lbz); |
2349 |
} |
2350 |
|
2351 |
/* dcbi (Supervisor only) */
|
2352 |
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE) |
2353 |
{ |
2354 |
#if defined(CONFIG_USER_ONLY)
|
2355 |
RET_PRIVOPC(ctx); |
2356 |
#else
|
2357 |
if (!ctx->supervisor) {
|
2358 |
RET_PRIVOPC(ctx); |
2359 |
return;
|
2360 |
} |
2361 |
if (rA(ctx->opcode) == 0) { |
2362 |
gen_op_load_gpr_T0(rB(ctx->opcode)); |
2363 |
} else {
|
2364 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
2365 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
2366 |
gen_op_add(); |
2367 |
} |
2368 |
op_ldst(lbz); |
2369 |
op_ldst(stb); |
2370 |
#endif
|
2371 |
} |
2372 |
|
2373 |
/* dcdst */
|
2374 |
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE) |
2375 |
{ |
2376 |
if (rA(ctx->opcode) == 0) { |
2377 |
gen_op_load_gpr_T0(rB(ctx->opcode)); |
2378 |
} else {
|
2379 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
2380 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
2381 |
gen_op_add(); |
2382 |
} |
2383 |
op_ldst(lbz); |
2384 |
} |
2385 |
|
2386 |
/* dcbt */
|
2387 |
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE) |
2388 |
{ |
2389 |
} |
2390 |
|
2391 |
/* dcbtst */
|
2392 |
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE) |
2393 |
{ |
2394 |
} |
2395 |
|
2396 |
/* dcbz */
|
2397 |
#if defined(CONFIG_USER_ONLY)
|
2398 |
#define op_dcbz() gen_op_dcbz_raw()
|
2399 |
#else
|
2400 |
#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
|
2401 |
static GenOpFunc *gen_op_dcbz[] = {
|
2402 |
&gen_op_dcbz_user, |
2403 |
&gen_op_dcbz_kernel, |
2404 |
}; |
2405 |
#endif
|
2406 |
|
2407 |
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE) |
2408 |
{ |
2409 |
if (rA(ctx->opcode) == 0) { |
2410 |
gen_op_load_gpr_T0(rB(ctx->opcode)); |
2411 |
} else {
|
2412 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
2413 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
2414 |
gen_op_add(); |
2415 |
} |
2416 |
op_dcbz(); |
2417 |
gen_op_check_reservation(); |
2418 |
} |
2419 |
|
2420 |
/* icbi */
|
2421 |
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE) |
2422 |
{ |
2423 |
if (rA(ctx->opcode) == 0) { |
2424 |
gen_op_load_gpr_T0(rB(ctx->opcode)); |
2425 |
} else {
|
2426 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
2427 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
2428 |
gen_op_add(); |
2429 |
} |
2430 |
gen_op_icbi(); |
2431 |
} |
2432 |
|
2433 |
/* Optional: */
|
2434 |
/* dcba */
|
2435 |
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_OPT) |
2436 |
{ |
2437 |
} |
2438 |
|
2439 |
/*** Segment register manipulation ***/
|
2440 |
/* Supervisor only: */
|
2441 |
/* mfsr */
|
2442 |
GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT) |
2443 |
{ |
2444 |
#if defined(CONFIG_USER_ONLY)
|
2445 |
RET_PRIVREG(ctx); |
2446 |
#else
|
2447 |
if (!ctx->supervisor) {
|
2448 |
RET_PRIVREG(ctx); |
2449 |
return;
|
2450 |
} |
2451 |
gen_op_load_sr(SR(ctx->opcode)); |
2452 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
2453 |
#endif
|
2454 |
} |
2455 |
|
2456 |
/* mfsrin */
|
2457 |
GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT) |
2458 |
{ |
2459 |
#if defined(CONFIG_USER_ONLY)
|
2460 |
RET_PRIVREG(ctx); |
2461 |
#else
|
2462 |
if (!ctx->supervisor) {
|
2463 |
RET_PRIVREG(ctx); |
2464 |
return;
|
2465 |
} |
2466 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
2467 |
gen_op_load_srin(); |
2468 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
2469 |
#endif
|
2470 |
} |
2471 |
|
2472 |
/* mtsr */
|
2473 |
GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) |
2474 |
{ |
2475 |
#if defined(CONFIG_USER_ONLY)
|
2476 |
RET_PRIVREG(ctx); |
2477 |
#else
|
2478 |
if (!ctx->supervisor) {
|
2479 |
RET_PRIVREG(ctx); |
2480 |
return;
|
2481 |
} |
2482 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
2483 |
gen_op_store_sr(SR(ctx->opcode)); |
2484 |
#endif
|
2485 |
} |
2486 |
|
2487 |
/* mtsrin */
|
2488 |
GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT) |
2489 |
{ |
2490 |
#if defined(CONFIG_USER_ONLY)
|
2491 |
RET_PRIVREG(ctx); |
2492 |
#else
|
2493 |
if (!ctx->supervisor) {
|
2494 |
RET_PRIVREG(ctx); |
2495 |
return;
|
2496 |
} |
2497 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
2498 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
2499 |
gen_op_store_srin(); |
2500 |
#endif
|
2501 |
} |
2502 |
|
2503 |
/*** Lookaside buffer management ***/
|
2504 |
/* Optional & supervisor only: */
|
2505 |
/* tlbia */
|
2506 |
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT) |
2507 |
{ |
2508 |
#if defined(CONFIG_USER_ONLY)
|
2509 |
RET_PRIVOPC(ctx); |
2510 |
#else
|
2511 |
if (!ctx->supervisor) {
|
2512 |
if (loglevel)
|
2513 |
fprintf(logfile, "%s: ! supervisor\n", __func__);
|
2514 |
RET_PRIVOPC(ctx); |
2515 |
return;
|
2516 |
} |
2517 |
gen_op_tlbia(); |
2518 |
RET_MTMSR(ctx); |
2519 |
#endif
|
2520 |
} |
2521 |
|
2522 |
/* tlbie */
|
2523 |
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM) |
2524 |
{ |
2525 |
#if defined(CONFIG_USER_ONLY)
|
2526 |
RET_PRIVOPC(ctx); |
2527 |
#else
|
2528 |
if (!ctx->supervisor) {
|
2529 |
RET_PRIVOPC(ctx); |
2530 |
return;
|
2531 |
} |
2532 |
gen_op_load_gpr_T0(rB(ctx->opcode)); |
2533 |
gen_op_tlbie(); |
2534 |
RET_MTMSR(ctx); |
2535 |
#endif
|
2536 |
} |
2537 |
|
2538 |
/* tlbsync */
|
2539 |
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM) |
2540 |
{ |
2541 |
#if defined(CONFIG_USER_ONLY)
|
2542 |
RET_PRIVOPC(ctx); |
2543 |
#else
|
2544 |
if (!ctx->supervisor) {
|
2545 |
RET_PRIVOPC(ctx); |
2546 |
return;
|
2547 |
} |
2548 |
/* This has no effect: it should ensure that all previous
|
2549 |
* tlbie have completed
|
2550 |
*/
|
2551 |
RET_MTMSR(ctx); |
2552 |
#endif
|
2553 |
} |
2554 |
|
2555 |
/*** External control ***/
|
2556 |
/* Optional: */
|
2557 |
#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
|
2558 |
#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
|
2559 |
#if defined(CONFIG_USER_ONLY)
|
2560 |
static GenOpFunc *gen_op_eciwx[] = {
|
2561 |
&gen_op_eciwx_raw, |
2562 |
&gen_op_eciwx_le_raw, |
2563 |
}; |
2564 |
static GenOpFunc *gen_op_ecowx[] = {
|
2565 |
&gen_op_ecowx_raw, |
2566 |
&gen_op_ecowx_le_raw, |
2567 |
}; |
2568 |
#else
|
2569 |
static GenOpFunc *gen_op_eciwx[] = {
|
2570 |
&gen_op_eciwx_user, |
2571 |
&gen_op_eciwx_le_user, |
2572 |
&gen_op_eciwx_kernel, |
2573 |
&gen_op_eciwx_le_kernel, |
2574 |
}; |
2575 |
static GenOpFunc *gen_op_ecowx[] = {
|
2576 |
&gen_op_ecowx_user, |
2577 |
&gen_op_ecowx_le_user, |
2578 |
&gen_op_ecowx_kernel, |
2579 |
&gen_op_ecowx_le_kernel, |
2580 |
}; |
2581 |
#endif
|
2582 |
|
2583 |
/* eciwx */
|
2584 |
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN) |
2585 |
{ |
2586 |
/* Should check EAR[E] & alignment ! */
|
2587 |
if (rA(ctx->opcode) == 0) { |
2588 |
gen_op_load_gpr_T0(rB(ctx->opcode)); |
2589 |
} else {
|
2590 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
2591 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
2592 |
gen_op_add(); |
2593 |
} |
2594 |
op_eciwx(); |
2595 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
2596 |
} |
2597 |
|
2598 |
/* ecowx */
|
2599 |
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN) |
2600 |
{ |
2601 |
/* Should check EAR[E] & alignment ! */
|
2602 |
if (rA(ctx->opcode) == 0) { |
2603 |
gen_op_load_gpr_T0(rB(ctx->opcode)); |
2604 |
} else {
|
2605 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
2606 |
gen_op_load_gpr_T1(rB(ctx->opcode)); |
2607 |
gen_op_add(); |
2608 |
} |
2609 |
gen_op_load_gpr_T2(rS(ctx->opcode)); |
2610 |
op_ecowx(); |
2611 |
} |
2612 |
|
2613 |
/* End opcode list */
|
2614 |
GEN_OPCODE_MARK(end); |
2615 |
|
2616 |
/*****************************************************************************/
|
2617 |
#include <stdlib.h> |
2618 |
#include <string.h> |
2619 |
|
2620 |
int fflush (FILE *stream);
|
2621 |
|
2622 |
/* Main ppc opcodes table:
|
2623 |
* at init, all opcodes are invalids
|
2624 |
*/
|
2625 |
static opc_handler_t *ppc_opcodes[0x40]; |
2626 |
|
2627 |
/* Opcode types */
|
2628 |
enum {
|
2629 |
PPC_DIRECT = 0, /* Opcode routine */ |
2630 |
PPC_INDIRECT = 1, /* Indirect opcode table */ |
2631 |
}; |
2632 |
|
2633 |
static inline int is_indirect_opcode (void *handler) |
2634 |
{ |
2635 |
return ((unsigned long)handler & 0x03) == PPC_INDIRECT; |
2636 |
} |
2637 |
|
2638 |
static inline opc_handler_t **ind_table(void *handler) |
2639 |
{ |
2640 |
return (opc_handler_t **)((unsigned long)handler & ~3); |
2641 |
} |
2642 |
|
2643 |
/* Instruction table creation */
|
2644 |
/* Opcodes tables creation */
|
2645 |
static void fill_new_table (opc_handler_t **table, int len) |
2646 |
{ |
2647 |
int i;
|
2648 |
|
2649 |
for (i = 0; i < len; i++) |
2650 |
table[i] = &invalid_handler; |
2651 |
} |
2652 |
|
2653 |
static int create_new_table (opc_handler_t **table, unsigned char idx) |
2654 |
{ |
2655 |
opc_handler_t **tmp; |
2656 |
|
2657 |
tmp = malloc(0x20 * sizeof(opc_handler_t)); |
2658 |
if (tmp == NULL) |
2659 |
return -1; |
2660 |
fill_new_table(tmp, 0x20);
|
2661 |
table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT); |
2662 |
|
2663 |
return 0; |
2664 |
} |
2665 |
|
2666 |
static int insert_in_table (opc_handler_t **table, unsigned char idx, |
2667 |
opc_handler_t *handler) |
2668 |
{ |
2669 |
if (table[idx] != &invalid_handler)
|
2670 |
return -1; |
2671 |
table[idx] = handler; |
2672 |
|
2673 |
return 0; |
2674 |
} |
2675 |
|
2676 |
static int register_direct_insn (opc_handler_t **ppc_opcodes, |
2677 |
unsigned char idx, opc_handler_t *handler) |
2678 |
{ |
2679 |
if (insert_in_table(ppc_opcodes, idx, handler) < 0) { |
2680 |
printf("*** ERROR: opcode %02x already assigned in main "
|
2681 |
"opcode table\n", idx);
|
2682 |
return -1; |
2683 |
} |
2684 |
|
2685 |
return 0; |
2686 |
} |
2687 |
|
2688 |
static int register_ind_in_table (opc_handler_t **table, |
2689 |
unsigned char idx1, unsigned char idx2, |
2690 |
opc_handler_t *handler) |
2691 |
{ |
2692 |
if (table[idx1] == &invalid_handler) {
|
2693 |
if (create_new_table(table, idx1) < 0) { |
2694 |
printf("*** ERROR: unable to create indirect table "
|
2695 |
"idx=%02x\n", idx1);
|
2696 |
return -1; |
2697 |
} |
2698 |
} else {
|
2699 |
if (!is_indirect_opcode(table[idx1])) {
|
2700 |
printf("*** ERROR: idx %02x already assigned to a direct "
|
2701 |
"opcode\n", idx1);
|
2702 |
return -1; |
2703 |
} |
2704 |
} |
2705 |
if (handler != NULL && |
2706 |
insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
|
2707 |
printf("*** ERROR: opcode %02x already assigned in "
|
2708 |
"opcode table %02x\n", idx2, idx1);
|
2709 |
return -1; |
2710 |
} |
2711 |
|
2712 |
return 0; |
2713 |
} |
2714 |
|
2715 |
static int register_ind_insn (opc_handler_t **ppc_opcodes, |
2716 |
unsigned char idx1, unsigned char idx2, |
2717 |
opc_handler_t *handler) |
2718 |
{ |
2719 |
int ret;
|
2720 |
|
2721 |
ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler); |
2722 |
|
2723 |
return ret;
|
2724 |
} |
2725 |
|
2726 |
static int register_dblind_insn (opc_handler_t **ppc_opcodes, |
2727 |
unsigned char idx1, unsigned char idx2, |
2728 |
unsigned char idx3, opc_handler_t *handler) |
2729 |
{ |
2730 |
if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { |
2731 |
printf("*** ERROR: unable to join indirect table idx "
|
2732 |
"[%02x-%02x]\n", idx1, idx2);
|
2733 |
return -1; |
2734 |
} |
2735 |
if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
|
2736 |
handler) < 0) {
|
2737 |
printf("*** ERROR: unable to insert opcode "
|
2738 |
"[%02x-%02x-%02x]\n", idx1, idx2, idx3);
|
2739 |
return -1; |
2740 |
} |
2741 |
|
2742 |
return 0; |
2743 |
} |
2744 |
|
2745 |
static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) |
2746 |
{ |
2747 |
if (insn->opc2 != 0xFF) { |
2748 |
if (insn->opc3 != 0xFF) { |
2749 |
if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
|
2750 |
insn->opc3, &insn->handler) < 0)
|
2751 |
return -1; |
2752 |
} else {
|
2753 |
if (register_ind_insn(ppc_opcodes, insn->opc1,
|
2754 |
insn->opc2, &insn->handler) < 0)
|
2755 |
return -1; |
2756 |
} |
2757 |
} else {
|
2758 |
if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) |
2759 |
return -1; |
2760 |
} |
2761 |
|
2762 |
return 0; |
2763 |
} |
2764 |
|
2765 |
static int test_opcode_table (opc_handler_t **table, int len) |
2766 |
{ |
2767 |
int i, count, tmp;
|
2768 |
|
2769 |
for (i = 0, count = 0; i < len; i++) { |
2770 |
/* Consistency fixup */
|
2771 |
if (table[i] == NULL) |
2772 |
table[i] = &invalid_handler; |
2773 |
if (table[i] != &invalid_handler) {
|
2774 |
if (is_indirect_opcode(table[i])) {
|
2775 |
tmp = test_opcode_table(ind_table(table[i]), 0x20);
|
2776 |
if (tmp == 0) { |
2777 |
free(table[i]); |
2778 |
table[i] = &invalid_handler; |
2779 |
} else {
|
2780 |
count++; |
2781 |
} |
2782 |
} else {
|
2783 |
count++; |
2784 |
} |
2785 |
} |
2786 |
} |
2787 |
|
2788 |
return count;
|
2789 |
} |
2790 |
|
2791 |
static void fix_opcode_tables (opc_handler_t **ppc_opcodes) |
2792 |
{ |
2793 |
if (test_opcode_table(ppc_opcodes, 0x40) == 0) |
2794 |
printf("*** WARNING: no opcode defined !\n");
|
2795 |
} |
2796 |
|
2797 |
#define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw))) |
2798 |
#define SPR_UR SPR_RIGHTS(0, 0) |
2799 |
#define SPR_UW SPR_RIGHTS(1, 0) |
2800 |
#define SPR_SR SPR_RIGHTS(0, 1) |
2801 |
#define SPR_SW SPR_RIGHTS(1, 1) |
2802 |
|
2803 |
#define spr_set_rights(spr, rights) \
|
2804 |
do { \
|
2805 |
spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \ |
2806 |
} while (0) |
2807 |
|
2808 |
static void init_spr_rights (uint32_t pvr) |
2809 |
{ |
2810 |
/* XER (SPR 1) */
|
2811 |
spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW); |
2812 |
/* LR (SPR 8) */
|
2813 |
spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW); |
2814 |
/* CTR (SPR 9) */
|
2815 |
spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW); |
2816 |
/* TBL (SPR 268) */
|
2817 |
spr_set_rights(V_TBL, SPR_UR | SPR_SR); |
2818 |
/* TBU (SPR 269) */
|
2819 |
spr_set_rights(V_TBU, SPR_UR | SPR_SR); |
2820 |
/* DSISR (SPR 18) */
|
2821 |
spr_set_rights(DSISR, SPR_SR | SPR_SW); |
2822 |
/* DAR (SPR 19) */
|
2823 |
spr_set_rights(DAR, SPR_SR | SPR_SW); |
2824 |
/* DEC (SPR 22) */
|
2825 |
spr_set_rights(DECR, SPR_SR | SPR_SW); |
2826 |
/* SDR1 (SPR 25) */
|
2827 |
spr_set_rights(SDR1, SPR_SR | SPR_SW); |
2828 |
/* SRR0 (SPR 26) */
|
2829 |
spr_set_rights(SRR0, SPR_SR | SPR_SW); |
2830 |
/* SRR1 (SPR 27) */
|
2831 |
spr_set_rights(SRR1, SPR_SR | SPR_SW); |
2832 |
/* SPRG0 (SPR 272) */
|
2833 |
spr_set_rights(SPRG0, SPR_SR | SPR_SW); |
2834 |
/* SPRG1 (SPR 273) */
|
2835 |
spr_set_rights(SPRG1, SPR_SR | SPR_SW); |
2836 |
/* SPRG2 (SPR 274) */
|
2837 |
spr_set_rights(SPRG2, SPR_SR | SPR_SW); |
2838 |
/* SPRG3 (SPR 275) */
|
2839 |
spr_set_rights(SPRG3, SPR_SR | SPR_SW); |
2840 |
/* ASR (SPR 280) */
|
2841 |
spr_set_rights(ASR, SPR_SR | SPR_SW); |
2842 |
/* EAR (SPR 282) */
|
2843 |
spr_set_rights(EAR, SPR_SR | SPR_SW); |
2844 |
/* TBL (SPR 284) */
|
2845 |
spr_set_rights(O_TBL, SPR_SW); |
2846 |
/* TBU (SPR 285) */
|
2847 |
spr_set_rights(O_TBU, SPR_SW); |
2848 |
/* PVR (SPR 287) */
|
2849 |
spr_set_rights(PVR, SPR_SR); |
2850 |
/* IBAT0U (SPR 528) */
|
2851 |
spr_set_rights(IBAT0U, SPR_SR | SPR_SW); |
2852 |
/* IBAT0L (SPR 529) */
|
2853 |
spr_set_rights(IBAT0L, SPR_SR | SPR_SW); |
2854 |
/* IBAT1U (SPR 530) */
|
2855 |
spr_set_rights(IBAT1U, SPR_SR | SPR_SW); |
2856 |
/* IBAT1L (SPR 531) */
|
2857 |
spr_set_rights(IBAT1L, SPR_SR | SPR_SW); |
2858 |
/* IBAT2U (SPR 532) */
|
2859 |
spr_set_rights(IBAT2U, SPR_SR | SPR_SW); |
2860 |
/* IBAT2L (SPR 533) */
|
2861 |
spr_set_rights(IBAT2L, SPR_SR | SPR_SW); |
2862 |
/* IBAT3U (SPR 534) */
|
2863 |
spr_set_rights(IBAT3U, SPR_SR | SPR_SW); |
2864 |
/* IBAT3L (SPR 535) */
|
2865 |
spr_set_rights(IBAT3L, SPR_SR | SPR_SW); |
2866 |
/* DBAT0U (SPR 536) */
|
2867 |
spr_set_rights(DBAT0U, SPR_SR | SPR_SW); |
2868 |
/* DBAT0L (SPR 537) */
|
2869 |
spr_set_rights(DBAT0L, SPR_SR | SPR_SW); |
2870 |
/* DBAT1U (SPR 538) */
|
2871 |
spr_set_rights(DBAT1U, SPR_SR | SPR_SW); |
2872 |
/* DBAT1L (SPR 539) */
|
2873 |
spr_set_rights(DBAT1L, SPR_SR | SPR_SW); |
2874 |
/* DBAT2U (SPR 540) */
|
2875 |
spr_set_rights(DBAT2U, SPR_SR | SPR_SW); |
2876 |
/* DBAT2L (SPR 541) */
|
2877 |
spr_set_rights(DBAT2L, SPR_SR | SPR_SW); |
2878 |
/* DBAT3U (SPR 542) */
|
2879 |
spr_set_rights(DBAT3U, SPR_SR | SPR_SW); |
2880 |
/* DBAT3L (SPR 543) */
|
2881 |
spr_set_rights(DBAT3L, SPR_SR | SPR_SW); |
2882 |
/* FPECR (SPR 1022) */
|
2883 |
spr_set_rights(FPECR, SPR_SR | SPR_SW); |
2884 |
/* Special registers for PPC 604 */
|
2885 |
if ((pvr & 0xFFFF0000) == 0x00040000) { |
2886 |
/* IABR */
|
2887 |
spr_set_rights(IABR , SPR_SR | SPR_SW); |
2888 |
/* DABR (SPR 1013) */
|
2889 |
spr_set_rights(DABR, SPR_SR | SPR_SW); |
2890 |
/* HID0 */
|
2891 |
spr_set_rights(HID0, SPR_SR | SPR_SW); |
2892 |
/* PIR */
|
2893 |
spr_set_rights(PIR, SPR_SR | SPR_SW); |
2894 |
/* PMC1 */
|
2895 |
spr_set_rights(PMC1, SPR_SR | SPR_SW); |
2896 |
/* PMC2 */
|
2897 |
spr_set_rights(PMC2, SPR_SR | SPR_SW); |
2898 |
/* MMCR0 */
|
2899 |
spr_set_rights(MMCR0, SPR_SR | SPR_SW); |
2900 |
/* SIA */
|
2901 |
spr_set_rights(SIA, SPR_SR | SPR_SW); |
2902 |
/* SDA */
|
2903 |
spr_set_rights(SDA, SPR_SR | SPR_SW); |
2904 |
} |
2905 |
/* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
|
2906 |
if ((pvr & 0xFFFF0000) == 0x00080000 || |
2907 |
(pvr & 0xFFFF0000) == 0x70000000) { |
2908 |
/* HID0 */
|
2909 |
spr_set_rights(HID0, SPR_SR | SPR_SW); |
2910 |
/* HID1 */
|
2911 |
spr_set_rights(HID1, SPR_SR | SPR_SW); |
2912 |
/* IABR */
|
2913 |
spr_set_rights(IABR, SPR_SR | SPR_SW); |
2914 |
/* ICTC */
|
2915 |
spr_set_rights(ICTC, SPR_SR | SPR_SW); |
2916 |
/* L2CR */
|
2917 |
spr_set_rights(L2CR, SPR_SR | SPR_SW); |
2918 |
/* MMCR0 */
|
2919 |
spr_set_rights(MMCR0, SPR_SR | SPR_SW); |
2920 |
/* MMCR1 */
|
2921 |
spr_set_rights(MMCR1, SPR_SR | SPR_SW); |
2922 |
/* PMC1 */
|
2923 |
spr_set_rights(PMC1, SPR_SR | SPR_SW); |
2924 |
/* PMC2 */
|
2925 |
spr_set_rights(PMC2, SPR_SR | SPR_SW); |
2926 |
/* PMC3 */
|
2927 |
spr_set_rights(PMC3, SPR_SR | SPR_SW); |
2928 |
/* PMC4 */
|
2929 |
spr_set_rights(PMC4, SPR_SR | SPR_SW); |
2930 |
/* SIA */
|
2931 |
spr_set_rights(SIA, SPR_SR | SPR_SW); |
2932 |
/* SDA */
|
2933 |
spr_set_rights(SDA, SPR_SR | SPR_SW); |
2934 |
/* THRM1 */
|
2935 |
spr_set_rights(THRM1, SPR_SR | SPR_SW); |
2936 |
/* THRM2 */
|
2937 |
spr_set_rights(THRM2, SPR_SR | SPR_SW); |
2938 |
/* THRM3 */
|
2939 |
spr_set_rights(THRM3, SPR_SR | SPR_SW); |
2940 |
/* UMMCR0 */
|
2941 |
spr_set_rights(UMMCR0, SPR_UR | SPR_UW); |
2942 |
/* UMMCR1 */
|
2943 |
spr_set_rights(UMMCR1, SPR_UR | SPR_UW); |
2944 |
/* UPMC1 */
|
2945 |
spr_set_rights(UPMC1, SPR_UR | SPR_UW); |
2946 |
/* UPMC2 */
|
2947 |
spr_set_rights(UPMC2, SPR_UR | SPR_UW); |
2948 |
/* UPMC3 */
|
2949 |
spr_set_rights(UPMC3, SPR_UR | SPR_UW); |
2950 |
/* UPMC4 */
|
2951 |
spr_set_rights(UPMC4, SPR_UR | SPR_UW); |
2952 |
/* USIA */
|
2953 |
spr_set_rights(USIA, SPR_UR | SPR_UW); |
2954 |
} |
2955 |
/* MPC755 has special registers */
|
2956 |
if (pvr == 0x00083100) { |
2957 |
/* SPRG4 */
|
2958 |
spr_set_rights(SPRG4, SPR_SR | SPR_SW); |
2959 |
/* SPRG5 */
|
2960 |
spr_set_rights(SPRG5, SPR_SR | SPR_SW); |
2961 |
/* SPRG6 */
|
2962 |
spr_set_rights(SPRG6, SPR_SR | SPR_SW); |
2963 |
/* SPRG7 */
|
2964 |
spr_set_rights(SPRG7, SPR_SR | SPR_SW); |
2965 |
/* IBAT4U */
|
2966 |
spr_set_rights(IBAT4U, SPR_SR | SPR_SW); |
2967 |
/* IBAT4L */
|
2968 |
spr_set_rights(IBAT4L, SPR_SR | SPR_SW); |
2969 |
/* IBAT5U */
|
2970 |
spr_set_rights(IBAT5U, SPR_SR | SPR_SW); |
2971 |
/* IBAT5L */
|
2972 |
spr_set_rights(IBAT5L, SPR_SR | SPR_SW); |
2973 |
/* IBAT6U */
|
2974 |
spr_set_rights(IBAT6U, SPR_SR | SPR_SW); |
2975 |
/* IBAT6L */
|
2976 |
spr_set_rights(IBAT6L, SPR_SR | SPR_SW); |
2977 |
/* IBAT7U */
|
2978 |
spr_set_rights(IBAT7U, SPR_SR | SPR_SW); |
2979 |
/* IBAT7L */
|
2980 |
spr_set_rights(IBAT7L, SPR_SR | SPR_SW); |
2981 |
/* DBAT4U */
|
2982 |
spr_set_rights(DBAT4U, SPR_SR | SPR_SW); |
2983 |
/* DBAT4L */
|
2984 |
spr_set_rights(DBAT4L, SPR_SR | SPR_SW); |
2985 |
/* DBAT5U */
|
2986 |
spr_set_rights(DBAT5U, SPR_SR | SPR_SW); |
2987 |
/* DBAT5L */
|
2988 |
spr_set_rights(DBAT5L, SPR_SR | SPR_SW); |
2989 |
/* DBAT6U */
|
2990 |
spr_set_rights(DBAT6U, SPR_SR | SPR_SW); |
2991 |
/* DBAT6L */
|
2992 |
spr_set_rights(DBAT6L, SPR_SR | SPR_SW); |
2993 |
/* DBAT7U */
|
2994 |
spr_set_rights(DBAT7U, SPR_SR | SPR_SW); |
2995 |
/* DBAT7L */
|
2996 |
spr_set_rights(DBAT7L, SPR_SR | SPR_SW); |
2997 |
/* DMISS */
|
2998 |
spr_set_rights(DMISS, SPR_SR | SPR_SW); |
2999 |
/* DCMP */
|
3000 |
spr_set_rights(DCMP, SPR_SR | SPR_SW); |
3001 |
/* DHASH1 */
|
3002 |
spr_set_rights(DHASH1, SPR_SR | SPR_SW); |
3003 |
/* DHASH2 */
|
3004 |
spr_set_rights(DHASH2, SPR_SR | SPR_SW); |
3005 |
/* IMISS */
|
3006 |
spr_set_rights(IMISS, SPR_SR | SPR_SW); |
3007 |
/* ICMP */
|
3008 |
spr_set_rights(ICMP, SPR_SR | SPR_SW); |
3009 |
/* RPA */
|
3010 |
spr_set_rights(RPA, SPR_SR | SPR_SW); |
3011 |
/* HID2 */
|
3012 |
spr_set_rights(HID2, SPR_SR | SPR_SW); |
3013 |
/* L2PM */
|
3014 |
spr_set_rights(L2PM, SPR_SR | SPR_SW); |
3015 |
} |
3016 |
} |
3017 |
|
3018 |
/*****************************************************************************/
|
3019 |
/* PPC "main stream" common instructions (no optional ones) */
|
3020 |
|
3021 |
typedef struct ppc_proc_t { |
3022 |
int flags;
|
3023 |
void *specific;
|
3024 |
} ppc_proc_t; |
3025 |
|
3026 |
typedef struct ppc_def_t { |
3027 |
unsigned long pvr; |
3028 |
unsigned long pvr_mask; |
3029 |
ppc_proc_t *proc; |
3030 |
} ppc_def_t; |
3031 |
|
3032 |
static ppc_proc_t ppc_proc_common = {
|
3033 |
.flags = PPC_COMMON, |
3034 |
.specific = NULL,
|
3035 |
}; |
3036 |
|
3037 |
static ppc_proc_t ppc_proc_G3 = {
|
3038 |
.flags = PPC_750, |
3039 |
.specific = NULL,
|
3040 |
}; |
3041 |
|
3042 |
static ppc_def_t ppc_defs[] =
|
3043 |
{ |
3044 |
/* MPC740/745/750/755 (G3) */
|
3045 |
{ |
3046 |
.pvr = 0x00080000,
|
3047 |
.pvr_mask = 0xFFFF0000,
|
3048 |
.proc = &ppc_proc_G3, |
3049 |
}, |
3050 |
/* IBM 750FX (G3 embedded) */
|
3051 |
{ |
3052 |
.pvr = 0x70000000,
|
3053 |
.pvr_mask = 0xFFFF0000,
|
3054 |
.proc = &ppc_proc_G3, |
3055 |
}, |
3056 |
/* Fallback (generic PPC) */
|
3057 |
{ |
3058 |
.pvr = 0x00000000,
|
3059 |
.pvr_mask = 0x00000000,
|
3060 |
.proc = &ppc_proc_common, |
3061 |
}, |
3062 |
}; |
3063 |
|
3064 |
static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr) |
3065 |
{ |
3066 |
opcode_t *opc, *start, *end; |
3067 |
int i, flags;
|
3068 |
|
3069 |
fill_new_table(ppc_opcodes, 0x40);
|
3070 |
for (i = 0; ; i++) { |
3071 |
if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) ==
|
3072 |
(pvr & ppc_defs[i].pvr_mask)) { |
3073 |
flags = ppc_defs[i].proc->flags; |
3074 |
break;
|
3075 |
} |
3076 |
} |
3077 |
|
3078 |
if (&opc_start < &opc_end) {
|
3079 |
start = &opc_start; |
3080 |
end = &opc_end; |
3081 |
} else {
|
3082 |
start = &opc_end; |
3083 |
end = &opc_start; |
3084 |
} |
3085 |
for (opc = start + 1; opc != end; opc++) { |
3086 |
if ((opc->handler.type & flags) != 0) |
3087 |
if (register_insn(ppc_opcodes, opc) < 0) { |
3088 |
printf("*** ERROR initializing PPC instruction "
|
3089 |
"0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
|
3090 |
opc->opc3); |
3091 |
return -1; |
3092 |
} |
3093 |
} |
3094 |
fix_opcode_tables(ppc_opcodes); |
3095 |
|
3096 |
return 0; |
3097 |
} |
3098 |
|
3099 |
|
3100 |
/*****************************************************************************/
|
3101 |
/* Misc PPC helpers */
|
3102 |
|
3103 |
void cpu_dump_state(CPUState *env, FILE *f,
|
3104 |
int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
3105 |
int flags)
|
3106 |
{ |
3107 |
int i;
|
3108 |
|
3109 |
cpu_fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
|
3110 |
"MSR=0x%08x\n", env->nip, env->lr, env->ctr,
|
3111 |
_load_xer(env), _load_msr(env)); |
3112 |
for (i = 0; i < 32; i++) { |
3113 |
if ((i & 7) == 0) |
3114 |
cpu_fprintf(f, "GPR%02d:", i);
|
3115 |
cpu_fprintf(f, " %08x", env->gpr[i]);
|
3116 |
if ((i & 7) == 7) |
3117 |
cpu_fprintf(f, "\n");
|
3118 |
} |
3119 |
cpu_fprintf(f, "CR: 0x");
|
3120 |
for (i = 0; i < 8; i++) |
3121 |
cpu_fprintf(f, "%01x", env->crf[i]);
|
3122 |
cpu_fprintf(f, " [");
|
3123 |
for (i = 0; i < 8; i++) { |
3124 |
char a = '-'; |
3125 |
if (env->crf[i] & 0x08) |
3126 |
a = 'L';
|
3127 |
else if (env->crf[i] & 0x04) |
3128 |
a = 'G';
|
3129 |
else if (env->crf[i] & 0x02) |
3130 |
a = 'E';
|
3131 |
cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
3132 |
} |
3133 |
cpu_fprintf(f, " ] ");
|
3134 |
cpu_fprintf(f, "TB: 0x%08x %08x\n", cpu_ppc_load_tbu(env),
|
3135 |
cpu_ppc_load_tbl(env)); |
3136 |
for (i = 0; i < 16; i++) { |
3137 |
if ((i & 3) == 0) |
3138 |
cpu_fprintf(f, "FPR%02d:", i);
|
3139 |
cpu_fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i]));
|
3140 |
if ((i & 3) == 3) |
3141 |
cpu_fprintf(f, "\n");
|
3142 |
} |
3143 |
cpu_fprintf(f, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x\n",
|
3144 |
env->spr[SRR0], env->spr[SRR1], cpu_ppc_load_decr(env)); |
3145 |
cpu_fprintf(f, "reservation 0x%08x\n", env->reserve);
|
3146 |
} |
3147 |
|
3148 |
CPUPPCState *cpu_ppc_init(void)
|
3149 |
{ |
3150 |
CPUPPCState *env; |
3151 |
|
3152 |
cpu_exec_init(); |
3153 |
|
3154 |
env = qemu_mallocz(sizeof(CPUPPCState));
|
3155 |
if (!env)
|
3156 |
return NULL; |
3157 |
// env->spr[PVR] = 0; /* Basic PPC */
|
3158 |
env->spr[PVR] = 0x00080100; /* G3 CPU */ |
3159 |
// env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
|
3160 |
// env->spr[PVR] = 0x00070100; /* IBM 750FX */
|
3161 |
tlb_flush(env, 1);
|
3162 |
#if defined (DO_SINGLE_STEP)
|
3163 |
/* Single step trace mode */
|
3164 |
msr_se = 1;
|
3165 |
#endif
|
3166 |
msr_fp = 1; /* Allow floating point exceptions */ |
3167 |
msr_me = 1; /* Allow machine check exceptions */ |
3168 |
#if defined(CONFIG_USER_ONLY)
|
3169 |
msr_pr = 1;
|
3170 |
cpu_ppc_register(env, 0x00080000);
|
3171 |
#else
|
3172 |
env->nip = 0xFFFFFFFC;
|
3173 |
#endif
|
3174 |
cpu_single_env = env; |
3175 |
return env;
|
3176 |
} |
3177 |
|
3178 |
int cpu_ppc_register (CPUPPCState *env, uint32_t pvr)
|
3179 |
{ |
3180 |
env->spr[PVR] = pvr; |
3181 |
if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0) |
3182 |
return -1; |
3183 |
init_spr_rights(env->spr[PVR]); |
3184 |
|
3185 |
return 0; |
3186 |
} |
3187 |
|
3188 |
void cpu_ppc_close(CPUPPCState *env)
|
3189 |
{ |
3190 |
/* Should also remove all opcode tables... */
|
3191 |
free(env); |
3192 |
} |
3193 |
|
3194 |
/*****************************************************************************/
|
3195 |
int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
|
3196 |
int search_pc)
|
3197 |
{ |
3198 |
DisasContext ctx, *ctxp = &ctx; |
3199 |
opc_handler_t **table, *handler; |
3200 |
target_ulong pc_start; |
3201 |
uint16_t *gen_opc_end; |
3202 |
int j, lj = -1; |
3203 |
|
3204 |
pc_start = tb->pc; |
3205 |
gen_opc_ptr = gen_opc_buf; |
3206 |
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
3207 |
gen_opparam_ptr = gen_opparam_buf; |
3208 |
ctx.nip = pc_start; |
3209 |
ctx.tb = tb; |
3210 |
ctx.exception = EXCP_NONE; |
3211 |
#if defined(CONFIG_USER_ONLY)
|
3212 |
ctx.mem_idx = msr_le; |
3213 |
#else
|
3214 |
ctx.supervisor = 1 - msr_pr;
|
3215 |
ctx.mem_idx = ((1 - msr_pr) << 1) | msr_le; |
3216 |
#endif
|
3217 |
ctx.fpu_enabled = msr_fp; |
3218 |
#if defined (DO_SINGLE_STEP)
|
3219 |
/* Single step trace mode */
|
3220 |
msr_se = 1;
|
3221 |
#endif
|
3222 |
/* Set env in case of segfault during code fetch */
|
3223 |
while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
|
3224 |
if (search_pc) {
|
3225 |
j = gen_opc_ptr - gen_opc_buf; |
3226 |
if (lj < j) {
|
3227 |
lj++; |
3228 |
while (lj < j)
|
3229 |
gen_opc_instr_start[lj++] = 0;
|
3230 |
gen_opc_pc[lj] = ctx.nip; |
3231 |
gen_opc_instr_start[lj] = 1;
|
3232 |
} |
3233 |
} |
3234 |
#if defined PPC_DEBUG_DISAS
|
3235 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
3236 |
fprintf(logfile, "----------------\n");
|
3237 |
fprintf(logfile, "nip=%08x super=%d ir=%d\n",
|
3238 |
ctx.nip, 1 - msr_pr, msr_ir);
|
3239 |
} |
3240 |
#endif
|
3241 |
ctx.opcode = ldl_code(ctx.nip); |
3242 |
if (msr_le) {
|
3243 |
ctx.opcode = ((ctx.opcode & 0xFF000000) >> 24) | |
3244 |
((ctx.opcode & 0x00FF0000) >> 8) | |
3245 |
((ctx.opcode & 0x0000FF00) << 8) | |
3246 |
((ctx.opcode & 0x000000FF) << 24); |
3247 |
} |
3248 |
#if defined PPC_DEBUG_DISAS
|
3249 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
3250 |
fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
|
3251 |
ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
3252 |
opc3(ctx.opcode), msr_le ? "little" : "big"); |
3253 |
} |
3254 |
#endif
|
3255 |
ctx.nip += 4;
|
3256 |
table = ppc_opcodes; |
3257 |
handler = table[opc1(ctx.opcode)]; |
3258 |
if (is_indirect_opcode(handler)) {
|
3259 |
table = ind_table(handler); |
3260 |
handler = table[opc2(ctx.opcode)]; |
3261 |
if (is_indirect_opcode(handler)) {
|
3262 |
table = ind_table(handler); |
3263 |
handler = table[opc3(ctx.opcode)]; |
3264 |
} |
3265 |
} |
3266 |
/* Is opcode *REALLY* valid ? */
|
3267 |
if (handler->handler == &gen_invalid) {
|
3268 |
if (loglevel > 0) { |
3269 |
fprintf(logfile, "invalid/unsupported opcode: "
|
3270 |
"%02x - %02x - %02x (%08x) 0x%08x %d\n",
|
3271 |
opc1(ctx.opcode), opc2(ctx.opcode), |
3272 |
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
|
3273 |
} else {
|
3274 |
printf("invalid/unsupported opcode: "
|
3275 |
"%02x - %02x - %02x (%08x) 0x%08x %d\n",
|
3276 |
opc1(ctx.opcode), opc2(ctx.opcode), |
3277 |
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
|
3278 |
} |
3279 |
} else {
|
3280 |
if ((ctx.opcode & handler->inval) != 0) { |
3281 |
if (loglevel > 0) { |
3282 |
fprintf(logfile, "invalid bits: %08x for opcode: "
|
3283 |
"%02x -%02x - %02x (0x%08x) (0x%08x)\n",
|
3284 |
ctx.opcode & handler->inval, opc1(ctx.opcode), |
3285 |
opc2(ctx.opcode), opc3(ctx.opcode), |
3286 |
ctx.opcode, ctx.nip - 4);
|
3287 |
} else {
|
3288 |
printf("invalid bits: %08x for opcode: "
|
3289 |
"%02x -%02x - %02x (0x%08x) (0x%08x)\n",
|
3290 |
ctx.opcode & handler->inval, opc1(ctx.opcode), |
3291 |
opc2(ctx.opcode), opc3(ctx.opcode), |
3292 |
ctx.opcode, ctx.nip - 4);
|
3293 |
} |
3294 |
RET_INVAL(ctxp); |
3295 |
break;
|
3296 |
} |
3297 |
} |
3298 |
(*(handler->handler))(&ctx); |
3299 |
/* Check trace mode exceptions */
|
3300 |
if ((msr_be && ctx.exception == EXCP_BRANCH) ||
|
3301 |
/* Check in single step trace mode
|
3302 |
* we need to stop except if:
|
3303 |
* - rfi, trap or syscall
|
3304 |
* - first instruction of an exception handler
|
3305 |
*/
|
3306 |
(msr_se && (ctx.nip < 0x100 ||
|
3307 |
ctx.nip > 0xF00 ||
|
3308 |
(ctx.nip & 0xFC) != 0x04) && |
3309 |
ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI && |
3310 |
ctx.exception != EXCP_TRAP)) { |
3311 |
RET_EXCP(ctxp, EXCP_TRACE, 0);
|
3312 |
} |
3313 |
/* if we reach a page boundary, stop generation */
|
3314 |
if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) { |
3315 |
RET_EXCP(ctxp, EXCP_BRANCH, 0);
|
3316 |
} |
3317 |
} |
3318 |
if (ctx.exception == EXCP_NONE) {
|
3319 |
gen_op_b((unsigned long)ctx.tb, ctx.nip); |
3320 |
} else if (ctx.exception != EXCP_BRANCH) { |
3321 |
gen_op_set_T0(0);
|
3322 |
} |
3323 |
#if 1 |
3324 |
/* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
|
3325 |
* do bad business and then qemu crashes !
|
3326 |
*/
|
3327 |
gen_op_set_T0(0);
|
3328 |
#endif
|
3329 |
/* Generate the return instruction */
|
3330 |
gen_op_exit_tb(); |
3331 |
*gen_opc_ptr = INDEX_op_end; |
3332 |
if (search_pc) {
|
3333 |
j = gen_opc_ptr - gen_opc_buf; |
3334 |
lj++; |
3335 |
while (lj <= j)
|
3336 |
gen_opc_instr_start[lj++] = 0;
|
3337 |
tb->size = 0;
|
3338 |
#if 0
|
3339 |
if (loglevel > 0) {
|
3340 |
page_dump(logfile);
|
3341 |
}
|
3342 |
#endif
|
3343 |
} else {
|
3344 |
tb->size = ctx.nip - pc_start; |
3345 |
} |
3346 |
#ifdef DEBUG_DISAS
|
3347 |
if (loglevel & CPU_LOG_TB_CPU) {
|
3348 |
fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
|
3349 |
cpu_dump_state(env, logfile, fprintf, 0);
|
3350 |
} |
3351 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
3352 |
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
3353 |
target_disas(logfile, pc_start, ctx.nip - pc_start, 0);
|
3354 |
fprintf(logfile, "\n");
|
3355 |
} |
3356 |
if (loglevel & CPU_LOG_TB_OP) {
|
3357 |
fprintf(logfile, "OP:\n");
|
3358 |
dump_ops(gen_opc_buf, gen_opparam_buf); |
3359 |
fprintf(logfile, "\n");
|
3360 |
} |
3361 |
#endif
|
3362 |
return 0; |
3363 |
} |
3364 |
|
3365 |
int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
3366 |
{ |
3367 |
return gen_intermediate_code_internal(env, tb, 0); |
3368 |
} |
3369 |
|
3370 |
int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
3371 |
{ |
3372 |
return gen_intermediate_code_internal(env, tb, 1); |
3373 |
} |