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1 | 7d13299d | bellard | /*
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2 | 7d13299d | bellard | * i386 emulator main execution loop
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3 | 7d13299d | bellard | *
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4 | 7d13299d | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 7d13299d | bellard | *
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6 | 3ef693a0 | bellard | * This library is free software; you can redistribute it and/or
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7 | 3ef693a0 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 3ef693a0 | bellard | * License as published by the Free Software Foundation; either
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9 | 3ef693a0 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 7d13299d | bellard | *
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11 | 3ef693a0 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 3ef693a0 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 3ef693a0 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 3ef693a0 | bellard | * Lesser General Public License for more details.
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15 | 7d13299d | bellard | *
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16 | 3ef693a0 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 3ef693a0 | bellard | * License along with this library; if not, write to the Free Software
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18 | 3ef693a0 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 7d13299d | bellard | */
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20 | 7d13299d | bellard | #include "exec-i386.h" |
21 | 956034d7 | bellard | #include "disas.h" |
22 | 7d13299d | bellard | |
23 | dc99065b | bellard | //#define DEBUG_EXEC
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24 | 9de5e440 | bellard | //#define DEBUG_SIGNAL
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25 | 7d13299d | bellard | |
26 | 7d13299d | bellard | /* main execution loop */
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27 | 7d13299d | bellard | |
28 | 1b6b029e | bellard | /* thread support */
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29 | 1b6b029e | bellard | |
30 | 25eb4484 | bellard | spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
31 | 1b6b029e | bellard | |
32 | 1b6b029e | bellard | void cpu_lock(void) |
33 | 1b6b029e | bellard | { |
34 | 25eb4484 | bellard | spin_lock(&global_cpu_lock); |
35 | 1b6b029e | bellard | } |
36 | 1b6b029e | bellard | |
37 | 1b6b029e | bellard | void cpu_unlock(void) |
38 | 1b6b029e | bellard | { |
39 | 25eb4484 | bellard | spin_unlock(&global_cpu_lock); |
40 | 1b6b029e | bellard | } |
41 | 1b6b029e | bellard | |
42 | a513fe19 | bellard | void cpu_loop_exit(void) |
43 | 9de5e440 | bellard | { |
44 | 9de5e440 | bellard | /* NOTE: the register at this point must be saved by hand because
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45 | 9de5e440 | bellard | longjmp restore them */
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46 | ae228531 | bellard | #ifdef __sparc__
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47 | ae228531 | bellard | /* We have to stay in the same register window as our caller,
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48 | ae228531 | bellard | * thus this trick.
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49 | ae228531 | bellard | */
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50 | ae228531 | bellard | __asm__ __volatile__("restore\n\t"
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51 | ae228531 | bellard | "mov\t%o0, %i0");
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52 | ae228531 | bellard | #endif
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53 | 9de5e440 | bellard | #ifdef reg_EAX
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54 | 9de5e440 | bellard | env->regs[R_EAX] = EAX; |
55 | 9de5e440 | bellard | #endif
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56 | 9de5e440 | bellard | #ifdef reg_ECX
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57 | 9de5e440 | bellard | env->regs[R_ECX] = ECX; |
58 | 9de5e440 | bellard | #endif
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59 | 9de5e440 | bellard | #ifdef reg_EDX
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60 | 9de5e440 | bellard | env->regs[R_EDX] = EDX; |
61 | 9de5e440 | bellard | #endif
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62 | 9de5e440 | bellard | #ifdef reg_EBX
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63 | 9de5e440 | bellard | env->regs[R_EBX] = EBX; |
64 | 9de5e440 | bellard | #endif
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65 | 9de5e440 | bellard | #ifdef reg_ESP
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66 | 9de5e440 | bellard | env->regs[R_ESP] = ESP; |
67 | 9de5e440 | bellard | #endif
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68 | 9de5e440 | bellard | #ifdef reg_EBP
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69 | 9de5e440 | bellard | env->regs[R_EBP] = EBP; |
70 | 9de5e440 | bellard | #endif
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71 | 9de5e440 | bellard | #ifdef reg_ESI
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72 | 9de5e440 | bellard | env->regs[R_ESI] = ESI; |
73 | 9de5e440 | bellard | #endif
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74 | 9de5e440 | bellard | #ifdef reg_EDI
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75 | 9de5e440 | bellard | env->regs[R_EDI] = EDI; |
76 | 9de5e440 | bellard | #endif
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77 | 9de5e440 | bellard | longjmp(env->jmp_env, 1);
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78 | 9de5e440 | bellard | } |
79 | 9de5e440 | bellard | |
80 | 7d13299d | bellard | int cpu_x86_exec(CPUX86State *env1)
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81 | 7d13299d | bellard | { |
82 | 7d13299d | bellard | int saved_T0, saved_T1, saved_A0;
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83 | 7d13299d | bellard | CPUX86State *saved_env; |
84 | 04369ff2 | bellard | #ifdef reg_EAX
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85 | 04369ff2 | bellard | int saved_EAX;
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86 | 04369ff2 | bellard | #endif
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87 | 04369ff2 | bellard | #ifdef reg_ECX
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88 | 04369ff2 | bellard | int saved_ECX;
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89 | 04369ff2 | bellard | #endif
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90 | 04369ff2 | bellard | #ifdef reg_EDX
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91 | 04369ff2 | bellard | int saved_EDX;
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92 | 04369ff2 | bellard | #endif
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93 | 04369ff2 | bellard | #ifdef reg_EBX
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94 | 04369ff2 | bellard | int saved_EBX;
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95 | 04369ff2 | bellard | #endif
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96 | 04369ff2 | bellard | #ifdef reg_ESP
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97 | 04369ff2 | bellard | int saved_ESP;
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98 | 04369ff2 | bellard | #endif
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99 | 04369ff2 | bellard | #ifdef reg_EBP
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100 | 04369ff2 | bellard | int saved_EBP;
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101 | 04369ff2 | bellard | #endif
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102 | 04369ff2 | bellard | #ifdef reg_ESI
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103 | 04369ff2 | bellard | int saved_ESI;
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104 | 04369ff2 | bellard | #endif
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105 | 04369ff2 | bellard | #ifdef reg_EDI
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106 | 04369ff2 | bellard | int saved_EDI;
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107 | 04369ff2 | bellard | #endif
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108 | a513fe19 | bellard | int code_gen_size, ret;
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109 | 7d13299d | bellard | void (*gen_func)(void); |
110 | 9de5e440 | bellard | TranslationBlock *tb, **ptb; |
111 | dab2ed99 | bellard | uint8_t *tc_ptr, *cs_base, *pc; |
112 | 6dbad63e | bellard | unsigned int flags; |
113 | d4e8164f | bellard | |
114 | 7d13299d | bellard | /* first we save global registers */
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115 | 7d13299d | bellard | saved_T0 = T0; |
116 | 7d13299d | bellard | saved_T1 = T1; |
117 | 7d13299d | bellard | saved_A0 = A0; |
118 | 7d13299d | bellard | saved_env = env; |
119 | 7d13299d | bellard | env = env1; |
120 | 04369ff2 | bellard | #ifdef reg_EAX
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121 | 04369ff2 | bellard | saved_EAX = EAX; |
122 | 04369ff2 | bellard | EAX = env->regs[R_EAX]; |
123 | 04369ff2 | bellard | #endif
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124 | 04369ff2 | bellard | #ifdef reg_ECX
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125 | 04369ff2 | bellard | saved_ECX = ECX; |
126 | 04369ff2 | bellard | ECX = env->regs[R_ECX]; |
127 | 04369ff2 | bellard | #endif
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128 | 04369ff2 | bellard | #ifdef reg_EDX
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129 | 04369ff2 | bellard | saved_EDX = EDX; |
130 | 04369ff2 | bellard | EDX = env->regs[R_EDX]; |
131 | 04369ff2 | bellard | #endif
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132 | 04369ff2 | bellard | #ifdef reg_EBX
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133 | 04369ff2 | bellard | saved_EBX = EBX; |
134 | 04369ff2 | bellard | EBX = env->regs[R_EBX]; |
135 | 04369ff2 | bellard | #endif
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136 | 04369ff2 | bellard | #ifdef reg_ESP
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137 | 04369ff2 | bellard | saved_ESP = ESP; |
138 | 04369ff2 | bellard | ESP = env->regs[R_ESP]; |
139 | 04369ff2 | bellard | #endif
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140 | 04369ff2 | bellard | #ifdef reg_EBP
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141 | 04369ff2 | bellard | saved_EBP = EBP; |
142 | 04369ff2 | bellard | EBP = env->regs[R_EBP]; |
143 | 04369ff2 | bellard | #endif
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144 | 04369ff2 | bellard | #ifdef reg_ESI
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145 | 04369ff2 | bellard | saved_ESI = ESI; |
146 | 04369ff2 | bellard | ESI = env->regs[R_ESI]; |
147 | 04369ff2 | bellard | #endif
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148 | 04369ff2 | bellard | #ifdef reg_EDI
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149 | 04369ff2 | bellard | saved_EDI = EDI; |
150 | 04369ff2 | bellard | EDI = env->regs[R_EDI]; |
151 | 04369ff2 | bellard | #endif
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152 | 7d13299d | bellard | |
153 | 9de5e440 | bellard | /* put eflags in CPU temporary format */
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154 | fc2b4c48 | bellard | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
155 | fc2b4c48 | bellard | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
156 | 9de5e440 | bellard | CC_OP = CC_OP_EFLAGS; |
157 | fc2b4c48 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
158 | 9de5e440 | bellard | env->interrupt_request = 0;
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159 | 9d27abd9 | bellard | |
160 | 7d13299d | bellard | /* prepare setjmp context for exception handling */
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161 | 7d13299d | bellard | if (setjmp(env->jmp_env) == 0) { |
162 | d4e8164f | bellard | T0 = 0; /* force lookup of first TB */ |
163 | 7d13299d | bellard | for(;;) {
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164 | 9de5e440 | bellard | if (env->interrupt_request) {
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165 | a513fe19 | bellard | env->exception_index = EXCP_INTERRUPT; |
166 | a513fe19 | bellard | cpu_loop_exit(); |
167 | 9de5e440 | bellard | } |
168 | 7d13299d | bellard | #ifdef DEBUG_EXEC
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169 | 7d13299d | bellard | if (loglevel) {
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170 | 9d27abd9 | bellard | /* XXX: save all volatile state in cpu state */
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171 | 9d27abd9 | bellard | /* restore flags in standard format */
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172 | 9d27abd9 | bellard | env->regs[R_EAX] = EAX; |
173 | 9d27abd9 | bellard | env->regs[R_EBX] = EBX; |
174 | 9d27abd9 | bellard | env->regs[R_ECX] = ECX; |
175 | 9d27abd9 | bellard | env->regs[R_EDX] = EDX; |
176 | 9d27abd9 | bellard | env->regs[R_ESI] = ESI; |
177 | 9d27abd9 | bellard | env->regs[R_EDI] = EDI; |
178 | 9d27abd9 | bellard | env->regs[R_EBP] = EBP; |
179 | 9d27abd9 | bellard | env->regs[R_ESP] = ESP; |
180 | 9d27abd9 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
181 | 9d27abd9 | bellard | cpu_x86_dump_state(env, logfile, 0);
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182 | 9d27abd9 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
183 | 7d13299d | bellard | } |
184 | 7d13299d | bellard | #endif
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185 | 6dbad63e | bellard | /* we compute the CPU state. We assume it will not
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186 | 6dbad63e | bellard | change during the whole generated block. */
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187 | 6dbad63e | bellard | flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT; |
188 | dab2ed99 | bellard | flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT; |
189 | 6dbad63e | bellard | flags |= (((unsigned long)env->seg_cache[R_DS].base | |
190 | 6dbad63e | bellard | (unsigned long)env->seg_cache[R_ES].base | |
191 | 6dbad63e | bellard | (unsigned long)env->seg_cache[R_SS].base) != 0) << |
192 | 6dbad63e | bellard | GEN_FLAG_ADDSEG_SHIFT; |
193 | 9d27abd9 | bellard | if (!(env->eflags & VM_MASK)) {
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194 | 9d27abd9 | bellard | flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT;
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195 | 9d27abd9 | bellard | } else {
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196 | 9d27abd9 | bellard | /* NOTE: a dummy CPL is kept */
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197 | 9d27abd9 | bellard | flags |= (1 << GEN_FLAG_VM_SHIFT);
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198 | 9d27abd9 | bellard | flags |= (3 << GEN_FLAG_CPL_SHIFT);
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199 | 9d27abd9 | bellard | } |
200 | cf25629d | bellard | flags |= (env->eflags & (IOPL_MASK | TF_MASK)); |
201 | dab2ed99 | bellard | cs_base = env->seg_cache[R_CS].base; |
202 | dab2ed99 | bellard | pc = cs_base + env->eip; |
203 | 9de5e440 | bellard | tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, |
204 | 9de5e440 | bellard | flags); |
205 | 9de5e440 | bellard | if (!tb) {
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206 | cf25629d | bellard | spin_lock(&tb_lock); |
207 | 7d13299d | bellard | /* if no translated code available, then translate it now */
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208 | d4e8164f | bellard | tb = tb_alloc((unsigned long)pc); |
209 | d4e8164f | bellard | if (!tb) {
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210 | d4e8164f | bellard | /* flush must be done */
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211 | d4e8164f | bellard | tb_flush(); |
212 | d4e8164f | bellard | /* cannot fail at this point */
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213 | d4e8164f | bellard | tb = tb_alloc((unsigned long)pc); |
214 | d4e8164f | bellard | /* don't forget to invalidate previous TB info */
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215 | d4e8164f | bellard | ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; |
216 | d4e8164f | bellard | T0 = 0;
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217 | d4e8164f | bellard | } |
218 | 7d13299d | bellard | tc_ptr = code_gen_ptr; |
219 | d4e8164f | bellard | tb->tc_ptr = tc_ptr; |
220 | a513fe19 | bellard | tb->cs_base = (unsigned long)cs_base; |
221 | a513fe19 | bellard | tb->flags = flags; |
222 | a513fe19 | bellard | ret = cpu_x86_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
223 | 9de5e440 | bellard | /* if invalid instruction, signal it */
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224 | 9de5e440 | bellard | if (ret != 0) { |
225 | d4e8164f | bellard | /* NOTE: the tb is allocated but not linked, so we
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226 | d4e8164f | bellard | can leave it */
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227 | 25eb4484 | bellard | spin_unlock(&tb_lock); |
228 | 9de5e440 | bellard | raise_exception(EXCP06_ILLOP); |
229 | 9de5e440 | bellard | } |
230 | 9de5e440 | bellard | *ptb = tb; |
231 | 9de5e440 | bellard | tb->hash_next = NULL;
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232 | d4e8164f | bellard | tb_link(tb); |
233 | 7d13299d | bellard | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
234 | cf25629d | bellard | spin_unlock(&tb_lock); |
235 | 7d13299d | bellard | } |
236 | 9d27abd9 | bellard | #ifdef DEBUG_EXEC
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237 | 956034d7 | bellard | if (loglevel) {
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238 | 956034d7 | bellard | fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
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239 | 956034d7 | bellard | (long)tb->tc_ptr, (long)tb->pc, |
240 | 956034d7 | bellard | lookup_symbol((void *)tb->pc));
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241 | 956034d7 | bellard | } |
242 | 9d27abd9 | bellard | #endif
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243 | d4e8164f | bellard | /* see if we can patch the calling TB */
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244 | d4e8164f | bellard | if (T0 != 0 && !(env->eflags & TF_MASK)) { |
245 | cf25629d | bellard | spin_lock(&tb_lock); |
246 | d4e8164f | bellard | tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb); |
247 | cf25629d | bellard | spin_unlock(&tb_lock); |
248 | d4e8164f | bellard | } |
249 | cf25629d | bellard | |
250 | 9de5e440 | bellard | tc_ptr = tb->tc_ptr; |
251 | d4e8164f | bellard | |
252 | d4e8164f | bellard | /* execute the generated code */
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253 | 7d13299d | bellard | gen_func = (void *)tc_ptr;
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254 | ae228531 | bellard | #ifdef __sparc__
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255 | ae228531 | bellard | __asm__ __volatile__("call %0\n\t"
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256 | ae228531 | bellard | " mov %%o7,%%i0"
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257 | ae228531 | bellard | : /* no outputs */
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258 | d4e8164f | bellard | : "r" (gen_func)
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259 | ae228531 | bellard | : "i0", "i1", "i2", "i3", "i4", "i5"); |
260 | ae228531 | bellard | #else
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261 | 7d13299d | bellard | gen_func(); |
262 | ae228531 | bellard | #endif
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263 | 7d13299d | bellard | } |
264 | 7d13299d | bellard | } |
265 | 7d13299d | bellard | ret = env->exception_index; |
266 | 7d13299d | bellard | |
267 | 9de5e440 | bellard | /* restore flags in standard format */
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268 | fc2b4c48 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
269 | 9de5e440 | bellard | |
270 | 7d13299d | bellard | /* restore global registers */
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271 | 04369ff2 | bellard | #ifdef reg_EAX
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272 | 04369ff2 | bellard | EAX = saved_EAX; |
273 | 04369ff2 | bellard | #endif
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274 | 04369ff2 | bellard | #ifdef reg_ECX
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275 | 04369ff2 | bellard | ECX = saved_ECX; |
276 | 04369ff2 | bellard | #endif
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277 | 04369ff2 | bellard | #ifdef reg_EDX
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278 | 04369ff2 | bellard | EDX = saved_EDX; |
279 | 04369ff2 | bellard | #endif
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280 | 04369ff2 | bellard | #ifdef reg_EBX
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281 | 04369ff2 | bellard | EBX = saved_EBX; |
282 | 04369ff2 | bellard | #endif
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283 | 04369ff2 | bellard | #ifdef reg_ESP
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284 | 04369ff2 | bellard | ESP = saved_ESP; |
285 | 04369ff2 | bellard | #endif
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286 | 04369ff2 | bellard | #ifdef reg_EBP
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287 | 04369ff2 | bellard | EBP = saved_EBP; |
288 | 04369ff2 | bellard | #endif
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289 | 04369ff2 | bellard | #ifdef reg_ESI
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290 | 04369ff2 | bellard | ESI = saved_ESI; |
291 | 04369ff2 | bellard | #endif
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292 | 04369ff2 | bellard | #ifdef reg_EDI
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293 | 04369ff2 | bellard | EDI = saved_EDI; |
294 | 04369ff2 | bellard | #endif
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295 | 7d13299d | bellard | T0 = saved_T0; |
296 | 7d13299d | bellard | T1 = saved_T1; |
297 | 7d13299d | bellard | A0 = saved_A0; |
298 | 7d13299d | bellard | env = saved_env; |
299 | 7d13299d | bellard | return ret;
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300 | 7d13299d | bellard | } |
301 | 6dbad63e | bellard | |
302 | 9de5e440 | bellard | void cpu_x86_interrupt(CPUX86State *s)
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303 | 9de5e440 | bellard | { |
304 | 9de5e440 | bellard | s->interrupt_request = 1;
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305 | 9de5e440 | bellard | } |
306 | 9de5e440 | bellard | |
307 | 9de5e440 | bellard | |
308 | 6dbad63e | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
309 | 6dbad63e | bellard | { |
310 | 6dbad63e | bellard | CPUX86State *saved_env; |
311 | 6dbad63e | bellard | |
312 | 6dbad63e | bellard | saved_env = env; |
313 | 6dbad63e | bellard | env = s; |
314 | a513fe19 | bellard | if (env->eflags & VM_MASK) {
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315 | a513fe19 | bellard | SegmentCache *sc; |
316 | a513fe19 | bellard | selector &= 0xffff;
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317 | a513fe19 | bellard | sc = &env->seg_cache[seg_reg]; |
318 | a513fe19 | bellard | /* NOTE: in VM86 mode, limit and seg_32bit are never reloaded,
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319 | a513fe19 | bellard | so we must load them here */
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320 | a513fe19 | bellard | sc->base = (void *)(selector << 4); |
321 | a513fe19 | bellard | sc->limit = 0xffff;
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322 | a513fe19 | bellard | sc->seg_32bit = 0;
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323 | a513fe19 | bellard | env->segs[seg_reg] = selector; |
324 | a513fe19 | bellard | } else {
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325 | a513fe19 | bellard | load_seg(seg_reg, selector, 0);
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326 | a513fe19 | bellard | } |
327 | 6dbad63e | bellard | env = saved_env; |
328 | 6dbad63e | bellard | } |
329 | 9de5e440 | bellard | |
330 | d0a1ffc9 | bellard | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
331 | d0a1ffc9 | bellard | { |
332 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
333 | d0a1ffc9 | bellard | |
334 | d0a1ffc9 | bellard | saved_env = env; |
335 | d0a1ffc9 | bellard | env = s; |
336 | d0a1ffc9 | bellard | |
337 | d0a1ffc9 | bellard | helper_fsave(ptr, data32); |
338 | d0a1ffc9 | bellard | |
339 | d0a1ffc9 | bellard | env = saved_env; |
340 | d0a1ffc9 | bellard | } |
341 | d0a1ffc9 | bellard | |
342 | d0a1ffc9 | bellard | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
343 | d0a1ffc9 | bellard | { |
344 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
345 | d0a1ffc9 | bellard | |
346 | d0a1ffc9 | bellard | saved_env = env; |
347 | d0a1ffc9 | bellard | env = s; |
348 | d0a1ffc9 | bellard | |
349 | d0a1ffc9 | bellard | helper_frstor(ptr, data32); |
350 | d0a1ffc9 | bellard | |
351 | d0a1ffc9 | bellard | env = saved_env; |
352 | d0a1ffc9 | bellard | } |
353 | d0a1ffc9 | bellard | |
354 | 9de5e440 | bellard | #undef EAX
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355 | 9de5e440 | bellard | #undef ECX
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356 | 9de5e440 | bellard | #undef EDX
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357 | 9de5e440 | bellard | #undef EBX
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358 | 9de5e440 | bellard | #undef ESP
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359 | 9de5e440 | bellard | #undef EBP
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360 | 9de5e440 | bellard | #undef ESI
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361 | 9de5e440 | bellard | #undef EDI
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362 | 9de5e440 | bellard | #undef EIP
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363 | 9de5e440 | bellard | #include <signal.h> |
364 | 9de5e440 | bellard | #include <sys/ucontext.h> |
365 | 9de5e440 | bellard | |
366 | b56dad1c | bellard | /* 'pc' is the host PC at which the exception was raised. 'address' is
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367 | fd6ce8f6 | bellard | the effective address of the memory exception. 'is_write' is 1 if a
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368 | fd6ce8f6 | bellard | write caused the exception and otherwise 0'. 'old_set' is the
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369 | fd6ce8f6 | bellard | signal set which should be restored */
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370 | 2b413144 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
371 | 2b413144 | bellard | int is_write, sigset_t *old_set)
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372 | 9de5e440 | bellard | { |
373 | a513fe19 | bellard | TranslationBlock *tb; |
374 | a513fe19 | bellard | int ret;
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375 | a513fe19 | bellard | uint32_t found_pc; |
376 | a513fe19 | bellard | |
377 | fd6ce8f6 | bellard | #if defined(DEBUG_SIGNAL)
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378 | fd6ce8f6 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n",
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379 | fd6ce8f6 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
380 | 9de5e440 | bellard | #endif
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381 | 25eb4484 | bellard | /* XXX: locking issue */
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382 | fd6ce8f6 | bellard | if (is_write && page_unprotect(address)) {
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383 | fd6ce8f6 | bellard | return 1; |
384 | fd6ce8f6 | bellard | } |
385 | a513fe19 | bellard | tb = tb_find_pc(pc); |
386 | a513fe19 | bellard | if (tb) {
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387 | 9de5e440 | bellard | /* the PC is inside the translated code. It means that we have
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388 | 9de5e440 | bellard | a virtual CPU fault */
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389 | a513fe19 | bellard | ret = cpu_x86_search_pc(tb, &found_pc, pc); |
390 | a513fe19 | bellard | if (ret < 0) |
391 | a513fe19 | bellard | return 0; |
392 | a513fe19 | bellard | env->eip = found_pc - tb->cs_base; |
393 | a513fe19 | bellard | env->cr2 = address; |
394 | 9de5e440 | bellard | /* we restore the process signal mask as the sigreturn should
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395 | a513fe19 | bellard | do it (XXX: use sigsetjmp) */
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396 | 9de5e440 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
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397 | fd6ce8f6 | bellard | raise_exception_err(EXCP0E_PAGE, 4 | (is_write << 1)); |
398 | 9de5e440 | bellard | /* never comes here */
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399 | 9de5e440 | bellard | return 1; |
400 | 9de5e440 | bellard | } else {
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401 | 9de5e440 | bellard | return 0; |
402 | 9de5e440 | bellard | } |
403 | 9de5e440 | bellard | } |
404 | 9de5e440 | bellard | |
405 | 2b413144 | bellard | #if defined(__i386__)
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406 | 2b413144 | bellard | |
407 | 9de5e440 | bellard | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
408 | 9de5e440 | bellard | void *puc)
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409 | 9de5e440 | bellard | { |
410 | 9de5e440 | bellard | struct ucontext *uc = puc;
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411 | 9de5e440 | bellard | unsigned long pc; |
412 | 9de5e440 | bellard | |
413 | d691f669 | bellard | #ifndef REG_EIP
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414 | d691f669 | bellard | /* for glibc 2.1 */
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415 | fd6ce8f6 | bellard | #define REG_EIP EIP
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416 | fd6ce8f6 | bellard | #define REG_ERR ERR
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417 | fd6ce8f6 | bellard | #define REG_TRAPNO TRAPNO
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418 | d691f669 | bellard | #endif
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419 | fc2b4c48 | bellard | pc = uc->uc_mcontext.gregs[REG_EIP]; |
420 | fd6ce8f6 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
421 | fd6ce8f6 | bellard | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
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422 | fd6ce8f6 | bellard | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
423 | 2b413144 | bellard | &uc->uc_sigmask); |
424 | 2b413144 | bellard | } |
425 | 2b413144 | bellard | |
426 | 25eb4484 | bellard | #elif defined(__powerpc)
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427 | 2b413144 | bellard | |
428 | 2b413144 | bellard | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
429 | 2b413144 | bellard | void *puc)
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430 | 2b413144 | bellard | { |
431 | 25eb4484 | bellard | struct ucontext *uc = puc;
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432 | 25eb4484 | bellard | struct pt_regs *regs = uc->uc_mcontext.regs;
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433 | 25eb4484 | bellard | unsigned long pc; |
434 | 25eb4484 | bellard | int is_write;
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435 | 25eb4484 | bellard | |
436 | 25eb4484 | bellard | pc = regs->nip; |
437 | 25eb4484 | bellard | is_write = 0;
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438 | 25eb4484 | bellard | #if 0
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439 | 25eb4484 | bellard | /* ppc 4xx case */
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440 | 25eb4484 | bellard | if (regs->dsisr & 0x00800000)
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441 | 25eb4484 | bellard | is_write = 1;
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442 | 25eb4484 | bellard | #else
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443 | 25eb4484 | bellard | if (regs->trap != 0x400 && (regs->dsisr & 0x02000000)) |
444 | 25eb4484 | bellard | is_write = 1;
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445 | 25eb4484 | bellard | #endif
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446 | 25eb4484 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
447 | 2b413144 | bellard | is_write, &uc->uc_sigmask); |
448 | 2b413144 | bellard | } |
449 | 2b413144 | bellard | |
450 | 9de5e440 | bellard | #else
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451 | 2b413144 | bellard | |
452 | 25eb4484 | bellard | #error CPU specific signal handler needed
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453 | 2b413144 | bellard | |
454 | 9de5e440 | bellard | #endif |