Statistics
| Branch: | Revision:

root / target-mips / exec.h @ 43057ab1

History | View | Annotate | Download (3 kB)

1 6af0bf9c bellard
#if !defined(__QEMU_MIPS_EXEC_H__)
2 6af0bf9c bellard
#define __QEMU_MIPS_EXEC_H__
3 6af0bf9c bellard
4 01dbbdf1 bellard
//#define DEBUG_OP
5 6af0bf9c bellard
6 6af0bf9c bellard
#include "mips-defs.h"
7 6af0bf9c bellard
#include "dyngen-exec.h"
8 6af0bf9c bellard
9 6af0bf9c bellard
register struct CPUMIPSState *env asm(AREG0);
10 6af0bf9c bellard
11 6af0bf9c bellard
#if defined (USE_64BITS_REGS)
12 6af0bf9c bellard
typedef int64_t host_int_t;
13 6af0bf9c bellard
typedef uint64_t host_uint_t;
14 6af0bf9c bellard
#else
15 6af0bf9c bellard
typedef int32_t host_int_t;
16 6af0bf9c bellard
typedef uint32_t host_uint_t;
17 6af0bf9c bellard
#endif
18 6af0bf9c bellard
19 6af0bf9c bellard
register host_uint_t T0 asm(AREG1);
20 6af0bf9c bellard
register host_uint_t T1 asm(AREG2);
21 6af0bf9c bellard
register host_uint_t T2 asm(AREG3);
22 6af0bf9c bellard
23 6af0bf9c bellard
#if defined (USE_HOST_FLOAT_REGS)
24 6ea83fed bellard
#error "implement me."
25 6af0bf9c bellard
#else
26 6ea83fed bellard
#define FDT0 (env->ft0.fd)
27 6ea83fed bellard
#define FDT1 (env->ft1.fd)
28 6ea83fed bellard
#define FDT2 (env->ft2.fd)
29 6ea83fed bellard
#define FST0 (env->ft0.fs[FP_ENDIAN_IDX])
30 6ea83fed bellard
#define FST1 (env->ft1.fs[FP_ENDIAN_IDX])
31 6ea83fed bellard
#define FST2 (env->ft2.fs[FP_ENDIAN_IDX])
32 6ea83fed bellard
#define DT0 (env->ft0.d)
33 6ea83fed bellard
#define DT1 (env->ft1.d)
34 6ea83fed bellard
#define DT2 (env->ft2.d)
35 6ea83fed bellard
#define WT0 (env->ft0.w[FP_ENDIAN_IDX])
36 6ea83fed bellard
#define WT1 (env->ft1.w[FP_ENDIAN_IDX])
37 6ea83fed bellard
#define WT2 (env->ft2.w[FP_ENDIAN_IDX])
38 6af0bf9c bellard
#endif
39 6af0bf9c bellard
40 6af0bf9c bellard
#if defined (DEBUG_OP)
41 6af0bf9c bellard
#define RETURN() __asm__ __volatile__("nop");
42 6af0bf9c bellard
#else
43 6af0bf9c bellard
#define RETURN() __asm__ __volatile__("");
44 6af0bf9c bellard
#endif
45 6af0bf9c bellard
46 6af0bf9c bellard
#include "cpu.h"
47 6af0bf9c bellard
#include "exec-all.h"
48 6af0bf9c bellard
49 6af0bf9c bellard
#if !defined(CONFIG_USER_ONLY)
50 a9049a07 bellard
#include "softmmu_exec.h"
51 6af0bf9c bellard
#endif /* !defined(CONFIG_USER_ONLY) */
52 6af0bf9c bellard
53 6af0bf9c bellard
static inline void env_to_regs(void)
54 6af0bf9c bellard
{
55 6af0bf9c bellard
}
56 6af0bf9c bellard
57 6af0bf9c bellard
static inline void regs_to_env(void)
58 6af0bf9c bellard
{
59 6af0bf9c bellard
}
60 6af0bf9c bellard
61 6af0bf9c bellard
#if (HOST_LONG_BITS == 32)
62 6af0bf9c bellard
void do_mult (void);
63 6af0bf9c bellard
void do_multu (void);
64 6af0bf9c bellard
void do_madd (void);
65 6af0bf9c bellard
void do_maddu (void);
66 6af0bf9c bellard
void do_msub (void);
67 6af0bf9c bellard
void do_msubu (void);
68 6af0bf9c bellard
#endif
69 6af0bf9c bellard
void do_mfc0(int reg, int sel);
70 6af0bf9c bellard
void do_mtc0(int reg, int sel);
71 6af0bf9c bellard
void do_tlbwi (void);
72 6af0bf9c bellard
void do_tlbwr (void);
73 6af0bf9c bellard
void do_tlbp (void);
74 6af0bf9c bellard
void do_tlbr (void);
75 6ea83fed bellard
#ifdef MIPS_USES_FPU
76 6ea83fed bellard
void dump_fpu(CPUState *env);
77 6ea83fed bellard
void fpu_dump_state(CPUState *env, FILE *f, 
78 6ea83fed bellard
                    int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
79 6ea83fed bellard
                    int flags);
80 6ea83fed bellard
#endif
81 6ea83fed bellard
void dump_sc (void);
82 4ad40f36 bellard
void do_lwl_raw (uint32_t);
83 4ad40f36 bellard
void do_lwr_raw (uint32_t);
84 4ad40f36 bellard
uint32_t do_swl_raw (uint32_t);
85 4ad40f36 bellard
uint32_t do_swr_raw (uint32_t);
86 6af0bf9c bellard
#if !defined(CONFIG_USER_ONLY)
87 4ad40f36 bellard
void do_lwl_user (uint32_t);
88 4ad40f36 bellard
void do_lwl_kernel (uint32_t);
89 4ad40f36 bellard
void do_lwr_user (uint32_t);
90 4ad40f36 bellard
void do_lwr_kernel (uint32_t);
91 4ad40f36 bellard
uint32_t do_swl_user (uint32_t);
92 4ad40f36 bellard
uint32_t do_swl_kernel (uint32_t);
93 4ad40f36 bellard
uint32_t do_swr_user (uint32_t);
94 4ad40f36 bellard
uint32_t do_swr_kernel (uint32_t);
95 6af0bf9c bellard
#endif
96 6af0bf9c bellard
void do_pmon (int function);
97 6af0bf9c bellard
98 d2ec1774 pbrook
void dump_sc (void);
99 d2ec1774 pbrook
100 6af0bf9c bellard
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
101 6af0bf9c bellard
                               int is_user, int is_softmmu);
102 6af0bf9c bellard
void do_interrupt (CPUState *env);
103 6af0bf9c bellard
104 6af0bf9c bellard
void cpu_loop_exit(void);
105 6af0bf9c bellard
void do_raise_exception_err (uint32_t exception, int error_code);
106 6af0bf9c bellard
void do_raise_exception (uint32_t exception);
107 4ad40f36 bellard
void do_raise_exception_direct (uint32_t exception);
108 6af0bf9c bellard
109 6af0bf9c bellard
void cpu_dump_state(CPUState *env, FILE *f, 
110 6af0bf9c bellard
                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
111 6af0bf9c bellard
                    int flags);
112 6af0bf9c bellard
void cpu_mips_irqctrl_init (void);
113 6af0bf9c bellard
uint32_t cpu_mips_get_random (CPUState *env);
114 6af0bf9c bellard
uint32_t cpu_mips_get_count (CPUState *env);
115 6af0bf9c bellard
void cpu_mips_store_count (CPUState *env, uint32_t value);
116 6af0bf9c bellard
void cpu_mips_store_compare (CPUState *env, uint32_t value);
117 6af0bf9c bellard
void cpu_mips_clock_init (CPUState *env);
118 6af0bf9c bellard
119 6af0bf9c bellard
#endif /* !defined(__QEMU_MIPS_EXEC_H__) */