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/*
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* QEMU USB OHCI Emulation
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* Copyright (c) 2004 Gianni Tedesco
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* Copyright (c) 2006 CodeSourcery
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* TODO:
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* o Isochronous transfers
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* o Allocate bandwidth in frames properly
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* o Disable timers when nothing needs to be done, or remove timer usage
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* all together.
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* o Handle unrecoverable errors properly
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* o BIOS work to boot from USB storage
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*/
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#include "vl.h" |
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//#define DEBUG_OHCI
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/* Dump packet contents. */
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//#define DEBUG_PACKET
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/* This causes frames to occur 1000x slower */
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//#define OHCI_TIME_WARP 1
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#ifdef DEBUG_OHCI
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#define dprintf printf
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#else
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#define dprintf(...)
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#endif
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/* Number of Downstream Ports on the root hub. */
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#define OHCI_MAX_PORTS 15 |
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static int64_t usb_frame_time;
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static int64_t usb_bit_time;
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typedef struct OHCIPort { |
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USBPort port; |
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uint32_t ctrl; |
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} OHCIPort; |
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|
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typedef struct { |
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struct PCIDevice pci_dev;
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target_phys_addr_t mem_base; |
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int mem;
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int num_ports;
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QEMUTimer *eof_timer; |
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int64_t sof_time; |
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/* OHCI state */
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/* Control partition */
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uint32_t ctl, status; |
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uint32_t intr_status; |
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uint32_t intr; |
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/* memory pointer partition */
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uint32_t hcca; |
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uint32_t ctrl_head, ctrl_cur; |
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uint32_t bulk_head, bulk_cur; |
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uint32_t per_cur; |
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uint32_t done; |
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int done_count;
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|
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/* Frame counter partition */
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uint32_t fsmps:15;
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uint32_t fit:1;
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uint32_t fi:14;
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uint32_t frt:1;
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uint16_t frame_number; |
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uint16_t padding; |
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uint32_t pstart; |
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uint32_t lst; |
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/* Root Hub partition */
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uint32_t rhdesc_a, rhdesc_b; |
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uint32_t rhstatus; |
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OHCIPort rhport[OHCI_MAX_PORTS]; |
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} OHCIState; |
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/* Host Controller Communications Area */
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struct ohci_hcca {
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uint32_t intr[32];
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uint16_t frame, pad; |
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uint32_t done; |
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}; |
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/* Bitfields for the first word of an Endpoint Desciptor. */
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#define OHCI_ED_FA_SHIFT 0 |
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#define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT) |
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#define OHCI_ED_EN_SHIFT 7 |
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#define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT) |
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#define OHCI_ED_D_SHIFT 11 |
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#define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) |
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#define OHCI_ED_S (1<<13) |
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#define OHCI_ED_K (1<<14) |
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#define OHCI_ED_F (1<<15) |
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#define OHCI_ED_MPS_SHIFT 7 |
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#define OHCI_ED_MPS_MASK (0xf<<OHCI_ED_FA_SHIFT) |
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|
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/* Flags in the head field of an Endpoint Desciptor. */
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#define OHCI_ED_H 1 |
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#define OHCI_ED_C 2 |
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|
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/* Bitfields for the first word of a Transfer Desciptor. */
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#define OHCI_TD_R (1<<18) |
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#define OHCI_TD_DP_SHIFT 19 |
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#define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) |
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#define OHCI_TD_DI_SHIFT 21 |
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#define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) |
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#define OHCI_TD_T0 (1<<24) |
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#define OHCI_TD_T1 (1<<24) |
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#define OHCI_TD_EC_SHIFT 26 |
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#define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) |
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#define OHCI_TD_CC_SHIFT 28 |
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#define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT) |
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#define OHCI_DPTR_MASK 0xfffffff0 |
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#define OHCI_BM(val, field) \
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(((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT) |
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#define OHCI_SET_BM(val, field, newval) do { \ |
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val &= ~OHCI_##field##_MASK; \ |
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val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \ |
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} while(0) |
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/* endpoint descriptor */
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struct ohci_ed {
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uint32_t flags; |
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uint32_t tail; |
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uint32_t head; |
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uint32_t next; |
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}; |
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/* General transfer descriptor */
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struct ohci_td {
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uint32_t flags; |
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uint32_t cbp; |
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uint32_t next; |
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uint32_t be; |
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}; |
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#define USB_HZ 12000000 |
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/* OHCI Local stuff */
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#define OHCI_CTL_CBSR ((1<<0)|(1<<1)) |
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#define OHCI_CTL_PLE (1<<2) |
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#define OHCI_CTL_IE (1<<3) |
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#define OHCI_CTL_CLE (1<<4) |
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#define OHCI_CTL_BLE (1<<5) |
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#define OHCI_CTL_HCFS ((1<<6)|(1<<7)) |
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#define OHCI_USB_RESET 0x00 |
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#define OHCI_USB_RESUME 0x40 |
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#define OHCI_USB_OPERATIONAL 0x80 |
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#define OHCI_USB_SUSPEND 0xc0 |
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#define OHCI_CTL_IR (1<<8) |
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#define OHCI_CTL_RWC (1<<9) |
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#define OHCI_CTL_RWE (1<<10) |
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|
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#define OHCI_STATUS_HCR (1<<0) |
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#define OHCI_STATUS_CLF (1<<1) |
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#define OHCI_STATUS_BLF (1<<2) |
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#define OHCI_STATUS_OCR (1<<3) |
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#define OHCI_STATUS_SOC ((1<<6)|(1<<7)) |
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|
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#define OHCI_INTR_SO (1<<0) /* Scheduling overrun */ |
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#define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */ |
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#define OHCI_INTR_SF (1<<2) /* Start of frame */ |
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#define OHCI_INTR_RD (1<<3) /* Resume detect */ |
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#define OHCI_INTR_UE (1<<4) /* Unrecoverable error */ |
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#define OHCI_INTR_FNO (1<<5) /* Frame number overflow */ |
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#define OHCI_INTR_RHSC (1<<6) /* Root hub status change */ |
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#define OHCI_INTR_OC (1<<30) /* Ownership change */ |
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#define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */ |
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#define OHCI_HCCA_SIZE 0x100 |
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#define OHCI_HCCA_MASK 0xffffff00 |
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#define OHCI_EDPTR_MASK 0xfffffff0 |
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#define OHCI_FMI_FI 0x00003fff |
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#define OHCI_FMI_FSMPS 0xffff0000 |
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#define OHCI_FMI_FIT 0x80000000 |
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#define OHCI_FR_RT (1<<31) |
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#define OHCI_LS_THRESH 0x628 |
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#define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */ |
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#define OHCI_RHA_PSM (1<<8) |
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#define OHCI_RHA_NPS (1<<9) |
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#define OHCI_RHA_DT (1<<10) |
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#define OHCI_RHA_OCPM (1<<11) |
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#define OHCI_RHA_NOCP (1<<12) |
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#define OHCI_RHA_POTPGT_MASK 0xff000000 |
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#define OHCI_RHS_LPS (1<<0) |
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#define OHCI_RHS_OCI (1<<1) |
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#define OHCI_RHS_DRWE (1<<15) |
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#define OHCI_RHS_LPSC (1<<16) |
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#define OHCI_RHS_OCIC (1<<17) |
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#define OHCI_RHS_CRWE (1<<31) |
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#define OHCI_PORT_CCS (1<<0) |
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#define OHCI_PORT_PES (1<<1) |
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#define OHCI_PORT_PSS (1<<2) |
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#define OHCI_PORT_POCI (1<<3) |
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#define OHCI_PORT_PRS (1<<4) |
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#define OHCI_PORT_PPS (1<<8) |
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#define OHCI_PORT_LSDA (1<<9) |
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#define OHCI_PORT_CSC (1<<16) |
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#define OHCI_PORT_PESC (1<<17) |
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#define OHCI_PORT_PSSC (1<<18) |
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#define OHCI_PORT_OCIC (1<<19) |
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#define OHCI_PORT_PRSC (1<<20) |
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#define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
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|OHCI_PORT_OCIC|OHCI_PORT_PRSC) |
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#define OHCI_TD_DIR_SETUP 0x0 |
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#define OHCI_TD_DIR_OUT 0x1 |
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#define OHCI_TD_DIR_IN 0x2 |
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#define OHCI_TD_DIR_RESERVED 0x3 |
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|
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#define OHCI_CC_NOERROR 0x0 |
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#define OHCI_CC_CRC 0x1 |
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#define OHCI_CC_BITSTUFFING 0x2 |
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#define OHCI_CC_DATATOGGLEMISMATCH 0x3 |
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#define OHCI_CC_STALL 0x4 |
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#define OHCI_CC_DEVICENOTRESPONDING 0x5 |
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#define OHCI_CC_PIDCHECKFAILURE 0x6 |
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#define OHCI_CC_UNDEXPETEDPID 0x7 |
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#define OHCI_CC_DATAOVERRUN 0x8 |
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#define OHCI_CC_DATAUNDERRUN 0x9 |
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#define OHCI_CC_BUFFEROVERRUN 0xc |
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#define OHCI_CC_BUFFERUNDERRUN 0xd |
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|
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/* Update IRQ levels */
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static inline void ohci_intr_update(OHCIState *ohci) |
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{ |
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int level = 0; |
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if ((ohci->intr & OHCI_INTR_MIE) &&
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(ohci->intr_status & ohci->intr)) |
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level = 1;
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pci_set_irq(&ohci->pci_dev, 0, level);
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} |
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/* Set an interrupt */
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static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr) |
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{ |
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ohci->intr_status |= intr; |
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ohci_intr_update(ohci); |
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} |
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/* Attach or detach a device on a root hub port. */
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static void ohci_attach(USBPort *port1, USBDevice *dev) |
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{ |
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OHCIState *s = port1->opaque; |
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OHCIPort *port = &s->rhport[port1->index]; |
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uint32_t old_state = port->ctrl; |
276 |
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if (dev) {
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if (port->port.dev) {
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usb_attach(port1, NULL);
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} |
281 |
/* set connect status */
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port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC; |
283 |
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/* update speed */
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if (dev->speed == USB_SPEED_LOW)
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port->ctrl |= OHCI_PORT_LSDA; |
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else
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port->ctrl &= ~OHCI_PORT_LSDA; |
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port->port.dev = dev; |
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/* send the attach message */
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dev->handle_packet(dev, |
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USB_MSG_ATTACH, 0, 0, NULL, 0); |
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dprintf("usb-ohci: Attached port %d\n", port1->index);
|
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} else {
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/* set connect status */
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if (port->ctrl & OHCI_PORT_CCS) {
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port->ctrl &= ~OHCI_PORT_CCS; |
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port->ctrl |= OHCI_PORT_CSC; |
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} |
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/* disable port */
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if (port->ctrl & OHCI_PORT_PES) {
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port->ctrl &= ~OHCI_PORT_PES; |
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port->ctrl |= OHCI_PORT_PESC; |
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} |
305 |
dev = port->port.dev; |
306 |
if (dev) {
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/* send the detach message */
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dev->handle_packet(dev, |
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USB_MSG_DETACH, 0, 0, NULL, 0); |
310 |
} |
311 |
port->port.dev = NULL;
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dprintf("usb-ohci: Detached port %d\n", port1->index);
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} |
314 |
|
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if (old_state != port->ctrl)
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ohci_set_interrupt(s, OHCI_INTR_RHSC); |
317 |
} |
318 |
|
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/* Reset the controller */
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static void ohci_reset(OHCIState *ohci) |
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{ |
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OHCIPort *port; |
323 |
int i;
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324 |
|
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ohci->ctl = 0;
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ohci->status = 0;
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ohci->intr_status = 0;
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ohci->intr = OHCI_INTR_MIE; |
329 |
|
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ohci->hcca = 0;
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ohci->ctrl_head = ohci->ctrl_cur = 0;
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ohci->bulk_head = ohci->bulk_cur = 0;
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ohci->per_cur = 0;
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ohci->done = 0;
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ohci->done_count = 7;
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336 |
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/* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
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* I took the value linux sets ...
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*/
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ohci->fsmps = 0x2778;
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ohci->fi = 0x2edf;
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ohci->fit = 0;
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ohci->frt = 0;
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ohci->frame_number = 0;
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ohci->pstart = 0;
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ohci->lst = OHCI_LS_THRESH; |
347 |
|
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ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; |
349 |
ohci->rhdesc_b = 0x0; /* Impl. specific */ |
350 |
ohci->rhstatus = 0;
|
351 |
|
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for (i = 0; i < ohci->num_ports; i++) |
353 |
{ |
354 |
port = &ohci->rhport[i]; |
355 |
port->ctrl = 0;
|
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if (port->port.dev)
|
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ohci_attach(&port->port, port->port.dev); |
358 |
} |
359 |
dprintf("usb-ohci: Reset %s\n", ohci->pci_dev.name);
|
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} |
361 |
|
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/* Get an array of dwords from main memory */
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static inline int get_dwords(uint32_t addr, uint32_t *buf, int num) |
364 |
{ |
365 |
int i;
|
366 |
|
367 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
368 |
cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0); |
369 |
*buf = le32_to_cpu(*buf); |
370 |
} |
371 |
|
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return 1; |
373 |
} |
374 |
|
375 |
/* Put an array of dwords in to main memory */
|
376 |
static inline int put_dwords(uint32_t addr, uint32_t *buf, int num) |
377 |
{ |
378 |
int i;
|
379 |
|
380 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
381 |
uint32_t tmp = cpu_to_le32(*buf); |
382 |
cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1); |
383 |
} |
384 |
|
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return 1; |
386 |
} |
387 |
|
388 |
static inline int ohci_read_ed(uint32_t addr, struct ohci_ed *ed) |
389 |
{ |
390 |
return get_dwords(addr, (uint32_t *)ed, sizeof(*ed) >> 2); |
391 |
} |
392 |
|
393 |
static inline int ohci_read_td(uint32_t addr, struct ohci_td *td) |
394 |
{ |
395 |
return get_dwords(addr, (uint32_t *)td, sizeof(*td) >> 2); |
396 |
} |
397 |
|
398 |
static inline int ohci_put_ed(uint32_t addr, struct ohci_ed *ed) |
399 |
{ |
400 |
return put_dwords(addr, (uint32_t *)ed, sizeof(*ed) >> 2); |
401 |
} |
402 |
|
403 |
static inline int ohci_put_td(uint32_t addr, struct ohci_td *td) |
404 |
{ |
405 |
return put_dwords(addr, (uint32_t *)td, sizeof(*td) >> 2); |
406 |
} |
407 |
|
408 |
/* Read/Write the contents of a TD from/to main memory. */
|
409 |
static void ohci_copy_td(struct ohci_td *td, uint8_t *buf, int len, int write) |
410 |
{ |
411 |
uint32_t ptr; |
412 |
uint32_t n; |
413 |
|
414 |
ptr = td->cbp; |
415 |
n = 0x1000 - (ptr & 0xfff); |
416 |
if (n > len)
|
417 |
n = len; |
418 |
cpu_physical_memory_rw(ptr, buf, n, write); |
419 |
if (n == len)
|
420 |
return;
|
421 |
ptr = td->be & ~0xfffu;
|
422 |
buf += n; |
423 |
cpu_physical_memory_rw(ptr, buf, len - n, write); |
424 |
} |
425 |
|
426 |
/* Service a transport descriptor.
|
427 |
Returns nonzero to terminate processing of this endpoint. */
|
428 |
|
429 |
static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) |
430 |
{ |
431 |
int dir;
|
432 |
size_t len = 0;
|
433 |
uint8_t buf[8192];
|
434 |
char *str = NULL; |
435 |
int pid;
|
436 |
int ret;
|
437 |
int i;
|
438 |
USBDevice *dev; |
439 |
struct ohci_td td;
|
440 |
uint32_t addr; |
441 |
int flag_r;
|
442 |
|
443 |
addr = ed->head & OHCI_DPTR_MASK; |
444 |
if (!ohci_read_td(addr, &td)) {
|
445 |
fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
|
446 |
return 0; |
447 |
} |
448 |
|
449 |
dir = OHCI_BM(ed->flags, ED_D); |
450 |
switch (dir) {
|
451 |
case OHCI_TD_DIR_OUT:
|
452 |
case OHCI_TD_DIR_IN:
|
453 |
/* Same value. */
|
454 |
break;
|
455 |
default:
|
456 |
dir = OHCI_BM(td.flags, TD_DP); |
457 |
break;
|
458 |
} |
459 |
|
460 |
switch (dir) {
|
461 |
case OHCI_TD_DIR_IN:
|
462 |
str = "in";
|
463 |
pid = USB_TOKEN_IN; |
464 |
break;
|
465 |
case OHCI_TD_DIR_OUT:
|
466 |
str = "out";
|
467 |
pid = USB_TOKEN_OUT; |
468 |
break;
|
469 |
case OHCI_TD_DIR_SETUP:
|
470 |
str = "setup";
|
471 |
pid = USB_TOKEN_SETUP; |
472 |
break;
|
473 |
default:
|
474 |
fprintf(stderr, "usb-ohci: Bad direction\n");
|
475 |
return 1; |
476 |
} |
477 |
if (td.cbp && td.be) {
|
478 |
if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { |
479 |
len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); |
480 |
} else {
|
481 |
len = (td.be - td.cbp) + 1;
|
482 |
} |
483 |
|
484 |
if (len && dir != OHCI_TD_DIR_IN) {
|
485 |
ohci_copy_td(&td, buf, len, 0);
|
486 |
} |
487 |
} |
488 |
|
489 |
flag_r = (td.flags & OHCI_TD_R) != 0;
|
490 |
#ifdef DEBUG_PACKET
|
491 |
dprintf(" TD @ 0x%.8x %u bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
|
492 |
addr, len, str, flag_r, td.cbp, td.be); |
493 |
|
494 |
if (len >= 0 && dir != OHCI_TD_DIR_IN) { |
495 |
dprintf(" data:");
|
496 |
for (i = 0; i < len; i++) |
497 |
printf(" %.2x", buf[i]);
|
498 |
dprintf("\n");
|
499 |
} |
500 |
#endif
|
501 |
ret = USB_RET_NODEV; |
502 |
for (i = 0; i < ohci->num_ports; i++) { |
503 |
dev = ohci->rhport[i].port.dev; |
504 |
if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) |
505 |
continue;
|
506 |
|
507 |
ret = dev->handle_packet(dev, pid, OHCI_BM(ed->flags, ED_FA), |
508 |
OHCI_BM(ed->flags, ED_EN), buf, len); |
509 |
if (ret != USB_RET_NODEV)
|
510 |
break;
|
511 |
} |
512 |
#ifdef DEBUG_PACKET
|
513 |
dprintf("ret=%d\n", ret);
|
514 |
#endif
|
515 |
if (ret >= 0) { |
516 |
if (dir == OHCI_TD_DIR_IN) {
|
517 |
ohci_copy_td(&td, buf, ret, 1);
|
518 |
#ifdef DEBUG_PACKET
|
519 |
dprintf(" data:");
|
520 |
for (i = 0; i < ret; i++) |
521 |
printf(" %.2x", buf[i]);
|
522 |
dprintf("\n");
|
523 |
#endif
|
524 |
} else {
|
525 |
ret = len; |
526 |
} |
527 |
} |
528 |
|
529 |
/* Writeback */
|
530 |
if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { |
531 |
/* Transmission succeeded. */
|
532 |
if (ret == len) {
|
533 |
td.cbp = 0;
|
534 |
} else {
|
535 |
td.cbp += ret; |
536 |
if ((td.cbp & 0xfff) + ret > 0xfff) { |
537 |
td.cbp &= 0xfff;
|
538 |
td.cbp |= td.be & ~0xfff;
|
539 |
} |
540 |
} |
541 |
td.flags |= OHCI_TD_T1; |
542 |
td.flags ^= OHCI_TD_T0; |
543 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); |
544 |
OHCI_SET_BM(td.flags, TD_EC, 0);
|
545 |
|
546 |
ed->head &= ~OHCI_ED_C; |
547 |
if (td.flags & OHCI_TD_T0)
|
548 |
ed->head |= OHCI_ED_C; |
549 |
} else {
|
550 |
if (ret >= 0) { |
551 |
dprintf("usb-ohci: Underrun\n");
|
552 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN); |
553 |
} else {
|
554 |
switch (ret) {
|
555 |
case USB_RET_NODEV:
|
556 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING); |
557 |
case USB_RET_NAK:
|
558 |
dprintf("usb-ohci: got NAK\n");
|
559 |
return 1; |
560 |
case USB_RET_STALL:
|
561 |
dprintf("usb-ohci: got STALL\n");
|
562 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL); |
563 |
break;
|
564 |
case USB_RET_BABBLE:
|
565 |
dprintf("usb-ohci: got BABBLE\n");
|
566 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN); |
567 |
break;
|
568 |
default:
|
569 |
fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
|
570 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID); |
571 |
OHCI_SET_BM(td.flags, TD_EC, 3);
|
572 |
break;
|
573 |
} |
574 |
} |
575 |
ed->head |= OHCI_ED_H; |
576 |
} |
577 |
|
578 |
/* Retire this TD */
|
579 |
ed->head &= ~OHCI_DPTR_MASK; |
580 |
ed->head |= td.next & OHCI_DPTR_MASK; |
581 |
td.next = ohci->done; |
582 |
ohci->done = addr; |
583 |
i = OHCI_BM(td.flags, TD_DI); |
584 |
if (i < ohci->done_count)
|
585 |
ohci->done_count = i; |
586 |
ohci_put_td(addr, &td); |
587 |
return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
|
588 |
} |
589 |
|
590 |
/* Service an endpoint list. Returns nonzero if active TD were found. */
|
591 |
static int ohci_service_ed_list(OHCIState *ohci, uint32_t head) |
592 |
{ |
593 |
struct ohci_ed ed;
|
594 |
uint32_t next_ed; |
595 |
uint32_t cur; |
596 |
int active;
|
597 |
|
598 |
active = 0;
|
599 |
|
600 |
if (head == 0) |
601 |
return 0; |
602 |
|
603 |
for (cur = head; cur; cur = next_ed) {
|
604 |
if (!ohci_read_ed(cur, &ed)) {
|
605 |
fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
|
606 |
return 0; |
607 |
} |
608 |
|
609 |
next_ed = ed.next & OHCI_DPTR_MASK; |
610 |
|
611 |
if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K))
|
612 |
continue;
|
613 |
|
614 |
/* Skip isochronous endpoints. */
|
615 |
if (ed.flags & OHCI_ED_F)
|
616 |
continue;
|
617 |
|
618 |
while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
|
619 |
#ifdef DEBUG_PACKET
|
620 |
dprintf("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
|
621 |
"h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
|
622 |
OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN), |
623 |
OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
|
624 |
(ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0, |
625 |
OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
|
626 |
(ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
|
627 |
ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK); |
628 |
#endif
|
629 |
active = 1;
|
630 |
|
631 |
if (ohci_service_td(ohci, &ed))
|
632 |
break;
|
633 |
} |
634 |
|
635 |
ohci_put_ed(cur, &ed); |
636 |
} |
637 |
|
638 |
return active;
|
639 |
} |
640 |
|
641 |
/* Generate a SOF event, and set a timer for EOF */
|
642 |
static void ohci_sof(OHCIState *ohci) |
643 |
{ |
644 |
ohci->sof_time = qemu_get_clock(vm_clock); |
645 |
qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time); |
646 |
ohci_set_interrupt(ohci, OHCI_INTR_SF); |
647 |
} |
648 |
|
649 |
/* Do frame processing on frame boundary */
|
650 |
static void ohci_frame_boundary(void *opaque) |
651 |
{ |
652 |
OHCIState *ohci = opaque; |
653 |
struct ohci_hcca hcca;
|
654 |
|
655 |
cpu_physical_memory_rw(ohci->hcca, (uint8_t *)&hcca, sizeof(hcca), 0); |
656 |
|
657 |
/* Process all the lists at the end of the frame */
|
658 |
if (ohci->ctl & OHCI_CTL_PLE) {
|
659 |
int n;
|
660 |
|
661 |
n = ohci->frame_number & 0x1f;
|
662 |
ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n])); |
663 |
} |
664 |
if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
|
665 |
if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head)
|
666 |
dprintf("usb-ohci: head %x, cur %x\n", ohci->ctrl_head, ohci->ctrl_cur);
|
667 |
if (!ohci_service_ed_list(ohci, ohci->ctrl_head)) {
|
668 |
ohci->ctrl_cur = 0;
|
669 |
ohci->status &= ~OHCI_STATUS_CLF; |
670 |
} |
671 |
} |
672 |
|
673 |
if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
|
674 |
if (!ohci_service_ed_list(ohci, ohci->bulk_head)) {
|
675 |
ohci->bulk_cur = 0;
|
676 |
ohci->status &= ~OHCI_STATUS_BLF; |
677 |
} |
678 |
} |
679 |
|
680 |
/* Frame boundary, so do EOF stuf here */
|
681 |
ohci->frt = ohci->fit; |
682 |
|
683 |
/* XXX: endianness */
|
684 |
ohci->frame_number = (ohci->frame_number + 1) & 0xffff; |
685 |
hcca.frame = cpu_to_le32(ohci->frame_number); |
686 |
|
687 |
if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) { |
688 |
if (!ohci->done)
|
689 |
abort(); |
690 |
if (ohci->intr & ohci->intr_status)
|
691 |
ohci->done |= 1;
|
692 |
hcca.done = cpu_to_le32(ohci->done); |
693 |
ohci->done = 0;
|
694 |
ohci->done_count = 7;
|
695 |
ohci_set_interrupt(ohci, OHCI_INTR_WD); |
696 |
} |
697 |
|
698 |
if (ohci->done_count != 7 && ohci->done_count != 0) |
699 |
ohci->done_count--; |
700 |
|
701 |
/* Do SOF stuff here */
|
702 |
ohci_sof(ohci); |
703 |
|
704 |
/* Writeback HCCA */
|
705 |
cpu_physical_memory_rw(ohci->hcca, (uint8_t *)&hcca, sizeof(hcca), 1); |
706 |
} |
707 |
|
708 |
/* Start sending SOF tokens across the USB bus, lists are processed in
|
709 |
* next frame
|
710 |
*/
|
711 |
static int ohci_bus_start(OHCIState *ohci) |
712 |
{ |
713 |
ohci->eof_timer = qemu_new_timer(vm_clock, |
714 |
ohci_frame_boundary, |
715 |
ohci); |
716 |
|
717 |
if (ohci->eof_timer == NULL) { |
718 |
fprintf(stderr, "usb-ohci: %s: qemu_new_timer failed\n",
|
719 |
ohci->pci_dev.name); |
720 |
/* TODO: Signal unrecoverable error */
|
721 |
return 0; |
722 |
} |
723 |
|
724 |
dprintf("usb-ohci: %s: USB Operational\n", ohci->pci_dev.name);
|
725 |
|
726 |
ohci_sof(ohci); |
727 |
|
728 |
return 1; |
729 |
} |
730 |
|
731 |
/* Stop sending SOF tokens on the bus */
|
732 |
static void ohci_bus_stop(OHCIState *ohci) |
733 |
{ |
734 |
if (ohci->eof_timer)
|
735 |
qemu_del_timer(ohci->eof_timer); |
736 |
} |
737 |
|
738 |
/* Sets a flag in a port status register but only set it if the port is
|
739 |
* connected, if not set ConnectStatusChange flag. If flag is enabled
|
740 |
* return 1.
|
741 |
*/
|
742 |
static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val) |
743 |
{ |
744 |
int ret = 1; |
745 |
|
746 |
/* writing a 0 has no effect */
|
747 |
if (val == 0) |
748 |
return 0; |
749 |
|
750 |
/* If CurrentConnectStatus is cleared we set
|
751 |
* ConnectStatusChange
|
752 |
*/
|
753 |
if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
|
754 |
ohci->rhport[i].ctrl |= OHCI_PORT_CSC; |
755 |
if (ohci->rhstatus & OHCI_RHS_DRWE) {
|
756 |
/* TODO: CSC is a wakeup event */
|
757 |
} |
758 |
return 0; |
759 |
} |
760 |
|
761 |
if (ohci->rhport[i].ctrl & val)
|
762 |
ret = 0;
|
763 |
|
764 |
/* set the bit */
|
765 |
ohci->rhport[i].ctrl |= val; |
766 |
|
767 |
return ret;
|
768 |
} |
769 |
|
770 |
/* Set the frame interval - frame interval toggle is manipulated by the hcd only */
|
771 |
static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val) |
772 |
{ |
773 |
val &= OHCI_FMI_FI; |
774 |
|
775 |
if (val != ohci->fi) {
|
776 |
dprintf("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
|
777 |
ohci->pci_dev.name, ohci->fi, ohci->fi); |
778 |
} |
779 |
|
780 |
ohci->fi = val; |
781 |
} |
782 |
|
783 |
static void ohci_port_power(OHCIState *ohci, int i, int p) |
784 |
{ |
785 |
if (p) {
|
786 |
ohci->rhport[i].ctrl |= OHCI_PORT_PPS; |
787 |
} else {
|
788 |
ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS| |
789 |
OHCI_PORT_CCS| |
790 |
OHCI_PORT_PSS| |
791 |
OHCI_PORT_PRS); |
792 |
} |
793 |
} |
794 |
|
795 |
/* Set HcControlRegister */
|
796 |
static void ohci_set_ctl(OHCIState *ohci, uint32_t val) |
797 |
{ |
798 |
uint32_t old_state; |
799 |
uint32_t new_state; |
800 |
|
801 |
old_state = ohci->ctl & OHCI_CTL_HCFS; |
802 |
ohci->ctl = val; |
803 |
new_state = ohci->ctl & OHCI_CTL_HCFS; |
804 |
|
805 |
/* no state change */
|
806 |
if (old_state == new_state)
|
807 |
return;
|
808 |
|
809 |
switch (new_state) {
|
810 |
case OHCI_USB_OPERATIONAL:
|
811 |
ohci_bus_start(ohci); |
812 |
break;
|
813 |
case OHCI_USB_SUSPEND:
|
814 |
ohci_bus_stop(ohci); |
815 |
dprintf("usb-ohci: %s: USB Suspended\n", ohci->pci_dev.name);
|
816 |
break;
|
817 |
case OHCI_USB_RESUME:
|
818 |
dprintf("usb-ohci: %s: USB Resume\n", ohci->pci_dev.name);
|
819 |
break;
|
820 |
case OHCI_USB_RESET:
|
821 |
dprintf("usb-ohci: %s: USB Reset\n", ohci->pci_dev.name);
|
822 |
break;
|
823 |
} |
824 |
} |
825 |
|
826 |
static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
|
827 |
{ |
828 |
uint16_t fr; |
829 |
int64_t tks; |
830 |
|
831 |
if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
|
832 |
return (ohci->frt << 31); |
833 |
|
834 |
/* Being in USB operational state guarnatees sof_time was
|
835 |
* set already.
|
836 |
*/
|
837 |
tks = qemu_get_clock(vm_clock) - ohci->sof_time; |
838 |
|
839 |
/* avoid muldiv if possible */
|
840 |
if (tks >= usb_frame_time)
|
841 |
return (ohci->frt << 31); |
842 |
|
843 |
tks = muldiv64(1, tks, usb_bit_time);
|
844 |
fr = (uint16_t)(ohci->fi - tks); |
845 |
|
846 |
return (ohci->frt << 31) | fr; |
847 |
} |
848 |
|
849 |
|
850 |
/* Set root hub status */
|
851 |
static void ohci_set_hub_status(OHCIState *ohci, uint32_t val) |
852 |
{ |
853 |
uint32_t old_state; |
854 |
|
855 |
old_state = ohci->rhstatus; |
856 |
|
857 |
/* write 1 to clear OCIC */
|
858 |
if (val & OHCI_RHS_OCIC)
|
859 |
ohci->rhstatus &= ~OHCI_RHS_OCIC; |
860 |
|
861 |
if (val & OHCI_RHS_LPS) {
|
862 |
int i;
|
863 |
|
864 |
for (i = 0; i < ohci->num_ports; i++) |
865 |
ohci_port_power(ohci, i, 0);
|
866 |
dprintf("usb-ohci: powered down all ports\n");
|
867 |
} |
868 |
|
869 |
if (val & OHCI_RHS_LPSC) {
|
870 |
int i;
|
871 |
|
872 |
for (i = 0; i < ohci->num_ports; i++) |
873 |
ohci_port_power(ohci, i, 1);
|
874 |
dprintf("usb-ohci: powered up all ports\n");
|
875 |
} |
876 |
|
877 |
if (val & OHCI_RHS_DRWE)
|
878 |
ohci->rhstatus |= OHCI_RHS_DRWE; |
879 |
|
880 |
if (val & OHCI_RHS_CRWE)
|
881 |
ohci->rhstatus &= ~OHCI_RHS_DRWE; |
882 |
|
883 |
if (old_state != ohci->rhstatus)
|
884 |
ohci_set_interrupt(ohci, OHCI_INTR_RHSC); |
885 |
} |
886 |
|
887 |
/* Set root hub port status */
|
888 |
static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) |
889 |
{ |
890 |
uint32_t old_state; |
891 |
OHCIPort *port; |
892 |
|
893 |
port = &ohci->rhport[portnum]; |
894 |
old_state = port->ctrl; |
895 |
|
896 |
/* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
|
897 |
if (val & OHCI_PORT_WTC)
|
898 |
port->ctrl &= ~(val & OHCI_PORT_WTC); |
899 |
|
900 |
if (val & OHCI_PORT_CCS)
|
901 |
port->ctrl &= ~OHCI_PORT_PES; |
902 |
|
903 |
ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES); |
904 |
|
905 |
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS))
|
906 |
dprintf("usb-ohci: port %d: SUSPEND\n", portnum);
|
907 |
|
908 |
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
|
909 |
dprintf("usb-ohci: port %d: RESET\n", portnum);
|
910 |
port->port.dev->handle_packet(port->port.dev, USB_MSG_RESET, |
911 |
0, 0, NULL, 0); |
912 |
port->ctrl &= ~OHCI_PORT_PRS; |
913 |
/* ??? Should this also set OHCI_PORT_PESC. */
|
914 |
port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC; |
915 |
} |
916 |
|
917 |
/* Invert order here to ensure in ambiguous case, device is
|
918 |
* powered up...
|
919 |
*/
|
920 |
if (val & OHCI_PORT_LSDA)
|
921 |
ohci_port_power(ohci, portnum, 0);
|
922 |
if (val & OHCI_PORT_PPS)
|
923 |
ohci_port_power(ohci, portnum, 1);
|
924 |
|
925 |
if (old_state != port->ctrl)
|
926 |
ohci_set_interrupt(ohci, OHCI_INTR_RHSC); |
927 |
|
928 |
return;
|
929 |
} |
930 |
|
931 |
static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr) |
932 |
{ |
933 |
OHCIState *ohci = ptr; |
934 |
|
935 |
addr -= ohci->mem_base; |
936 |
|
937 |
/* Only aligned reads are allowed on OHCI */
|
938 |
if (addr & 3) { |
939 |
fprintf(stderr, "usb-ohci: Mis-aligned read\n");
|
940 |
return 0xffffffff; |
941 |
} |
942 |
|
943 |
if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { |
944 |
/* HcRhPortStatus */
|
945 |
return ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; |
946 |
} |
947 |
|
948 |
switch (addr >> 2) { |
949 |
case 0: /* HcRevision */ |
950 |
return 0x10; |
951 |
|
952 |
case 1: /* HcControl */ |
953 |
return ohci->ctl;
|
954 |
|
955 |
case 2: /* HcCommandStatus */ |
956 |
return ohci->status;
|
957 |
|
958 |
case 3: /* HcInterruptStatus */ |
959 |
return ohci->intr_status;
|
960 |
|
961 |
case 4: /* HcInterruptEnable */ |
962 |
case 5: /* HcInterruptDisable */ |
963 |
return ohci->intr;
|
964 |
|
965 |
case 6: /* HcHCCA */ |
966 |
return ohci->hcca;
|
967 |
|
968 |
case 7: /* HcPeriodCurrentED */ |
969 |
return ohci->per_cur;
|
970 |
|
971 |
case 8: /* HcControlHeadED */ |
972 |
return ohci->ctrl_head;
|
973 |
|
974 |
case 9: /* HcControlCurrentED */ |
975 |
return ohci->ctrl_cur;
|
976 |
|
977 |
case 10: /* HcBulkHeadED */ |
978 |
return ohci->bulk_head;
|
979 |
|
980 |
case 11: /* HcBulkCurrentED */ |
981 |
return ohci->bulk_cur;
|
982 |
|
983 |
case 12: /* HcDoneHead */ |
984 |
return ohci->done;
|
985 |
|
986 |
case 13: /* HcFmInterval */ |
987 |
return (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); |
988 |
|
989 |
case 14: /* HcFmRemaining */ |
990 |
return ohci_get_frame_remaining(ohci);
|
991 |
|
992 |
case 15: /* HcFmNumber */ |
993 |
return ohci->frame_number;
|
994 |
|
995 |
case 16: /* HcPeriodicStart */ |
996 |
return ohci->pstart;
|
997 |
|
998 |
case 17: /* HcLSThreshold */ |
999 |
return ohci->lst;
|
1000 |
|
1001 |
case 18: /* HcRhDescriptorA */ |
1002 |
return ohci->rhdesc_a;
|
1003 |
|
1004 |
case 19: /* HcRhDescriptorB */ |
1005 |
return ohci->rhdesc_b;
|
1006 |
|
1007 |
case 20: /* HcRhStatus */ |
1008 |
return ohci->rhstatus;
|
1009 |
|
1010 |
default:
|
1011 |
fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr); |
1012 |
return 0xffffffff; |
1013 |
} |
1014 |
} |
1015 |
|
1016 |
static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val) |
1017 |
{ |
1018 |
OHCIState *ohci = ptr; |
1019 |
|
1020 |
addr -= ohci->mem_base; |
1021 |
|
1022 |
/* Only aligned reads are allowed on OHCI */
|
1023 |
if (addr & 3) { |
1024 |
fprintf(stderr, "usb-ohci: Mis-aligned write\n");
|
1025 |
return;
|
1026 |
} |
1027 |
|
1028 |
if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { |
1029 |
/* HcRhPortStatus */
|
1030 |
ohci_port_set_status(ohci, (addr - 0x54) >> 2, val); |
1031 |
return;
|
1032 |
} |
1033 |
|
1034 |
switch (addr >> 2) { |
1035 |
case 1: /* HcControl */ |
1036 |
ohci_set_ctl(ohci, val); |
1037 |
break;
|
1038 |
|
1039 |
case 2: /* HcCommandStatus */ |
1040 |
/* SOC is read-only */
|
1041 |
val = (val & ~OHCI_STATUS_SOC); |
1042 |
|
1043 |
/* Bits written as '0' remain unchanged in the register */
|
1044 |
ohci->status |= val; |
1045 |
|
1046 |
if (ohci->status & OHCI_STATUS_HCR)
|
1047 |
ohci_reset(ohci); |
1048 |
break;
|
1049 |
|
1050 |
case 3: /* HcInterruptStatus */ |
1051 |
ohci->intr_status &= ~val; |
1052 |
ohci_intr_update(ohci); |
1053 |
break;
|
1054 |
|
1055 |
case 4: /* HcInterruptEnable */ |
1056 |
ohci->intr |= val; |
1057 |
ohci_intr_update(ohci); |
1058 |
break;
|
1059 |
|
1060 |
case 5: /* HcInterruptDisable */ |
1061 |
ohci->intr &= ~val; |
1062 |
ohci_intr_update(ohci); |
1063 |
break;
|
1064 |
|
1065 |
case 6: /* HcHCCA */ |
1066 |
ohci->hcca = val & OHCI_HCCA_MASK; |
1067 |
break;
|
1068 |
|
1069 |
case 8: /* HcControlHeadED */ |
1070 |
ohci->ctrl_head = val & OHCI_EDPTR_MASK; |
1071 |
break;
|
1072 |
|
1073 |
case 9: /* HcControlCurrentED */ |
1074 |
ohci->ctrl_cur = val & OHCI_EDPTR_MASK; |
1075 |
break;
|
1076 |
|
1077 |
case 10: /* HcBulkHeadED */ |
1078 |
ohci->bulk_head = val & OHCI_EDPTR_MASK; |
1079 |
break;
|
1080 |
|
1081 |
case 11: /* HcBulkCurrentED */ |
1082 |
ohci->bulk_cur = val & OHCI_EDPTR_MASK; |
1083 |
break;
|
1084 |
|
1085 |
case 13: /* HcFmInterval */ |
1086 |
ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
|
1087 |
ohci->fit = (val & OHCI_FMI_FIT) >> 31;
|
1088 |
ohci_set_frame_interval(ohci, val); |
1089 |
break;
|
1090 |
|
1091 |
case 16: /* HcPeriodicStart */ |
1092 |
ohci->pstart = val & 0xffff;
|
1093 |
break;
|
1094 |
|
1095 |
case 17: /* HcLSThreshold */ |
1096 |
ohci->lst = val & 0xffff;
|
1097 |
break;
|
1098 |
|
1099 |
case 18: /* HcRhDescriptorA */ |
1100 |
ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK; |
1101 |
ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK; |
1102 |
break;
|
1103 |
|
1104 |
case 19: /* HcRhDescriptorB */ |
1105 |
break;
|
1106 |
|
1107 |
case 20: /* HcRhStatus */ |
1108 |
ohci_set_hub_status(ohci, val); |
1109 |
break;
|
1110 |
|
1111 |
default:
|
1112 |
fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr); |
1113 |
break;
|
1114 |
} |
1115 |
} |
1116 |
|
1117 |
/* Only dword reads are defined on OHCI register space */
|
1118 |
static CPUReadMemoryFunc *ohci_readfn[3]={ |
1119 |
ohci_mem_read, |
1120 |
ohci_mem_read, |
1121 |
ohci_mem_read |
1122 |
}; |
1123 |
|
1124 |
/* Only dword writes are defined on OHCI register space */
|
1125 |
static CPUWriteMemoryFunc *ohci_writefn[3]={ |
1126 |
ohci_mem_write, |
1127 |
ohci_mem_write, |
1128 |
ohci_mem_write |
1129 |
}; |
1130 |
|
1131 |
static void ohci_mapfunc(PCIDevice *pci_dev, int i, |
1132 |
uint32_t addr, uint32_t size, int type)
|
1133 |
{ |
1134 |
OHCIState *ohci = (OHCIState *)pci_dev; |
1135 |
ohci->mem_base = addr; |
1136 |
cpu_register_physical_memory(addr, size, ohci->mem); |
1137 |
} |
1138 |
|
1139 |
void usb_ohci_init(struct PCIBus *bus, int num_ports, int devfn) |
1140 |
{ |
1141 |
OHCIState *ohci; |
1142 |
int vid = 0x106b; |
1143 |
int did = 0x003f; |
1144 |
int i;
|
1145 |
|
1146 |
|
1147 |
if (usb_frame_time == 0) { |
1148 |
#if OHCI_TIME_WARP
|
1149 |
usb_frame_time = ticks_per_sec; |
1150 |
usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ/1000); |
1151 |
#else
|
1152 |
usb_frame_time = muldiv64(1, ticks_per_sec, 1000); |
1153 |
if (ticks_per_sec >= USB_HZ) {
|
1154 |
usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ);
|
1155 |
} else {
|
1156 |
usb_bit_time = 1;
|
1157 |
} |
1158 |
#endif
|
1159 |
dprintf("usb-ohci: usb_bit_time=%lli usb_frame_time=%lli\n",
|
1160 |
usb_frame_time, usb_bit_time); |
1161 |
} |
1162 |
|
1163 |
ohci = (OHCIState *)pci_register_device(bus, "OHCI USB", sizeof(*ohci), |
1164 |
devfn, NULL, NULL); |
1165 |
if (ohci == NULL) { |
1166 |
fprintf(stderr, "usb-ohci: Failed to register PCI device\n");
|
1167 |
return;
|
1168 |
} |
1169 |
|
1170 |
ohci->pci_dev.config[0x00] = vid & 0xff; |
1171 |
ohci->pci_dev.config[0x01] = (vid >> 8) & 0xff; |
1172 |
ohci->pci_dev.config[0x02] = did & 0xff; |
1173 |
ohci->pci_dev.config[0x03] = (did >> 8) & 0xff; |
1174 |
ohci->pci_dev.config[0x09] = 0x10; /* OHCI */ |
1175 |
ohci->pci_dev.config[0x0a] = 0x3; |
1176 |
ohci->pci_dev.config[0x0b] = 0xc; |
1177 |
ohci->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */ |
1178 |
|
1179 |
ohci->mem = cpu_register_io_memory(0, ohci_readfn, ohci_writefn, ohci);
|
1180 |
|
1181 |
pci_register_io_region((struct PCIDevice *)ohci, 0, 256, |
1182 |
PCI_ADDRESS_SPACE_MEM, ohci_mapfunc); |
1183 |
|
1184 |
ohci->num_ports = num_ports; |
1185 |
for (i = 0; i < num_ports; i++) { |
1186 |
qemu_register_usb_port(&ohci->rhport[i].port, ohci, i, ohci_attach); |
1187 |
} |
1188 |
|
1189 |
ohci_reset(ohci); |
1190 |
} |