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/*
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* User emulator execution
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "config.h" |
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#include "exec.h" |
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#include "disas.h" |
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#include "tcg.h" |
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|
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#undef EAX
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#undef ECX
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#undef EDX
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#undef EBX
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#undef ESP
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#undef EBP
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#undef ESI
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#undef EDI
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#undef EIP
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#include <signal.h> |
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#ifdef __linux__
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#include <sys/ucontext.h> |
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#endif
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//#define DEBUG_SIGNAL
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static void exception_action(CPUState *env1) |
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{
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#if defined(TARGET_I386)
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raise_exception_err(env1->exception_index, env1->error_code); |
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#else
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cpu_loop_exit(env1); |
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#endif
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} |
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/* exit the current TB from a signal handler. The host registers are
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restored in a state compatible with the CPU emulator
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*/
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void cpu_resume_from_signal(CPUState *env1, void *puc) |
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{
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#ifdef __linux__
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struct ucontext *uc = puc;
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#elif defined(__OpenBSD__)
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struct sigcontext *uc = puc;
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#endif
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env = env1; |
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/* XXX: restore cpu registers saved in host registers */
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if (puc) {
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/* XXX: use siglongjmp ? */
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#ifdef __linux__
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#ifdef __ia64
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sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
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#else
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sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
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#endif
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#elif defined(__OpenBSD__)
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sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
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#endif
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} |
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env->exception_index = -1;
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longjmp(env->jmp_env, 1);
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} |
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/* 'pc' is the host PC at which the exception was raised. 'address' is
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the effective address of the memory exception. 'is_write' is 1 if a
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write caused the exception and otherwise 0'. 'old_set' is the
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signal set which should be restored */
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static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
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int is_write, sigset_t *old_set,
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void *puc)
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{
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TranslationBlock *tb; |
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int ret;
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if (cpu_single_env) {
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env = cpu_single_env; /* XXX: find a correct solution for multithread */
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} |
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#if defined(DEBUG_SIGNAL)
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qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
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pc, address, is_write, *(unsigned long *)old_set); |
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#endif
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/* XXX: locking issue */
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if (is_write && page_unprotect(h2g(address), pc, puc)) {
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return 1; |
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} |
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/* see if it is an MMU fault */
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ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
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if (ret < 0) { |
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return 0; /* not an MMU fault */ |
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} |
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if (ret == 0) { |
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return 1; /* the MMU fault was handled without causing real CPU fault */ |
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} |
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/* now we have a real cpu fault */
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tb = tb_find_pc(pc); |
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, pc); |
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} |
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/* we restore the process signal mask as the sigreturn should
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do it (XXX: use sigsetjmp) */
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sigprocmask(SIG_SETMASK, old_set, NULL);
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exception_action(env); |
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/* never comes here */
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return 1; |
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} |
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#if defined(__i386__)
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#if defined(__APPLE__)
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#include <sys/ucontext.h> |
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#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext->ss.eip)) |
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#define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
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#define ERROR_sig(context) ((context)->uc_mcontext->es.err)
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#define MASK_sig(context) ((context)->uc_sigmask)
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#elif defined(__NetBSD__)
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#include <ucontext.h> |
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#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
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#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
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#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
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#define MASK_sig(context) ((context)->uc_sigmask)
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#elif defined(__FreeBSD__) || defined(__DragonFly__)
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#include <ucontext.h> |
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#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip)) |
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#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
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#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
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#define MASK_sig(context) ((context)->uc_sigmask)
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#elif defined(__OpenBSD__)
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#define EIP_sig(context) ((context)->sc_eip)
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#define TRAP_sig(context) ((context)->sc_trapno)
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#define ERROR_sig(context) ((context)->sc_err)
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#define MASK_sig(context) ((context)->sc_mask)
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#else
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#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
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#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
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#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
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#define MASK_sig(context) ((context)->uc_sigmask)
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#endif
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int cpu_signal_handler(int host_signum, void *pinfo, |
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void *puc)
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{
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siginfo_t *info = pinfo; |
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#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
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ucontext_t *uc = puc; |
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#elif defined(__OpenBSD__)
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struct sigcontext *uc = puc;
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#else
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struct ucontext *uc = puc;
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#endif
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unsigned long pc; |
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int trapno;
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#ifndef REG_EIP
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/* for glibc 2.1 */
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#define REG_EIP EIP
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#define REG_ERR ERR
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#define REG_TRAPNO TRAPNO
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#endif
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pc = EIP_sig(uc); |
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trapno = TRAP_sig(uc); |
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return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
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trapno == 0xe ?
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(ERROR_sig(uc) >> 1) & 1 : 0, |
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&MASK_sig(uc), puc); |
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} |
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#elif defined(__x86_64__)
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#ifdef __NetBSD__
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#define PC_sig(context) _UC_MACHINE_PC(context)
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#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
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#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
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#define MASK_sig(context) ((context)->uc_sigmask)
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#elif defined(__OpenBSD__)
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#define PC_sig(context) ((context)->sc_rip)
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#define TRAP_sig(context) ((context)->sc_trapno)
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#define ERROR_sig(context) ((context)->sc_err)
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#define MASK_sig(context) ((context)->sc_mask)
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#elif defined(__FreeBSD__) || defined(__DragonFly__)
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#include <ucontext.h> |
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#define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip)) |
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#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
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#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
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#define MASK_sig(context) ((context)->uc_sigmask)
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#else
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#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
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#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
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#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
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#define MASK_sig(context) ((context)->uc_sigmask)
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#endif
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int cpu_signal_handler(int host_signum, void *pinfo, |
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void *puc)
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{
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siginfo_t *info = pinfo; |
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unsigned long pc; |
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#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
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ucontext_t *uc = puc; |
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#elif defined(__OpenBSD__)
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struct sigcontext *uc = puc;
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#else
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struct ucontext *uc = puc;
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#endif
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pc = PC_sig(uc); |
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return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
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TRAP_sig(uc) == 0xe ?
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(ERROR_sig(uc) >> 1) & 1 : 0, |
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&MASK_sig(uc), puc); |
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} |
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#elif defined(_ARCH_PPC)
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/***********************************************************************
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* signal context platform-specific definitions
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* From Wine
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*/
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#ifdef linux
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/* All Registers access - only for local access */
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#define REG_sig(reg_name, context) \
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((context)->uc_mcontext.regs->reg_name) |
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/* Gpr Registers access */
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#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
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/* Program counter */
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#define IAR_sig(context) REG_sig(nip, context)
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/* Machine State Register (Supervisor) */
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#define MSR_sig(context) REG_sig(msr, context)
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/* Count register */
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#define CTR_sig(context) REG_sig(ctr, context)
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/* User's integer exception register */
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#define XER_sig(context) REG_sig(xer, context)
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/* Link register */
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#define LR_sig(context) REG_sig(link, context)
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/* Condition register */
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#define CR_sig(context) REG_sig(ccr, context)
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/* Float Registers access */
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#define FLOAT_sig(reg_num, context) \
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(((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) |
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#define FPSCR_sig(context) \
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(*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) |
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/* Exception Registers access */
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#define DAR_sig(context) REG_sig(dar, context)
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#define DSISR_sig(context) REG_sig(dsisr, context)
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#define TRAP_sig(context) REG_sig(trap, context)
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#endif /* linux */ |
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#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
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#include <ucontext.h> |
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#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
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#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
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#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
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#define XER_sig(context) ((context)->uc_mcontext.mc_xer)
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#define LR_sig(context) ((context)->uc_mcontext.mc_lr)
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#define CR_sig(context) ((context)->uc_mcontext.mc_cr)
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/* Exception Registers access */
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#define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
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#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
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#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
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#endif /* __FreeBSD__|| __FreeBSD_kernel__ */ |
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#ifdef __APPLE__
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#include <sys/ucontext.h> |
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typedef struct ucontext SIGCONTEXT; |
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/* All Registers access - only for local access */
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#define REG_sig(reg_name, context) \
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((context)->uc_mcontext->ss.reg_name) |
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#define FLOATREG_sig(reg_name, context) \
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((context)->uc_mcontext->fs.reg_name) |
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#define EXCEPREG_sig(reg_name, context) \
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((context)->uc_mcontext->es.reg_name) |
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#define VECREG_sig(reg_name, context) \
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((context)->uc_mcontext->vs.reg_name) |
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/* Gpr Registers access */
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#define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
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/* Program counter */
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#define IAR_sig(context) REG_sig(srr0, context)
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/* Machine State Register (Supervisor) */
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#define MSR_sig(context) REG_sig(srr1, context)
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#define CTR_sig(context) REG_sig(ctr, context)
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/* Link register */
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#define XER_sig(context) REG_sig(xer, context)
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/* User's integer exception register */
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#define LR_sig(context) REG_sig(lr, context)
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/* Condition register */
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#define CR_sig(context) REG_sig(cr, context)
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/* Float Registers access */
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#define FLOAT_sig(reg_num, context) \
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FLOATREG_sig(fpregs[reg_num], context) |
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#define FPSCR_sig(context) \
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((double)FLOATREG_sig(fpscr, context))
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/* Exception Registers access */
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/* Fault registers for coredump */
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#define DAR_sig(context) EXCEPREG_sig(dar, context)
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#define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
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/* number of powerpc exception taken */
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#define TRAP_sig(context) EXCEPREG_sig(exception, context)
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#endif /* __APPLE__ */ |
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int cpu_signal_handler(int host_signum, void *pinfo, |
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void *puc)
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{
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siginfo_t *info = pinfo; |
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#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
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ucontext_t *uc = puc; |
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#else
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struct ucontext *uc = puc;
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#endif
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unsigned long pc; |
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int is_write;
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pc = IAR_sig(uc); |
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is_write = 0;
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#if 0
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/* ppc 4xx case */
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if (DSISR_sig(uc) & 0x00800000) {
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is_write = 1;
|
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}
|
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#else
|
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if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) { |
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is_write = 1;
|
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} |
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#endif
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return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
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is_write, &uc->uc_sigmask, puc); |
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} |
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|
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#elif defined(__alpha__)
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|
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int cpu_signal_handler(int host_signum, void *pinfo, |
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void *puc)
|
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{
|
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siginfo_t *info = pinfo; |
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struct ucontext *uc = puc;
|
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uint32_t *pc = uc->uc_mcontext.sc_pc; |
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uint32_t insn = *pc; |
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int is_write = 0; |
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|
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/* XXX: need kernel patch to get write flag faster */
|
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switch (insn >> 26) { |
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case 0x0d: /* stw */ |
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case 0x0e: /* stb */ |
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case 0x0f: /* stq_u */ |
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case 0x24: /* stf */ |
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case 0x25: /* stg */ |
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case 0x26: /* sts */ |
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case 0x27: /* stt */ |
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case 0x2c: /* stl */ |
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case 0x2d: /* stq */ |
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case 0x2e: /* stl_c */ |
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case 0x2f: /* stq_c */ |
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is_write = 1;
|
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} |
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|
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return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
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is_write, &uc->uc_sigmask, puc); |
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} |
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#elif defined(__sparc__)
|
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|
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int cpu_signal_handler(int host_signum, void *pinfo, |
| 386 |
void *puc)
|
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{
|
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siginfo_t *info = pinfo; |
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int is_write;
|
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uint32_t insn; |
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#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
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uint32_t *regs = (uint32_t *)(info + 1);
|
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void *sigmask = (regs + 20); |
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/* XXX: is there a standard glibc define ? */
|
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unsigned long pc = regs[1]; |
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#else
|
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#ifdef __linux__
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struct sigcontext *sc = puc;
|
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unsigned long pc = sc->sigc_regs.tpc; |
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void *sigmask = (void *)sc->sigc_mask; |
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#elif defined(__OpenBSD__)
|
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struct sigcontext *uc = puc;
|
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unsigned long pc = uc->sc_pc; |
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void *sigmask = (void *)(long)uc->sc_mask; |
| 405 |
#endif
|
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#endif
|
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|
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/* XXX: need kernel patch to get write flag faster */
|
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is_write = 0;
|
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insn = *(uint32_t *)pc; |
| 411 |
if ((insn >> 30) == 3) { |
| 412 |
switch ((insn >> 19) & 0x3f) { |
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case 0x05: /* stb */ |
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case 0x15: /* stba */ |
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case 0x06: /* sth */ |
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case 0x16: /* stha */ |
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case 0x04: /* st */ |
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case 0x14: /* sta */ |
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case 0x07: /* std */ |
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case 0x17: /* stda */ |
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case 0x0e: /* stx */ |
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case 0x1e: /* stxa */ |
| 423 |
case 0x24: /* stf */ |
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case 0x34: /* stfa */ |
| 425 |
case 0x27: /* stdf */ |
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case 0x37: /* stdfa */ |
| 427 |
case 0x26: /* stqf */ |
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case 0x36: /* stqfa */ |
| 429 |
case 0x25: /* stfsr */ |
| 430 |
case 0x3c: /* casa */ |
| 431 |
case 0x3e: /* casxa */ |
| 432 |
is_write = 1;
|
| 433 |
break;
|
| 434 |
} |
| 435 |
} |
| 436 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 437 |
is_write, sigmask, NULL);
|
| 438 |
} |
| 439 |
|
| 440 |
#elif defined(__arm__)
|
| 441 |
|
| 442 |
int cpu_signal_handler(int host_signum, void *pinfo, |
| 443 |
void *puc)
|
| 444 |
{
|
| 445 |
siginfo_t *info = pinfo; |
| 446 |
struct ucontext *uc = puc;
|
| 447 |
unsigned long pc; |
| 448 |
int is_write;
|
| 449 |
|
| 450 |
#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) |
| 451 |
pc = uc->uc_mcontext.gregs[R15]; |
| 452 |
#else
|
| 453 |
pc = uc->uc_mcontext.arm_pc; |
| 454 |
#endif
|
| 455 |
/* XXX: compute is_write */
|
| 456 |
is_write = 0;
|
| 457 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 458 |
is_write, |
| 459 |
&uc->uc_sigmask, puc); |
| 460 |
} |
| 461 |
|
| 462 |
#elif defined(__mc68000)
|
| 463 |
|
| 464 |
int cpu_signal_handler(int host_signum, void *pinfo, |
| 465 |
void *puc)
|
| 466 |
{
|
| 467 |
siginfo_t *info = pinfo; |
| 468 |
struct ucontext *uc = puc;
|
| 469 |
unsigned long pc; |
| 470 |
int is_write;
|
| 471 |
|
| 472 |
pc = uc->uc_mcontext.gregs[16];
|
| 473 |
/* XXX: compute is_write */
|
| 474 |
is_write = 0;
|
| 475 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 476 |
is_write, |
| 477 |
&uc->uc_sigmask, puc); |
| 478 |
} |
| 479 |
|
| 480 |
#elif defined(__ia64)
|
| 481 |
|
| 482 |
#ifndef __ISR_VALID
|
| 483 |
/* This ought to be in <bits/siginfo.h>... */
|
| 484 |
# define __ISR_VALID 1 |
| 485 |
#endif
|
| 486 |
|
| 487 |
int cpu_signal_handler(int host_signum, void *pinfo, void *puc) |
| 488 |
{
|
| 489 |
siginfo_t *info = pinfo; |
| 490 |
struct ucontext *uc = puc;
|
| 491 |
unsigned long ip; |
| 492 |
int is_write = 0; |
| 493 |
|
| 494 |
ip = uc->uc_mcontext.sc_ip; |
| 495 |
switch (host_signum) {
|
| 496 |
case SIGILL:
|
| 497 |
case SIGFPE:
|
| 498 |
case SIGSEGV:
|
| 499 |
case SIGBUS:
|
| 500 |
case SIGTRAP:
|
| 501 |
if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
|
| 502 |
/* ISR.W (write-access) is bit 33: */
|
| 503 |
is_write = (info->si_isr >> 33) & 1; |
| 504 |
} |
| 505 |
break;
|
| 506 |
|
| 507 |
default:
|
| 508 |
break;
|
| 509 |
} |
| 510 |
return handle_cpu_signal(ip, (unsigned long)info->si_addr, |
| 511 |
is_write, |
| 512 |
(sigset_t *)&uc->uc_sigmask, puc); |
| 513 |
} |
| 514 |
|
| 515 |
#elif defined(__s390__)
|
| 516 |
|
| 517 |
int cpu_signal_handler(int host_signum, void *pinfo, |
| 518 |
void *puc)
|
| 519 |
{
|
| 520 |
siginfo_t *info = pinfo; |
| 521 |
struct ucontext *uc = puc;
|
| 522 |
unsigned long pc; |
| 523 |
uint16_t *pinsn; |
| 524 |
int is_write = 0; |
| 525 |
|
| 526 |
pc = uc->uc_mcontext.psw.addr; |
| 527 |
|
| 528 |
/* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
|
| 529 |
of the normal 2 arguments. The 3rd argument contains the "int_code"
|
| 530 |
from the hardware which does in fact contain the is_write value.
|
| 531 |
The rt signal handler, as far as I can tell, does not give this value
|
| 532 |
at all. Not that we could get to it from here even if it were. */
|
| 533 |
/* ??? This is not even close to complete, since it ignores all
|
| 534 |
of the read-modify-write instructions. */
|
| 535 |
pinsn = (uint16_t *)pc; |
| 536 |
switch (pinsn[0] >> 8) { |
| 537 |
case 0x50: /* ST */ |
| 538 |
case 0x42: /* STC */ |
| 539 |
case 0x40: /* STH */ |
| 540 |
is_write = 1;
|
| 541 |
break;
|
| 542 |
case 0xc4: /* RIL format insns */ |
| 543 |
switch (pinsn[0] & 0xf) { |
| 544 |
case 0xf: /* STRL */ |
| 545 |
case 0xb: /* STGRL */ |
| 546 |
case 0x7: /* STHRL */ |
| 547 |
is_write = 1;
|
| 548 |
} |
| 549 |
break;
|
| 550 |
case 0xe3: /* RXY format insns */ |
| 551 |
switch (pinsn[2] & 0xff) { |
| 552 |
case 0x50: /* STY */ |
| 553 |
case 0x24: /* STG */ |
| 554 |
case 0x72: /* STCY */ |
| 555 |
case 0x70: /* STHY */ |
| 556 |
case 0x8e: /* STPQ */ |
| 557 |
case 0x3f: /* STRVH */ |
| 558 |
case 0x3e: /* STRV */ |
| 559 |
case 0x2f: /* STRVG */ |
| 560 |
is_write = 1;
|
| 561 |
} |
| 562 |
break;
|
| 563 |
} |
| 564 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 565 |
is_write, &uc->uc_sigmask, puc); |
| 566 |
} |
| 567 |
|
| 568 |
#elif defined(__mips__)
|
| 569 |
|
| 570 |
int cpu_signal_handler(int host_signum, void *pinfo, |
| 571 |
void *puc)
|
| 572 |
{
|
| 573 |
siginfo_t *info = pinfo; |
| 574 |
struct ucontext *uc = puc;
|
| 575 |
greg_t pc = uc->uc_mcontext.pc; |
| 576 |
int is_write;
|
| 577 |
|
| 578 |
/* XXX: compute is_write */
|
| 579 |
is_write = 0;
|
| 580 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 581 |
is_write, &uc->uc_sigmask, puc); |
| 582 |
} |
| 583 |
|
| 584 |
#elif defined(__hppa__)
|
| 585 |
|
| 586 |
int cpu_signal_handler(int host_signum, void *pinfo, |
| 587 |
void *puc)
|
| 588 |
{
|
| 589 |
struct siginfo *info = pinfo;
|
| 590 |
struct ucontext *uc = puc;
|
| 591 |
unsigned long pc = uc->uc_mcontext.sc_iaoq[0]; |
| 592 |
uint32_t insn = *(uint32_t *)pc; |
| 593 |
int is_write = 0; |
| 594 |
|
| 595 |
/* XXX: need kernel patch to get write flag faster. */
|
| 596 |
switch (insn >> 26) { |
| 597 |
case 0x1a: /* STW */ |
| 598 |
case 0x19: /* STH */ |
| 599 |
case 0x18: /* STB */ |
| 600 |
case 0x1b: /* STWM */ |
| 601 |
is_write = 1;
|
| 602 |
break;
|
| 603 |
|
| 604 |
case 0x09: /* CSTWX, FSTWX, FSTWS */ |
| 605 |
case 0x0b: /* CSTDX, FSTDX, FSTDS */ |
| 606 |
/* Distinguish from coprocessor load ... */
|
| 607 |
is_write = (insn >> 9) & 1; |
| 608 |
break;
|
| 609 |
|
| 610 |
case 0x03: |
| 611 |
switch ((insn >> 6) & 15) { |
| 612 |
case 0xa: /* STWS */ |
| 613 |
case 0x9: /* STHS */ |
| 614 |
case 0x8: /* STBS */ |
| 615 |
case 0xe: /* STWAS */ |
| 616 |
case 0xc: /* STBYS */ |
| 617 |
is_write = 1;
|
| 618 |
} |
| 619 |
break;
|
| 620 |
} |
| 621 |
|
| 622 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 623 |
is_write, &uc->uc_sigmask, puc); |
| 624 |
} |
| 625 |
|
| 626 |
#else
|
| 627 |
|
| 628 |
#error host CPU specific signal handler needed
|
| 629 |
|
| 630 |
#endif
|
| 631 |
|
| 632 |
#if defined(TARGET_I386)
|
| 633 |
|
| 634 |
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
| 635 |
{
|
| 636 |
CPUX86State *saved_env; |
| 637 |
|
| 638 |
saved_env = env; |
| 639 |
env = s; |
| 640 |
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
| 641 |
selector &= 0xffff;
|
| 642 |
cpu_x86_load_seg_cache(env, seg_reg, selector, |
| 643 |
(selector << 4), 0xffff, 0); |
| 644 |
} else {
|
| 645 |
helper_load_seg(seg_reg, selector); |
| 646 |
} |
| 647 |
env = saved_env; |
| 648 |
} |
| 649 |
|
| 650 |
void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32) |
| 651 |
{
|
| 652 |
CPUX86State *saved_env; |
| 653 |
|
| 654 |
saved_env = env; |
| 655 |
env = s; |
| 656 |
|
| 657 |
helper_fsave(ptr, data32); |
| 658 |
|
| 659 |
env = saved_env; |
| 660 |
} |
| 661 |
|
| 662 |
void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32) |
| 663 |
{
|
| 664 |
CPUX86State *saved_env; |
| 665 |
|
| 666 |
saved_env = env; |
| 667 |
env = s; |
| 668 |
|
| 669 |
helper_frstor(ptr, data32); |
| 670 |
|
| 671 |
env = saved_env; |
| 672 |
} |
| 673 |
|
| 674 |
#endif /* TARGET_I386 */ |