Archipelago » qemu

    [CC_OP_ADCX] = USES_CC_DST | USES_CC_SRC,

    [CC_OP_ADOX] = USES_CC_SRC | USES_CC_SRC2,

    [CC_OP_ADCOX] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2,

};

static void set_cc_op(DisasContext *s, CCOp op)

    if (s->cc_op == CC_OP_EFLAGS) {

        return;

    }

    TCGV_UNUSED(zero);

    dst = cpu_cc_dst;

                             .reg2 = t1, .mask = -1, .use_reg2 = true };

    case CC_OP_LOGICB ... CC_OP_LOGICQ:

        return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 };

    case CC_OP_INCB ... CC_OP_INCQ:

    case CC_OP_ADCOX:

        return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,

                             .mask = CC_S };

    default:

        {

            int size = (s->cc_op - CC_OP_ADDB) & 3;

    case CC_OP_ADCOX:

        return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src2,

                             .mask = -1, .no_setcond = true };

    default:

        gen_compute_eflags(s);

        return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,

    case CC_OP_ADCOX:

        return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,

                             .mask = CC_Z };

    default:

        {

            int size = (s->cc_op - CC_OP_ADDB) & 3;

                } else if (op == OP_XORL && rm == reg) {

                xor_zero:

                    /* xor reg, reg optimisation */

                    gen_op_movl_T0_0();

                    gen_op_mov_reg_T0(ot, reg);

                    break;

                } else {

                    opreg = rm;